1 /* $OpenBSD: ichiic.c,v 1.45 2021/05/19 05:28:09 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C620_SMB }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_SMB }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_SMB }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_SMB }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_SMB }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_SMB }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SMB }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_SMB }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_SMB }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_SMB }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SMB }, 137 }; 138 139 int 140 ichiic_match(struct device *parent, void *match, void *aux) 141 { 142 return (pci_matchbyid(aux, ichiic_ids, 143 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 144 } 145 146 void 147 ichiic_attach(struct device *parent, struct device *self, void *aux) 148 { 149 struct ichiic_softc *sc = (struct ichiic_softc *)self; 150 struct pci_attach_args *pa = aux; 151 struct i2cbus_attach_args iba; 152 pcireg_t conf; 153 bus_size_t iosize; 154 pci_intr_handle_t ih; 155 const char *intrstr = NULL; 156 157 /* Read configuration */ 158 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 159 DPRINTF((": conf 0x%08x", conf)); 160 161 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 162 printf(": SMBus disabled\n"); 163 return; 164 } 165 166 /* Map I/O space */ 167 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 168 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 169 printf(": can't map i/o space\n"); 170 return; 171 } 172 173 sc->sc_poll = 1; 174 if (conf & ICH_SMB_HOSTC_SMIEN) { 175 /* No PCI IRQ */ 176 printf(": SMI"); 177 } else { 178 /* Install interrupt handler */ 179 if (pci_intr_map(pa, &ih) == 0) { 180 intrstr = pci_intr_string(pa->pa_pc, ih); 181 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 182 ichiic_intr, sc, sc->sc_dev.dv_xname); 183 if (sc->sc_ih != NULL) { 184 printf(": %s", intrstr); 185 sc->sc_poll = 0; 186 } 187 } 188 if (sc->sc_poll) 189 printf(": polling"); 190 } 191 192 printf("\n"); 193 194 /* Attach I2C bus */ 195 rw_init(&sc->sc_i2c_lock, "iiclk"); 196 sc->sc_i2c_tag.ic_cookie = sc; 197 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 198 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 199 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 200 201 bzero(&iba, sizeof(iba)); 202 iba.iba_name = "iic"; 203 iba.iba_tag = &sc->sc_i2c_tag; 204 config_found(self, &iba, iicbus_print); 205 206 return; 207 } 208 209 int 210 ichiic_i2c_acquire_bus(void *cookie, int flags) 211 { 212 struct ichiic_softc *sc = cookie; 213 214 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 215 return (0); 216 217 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 218 } 219 220 void 221 ichiic_i2c_release_bus(void *cookie, int flags) 222 { 223 struct ichiic_softc *sc = cookie; 224 225 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 226 return; 227 228 rw_exit(&sc->sc_i2c_lock); 229 } 230 231 int 232 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 233 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 234 { 235 struct ichiic_softc *sc = cookie; 236 u_int8_t *b; 237 u_int8_t ctl, st; 238 int retries; 239 240 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 241 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 242 len, flags)); 243 244 /* Wait for bus to be idle */ 245 for (retries = 100; retries > 0; retries--) { 246 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 247 if (!(st & ICH_SMB_HS_BUSY)) 248 break; 249 DELAY(ICHIIC_DELAY); 250 } 251 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 252 ICH_SMB_HS_BITS)); 253 if (st & ICH_SMB_HS_BUSY) 254 return (1); 255 256 if (cold || sc->sc_poll) 257 flags |= I2C_F_POLL; 258 259 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 260 return (1); 261 262 /* Setup transfer */ 263 sc->sc_i2c_xfer.op = op; 264 sc->sc_i2c_xfer.buf = buf; 265 sc->sc_i2c_xfer.len = len; 266 sc->sc_i2c_xfer.flags = flags; 267 sc->sc_i2c_xfer.error = 0; 268 269 /* Set slave address and transfer direction */ 270 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 271 ICH_SMB_TXSLVA_ADDR(addr) | 272 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 273 274 b = (void *)cmdbuf; 275 if (cmdlen > 0) 276 /* Set command byte */ 277 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 278 279 if (I2C_OP_WRITE_P(op)) { 280 /* Write data */ 281 b = buf; 282 if (len > 0) 283 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 284 ICH_SMB_HD0, b[0]); 285 if (len > 1) 286 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 287 ICH_SMB_HD1, b[1]); 288 } 289 290 /* Set SMBus command */ 291 if (len == 0) 292 ctl = ICH_SMB_HC_CMD_BYTE; 293 else if (len == 1) 294 ctl = ICH_SMB_HC_CMD_BDATA; 295 else if (len == 2) 296 ctl = ICH_SMB_HC_CMD_WDATA; 297 else 298 panic("%s: unexpected len %zd", __func__, len); 299 300 if ((flags & I2C_F_POLL) == 0) 301 ctl |= ICH_SMB_HC_INTREN; 302 303 /* Start transaction */ 304 ctl |= ICH_SMB_HC_START; 305 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 306 307 if (flags & I2C_F_POLL) { 308 /* Poll for completion */ 309 DELAY(ICHIIC_DELAY); 310 for (retries = 1000; retries > 0; retries--) { 311 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 312 ICH_SMB_HS); 313 if ((st & ICH_SMB_HS_BUSY) == 0) 314 break; 315 DELAY(ICHIIC_DELAY); 316 } 317 if (st & ICH_SMB_HS_BUSY) 318 goto timeout; 319 ichiic_intr(sc); 320 } else { 321 /* Wait for interrupt */ 322 if (tsleep_nsec(sc, PRIBIO, "ichiic", 323 SEC_TO_NSEC(ICHIIC_TIMEOUT))) 324 goto timeout; 325 } 326 327 if (sc->sc_i2c_xfer.error) 328 return (1); 329 330 return (0); 331 332 timeout: 333 /* 334 * Transfer timeout. Kill the transaction and clear status bits. 335 */ 336 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 337 ICH_SMB_HC_KILL); 338 DELAY(ICHIIC_DELAY); 339 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 340 if ((st & ICH_SMB_HS_FAILED) == 0) 341 printf("%s: abort failed, status 0x%b\n", 342 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 343 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 344 return (1); 345 } 346 347 int 348 ichiic_intr(void *arg) 349 { 350 struct ichiic_softc *sc = arg; 351 u_int8_t st; 352 u_int8_t *b; 353 size_t len; 354 355 /* Read status */ 356 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 357 358 /* Clear status bits */ 359 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 360 361 /* XXX Ignore SMBALERT# for now */ 362 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 363 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 364 ICH_SMB_HS_BDONE)) == 0) 365 /* Interrupt was not for us */ 366 return (0); 367 368 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 369 ICH_SMB_HS_BITS)); 370 371 /* Check for errors */ 372 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 373 sc->sc_i2c_xfer.error = 1; 374 goto done; 375 } 376 377 if (st & ICH_SMB_HS_INTR) { 378 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 379 goto done; 380 381 /* Read data */ 382 b = sc->sc_i2c_xfer.buf; 383 len = sc->sc_i2c_xfer.len; 384 if (len > 0) 385 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 386 ICH_SMB_HD0); 387 if (len > 1) 388 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 389 ICH_SMB_HD1); 390 } 391 392 done: 393 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 394 wakeup(sc); 395 return (1); 396 } 397