1 /* $OpenBSD: ichiic.c,v 1.28 2012/06/29 15:17:32 jasper Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB } 107 }; 108 109 int 110 ichiic_match(struct device *parent, void *match, void *aux) 111 { 112 return (pci_matchbyid(aux, ichiic_ids, 113 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 114 } 115 116 void 117 ichiic_attach(struct device *parent, struct device *self, void *aux) 118 { 119 struct ichiic_softc *sc = (struct ichiic_softc *)self; 120 struct pci_attach_args *pa = aux; 121 struct i2cbus_attach_args iba; 122 pcireg_t conf; 123 bus_size_t iosize; 124 pci_intr_handle_t ih; 125 const char *intrstr = NULL; 126 127 /* Read configuration */ 128 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 129 DPRINTF((": conf 0x%08x", conf)); 130 131 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 132 printf(": SMBus disabled\n"); 133 return; 134 } 135 136 /* Map I/O space */ 137 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 138 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 139 printf(": can't map i/o space\n"); 140 return; 141 } 142 143 sc->sc_poll = 1; 144 if (conf & ICH_SMB_HOSTC_SMIEN) { 145 /* No PCI IRQ */ 146 printf(": SMI"); 147 } else { 148 /* Install interrupt handler */ 149 if (pci_intr_map(pa, &ih) == 0) { 150 intrstr = pci_intr_string(pa->pa_pc, ih); 151 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 152 ichiic_intr, sc, sc->sc_dev.dv_xname); 153 if (sc->sc_ih != NULL) { 154 printf(": %s", intrstr); 155 sc->sc_poll = 0; 156 } 157 } 158 if (sc->sc_poll) 159 printf(": polling"); 160 } 161 162 printf("\n"); 163 164 /* Attach I2C bus */ 165 rw_init(&sc->sc_i2c_lock, "iiclk"); 166 sc->sc_i2c_tag.ic_cookie = sc; 167 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 168 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 169 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 170 171 bzero(&iba, sizeof(iba)); 172 iba.iba_name = "iic"; 173 iba.iba_tag = &sc->sc_i2c_tag; 174 config_found(self, &iba, iicbus_print); 175 176 return; 177 } 178 179 int 180 ichiic_i2c_acquire_bus(void *cookie, int flags) 181 { 182 struct ichiic_softc *sc = cookie; 183 184 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 185 return (0); 186 187 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 188 } 189 190 void 191 ichiic_i2c_release_bus(void *cookie, int flags) 192 { 193 struct ichiic_softc *sc = cookie; 194 195 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 196 return; 197 198 rw_exit(&sc->sc_i2c_lock); 199 } 200 201 int 202 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 203 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 204 { 205 struct ichiic_softc *sc = cookie; 206 u_int8_t *b; 207 u_int8_t ctl, st; 208 int retries; 209 210 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 211 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 212 len, flags)); 213 214 /* Wait for bus to be idle */ 215 for (retries = 100; retries > 0; retries--) { 216 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 217 if (!(st & ICH_SMB_HS_BUSY)) 218 break; 219 DELAY(ICHIIC_DELAY); 220 } 221 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 222 ICH_SMB_HS_BITS)); 223 if (st & ICH_SMB_HS_BUSY) 224 return (1); 225 226 if (cold || sc->sc_poll) 227 flags |= I2C_F_POLL; 228 229 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 230 return (1); 231 232 /* Setup transfer */ 233 sc->sc_i2c_xfer.op = op; 234 sc->sc_i2c_xfer.buf = buf; 235 sc->sc_i2c_xfer.len = len; 236 sc->sc_i2c_xfer.flags = flags; 237 sc->sc_i2c_xfer.error = 0; 238 239 /* Set slave address and transfer direction */ 240 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 241 ICH_SMB_TXSLVA_ADDR(addr) | 242 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 243 244 b = (void *)cmdbuf; 245 if (cmdlen > 0) 246 /* Set command byte */ 247 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 248 249 if (I2C_OP_WRITE_P(op)) { 250 /* Write data */ 251 b = buf; 252 if (len > 0) 253 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 254 ICH_SMB_HD0, b[0]); 255 if (len > 1) 256 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 257 ICH_SMB_HD1, b[1]); 258 } 259 260 /* Set SMBus command */ 261 if (len == 0) 262 ctl = ICH_SMB_HC_CMD_BYTE; 263 else if (len == 1) 264 ctl = ICH_SMB_HC_CMD_BDATA; 265 else if (len == 2) 266 ctl = ICH_SMB_HC_CMD_WDATA; 267 268 if ((flags & I2C_F_POLL) == 0) 269 ctl |= ICH_SMB_HC_INTREN; 270 271 /* Start transaction */ 272 ctl |= ICH_SMB_HC_START; 273 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 274 275 if (flags & I2C_F_POLL) { 276 /* Poll for completion */ 277 DELAY(ICHIIC_DELAY); 278 for (retries = 1000; retries > 0; retries--) { 279 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 280 ICH_SMB_HS); 281 if ((st & ICH_SMB_HS_BUSY) == 0) 282 break; 283 DELAY(ICHIIC_DELAY); 284 } 285 if (st & ICH_SMB_HS_BUSY) 286 goto timeout; 287 ichiic_intr(sc); 288 } else { 289 /* Wait for interrupt */ 290 if (tsleep(sc, PRIBIO, "ichiic", ICHIIC_TIMEOUT * hz)) 291 goto timeout; 292 } 293 294 if (sc->sc_i2c_xfer.error) 295 return (1); 296 297 return (0); 298 299 timeout: 300 /* 301 * Transfer timeout. Kill the transaction and clear status bits. 302 */ 303 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 304 ICH_SMB_HC_KILL); 305 DELAY(ICHIIC_DELAY); 306 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 307 if ((st & ICH_SMB_HS_FAILED) == 0) 308 printf("%s: abort failed, status 0x%b\n", 309 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 310 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 311 return (1); 312 } 313 314 int 315 ichiic_intr(void *arg) 316 { 317 struct ichiic_softc *sc = arg; 318 u_int8_t st; 319 u_int8_t *b; 320 size_t len; 321 322 /* Read status */ 323 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 324 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 325 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 326 ICH_SMB_HS_SMBAL | ICH_SMB_HS_BDONE)) == 0) 327 /* Interrupt was not for us */ 328 return (0); 329 330 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 331 ICH_SMB_HS_BITS)); 332 333 /* Clear status bits */ 334 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 335 336 /* Check for errors */ 337 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 338 sc->sc_i2c_xfer.error = 1; 339 goto done; 340 } 341 342 if (st & ICH_SMB_HS_INTR) { 343 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 344 goto done; 345 346 /* Read data */ 347 b = sc->sc_i2c_xfer.buf; 348 len = sc->sc_i2c_xfer.len; 349 if (len > 0) 350 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 351 ICH_SMB_HD0); 352 if (len > 1) 353 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 354 ICH_SMB_HD1); 355 } 356 357 done: 358 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 359 wakeup(sc); 360 return (1); 361 } 362