1 /* $OpenBSD: ichiic.c,v 1.50 2022/10/24 05:57:58 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 const struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C620_SMB }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_SMB }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_SMB }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_SMB }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_SMB }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_SMB }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SMB }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_SMB }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_SMB }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_SMB }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SMB }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_SMB }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_SMB }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_SMB }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_SMB }, 141 }; 142 143 int 144 ichiic_match(struct device *parent, void *match, void *aux) 145 { 146 return (pci_matchbyid(aux, ichiic_ids, 147 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 148 } 149 150 void 151 ichiic_attach(struct device *parent, struct device *self, void *aux) 152 { 153 struct ichiic_softc *sc = (struct ichiic_softc *)self; 154 struct pci_attach_args *pa = aux; 155 struct i2cbus_attach_args iba; 156 pcireg_t conf; 157 bus_size_t iosize; 158 pci_intr_handle_t ih; 159 const char *intrstr = NULL; 160 161 /* Read configuration */ 162 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 163 DPRINTF((": conf 0x%08x", conf)); 164 165 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 166 printf(": SMBus disabled\n"); 167 return; 168 } 169 170 /* Map I/O space */ 171 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 172 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 173 printf(": can't map i/o space\n"); 174 return; 175 } 176 177 sc->sc_poll = 1; 178 if (conf & ICH_SMB_HOSTC_SMIEN) { 179 /* No PCI IRQ */ 180 printf(": SMI"); 181 } else { 182 /* Install interrupt handler */ 183 if (pci_intr_map(pa, &ih) == 0) { 184 intrstr = pci_intr_string(pa->pa_pc, ih); 185 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 186 ichiic_intr, sc, sc->sc_dev.dv_xname); 187 if (sc->sc_ih != NULL) { 188 printf(": %s", intrstr); 189 sc->sc_poll = 0; 190 } 191 } 192 if (sc->sc_poll) 193 printf(": polling"); 194 } 195 196 printf("\n"); 197 198 /* Attach I2C bus */ 199 rw_init(&sc->sc_i2c_lock, "iiclk"); 200 sc->sc_i2c_tag.ic_cookie = sc; 201 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 202 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 203 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 204 205 bzero(&iba, sizeof(iba)); 206 iba.iba_name = "iic"; 207 iba.iba_tag = &sc->sc_i2c_tag; 208 config_found(self, &iba, iicbus_print); 209 210 return; 211 } 212 213 int 214 ichiic_i2c_acquire_bus(void *cookie, int flags) 215 { 216 struct ichiic_softc *sc = cookie; 217 218 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 219 return (0); 220 221 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 222 } 223 224 void 225 ichiic_i2c_release_bus(void *cookie, int flags) 226 { 227 struct ichiic_softc *sc = cookie; 228 229 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 230 return; 231 232 rw_exit(&sc->sc_i2c_lock); 233 } 234 235 int 236 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 237 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 238 { 239 struct ichiic_softc *sc = cookie; 240 u_int8_t *b; 241 u_int8_t ctl, st; 242 int retries; 243 244 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 245 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 246 len, flags)); 247 248 /* Wait for bus to be idle */ 249 for (retries = 100; retries > 0; retries--) { 250 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 251 if (!(st & ICH_SMB_HS_BUSY)) 252 break; 253 DELAY(ICHIIC_DELAY); 254 } 255 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 256 ICH_SMB_HS_BITS)); 257 if (st & ICH_SMB_HS_BUSY) 258 return (1); 259 260 if (cold || sc->sc_poll) 261 flags |= I2C_F_POLL; 262 263 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 264 return (1); 265 266 /* Setup transfer */ 267 sc->sc_i2c_xfer.op = op; 268 sc->sc_i2c_xfer.buf = buf; 269 sc->sc_i2c_xfer.len = len; 270 sc->sc_i2c_xfer.flags = flags; 271 sc->sc_i2c_xfer.error = 0; 272 273 /* Set slave address and transfer direction */ 274 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 275 ICH_SMB_TXSLVA_ADDR(addr) | 276 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 277 278 b = (void *)cmdbuf; 279 if (cmdlen > 0) 280 /* Set command byte */ 281 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 282 283 if (I2C_OP_WRITE_P(op)) { 284 /* Write data */ 285 b = buf; 286 if (len > 0) 287 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 288 ICH_SMB_HD0, b[0]); 289 if (len > 1) 290 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 291 ICH_SMB_HD1, b[1]); 292 } 293 294 /* Set SMBus command */ 295 if (len == 0) 296 ctl = ICH_SMB_HC_CMD_BYTE; 297 else if (len == 1) 298 ctl = ICH_SMB_HC_CMD_BDATA; 299 else if (len == 2) 300 ctl = ICH_SMB_HC_CMD_WDATA; 301 else 302 panic("%s: unexpected len %zd", __func__, len); 303 304 if ((flags & I2C_F_POLL) == 0) 305 ctl |= ICH_SMB_HC_INTREN; 306 307 /* Start transaction */ 308 ctl |= ICH_SMB_HC_START; 309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 310 311 if (flags & I2C_F_POLL) { 312 /* Poll for completion */ 313 DELAY(ICHIIC_DELAY); 314 for (retries = 1000; retries > 0; retries--) { 315 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 316 ICH_SMB_HS); 317 if ((st & ICH_SMB_HS_BUSY) == 0) 318 break; 319 DELAY(ICHIIC_DELAY); 320 } 321 if (st & ICH_SMB_HS_BUSY) 322 goto timeout; 323 ichiic_intr(sc); 324 } else { 325 /* Wait for interrupt */ 326 if (tsleep_nsec(sc, PRIBIO, "ichiic", 327 SEC_TO_NSEC(ICHIIC_TIMEOUT))) 328 goto timeout; 329 } 330 331 if (sc->sc_i2c_xfer.error) 332 return (1); 333 334 return (0); 335 336 timeout: 337 /* 338 * Transfer timeout. Kill the transaction and clear status bits. 339 */ 340 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 341 ICH_SMB_HC_KILL); 342 DELAY(ICHIIC_DELAY); 343 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 344 if ((st & ICH_SMB_HS_FAILED) == 0) 345 printf("%s: abort failed, status 0x%b\n", 346 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 347 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 348 return (1); 349 } 350 351 int 352 ichiic_intr(void *arg) 353 { 354 struct ichiic_softc *sc = arg; 355 u_int8_t st; 356 u_int8_t *b; 357 size_t len; 358 359 /* Read status */ 360 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 361 362 /* Clear status bits */ 363 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 364 365 /* XXX Ignore SMBALERT# for now */ 366 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 367 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 368 ICH_SMB_HS_BDONE)) == 0) 369 /* Interrupt was not for us */ 370 return (0); 371 372 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 373 ICH_SMB_HS_BITS)); 374 375 /* Check for errors */ 376 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 377 sc->sc_i2c_xfer.error = 1; 378 goto done; 379 } 380 381 if (st & ICH_SMB_HS_INTR) { 382 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 383 goto done; 384 385 /* Read data */ 386 b = sc->sc_i2c_xfer.buf; 387 len = sc->sc_i2c_xfer.len; 388 if (len > 0) 389 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 390 ICH_SMB_HD0); 391 if (len > 1) 392 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 393 ICH_SMB_HD1); 394 } 395 396 done: 397 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 398 wakeup(sc); 399 return (1); 400 } 401