1 /* $OpenBSD: ichiic.c,v 1.49 2022/06/21 04:17:21 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 const struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C620_SMB }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_SMB }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_SMB }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_SMB }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_SMB }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_SMB }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_SMB }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_SMB }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_SMB }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_SMB }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_SMB }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_SMB }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_SMB }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_SMB }, 140 }; 141 142 int 143 ichiic_match(struct device *parent, void *match, void *aux) 144 { 145 return (pci_matchbyid(aux, ichiic_ids, 146 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 147 } 148 149 void 150 ichiic_attach(struct device *parent, struct device *self, void *aux) 151 { 152 struct ichiic_softc *sc = (struct ichiic_softc *)self; 153 struct pci_attach_args *pa = aux; 154 struct i2cbus_attach_args iba; 155 pcireg_t conf; 156 bus_size_t iosize; 157 pci_intr_handle_t ih; 158 const char *intrstr = NULL; 159 160 /* Read configuration */ 161 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 162 DPRINTF((": conf 0x%08x", conf)); 163 164 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 165 printf(": SMBus disabled\n"); 166 return; 167 } 168 169 /* Map I/O space */ 170 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 171 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 172 printf(": can't map i/o space\n"); 173 return; 174 } 175 176 sc->sc_poll = 1; 177 if (conf & ICH_SMB_HOSTC_SMIEN) { 178 /* No PCI IRQ */ 179 printf(": SMI"); 180 } else { 181 /* Install interrupt handler */ 182 if (pci_intr_map(pa, &ih) == 0) { 183 intrstr = pci_intr_string(pa->pa_pc, ih); 184 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 185 ichiic_intr, sc, sc->sc_dev.dv_xname); 186 if (sc->sc_ih != NULL) { 187 printf(": %s", intrstr); 188 sc->sc_poll = 0; 189 } 190 } 191 if (sc->sc_poll) 192 printf(": polling"); 193 } 194 195 printf("\n"); 196 197 /* Attach I2C bus */ 198 rw_init(&sc->sc_i2c_lock, "iiclk"); 199 sc->sc_i2c_tag.ic_cookie = sc; 200 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 201 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 202 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 203 204 bzero(&iba, sizeof(iba)); 205 iba.iba_name = "iic"; 206 iba.iba_tag = &sc->sc_i2c_tag; 207 config_found(self, &iba, iicbus_print); 208 209 return; 210 } 211 212 int 213 ichiic_i2c_acquire_bus(void *cookie, int flags) 214 { 215 struct ichiic_softc *sc = cookie; 216 217 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 218 return (0); 219 220 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 221 } 222 223 void 224 ichiic_i2c_release_bus(void *cookie, int flags) 225 { 226 struct ichiic_softc *sc = cookie; 227 228 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 229 return; 230 231 rw_exit(&sc->sc_i2c_lock); 232 } 233 234 int 235 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 236 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 237 { 238 struct ichiic_softc *sc = cookie; 239 u_int8_t *b; 240 u_int8_t ctl, st; 241 int retries; 242 243 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 244 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 245 len, flags)); 246 247 /* Wait for bus to be idle */ 248 for (retries = 100; retries > 0; retries--) { 249 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 250 if (!(st & ICH_SMB_HS_BUSY)) 251 break; 252 DELAY(ICHIIC_DELAY); 253 } 254 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 255 ICH_SMB_HS_BITS)); 256 if (st & ICH_SMB_HS_BUSY) 257 return (1); 258 259 if (cold || sc->sc_poll) 260 flags |= I2C_F_POLL; 261 262 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 263 return (1); 264 265 /* Setup transfer */ 266 sc->sc_i2c_xfer.op = op; 267 sc->sc_i2c_xfer.buf = buf; 268 sc->sc_i2c_xfer.len = len; 269 sc->sc_i2c_xfer.flags = flags; 270 sc->sc_i2c_xfer.error = 0; 271 272 /* Set slave address and transfer direction */ 273 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 274 ICH_SMB_TXSLVA_ADDR(addr) | 275 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 276 277 b = (void *)cmdbuf; 278 if (cmdlen > 0) 279 /* Set command byte */ 280 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 281 282 if (I2C_OP_WRITE_P(op)) { 283 /* Write data */ 284 b = buf; 285 if (len > 0) 286 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 287 ICH_SMB_HD0, b[0]); 288 if (len > 1) 289 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 290 ICH_SMB_HD1, b[1]); 291 } 292 293 /* Set SMBus command */ 294 if (len == 0) 295 ctl = ICH_SMB_HC_CMD_BYTE; 296 else if (len == 1) 297 ctl = ICH_SMB_HC_CMD_BDATA; 298 else if (len == 2) 299 ctl = ICH_SMB_HC_CMD_WDATA; 300 else 301 panic("%s: unexpected len %zd", __func__, len); 302 303 if ((flags & I2C_F_POLL) == 0) 304 ctl |= ICH_SMB_HC_INTREN; 305 306 /* Start transaction */ 307 ctl |= ICH_SMB_HC_START; 308 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 309 310 if (flags & I2C_F_POLL) { 311 /* Poll for completion */ 312 DELAY(ICHIIC_DELAY); 313 for (retries = 1000; retries > 0; retries--) { 314 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 315 ICH_SMB_HS); 316 if ((st & ICH_SMB_HS_BUSY) == 0) 317 break; 318 DELAY(ICHIIC_DELAY); 319 } 320 if (st & ICH_SMB_HS_BUSY) 321 goto timeout; 322 ichiic_intr(sc); 323 } else { 324 /* Wait for interrupt */ 325 if (tsleep_nsec(sc, PRIBIO, "ichiic", 326 SEC_TO_NSEC(ICHIIC_TIMEOUT))) 327 goto timeout; 328 } 329 330 if (sc->sc_i2c_xfer.error) 331 return (1); 332 333 return (0); 334 335 timeout: 336 /* 337 * Transfer timeout. Kill the transaction and clear status bits. 338 */ 339 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 340 ICH_SMB_HC_KILL); 341 DELAY(ICHIIC_DELAY); 342 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 343 if ((st & ICH_SMB_HS_FAILED) == 0) 344 printf("%s: abort failed, status 0x%b\n", 345 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 346 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 347 return (1); 348 } 349 350 int 351 ichiic_intr(void *arg) 352 { 353 struct ichiic_softc *sc = arg; 354 u_int8_t st; 355 u_int8_t *b; 356 size_t len; 357 358 /* Read status */ 359 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 360 361 /* Clear status bits */ 362 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 363 364 /* XXX Ignore SMBALERT# for now */ 365 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 366 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 367 ICH_SMB_HS_BDONE)) == 0) 368 /* Interrupt was not for us */ 369 return (0); 370 371 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 372 ICH_SMB_HS_BITS)); 373 374 /* Check for errors */ 375 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 376 sc->sc_i2c_xfer.error = 1; 377 goto done; 378 } 379 380 if (st & ICH_SMB_HS_INTR) { 381 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 382 goto done; 383 384 /* Read data */ 385 b = sc->sc_i2c_xfer.buf; 386 len = sc->sc_i2c_xfer.len; 387 if (len > 0) 388 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 389 ICH_SMB_HD0); 390 if (len > 1) 391 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 392 ICH_SMB_HD1); 393 } 394 395 done: 396 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 397 wakeup(sc); 398 return (1); 399 } 400