1 /* $OpenBSD: ichiic.c,v 1.39 2016/04/24 06:50:58 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2005, 2006 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Intel ICH SMBus controller driver. 21 */ 22 23 #include <sys/param.h> 24 #include <sys/systm.h> 25 #include <sys/device.h> 26 #include <sys/kernel.h> 27 #include <sys/rwlock.h> 28 29 #include <machine/bus.h> 30 31 #include <dev/pci/pcidevs.h> 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 35 #include <dev/pci/ichreg.h> 36 37 #include <dev/i2c/i2cvar.h> 38 39 #ifdef ICHIIC_DEBUG 40 #define DPRINTF(x) printf x 41 #else 42 #define DPRINTF(x) 43 #endif 44 45 #define ICHIIC_DELAY 100 46 #define ICHIIC_TIMEOUT 1 47 48 struct ichiic_softc { 49 struct device sc_dev; 50 51 bus_space_tag_t sc_iot; 52 bus_space_handle_t sc_ioh; 53 void * sc_ih; 54 int sc_poll; 55 56 struct i2c_controller sc_i2c_tag; 57 struct rwlock sc_i2c_lock; 58 struct { 59 i2c_op_t op; 60 void * buf; 61 size_t len; 62 int flags; 63 volatile int error; 64 } sc_i2c_xfer; 65 }; 66 67 int ichiic_match(struct device *, void *, void *); 68 void ichiic_attach(struct device *, struct device *, void *); 69 70 int ichiic_i2c_acquire_bus(void *, int); 71 void ichiic_i2c_release_bus(void *, int); 72 int ichiic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 73 void *, size_t, int); 74 75 int ichiic_intr(void *); 76 77 struct cfattach ichiic_ca = { 78 sizeof(struct ichiic_softc), 79 ichiic_match, 80 ichiic_attach 81 }; 82 83 struct cfdriver ichiic_cd = { 84 NULL, "ichiic", DV_DULL 85 }; 86 87 const struct pci_matchid ichiic_ids[] = { 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_3400_SMB }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6SERIES_SMB }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6300ESB_SMB }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_6321ESB_SMB }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_7SERIES_SMB }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_SMB }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8SERIES_LP_SMB }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_SMB }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_9SERIES_LP_SMB }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_SMB }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_SMB }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_SMB }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_SMB }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_SMB }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_SMB }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_SMB }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_SMB }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_SMB }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801H_SMB }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801I_SMB }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JD_SMB }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SMB }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ATOMC2000_PCU_SMB }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BAYTRAIL_SMB }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_BRASWELL_SMB }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_1 }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_2 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C600_SMB_IDF_3 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_SMB }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_1 }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_2 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_C610_MS_SMB_3 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH8900_SMB }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_SMBUS }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_SMB }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_SMB } 125 }; 126 127 int 128 ichiic_match(struct device *parent, void *match, void *aux) 129 { 130 return (pci_matchbyid(aux, ichiic_ids, 131 sizeof(ichiic_ids) / sizeof(ichiic_ids[0]))); 132 } 133 134 void 135 ichiic_attach(struct device *parent, struct device *self, void *aux) 136 { 137 struct ichiic_softc *sc = (struct ichiic_softc *)self; 138 struct pci_attach_args *pa = aux; 139 struct i2cbus_attach_args iba; 140 pcireg_t conf; 141 bus_size_t iosize; 142 pci_intr_handle_t ih; 143 const char *intrstr = NULL; 144 145 /* Read configuration */ 146 conf = pci_conf_read(pa->pa_pc, pa->pa_tag, ICH_SMB_HOSTC); 147 DPRINTF((": conf 0x%08x", conf)); 148 149 if ((conf & ICH_SMB_HOSTC_HSTEN) == 0) { 150 printf(": SMBus disabled\n"); 151 return; 152 } 153 154 /* Map I/O space */ 155 if (pci_mapreg_map(pa, ICH_SMB_BASE, PCI_MAPREG_TYPE_IO, 0, 156 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 157 printf(": can't map i/o space\n"); 158 return; 159 } 160 161 sc->sc_poll = 1; 162 if (conf & ICH_SMB_HOSTC_SMIEN) { 163 /* No PCI IRQ */ 164 printf(": SMI"); 165 } else { 166 /* Install interrupt handler */ 167 if (pci_intr_map(pa, &ih) == 0) { 168 intrstr = pci_intr_string(pa->pa_pc, ih); 169 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, 170 ichiic_intr, sc, sc->sc_dev.dv_xname); 171 if (sc->sc_ih != NULL) { 172 printf(": %s", intrstr); 173 sc->sc_poll = 0; 174 } 175 } 176 if (sc->sc_poll) 177 printf(": polling"); 178 } 179 180 printf("\n"); 181 182 /* Attach I2C bus */ 183 rw_init(&sc->sc_i2c_lock, "iiclk"); 184 sc->sc_i2c_tag.ic_cookie = sc; 185 sc->sc_i2c_tag.ic_acquire_bus = ichiic_i2c_acquire_bus; 186 sc->sc_i2c_tag.ic_release_bus = ichiic_i2c_release_bus; 187 sc->sc_i2c_tag.ic_exec = ichiic_i2c_exec; 188 189 bzero(&iba, sizeof(iba)); 190 iba.iba_name = "iic"; 191 iba.iba_tag = &sc->sc_i2c_tag; 192 config_found(self, &iba, iicbus_print); 193 194 return; 195 } 196 197 int 198 ichiic_i2c_acquire_bus(void *cookie, int flags) 199 { 200 struct ichiic_softc *sc = cookie; 201 202 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 203 return (0); 204 205 return (rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR)); 206 } 207 208 void 209 ichiic_i2c_release_bus(void *cookie, int flags) 210 { 211 struct ichiic_softc *sc = cookie; 212 213 if (cold || sc->sc_poll || (flags & I2C_F_POLL)) 214 return; 215 216 rw_exit(&sc->sc_i2c_lock); 217 } 218 219 int 220 ichiic_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, 221 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags) 222 { 223 struct ichiic_softc *sc = cookie; 224 u_int8_t *b; 225 u_int8_t ctl, st; 226 int retries; 227 228 DPRINTF(("%s: exec: op %d, addr 0x%02x, cmdlen %d, len %d, " 229 "flags 0x%02x\n", sc->sc_dev.dv_xname, op, addr, cmdlen, 230 len, flags)); 231 232 /* Wait for bus to be idle */ 233 for (retries = 100; retries > 0; retries--) { 234 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 235 if (!(st & ICH_SMB_HS_BUSY)) 236 break; 237 DELAY(ICHIIC_DELAY); 238 } 239 DPRINTF(("%s: exec: st 0x%b\n", sc->sc_dev.dv_xname, st, 240 ICH_SMB_HS_BITS)); 241 if (st & ICH_SMB_HS_BUSY) 242 return (1); 243 244 if (cold || sc->sc_poll) 245 flags |= I2C_F_POLL; 246 247 if (!I2C_OP_STOP_P(op) || cmdlen > 1 || len > 2) 248 return (1); 249 250 /* Setup transfer */ 251 sc->sc_i2c_xfer.op = op; 252 sc->sc_i2c_xfer.buf = buf; 253 sc->sc_i2c_xfer.len = len; 254 sc->sc_i2c_xfer.flags = flags; 255 sc->sc_i2c_xfer.error = 0; 256 257 /* Set slave address and transfer direction */ 258 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_TXSLVA, 259 ICH_SMB_TXSLVA_ADDR(addr) | 260 (I2C_OP_READ_P(op) ? ICH_SMB_TXSLVA_READ : 0)); 261 262 b = (void *)cmdbuf; 263 if (cmdlen > 0) 264 /* Set command byte */ 265 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HCMD, b[0]); 266 267 if (I2C_OP_WRITE_P(op)) { 268 /* Write data */ 269 b = buf; 270 if (len > 0) 271 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 272 ICH_SMB_HD0, b[0]); 273 if (len > 1) 274 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 275 ICH_SMB_HD1, b[1]); 276 } 277 278 /* Set SMBus command */ 279 if (len == 0) 280 ctl = ICH_SMB_HC_CMD_BYTE; 281 else if (len == 1) 282 ctl = ICH_SMB_HC_CMD_BDATA; 283 else if (len == 2) 284 ctl = ICH_SMB_HC_CMD_WDATA; 285 else 286 panic("%s: unexpected len %zd", __func__, len); 287 288 if ((flags & I2C_F_POLL) == 0) 289 ctl |= ICH_SMB_HC_INTREN; 290 291 /* Start transaction */ 292 ctl |= ICH_SMB_HC_START; 293 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, ctl); 294 295 if (flags & I2C_F_POLL) { 296 /* Poll for completion */ 297 DELAY(ICHIIC_DELAY); 298 for (retries = 1000; retries > 0; retries--) { 299 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 300 ICH_SMB_HS); 301 if ((st & ICH_SMB_HS_BUSY) == 0) 302 break; 303 DELAY(ICHIIC_DELAY); 304 } 305 if (st & ICH_SMB_HS_BUSY) 306 goto timeout; 307 ichiic_intr(sc); 308 } else { 309 /* Wait for interrupt */ 310 if (tsleep(sc, PRIBIO, "ichiic", ICHIIC_TIMEOUT * hz)) 311 goto timeout; 312 } 313 314 if (sc->sc_i2c_xfer.error) 315 return (1); 316 317 return (0); 318 319 timeout: 320 /* 321 * Transfer timeout. Kill the transaction and clear status bits. 322 */ 323 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HC, 324 ICH_SMB_HC_KILL); 325 DELAY(ICHIIC_DELAY); 326 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 327 if ((st & ICH_SMB_HS_FAILED) == 0) 328 printf("%s: abort failed, status 0x%b\n", 329 sc->sc_dev.dv_xname, st, ICH_SMB_HS_BITS); 330 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 331 return (1); 332 } 333 334 int 335 ichiic_intr(void *arg) 336 { 337 struct ichiic_softc *sc = arg; 338 u_int8_t st; 339 u_int8_t *b; 340 size_t len; 341 342 /* Read status */ 343 st = bus_space_read_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS); 344 345 /* Clear status bits */ 346 bus_space_write_1(sc->sc_iot, sc->sc_ioh, ICH_SMB_HS, st); 347 348 /* XXX Ignore SMBALERT# for now */ 349 if ((st & ICH_SMB_HS_BUSY) != 0 || (st & (ICH_SMB_HS_INTR | 350 ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED | 351 ICH_SMB_HS_BDONE)) == 0) 352 /* Interrupt was not for us */ 353 return (0); 354 355 DPRINTF(("%s: intr st 0x%b\n", sc->sc_dev.dv_xname, st, 356 ICH_SMB_HS_BITS)); 357 358 /* Check for errors */ 359 if (st & (ICH_SMB_HS_DEVERR | ICH_SMB_HS_BUSERR | ICH_SMB_HS_FAILED)) { 360 sc->sc_i2c_xfer.error = 1; 361 goto done; 362 } 363 364 if (st & ICH_SMB_HS_INTR) { 365 if (I2C_OP_WRITE_P(sc->sc_i2c_xfer.op)) 366 goto done; 367 368 /* Read data */ 369 b = sc->sc_i2c_xfer.buf; 370 len = sc->sc_i2c_xfer.len; 371 if (len > 0) 372 b[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 373 ICH_SMB_HD0); 374 if (len > 1) 375 b[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 376 ICH_SMB_HD1); 377 } 378 379 done: 380 if ((sc->sc_i2c_xfer.flags & I2C_F_POLL) == 0) 381 wakeup(sc); 382 return (1); 383 } 384