1 /* $OpenBSD: gdt_pci.c,v 1.20 2006/02/24 00:04:27 brad Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * This driver would not have written if it was not for the hardware donations 29 * from both ICP-Vortex and �ko.neT. I want to thank them for their support. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/queue.h> 38 39 #include <machine/bus.h> 40 #include <machine/endian.h> 41 #include <machine/intr.h> 42 43 #include <scsi/scsi_all.h> 44 #include <scsi/scsiconf.h> 45 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <dev/ic/gdtreg.h> 51 #include <dev/ic/gdtvar.h> 52 53 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */ 54 #define GDT_PCI_PRODUCT_FC 0x200 55 56 #define GDT_DEVICE_ID_MIN 0x100 57 #define GDT_DEVICE_ID_MAX 0x2ff 58 #define GDT_DEVICE_ID_NEWRX 0x300 59 #define GDT_DEVICE_ID_NEWRX2 0x301 60 61 /* Mapping registers for various areas */ 62 #define GDT_PCI_DPMEM 0x10 63 #define GDT_PCINEW_IOMEM 0x10 64 #define GDT_PCINEW_IO 0x14 65 #define GDT_PCINEW_DPMEM 0x18 66 67 /* PCI SRAM structure */ 68 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */ 69 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */ 70 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */ 71 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */ 72 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */ 73 #define GDT_SRAM_SZ 0x40 74 75 /* DPRAM PCI controllers */ 76 #define GDT_DPR_IF 0x00 /* interface area */ 77 #define GDT_6SR (0xff0 - GDT_SRAM_SZ) 78 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */ 79 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */ 80 #define GDT_EVENT 0xff8 /* u_int8_t, release event */ 81 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */ 82 #define GDT_DPRAM_SZ 0x1000 83 84 /* PLX register structure (new PCI controllers) */ 85 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */ 86 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */ 87 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */ 88 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */ 89 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */ 90 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */ 91 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */ 92 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */ 93 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */ 94 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */ 95 #define GDT_PLX_SZ 0x80 96 97 /* DPRAM new PCI controllers */ 98 #define GDT_IC 0x00 /* interface */ 99 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ) 100 /* SRAM structure */ 101 #define GDT_PCINEW_SZ 0x4000 102 103 /* i960 register structure (PCI MPR controllers) */ 104 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */ 105 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */ 106 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */ 107 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */ 108 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */ 109 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */ 110 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */ 111 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */ 112 #define GDT_I960_SZ 0x1000 113 114 /* DPRAM PCI MPR controllers */ 115 #define GDT_I960R 0x00 /* 4KB i960 registers */ 116 #define GDT_MPR_IC GDT_I960_SZ 117 /* interface area */ 118 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ) 119 /* SRAM structure */ 120 #define GDT_MPR_SZ 0x4000 121 122 int gdt_pci_probe(struct device *, void *, void *); 123 void gdt_pci_attach(struct device *, struct device *, void *); 124 void gdt_pci_enable_intr(struct gdt_softc *); 125 126 void gdt_pci_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 127 u_int8_t gdt_pci_get_status(struct gdt_softc *); 128 void gdt_pci_intr(struct gdt_softc *, struct gdt_intr_ctx *); 129 void gdt_pci_release_event(struct gdt_softc *, struct gdt_ccb *); 130 void gdt_pci_set_sema0(struct gdt_softc *); 131 int gdt_pci_test_busy(struct gdt_softc *); 132 133 void gdt_pcinew_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 134 u_int8_t gdt_pcinew_get_status(struct gdt_softc *); 135 void gdt_pcinew_intr(struct gdt_softc *, struct gdt_intr_ctx *); 136 void gdt_pcinew_release_event(struct gdt_softc *, struct gdt_ccb *); 137 void gdt_pcinew_set_sema0(struct gdt_softc *); 138 int gdt_pcinew_test_busy(struct gdt_softc *); 139 140 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *); 141 u_int8_t gdt_mpr_get_status(struct gdt_softc *); 142 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *); 143 void gdt_mpr_release_event(struct gdt_softc *, struct gdt_ccb *); 144 void gdt_mpr_set_sema0(struct gdt_softc *); 145 int gdt_mpr_test_busy(struct gdt_softc *); 146 147 struct cfattach gdt_pci_ca = { 148 sizeof (struct gdt_softc), gdt_pci_probe, gdt_pci_attach 149 }; 150 151 int 152 gdt_pci_probe(parent, match, aux) 153 struct device *parent; 154 void *match, *aux; 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX && 159 ((PCI_PRODUCT(pa->pa_id) >= GDT_DEVICE_ID_MIN && 160 PCI_PRODUCT(pa->pa_id) <= GDT_DEVICE_ID_MAX) || 161 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX || 162 PCI_PRODUCT(pa->pa_id) == GDT_DEVICE_ID_NEWRX2)) 163 return (1); 164 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL && 165 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID1 || 166 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_INTEL_GDT_RAID2)) 167 return (1); 168 return (0); 169 } 170 171 void 172 gdt_pci_attach(parent, self, aux) 173 struct device *parent, *self; 174 void *aux; 175 { 176 struct pci_attach_args *pa = aux; 177 struct gdt_softc *gdt = (void *)self; 178 bus_space_tag_t dpmemt, iomemt, iot; 179 bus_space_handle_t dpmemh, iomemh, ioh; 180 bus_addr_t dpmembase, iomembase, iobase; 181 bus_size_t dpmemsize, iomemsize, iosize; 182 u_int16_t prod; 183 u_int32_t status = 0; 184 #define DPMEM_MAPPED 1 185 #define IOMEM_MAPPED 2 186 #define IO_MAPPED 4 187 #define INTR_ESTABLISHED 8 188 int retries; 189 u_int8_t protocol; 190 pci_intr_handle_t ih; 191 const char *intrstr; 192 193 printf(": "); 194 195 gdt->sc_class = 0; 196 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VORTEX) { 197 prod = PCI_PRODUCT(pa->pa_id); 198 switch (prod) { 199 case PCI_PRODUCT_VORTEX_GDT_60x0: 200 case PCI_PRODUCT_VORTEX_GDT_6000B: 201 gdt->sc_class = GDT_PCI; 202 break; 203 204 case PCI_PRODUCT_VORTEX_GDT_6x10: 205 case PCI_PRODUCT_VORTEX_GDT_6x20: 206 case PCI_PRODUCT_VORTEX_GDT_6530: 207 case PCI_PRODUCT_VORTEX_GDT_6550: 208 case PCI_PRODUCT_VORTEX_GDT_6x17: 209 case PCI_PRODUCT_VORTEX_GDT_6x27: 210 case PCI_PRODUCT_VORTEX_GDT_6537: 211 case PCI_PRODUCT_VORTEX_GDT_6557: 212 case PCI_PRODUCT_VORTEX_GDT_6x15: 213 case PCI_PRODUCT_VORTEX_GDT_6x25: 214 case PCI_PRODUCT_VORTEX_GDT_6535: 215 case PCI_PRODUCT_VORTEX_GDT_6555: 216 gdt->sc_class = GDT_PCINEW; 217 break; 218 219 case PCI_PRODUCT_VORTEX_GDT_6x17RP: 220 case PCI_PRODUCT_VORTEX_GDT_6x27RP: 221 case PCI_PRODUCT_VORTEX_GDT_6537RP: 222 case PCI_PRODUCT_VORTEX_GDT_6557RP: 223 case PCI_PRODUCT_VORTEX_GDT_6x11RP: 224 case PCI_PRODUCT_VORTEX_GDT_6x21RP: 225 case PCI_PRODUCT_VORTEX_GDT_6x17RD: 226 case PCI_PRODUCT_VORTEX_GDT_6x27RD: 227 case PCI_PRODUCT_VORTEX_GDT_6537RD: 228 case PCI_PRODUCT_VORTEX_GDT_6557RD: 229 case PCI_PRODUCT_VORTEX_GDT_6x11RD: 230 case PCI_PRODUCT_VORTEX_GDT_6x21RD: 231 case PCI_PRODUCT_VORTEX_GDT_6x18RD: 232 case PCI_PRODUCT_VORTEX_GDT_6x28RD: 233 case PCI_PRODUCT_VORTEX_GDT_6x38RD: 234 case PCI_PRODUCT_VORTEX_GDT_6x58RD: 235 case PCI_PRODUCT_VORTEX_GDT_6518RS: 236 case PCI_PRODUCT_VORTEX_GDT_7x18RN: 237 case PCI_PRODUCT_VORTEX_GDT_7x28RN: 238 case PCI_PRODUCT_VORTEX_GDT_7x38RN: 239 case PCI_PRODUCT_VORTEX_GDT_7x58RN: 240 case PCI_PRODUCT_VORTEX_GDT_6x19RD: 241 case PCI_PRODUCT_VORTEX_GDT_6x29RD: 242 case PCI_PRODUCT_VORTEX_GDT_7x19RN: 243 case PCI_PRODUCT_VORTEX_GDT_7x29RN: 244 case PCI_PRODUCT_VORTEX_GDT_7x43RN: 245 gdt->sc_class = GDT_MPR; 246 } 247 248 /* If we don't recognize it, determine class heuristically. */ 249 if (gdt->sc_class == 0) 250 gdt->sc_class = prod < 0x100 ? GDT_PCINEW : GDT_MPR; 251 252 if (prod >= GDT_PCI_PRODUCT_FC) 253 gdt->sc_class |= GDT_FC; 254 255 } else if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 256 gdt->sc_class = GDT_MPR; 257 } 258 259 if (pci_mapreg_map(pa, 260 GDT_CLASS(gdt) == GDT_PCINEW ? GDT_PCINEW_DPMEM : GDT_PCI_DPMEM, 261 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &dpmemt, 262 &dpmemh, &dpmembase, &dpmemsize, 0)) { 263 if (pci_mapreg_map(pa, 264 GDT_CLASS(gdt) == GDT_PCINEW ? GDT_PCINEW_DPMEM : 265 GDT_PCI_DPMEM, 266 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT_1M, 0, 267 &dpmemt,&dpmemh, &dpmembase, &dpmemsize, 0)) { 268 printf("cannot map DPMEM\n"); 269 goto bail_out; 270 } 271 } 272 status |= DPMEM_MAPPED; 273 gdt->sc_dpmemt = dpmemt; 274 gdt->sc_dpmemh = dpmemh; 275 gdt->sc_dpmembase = dpmembase; 276 gdt->sc_dmat = pa->pa_dmat; 277 278 /* 279 * The GDT_PCINEW series also has two other regions to map. 280 */ 281 if (GDT_CLASS(gdt) == GDT_PCINEW) { 282 if (pci_mapreg_map(pa, GDT_PCINEW_IOMEM, PCI_MAPREG_TYPE_MEM, 283 0, &iomemt, &iomemh, &iomembase, &iomemsize, 0)) { 284 printf("cannot map memory mapped I/O ports\n"); 285 goto bail_out; 286 } 287 status |= IOMEM_MAPPED; 288 289 if (pci_mapreg_map(pa, GDT_PCINEW_IO, PCI_MAPREG_TYPE_IO, 0, 290 &iot, &ioh, &iobase, &iosize, 0)) { 291 printf("cannot map I/O ports\n"); 292 goto bail_out; 293 } 294 status |= IO_MAPPED; 295 gdt->sc_iot = iot; 296 gdt->sc_ioh = ioh; 297 gdt->sc_iobase = iobase; 298 } 299 300 switch (GDT_CLASS(gdt)) { 301 case GDT_PCI: 302 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 303 GDT_DPR_IF_SZ >> 2); 304 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 305 printf("cannot write to DPMEM\n"); 306 goto bail_out; 307 } 308 309 #if 0 310 /* disable board interrupts, deinit services */ 311 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 312 gdth_writeb(0x00, &dp6_ptr->io.irqen); 313 gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status); 314 gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index); 315 316 gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]); 317 gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx); 318 gdth_writeb(0, &dp6_ptr->io.event); 319 retries = INIT_RETRIES; 320 gdth_delay(20); 321 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) { 322 if (--retries == 0) { 323 printk("initialization error (DEINIT failed)\n"); 324 gdth_munmap(ha->brd); 325 return 0; 326 } 327 gdth_delay(1); 328 } 329 prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]); 330 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 331 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 332 if (prot_ver != PROTOCOL_VERSION) { 333 printk("illegal protocol version\n"); 334 gdth_munmap(ha->brd); 335 return 0; 336 } 337 338 ha->type = GDT_PCI; 339 ha->ic_all_size = sizeof(dp6_ptr->u); 340 341 /* special command to controller BIOS */ 342 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]); 343 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]); 344 gdth_writel(0x01, &dp6_ptr->u.ic.S_Info[2]); 345 gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]); 346 gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx); 347 gdth_writeb(0, &dp6_ptr->io.event); 348 retries = INIT_RETRIES; 349 gdth_delay(20); 350 while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) { 351 if (--retries == 0) { 352 printk("initialization error\n"); 353 gdth_munmap(ha->brd); 354 return 0; 355 } 356 gdth_delay(1); 357 } 358 gdth_writeb(0, &dp6_ptr->u.ic.S_Status); 359 gdth_writeb(0xff, &dp6_ptr->io.irqdel); 360 #endif 361 362 gdt->sc_ic_all_size = GDT_DPRAM_SZ; 363 364 gdt->sc_copy_cmd = gdt_pci_copy_cmd; 365 gdt->sc_get_status = gdt_pci_get_status; 366 gdt->sc_intr = gdt_pci_intr; 367 gdt->sc_release_event = gdt_pci_release_event; 368 gdt->sc_set_sema0 = gdt_pci_set_sema0; 369 gdt->sc_test_busy = gdt_pci_test_busy; 370 371 break; 372 373 case GDT_PCINEW: 374 bus_space_set_region_4(dpmemt, dpmemh, 0, 0, 375 GDT_DPR_IF_SZ >> 2); 376 if (bus_space_read_1(dpmemt, dpmemh, 0) != 0) { 377 printf("cannot write to DPMEM\n"); 378 goto bail_out; 379 } 380 381 #if 0 382 /* disable board interrupts, deinit services */ 383 outb(0x00,PTR2USHORT(&ha->plx->control1)); 384 outb(0xff,PTR2USHORT(&ha->plx->edoor_reg)); 385 386 gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status); 387 gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index); 388 389 gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]); 390 gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx); 391 392 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 393 394 retries = INIT_RETRIES; 395 gdth_delay(20); 396 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) { 397 if (--retries == 0) { 398 printk("initialization error (DEINIT failed)\n"); 399 gdth_munmap(ha->brd); 400 return 0; 401 } 402 gdth_delay(1); 403 } 404 prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]); 405 gdth_writeb(0, &dp6c_ptr->u.ic.Status); 406 if (prot_ver != PROTOCOL_VERSION) { 407 printk("illegal protocol version\n"); 408 gdth_munmap(ha->brd); 409 return 0; 410 } 411 412 ha->type = GDT_PCINEW; 413 ha->ic_all_size = sizeof(dp6c_ptr->u); 414 415 /* special command to controller BIOS */ 416 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]); 417 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]); 418 gdth_writel(0x01, &dp6c_ptr->u.ic.S_Info[2]); 419 gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]); 420 gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx); 421 422 outb(1,PTR2USHORT(&ha->plx->ldoor_reg)); 423 424 retries = INIT_RETRIES; 425 gdth_delay(20); 426 while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) { 427 if (--retries == 0) { 428 printk("initialization error\n"); 429 gdth_munmap(ha->brd); 430 return 0; 431 } 432 gdth_delay(1); 433 } 434 gdth_writeb(0, &dp6c_ptr->u.ic.S_Status); 435 #endif 436 437 gdt->sc_ic_all_size = GDT_PCINEW_SZ; 438 439 gdt->sc_copy_cmd = gdt_pcinew_copy_cmd; 440 gdt->sc_get_status = gdt_pcinew_get_status; 441 gdt->sc_intr = gdt_pcinew_intr; 442 gdt->sc_release_event = gdt_pcinew_release_event; 443 gdt->sc_set_sema0 = gdt_pcinew_set_sema0; 444 gdt->sc_test_busy = gdt_pcinew_test_busy; 445 446 break; 447 448 case GDT_MPR: 449 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC, GDT_MPR_MAGIC); 450 if (bus_space_read_4(dpmemt, dpmemh, GDT_MPR_IC) != 451 GDT_MPR_MAGIC) { 452 printf("cannot access DPMEM at 0x%x (shadowed?)\n", 453 dpmembase); 454 goto bail_out; 455 } 456 457 /* 458 * XXX Here the Linux driver has a weird remapping logic I 459 * don't understand. My controller does not need it, and I 460 * cannot see what purpose it serves, therefore I did not 461 * do anything similar. 462 */ 463 464 bus_space_set_region_4(dpmemt, dpmemh, GDT_I960_SZ, 0, 465 GDT_DPR_IF_SZ >> 2); 466 467 /* Disable everything */ 468 bus_space_write_1(dpmemt, dpmemh, GDT_EDOOR_EN, 469 bus_space_read_1(dpmemt, dpmemh, GDT_EDOOR_EN) | 4); 470 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_EDOOR, 0xff); 471 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 472 0); 473 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_CMD_INDEX, 474 0); 475 476 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 477 dpmembase); 478 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 479 0xff); 480 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 481 482 DELAY(20); 483 retries = GDT_RETRIES; 484 while (bus_space_read_1(dpmemt, dpmemh, 485 GDT_MPR_IC + GDT_S_STATUS) != 0xff) { 486 if (--retries == 0) { 487 printf("DEINIT failed (status 0x%x)\n", 488 bus_space_read_1(dpmemt, dpmemh, 489 GDT_MPR_IC + GDT_S_STATUS)); 490 goto bail_out; 491 } 492 DELAY(1); 493 } 494 495 protocol = (u_int8_t)bus_space_read_4(dpmemt, dpmemh, 496 GDT_MPR_IC + GDT_S_INFO); 497 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 498 0); 499 if (protocol != GDT_PROTOCOL_VERSION) { 500 printf("unsupported protocol %d\n", protocol); 501 goto bail_out; 502 } 503 504 /* special commnd to controller BIOS */ 505 bus_space_write_4(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_INFO, 0); 506 bus_space_write_4(dpmemt, dpmemh, 507 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), 0); 508 bus_space_write_4(dpmemt, dpmemh, 509 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t), 1); 510 bus_space_write_4(dpmemt, dpmemh, 511 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t), 0); 512 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX, 513 0xfe); 514 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_LDOOR, 1); 515 516 DELAY(20); 517 retries = GDT_RETRIES; 518 while (bus_space_read_1(dpmemt, dpmemh, 519 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) { 520 if (--retries == 0) { 521 printf("initialization error\n"); 522 goto bail_out; 523 } 524 DELAY(1); 525 } 526 527 bus_space_write_1(dpmemt, dpmemh, GDT_MPR_IC + GDT_S_STATUS, 528 0); 529 530 gdt->sc_ic_all_size = GDT_MPR_SZ; 531 532 gdt->sc_copy_cmd = gdt_mpr_copy_cmd; 533 gdt->sc_get_status = gdt_mpr_get_status; 534 gdt->sc_intr = gdt_mpr_intr; 535 gdt->sc_release_event = gdt_mpr_release_event; 536 gdt->sc_set_sema0 = gdt_mpr_set_sema0; 537 gdt->sc_test_busy = gdt_mpr_test_busy; 538 } 539 540 if (pci_intr_map(pa, &ih)) { 541 printf("couldn't map interrupt\n"); 542 goto bail_out; 543 } 544 intrstr = pci_intr_string(pa->pa_pc, ih); 545 gdt->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, gdt_intr, gdt, 546 gdt->sc_dev.dv_xname); 547 if (gdt->sc_ih == NULL) { 548 printf("couldn't establish interrupt"); 549 if (intrstr != NULL) 550 printf(" at %s", intrstr); 551 printf("\n"); 552 goto bail_out; 553 } 554 status |= INTR_ESTABLISHED; 555 if (intrstr != NULL) 556 printf("%s ", intrstr); 557 558 if (gdt_attach(gdt)) 559 goto bail_out; 560 561 gdt_pci_enable_intr(gdt); 562 563 return; 564 565 bail_out: 566 if (status & DPMEM_MAPPED) 567 bus_space_unmap(dpmemt, dpmemh, dpmemsize); 568 if (status & IOMEM_MAPPED) 569 bus_space_unmap(iomemt, iomemh, iomembase); 570 if (status & IO_MAPPED) 571 bus_space_unmap(iot, ioh, iosize); 572 if (status & INTR_ESTABLISHED) 573 pci_intr_disestablish(pa->pa_pc, gdt->sc_ih); 574 return; 575 } 576 577 /* Enable interrupts */ 578 void 579 gdt_pci_enable_intr(gdt) 580 struct gdt_softc *gdt; 581 { 582 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt)); 583 584 switch(GDT_CLASS(gdt)) { 585 case GDT_PCI: 586 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_IRQDEL, 587 1); 588 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 589 GDT_CMD_INDEX, 0); 590 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_IRQEN, 591 1); 592 break; 593 594 case GDT_PCINEW: 595 bus_space_write_1(gdt->sc_iot, gdt->sc_ioh, GDT_EDOOR_REG, 596 0xff); 597 bus_space_write_1(gdt->sc_iot, gdt->sc_ioh, GDT_CONTROL1, 3); 598 break; 599 600 case GDT_MPR: 601 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 602 GDT_MPR_EDOOR, 0xff); 603 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN, 604 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 605 GDT_EDOOR_EN) & ~4); 606 break; 607 } 608 } 609 610 /* 611 * "old" PCI controller-specific functions 612 */ 613 614 void 615 gdt_pci_copy_cmd(gdt, ccb) 616 struct gdt_softc *gdt; 617 struct gdt_ccb *ccb; 618 { 619 /* XXX Not yet implemented */ 620 } 621 622 u_int8_t 623 gdt_pci_get_status(gdt) 624 struct gdt_softc *gdt; 625 { 626 /* XXX Not yet implemented */ 627 return (0); 628 } 629 630 void 631 gdt_pci_intr(gdt, ctx) 632 struct gdt_softc *gdt; 633 struct gdt_intr_ctx *ctx; 634 { 635 /* XXX Not yet implemented */ 636 } 637 638 void 639 gdt_pci_release_event(gdt, ccb) 640 struct gdt_softc *gdt; 641 struct gdt_ccb *ccb; 642 { 643 /* XXX Not yet implemented */ 644 } 645 646 void 647 gdt_pci_set_sema0(gdt) 648 struct gdt_softc *gdt; 649 { 650 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_SEMA0, 1); 651 } 652 653 int 654 gdt_pci_test_busy(gdt) 655 struct gdt_softc *gdt; 656 { 657 /* XXX Not yet implemented */ 658 return (0); 659 } 660 661 /* 662 * "new" PCI controller-specific functions 663 */ 664 665 void 666 gdt_pcinew_copy_cmd(gdt, ccb) 667 struct gdt_softc *gdt; 668 struct gdt_ccb *ccb; 669 { 670 /* XXX Not yet implemented */ 671 } 672 673 u_int8_t 674 gdt_pcinew_get_status(gdt) 675 struct gdt_softc *gdt; 676 { 677 /* XXX Not yet implemented */ 678 return (0); 679 } 680 681 void 682 gdt_pcinew_intr(gdt, ctx) 683 struct gdt_softc *gdt; 684 struct gdt_intr_ctx *ctx; 685 { 686 /* XXX Not yet implemented */ 687 } 688 689 void 690 gdt_pcinew_release_event(gdt, ccb) 691 struct gdt_softc *gdt; 692 struct gdt_ccb *ccb; 693 { 694 /* XXX Not yet implemented */ 695 } 696 697 void 698 gdt_pcinew_set_sema0(gdt) 699 struct gdt_softc *gdt; 700 { 701 bus_space_write_1(gdt->sc_iot, gdt->sc_ioh, GDT_SEMA0_REG, 1); 702 } 703 704 int 705 gdt_pcinew_test_busy(gdt) 706 struct gdt_softc *gdt; 707 { 708 /* XXX Not yet implemented */ 709 return (0); 710 } 711 712 /* 713 * MPR PCI controller-specific functions 714 */ 715 716 void 717 gdt_mpr_copy_cmd(gdt, ccb) 718 struct gdt_softc *gdt; 719 struct gdt_ccb *ccb; 720 { 721 u_int16_t cp_count = roundup(gdt->sc_cmd_len, sizeof (u_int32_t)); 722 u_int16_t dp_offset = gdt->sc_cmd_off; 723 u_int16_t cmd_no = gdt->sc_cmd_cnt++; 724 725 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt)); 726 727 gdt->sc_cmd_off += cp_count; 728 729 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 730 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET, 731 GDT_DPMEM_COMMAND_OFFSET + dp_offset); 732 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh, 733 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID, 734 ccb->gc_service); 735 bus_space_write_raw_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 736 GDT_MPR_IC + GDT_DPR_CMD + dp_offset, gdt->sc_cmd, cp_count); 737 } 738 739 u_int8_t 740 gdt_mpr_get_status(gdt) 741 struct gdt_softc *gdt; 742 { 743 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt)); 744 745 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR); 746 } 747 748 void 749 gdt_mpr_intr(gdt, ctx) 750 struct gdt_softc *gdt; 751 struct gdt_intr_ctx *ctx; 752 { 753 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt)); 754 755 if (ctx->istatus & 0x80) { /* error flag */ 756 ctx->istatus &= ~0x80; 757 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt, 758 gdt->sc_dpmemh, GDT_MPR_STATUS); 759 if (ctx->istatus == GDT_ASYNCINDEX) { 760 ctx->service = bus_space_read_2(gdt->sc_dpmemt, 761 gdt->sc_dpmemh, GDT_MPR_SERVICE); 762 ctx->info2 = bus_space_read_4(gdt->sc_dpmemt, 763 gdt->sc_dpmemh, GDT_MPR_INFO + sizeof (u_int32_t)); 764 } 765 } else /* no error */ 766 ctx->cmd_status = GDT_S_OK; 767 768 ctx->info = 769 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO); 770 771 if (gdt_polling) /* init. -> more info */ 772 ctx->info2 = bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, 773 GDT_MPR_INFO + sizeof (u_int32_t)); 774 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff); 775 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0); 776 } 777 778 void 779 gdt_mpr_release_event(gdt, ccb) 780 struct gdt_softc *gdt; 781 struct gdt_ccb *ccb; 782 { 783 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt)); 784 785 if (gdt_dec16(gdt->sc_cmd + GDT_CMD_OPCODE) == GDT_INIT) 786 ccb->gc_service |= 0x80; 787 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1); 788 } 789 790 void 791 gdt_mpr_set_sema0(gdt) 792 struct gdt_softc *gdt; 793 { 794 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt)); 795 796 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1); 797 } 798 799 int 800 gdt_mpr_test_busy(gdt) 801 struct gdt_softc *gdt; 802 { 803 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt)); 804 805 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, 806 GDT_MPR_SEMA0) & 1); 807 } 808