1 /* $OpenBSD: dwiic_pci.c,v 1.15 2020/12/25 21:48:27 jsg Exp $ */ 2 /* 3 * Synopsys DesignWare I2C controller 4 * PCI attachment 5 * 6 * Copyright (c) 2015-2017 joshua stein <jcs@openbsd.org> 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/param.h> 22 #include <sys/systm.h> 23 #include <sys/kernel.h> 24 25 #include <dev/pci/pcidevs.h> 26 #include <dev/pci/pcireg.h> 27 #include <dev/pci/pcivar.h> 28 29 #include <dev/ic/dwiicvar.h> 30 31 /* 13.3: I2C Additional Registers Summary */ 32 #define LPSS_RESETS 0x204 33 #define LPSS_RESETS_I2C (1 << 0) | (1 << 1) 34 #define LPSS_RESETS_IDMA (1 << 2) 35 #define LPSS_ACTIVELTR 0x210 36 #define LPSS_IDLELTR 0x214 37 #define LPSS_CAPS 0x2fc 38 #define LPSS_CAPS_NO_IDMA (1 << 8) 39 #define LPSS_CAPS_TYPE_SHIFT 4 40 #define LPSS_CAPS_TYPE_MASK (0xf << LPSS_CAPS_TYPE_SHIFT) 41 42 int dwiic_pci_match(struct device *, void *, void *); 43 void dwiic_pci_attach(struct device *, struct device *, void *); 44 int dwiic_pci_activate(struct device *, int); 45 void dwiic_pci_bus_scan(struct device *, 46 struct i2cbus_attach_args *, void *); 47 48 #include "acpi.h" 49 #if NACPI > 0 50 struct aml_node *acpi_pci_match(struct device *dev, struct pci_attach_args *pa); 51 #endif 52 53 struct cfattach dwiic_pci_ca = { 54 sizeof(struct dwiic_softc), 55 dwiic_pci_match, 56 dwiic_pci_attach, 57 NULL, 58 dwiic_pci_activate, 59 }; 60 61 const struct pci_matchid dwiic_pci_ids[] = { 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C0 }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C1 }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C2 }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C3 }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_1 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_2 }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_3 }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_4 }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_5 }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_6 }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_1 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_2 }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_3 }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_4 }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_1 }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_2 }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_3 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_4 }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_1 }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_2 }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_3 }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_4 }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_5 }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_6 }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_1 }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_3 }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_4 }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_1 }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_2 }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_3 }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_4 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_5 }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_6 }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_1 }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_2 }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_3 }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_4 }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_1 }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_2 }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_3 }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_4 }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_5 }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_6 }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_1 }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_2 }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_3 }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_4 }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_5 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_6 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_1 }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_2 }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_3 }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_4 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_5 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_6 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_7 }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_8 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_1 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_2 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_3 }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_4 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_5 }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_6 }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_7 }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_8 }, 128 }; 129 130 int 131 dwiic_pci_match(struct device *parent, void *match, void *aux) 132 { 133 return (pci_matchbyid(aux, dwiic_pci_ids, nitems(dwiic_pci_ids))); 134 } 135 136 void 137 dwiic_pci_attach(struct device *parent, struct device *self, void *aux) 138 { 139 struct dwiic_softc *sc = (struct dwiic_softc *)self; 140 struct pci_attach_args *pa = aux; 141 #if NACPI > 0 142 struct aml_node *node; 143 #endif 144 bus_size_t iosize; 145 pci_intr_handle_t ih; 146 const char *intrstr = NULL; 147 uint8_t type; 148 149 memcpy(&sc->sc_paa, pa, sizeof(sc->sc_paa)); 150 151 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 152 153 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_MEM_TYPE_64BIT, 0, 154 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 155 printf(": can't map mem space\n"); 156 return; 157 } 158 159 sc->sc_caps = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPSS_CAPS); 160 type = sc->sc_caps & LPSS_CAPS_TYPE_MASK; 161 type >>= LPSS_CAPS_TYPE_SHIFT; 162 if (type != 0) { 163 printf(": type %d not supported\n", type); 164 return; 165 } 166 167 /* un-reset - page 958 */ 168 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPSS_RESETS, 169 (LPSS_RESETS_I2C | LPSS_RESETS_IDMA)); 170 171 #if NACPI > 0 172 /* fetch timing parameters from ACPI, if possible */ 173 node = acpi_pci_match(self, &sc->sc_paa); 174 if (node != NULL) { 175 sc->sc_devnode = node; 176 177 dwiic_acpi_get_params(sc, "SSCN", &sc->ss_hcnt, &sc->ss_lcnt, 178 NULL); 179 dwiic_acpi_get_params(sc, "FMCN", &sc->fs_hcnt, &sc->fs_lcnt, 180 &sc->sda_hold_time); 181 } 182 #endif 183 184 if (dwiic_init(sc)) { 185 printf(": failed initializing\n"); 186 return; 187 } 188 189 /* leave the controller disabled */ 190 dwiic_write(sc, DW_IC_INTR_MASK, 0); 191 dwiic_enable(sc, 0); 192 dwiic_read(sc, DW_IC_CLR_INTR); 193 194 /* install interrupt handler */ 195 sc->sc_poll = 1; 196 if (pci_intr_map(&sc->sc_paa, &ih) == 0) { 197 intrstr = pci_intr_string(sc->sc_paa.pa_pc, ih); 198 sc->sc_ih = pci_intr_establish(sc->sc_paa.pa_pc, ih, IPL_BIO, 199 dwiic_intr, sc, sc->sc_dev.dv_xname); 200 if (sc->sc_ih != NULL) { 201 printf(": %s", intrstr); 202 sc->sc_poll = 0; 203 } 204 } 205 if (sc->sc_poll) 206 printf(": polling"); 207 208 printf("\n"); 209 210 rw_init(&sc->sc_i2c_lock, "iiclk"); 211 212 /* setup and attach iic bus */ 213 sc->sc_i2c_tag.ic_cookie = sc; 214 sc->sc_i2c_tag.ic_acquire_bus = dwiic_i2c_acquire_bus; 215 sc->sc_i2c_tag.ic_release_bus = dwiic_i2c_release_bus; 216 sc->sc_i2c_tag.ic_exec = dwiic_i2c_exec; 217 sc->sc_i2c_tag.ic_intr_establish = dwiic_i2c_intr_establish; 218 sc->sc_i2c_tag.ic_intr_string = dwiic_i2c_intr_string; 219 220 bzero(&sc->sc_iba, sizeof(sc->sc_iba)); 221 sc->sc_iba.iba_name = "iic"; 222 sc->sc_iba.iba_tag = &sc->sc_i2c_tag; 223 sc->sc_iba.iba_bus_scan = dwiic_pci_bus_scan; 224 sc->sc_iba.iba_bus_scan_arg = sc; 225 226 config_found((struct device *)sc, &sc->sc_iba, iicbus_print); 227 228 return; 229 } 230 231 int 232 dwiic_pci_activate(struct device *self, int act) 233 { 234 struct dwiic_softc *sc = (struct dwiic_softc *)self; 235 236 switch (act) { 237 case DVACT_WAKEUP: 238 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPSS_RESETS, 239 (LPSS_RESETS_I2C | LPSS_RESETS_IDMA)); 240 break; 241 } 242 243 dwiic_activate(self, act); 244 245 return 0; 246 } 247 248 void 249 dwiic_pci_bus_scan(struct device *iic, struct i2cbus_attach_args *iba, 250 void *aux) 251 { 252 struct dwiic_softc *sc = (struct dwiic_softc *)aux; 253 254 sc->sc_iic = iic; 255 256 #if NACPI > 0 257 if (sc->sc_devnode != NULL) 258 aml_find_node(sc->sc_devnode, "_HID", dwiic_acpi_found_hid, sc); 259 #endif 260 } 261