1 /* $OpenBSD: dwiic_pci.c,v 1.22 2022/10/24 05:57:58 jsg Exp $ */ 2 /* 3 * Synopsys DesignWare I2C controller 4 * PCI attachment 5 * 6 * Copyright (c) 2015-2017 joshua stein <jcs@openbsd.org> 7 * 8 * Permission to use, copy, modify, and/or distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #include <sys/param.h> 22 #include <sys/systm.h> 23 #include <sys/kernel.h> 24 25 #include <dev/pci/pcidevs.h> 26 #include <dev/pci/pcireg.h> 27 #include <dev/pci/pcivar.h> 28 29 #include <dev/ic/dwiicvar.h> 30 31 /* 13.3: I2C Additional Registers Summary */ 32 #define LPSS_RESETS 0x204 33 #define LPSS_RESETS_I2C (1 << 0) | (1 << 1) 34 #define LPSS_RESETS_IDMA (1 << 2) 35 #define LPSS_ACTIVELTR 0x210 36 #define LPSS_IDLELTR 0x214 37 #define LPSS_CAPS 0x2fc 38 #define LPSS_CAPS_NO_IDMA (1 << 8) 39 #define LPSS_CAPS_TYPE_SHIFT 4 40 #define LPSS_CAPS_TYPE_MASK (0xf << LPSS_CAPS_TYPE_SHIFT) 41 42 int dwiic_pci_match(struct device *, void *, void *); 43 void dwiic_pci_attach(struct device *, struct device *, void *); 44 int dwiic_pci_activate(struct device *, int); 45 void dwiic_pci_bus_scan(struct device *, 46 struct i2cbus_attach_args *, void *); 47 48 #include "acpi.h" 49 #if NACPI > 0 50 struct aml_node *acpi_pci_match(struct device *dev, struct pci_attach_args *pa); 51 #endif 52 53 const struct cfattach dwiic_pci_ca = { 54 sizeof(struct dwiic_softc), 55 dwiic_pci_match, 56 dwiic_pci_attach, 57 NULL, 58 dwiic_pci_activate, 59 }; 60 61 const struct pci_matchid dwiic_pci_ids[] = { 62 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C0 }, 63 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C1 }, 64 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C2 }, 65 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_I2C3 }, 66 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_1 }, 67 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_2 }, 68 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_3 }, 69 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_4 }, 70 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_5 }, 71 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_100SERIES_LP_I2C_6 }, 72 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_1 }, 73 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_2 }, 74 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_3 }, 75 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_200SERIES_I2C_4 }, 76 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_1 }, 77 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_2 }, 78 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_3 }, 79 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_I2C_4 }, 80 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_1 }, 81 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_2 }, 82 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_3 }, 83 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_4 }, 84 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_5 }, 85 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_300SERIES_U_I2C_6 }, 86 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_1 }, 87 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_2 }, 88 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_3 }, 89 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_I2C_4 }, 90 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_1 }, 91 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_2 }, 92 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_3 }, 93 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_4 }, 94 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_5 }, 95 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_LP_I2C_6 }, 96 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_1 }, 97 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_2 }, 98 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_3 }, 99 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_400SERIES_V_I2C_4 }, 100 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_1 }, 101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_2 }, 102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_3 }, 103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_4 }, 104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_5 }, 105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_495SERIES_LP_I2C_6 }, 106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_0 }, 107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_1 }, 108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_2 }, 109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_3 }, 110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_4 }, 111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_5 }, 112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_I2C_6 }, 113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_1 }, 114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_2 }, 115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_3 }, 116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_4 }, 117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_5 }, 118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_500SERIES_LP_I2C_6 }, 119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_0 }, 120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_1 }, 121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_2 }, 122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_3 }, 123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_4 }, 124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_I2C_5 }, 125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_0 }, 126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_1 }, 127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_2 }, 128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_3 }, 129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_4 }, 130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_5 }, 131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_6 }, 132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_600SERIES_LP_I2C_7 }, 133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_0 }, 134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_1 }, 135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_2 }, 136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_3 }, 137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_4 }, 138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_700SERIES_I2C_5 }, 139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_1 }, 140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_2 }, 141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_3 }, 142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_4 }, 143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_5 }, 144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_6 }, 145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_7 }, 146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_APOLLOLAKE_I2C_8 }, 147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_1 }, 148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_2 }, 149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_3 }, 150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_4 }, 151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_5 }, 152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_6 }, 153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_7 }, 154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_GLK_I2C_8 }, 155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_0 }, 156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_1 }, 157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_2 }, 158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_3 }, 159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_4 }, 160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_JSL_I2C_5 }, 161 }; 162 163 int 164 dwiic_pci_match(struct device *parent, void *match, void *aux) 165 { 166 return (pci_matchbyid(aux, dwiic_pci_ids, nitems(dwiic_pci_ids))); 167 } 168 169 void 170 dwiic_pci_attach(struct device *parent, struct device *self, void *aux) 171 { 172 struct dwiic_softc *sc = (struct dwiic_softc *)self; 173 struct pci_attach_args *pa = aux; 174 #if NACPI > 0 175 struct aml_node *node; 176 #endif 177 bus_size_t iosize; 178 pci_intr_handle_t ih; 179 const char *intrstr = NULL; 180 uint8_t type; 181 182 memcpy(&sc->sc_paa, pa, sizeof(sc->sc_paa)); 183 184 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 185 186 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_MEM_TYPE_64BIT, 0, 187 &sc->sc_iot, &sc->sc_ioh, NULL, &iosize, 0)) { 188 printf(": can't map mem space\n"); 189 return; 190 } 191 192 sc->sc_caps = bus_space_read_4(sc->sc_iot, sc->sc_ioh, LPSS_CAPS); 193 type = sc->sc_caps & LPSS_CAPS_TYPE_MASK; 194 type >>= LPSS_CAPS_TYPE_SHIFT; 195 if (type != 0) { 196 printf(": type %d not supported\n", type); 197 return; 198 } 199 200 /* un-reset - page 958 */ 201 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPSS_RESETS, 202 (LPSS_RESETS_I2C | LPSS_RESETS_IDMA)); 203 204 #if NACPI > 0 205 /* fetch timing parameters from ACPI, if possible */ 206 node = acpi_pci_match(self, &sc->sc_paa); 207 if (node != NULL) { 208 sc->sc_devnode = node; 209 210 dwiic_acpi_get_params(sc, "SSCN", &sc->ss_hcnt, &sc->ss_lcnt, 211 NULL); 212 dwiic_acpi_get_params(sc, "FMCN", &sc->fs_hcnt, &sc->fs_lcnt, 213 &sc->sda_hold_time); 214 } 215 #endif 216 217 if (dwiic_init(sc)) { 218 printf(": failed initializing\n"); 219 return; 220 } 221 222 /* leave the controller disabled */ 223 dwiic_write(sc, DW_IC_INTR_MASK, 0); 224 dwiic_enable(sc, 0); 225 dwiic_read(sc, DW_IC_CLR_INTR); 226 227 /* install interrupt handler */ 228 sc->sc_poll = 1; 229 if (pci_intr_map(&sc->sc_paa, &ih) == 0) { 230 intrstr = pci_intr_string(sc->sc_paa.pa_pc, ih); 231 sc->sc_ih = pci_intr_establish(sc->sc_paa.pa_pc, ih, IPL_BIO, 232 dwiic_intr, sc, sc->sc_dev.dv_xname); 233 if (sc->sc_ih != NULL) { 234 printf(": %s", intrstr); 235 sc->sc_poll = 0; 236 } 237 } 238 if (sc->sc_poll) 239 printf(": polling"); 240 241 printf("\n"); 242 243 rw_init(&sc->sc_i2c_lock, "iiclk"); 244 245 /* setup and attach iic bus */ 246 sc->sc_i2c_tag.ic_cookie = sc; 247 sc->sc_i2c_tag.ic_acquire_bus = dwiic_i2c_acquire_bus; 248 sc->sc_i2c_tag.ic_release_bus = dwiic_i2c_release_bus; 249 sc->sc_i2c_tag.ic_exec = dwiic_i2c_exec; 250 sc->sc_i2c_tag.ic_intr_establish = dwiic_i2c_intr_establish; 251 sc->sc_i2c_tag.ic_intr_string = dwiic_i2c_intr_string; 252 253 bzero(&sc->sc_iba, sizeof(sc->sc_iba)); 254 sc->sc_iba.iba_name = "iic"; 255 sc->sc_iba.iba_tag = &sc->sc_i2c_tag; 256 sc->sc_iba.iba_bus_scan = dwiic_pci_bus_scan; 257 sc->sc_iba.iba_bus_scan_arg = sc; 258 259 config_found((struct device *)sc, &sc->sc_iba, iicbus_print); 260 261 #if NACPI > 0 && !defined(SMALL_KERNEL) 262 if (sc->sc_devnode) { 263 sc->sc_devnode->i2c = &sc->sc_i2c_tag; 264 acpi_register_gsb(acpi_softc, sc->sc_devnode); 265 } 266 #endif 267 } 268 269 int 270 dwiic_pci_activate(struct device *self, int act) 271 { 272 struct dwiic_softc *sc = (struct dwiic_softc *)self; 273 274 switch (act) { 275 case DVACT_WAKEUP: 276 bus_space_write_4(sc->sc_iot, sc->sc_ioh, LPSS_RESETS, 277 (LPSS_RESETS_I2C | LPSS_RESETS_IDMA)); 278 break; 279 } 280 281 dwiic_activate(self, act); 282 283 return 0; 284 } 285 286 void 287 dwiic_pci_bus_scan(struct device *iic, struct i2cbus_attach_args *iba, 288 void *aux) 289 { 290 struct dwiic_softc *sc = (struct dwiic_softc *)aux; 291 292 sc->sc_iic = iic; 293 294 #if NACPI > 0 295 if (sc->sc_devnode != NULL) 296 aml_find_node(sc->sc_devnode, "_HID", dwiic_acpi_found_hid, sc); 297 #endif 298 } 299