1 /* $OpenBSD: si.c,v 1.15 2014/07/12 18:48:52 tedu Exp $ */ 2 /* 3 * Copyright 2011 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Alex Deucher 24 */ 25 #include <dev/pci/drm/drmP.h> 26 #include "radeon.h" 27 #include "radeon_asic.h" 28 #include <dev/pci/drm/radeon_drm.h> 29 #include "sid.h" 30 #include "atom.h" 31 #include "si_blit_shaders.h" 32 33 #define SI_PFP_UCODE_SIZE 2144 34 #define SI_PM4_UCODE_SIZE 2144 35 #define SI_CE_UCODE_SIZE 2144 36 #define SI_RLC_UCODE_SIZE 2048 37 #define SI_MC_UCODE_SIZE 7769 38 39 MODULE_FIRMWARE("radeon/TAHITI_pfp.bin"); 40 MODULE_FIRMWARE("radeon/TAHITI_me.bin"); 41 MODULE_FIRMWARE("radeon/TAHITI_ce.bin"); 42 MODULE_FIRMWARE("radeon/TAHITI_mc.bin"); 43 MODULE_FIRMWARE("radeon/TAHITI_rlc.bin"); 44 MODULE_FIRMWARE("radeon/PITCAIRN_pfp.bin"); 45 MODULE_FIRMWARE("radeon/PITCAIRN_me.bin"); 46 MODULE_FIRMWARE("radeon/PITCAIRN_ce.bin"); 47 MODULE_FIRMWARE("radeon/PITCAIRN_mc.bin"); 48 MODULE_FIRMWARE("radeon/PITCAIRN_rlc.bin"); 49 MODULE_FIRMWARE("radeon/VERDE_pfp.bin"); 50 MODULE_FIRMWARE("radeon/VERDE_me.bin"); 51 MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 52 MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 53 MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 54 55 extern int r600_ih_ring_alloc(struct radeon_device *rdev); 56 extern void r600_ih_ring_fini(struct radeon_device *rdev); 57 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); 58 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 59 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 60 extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 61 62 void si_rlc_fini(struct radeon_device *); 63 int si_rlc_init(struct radeon_device *); 64 void si_vram_gtt_location(struct radeon_device *, struct radeon_mc *); 65 void si_rlc_start(struct radeon_device *); 66 67 /* get temperature in millidegrees */ 68 int si_get_temp(struct radeon_device *rdev) 69 { 70 u32 temp; 71 int actual_temp = 0; 72 73 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >> 74 CTF_TEMP_SHIFT; 75 76 if (temp & 0x200) 77 actual_temp = 255; 78 else 79 actual_temp = temp & 0x1ff; 80 81 actual_temp = (actual_temp * 1000); 82 83 return actual_temp; 84 } 85 86 #define TAHITI_IO_MC_REGS_SIZE 36 87 88 static const u32 tahiti_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 89 {0x0000006f, 0x03044000}, 90 {0x00000070, 0x0480c018}, 91 {0x00000071, 0x00000040}, 92 {0x00000072, 0x01000000}, 93 {0x00000074, 0x000000ff}, 94 {0x00000075, 0x00143400}, 95 {0x00000076, 0x08ec0800}, 96 {0x00000077, 0x040000cc}, 97 {0x00000079, 0x00000000}, 98 {0x0000007a, 0x21000409}, 99 {0x0000007c, 0x00000000}, 100 {0x0000007d, 0xe8000000}, 101 {0x0000007e, 0x044408a8}, 102 {0x0000007f, 0x00000003}, 103 {0x00000080, 0x00000000}, 104 {0x00000081, 0x01000000}, 105 {0x00000082, 0x02000000}, 106 {0x00000083, 0x00000000}, 107 {0x00000084, 0xe3f3e4f4}, 108 {0x00000085, 0x00052024}, 109 {0x00000087, 0x00000000}, 110 {0x00000088, 0x66036603}, 111 {0x00000089, 0x01000000}, 112 {0x0000008b, 0x1c0a0000}, 113 {0x0000008c, 0xff010000}, 114 {0x0000008e, 0xffffefff}, 115 {0x0000008f, 0xfff3efff}, 116 {0x00000090, 0xfff3efbf}, 117 {0x00000094, 0x00101101}, 118 {0x00000095, 0x00000fff}, 119 {0x00000096, 0x00116fff}, 120 {0x00000097, 0x60010000}, 121 {0x00000098, 0x10010000}, 122 {0x00000099, 0x00006000}, 123 {0x0000009a, 0x00001000}, 124 {0x0000009f, 0x00a77400} 125 }; 126 127 static const u32 pitcairn_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 128 {0x0000006f, 0x03044000}, 129 {0x00000070, 0x0480c018}, 130 {0x00000071, 0x00000040}, 131 {0x00000072, 0x01000000}, 132 {0x00000074, 0x000000ff}, 133 {0x00000075, 0x00143400}, 134 {0x00000076, 0x08ec0800}, 135 {0x00000077, 0x040000cc}, 136 {0x00000079, 0x00000000}, 137 {0x0000007a, 0x21000409}, 138 {0x0000007c, 0x00000000}, 139 {0x0000007d, 0xe8000000}, 140 {0x0000007e, 0x044408a8}, 141 {0x0000007f, 0x00000003}, 142 {0x00000080, 0x00000000}, 143 {0x00000081, 0x01000000}, 144 {0x00000082, 0x02000000}, 145 {0x00000083, 0x00000000}, 146 {0x00000084, 0xe3f3e4f4}, 147 {0x00000085, 0x00052024}, 148 {0x00000087, 0x00000000}, 149 {0x00000088, 0x66036603}, 150 {0x00000089, 0x01000000}, 151 {0x0000008b, 0x1c0a0000}, 152 {0x0000008c, 0xff010000}, 153 {0x0000008e, 0xffffefff}, 154 {0x0000008f, 0xfff3efff}, 155 {0x00000090, 0xfff3efbf}, 156 {0x00000094, 0x00101101}, 157 {0x00000095, 0x00000fff}, 158 {0x00000096, 0x00116fff}, 159 {0x00000097, 0x60010000}, 160 {0x00000098, 0x10010000}, 161 {0x00000099, 0x00006000}, 162 {0x0000009a, 0x00001000}, 163 {0x0000009f, 0x00a47400} 164 }; 165 166 static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = { 167 {0x0000006f, 0x03044000}, 168 {0x00000070, 0x0480c018}, 169 {0x00000071, 0x00000040}, 170 {0x00000072, 0x01000000}, 171 {0x00000074, 0x000000ff}, 172 {0x00000075, 0x00143400}, 173 {0x00000076, 0x08ec0800}, 174 {0x00000077, 0x040000cc}, 175 {0x00000079, 0x00000000}, 176 {0x0000007a, 0x21000409}, 177 {0x0000007c, 0x00000000}, 178 {0x0000007d, 0xe8000000}, 179 {0x0000007e, 0x044408a8}, 180 {0x0000007f, 0x00000003}, 181 {0x00000080, 0x00000000}, 182 {0x00000081, 0x01000000}, 183 {0x00000082, 0x02000000}, 184 {0x00000083, 0x00000000}, 185 {0x00000084, 0xe3f3e4f4}, 186 {0x00000085, 0x00052024}, 187 {0x00000087, 0x00000000}, 188 {0x00000088, 0x66036603}, 189 {0x00000089, 0x01000000}, 190 {0x0000008b, 0x1c0a0000}, 191 {0x0000008c, 0xff010000}, 192 {0x0000008e, 0xffffefff}, 193 {0x0000008f, 0xfff3efff}, 194 {0x00000090, 0xfff3efbf}, 195 {0x00000094, 0x00101101}, 196 {0x00000095, 0x00000fff}, 197 {0x00000096, 0x00116fff}, 198 {0x00000097, 0x60010000}, 199 {0x00000098, 0x10010000}, 200 {0x00000099, 0x00006000}, 201 {0x0000009a, 0x00001000}, 202 {0x0000009f, 0x00a37400} 203 }; 204 205 /* ucode loading */ 206 static int si_mc_load_microcode(struct radeon_device *rdev) 207 { 208 const __be32 *fw_data; 209 u32 running, blackout = 0; 210 u32 *io_mc_regs; 211 int i, regs_size, ucode_size; 212 213 if (!rdev->mc_fw) 214 return -EINVAL; 215 216 ucode_size = rdev->mc_fw_size / 4; 217 218 switch (rdev->family) { 219 case CHIP_TAHITI: 220 io_mc_regs = (u32 *)&tahiti_io_mc_regs; 221 ucode_size = SI_MC_UCODE_SIZE; 222 regs_size = TAHITI_IO_MC_REGS_SIZE; 223 break; 224 case CHIP_PITCAIRN: 225 io_mc_regs = (u32 *)&pitcairn_io_mc_regs; 226 ucode_size = SI_MC_UCODE_SIZE; 227 regs_size = TAHITI_IO_MC_REGS_SIZE; 228 break; 229 case CHIP_VERDE: 230 default: 231 io_mc_regs = (u32 *)&verde_io_mc_regs; 232 ucode_size = SI_MC_UCODE_SIZE; 233 regs_size = TAHITI_IO_MC_REGS_SIZE; 234 break; 235 } 236 237 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 238 239 if (running == 0) { 240 if (running) { 241 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); 242 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); 243 } 244 245 /* reset the engine and set to writable */ 246 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 247 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); 248 249 /* load mc io regs */ 250 for (i = 0; i < regs_size; i++) { 251 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); 252 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); 253 } 254 /* load the MC ucode */ 255 fw_data = (const __be32 *)rdev->mc_fw; 256 for (i = 0; i < ucode_size; i++) 257 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); 258 259 /* put the engine back into the active state */ 260 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); 261 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); 262 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); 263 264 /* wait for training to complete */ 265 for (i = 0; i < rdev->usec_timeout; i++) { 266 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) 267 break; 268 udelay(1); 269 } 270 for (i = 0; i < rdev->usec_timeout; i++) { 271 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) 272 break; 273 udelay(1); 274 } 275 276 if (running) 277 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); 278 } 279 280 return 0; 281 } 282 283 static int si_init_microcode(struct radeon_device *rdev) 284 { 285 const char *chip_name; 286 const char *rlc_chip_name; 287 size_t pfp_req_size, me_req_size, ce_req_size, rlc_req_size, mc_req_size; 288 char fw_name[30]; 289 int err; 290 291 DRM_DEBUG("\n"); 292 293 switch (rdev->family) { 294 case CHIP_TAHITI: 295 chip_name = "tahiti"; 296 rlc_chip_name = "tahiti"; 297 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 298 me_req_size = SI_PM4_UCODE_SIZE * 4; 299 ce_req_size = SI_CE_UCODE_SIZE * 4; 300 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 301 mc_req_size = SI_MC_UCODE_SIZE * 4; 302 break; 303 case CHIP_PITCAIRN: 304 chip_name = "pitcairn"; 305 rlc_chip_name = "pitcairn"; 306 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 307 me_req_size = SI_PM4_UCODE_SIZE * 4; 308 ce_req_size = SI_CE_UCODE_SIZE * 4; 309 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 310 mc_req_size = SI_MC_UCODE_SIZE * 4; 311 break; 312 case CHIP_VERDE: 313 chip_name = "verde"; 314 rlc_chip_name = "verde"; 315 pfp_req_size = SI_PFP_UCODE_SIZE * 4; 316 me_req_size = SI_PM4_UCODE_SIZE * 4; 317 ce_req_size = SI_CE_UCODE_SIZE * 4; 318 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 319 mc_req_size = SI_MC_UCODE_SIZE * 4; 320 break; 321 default: BUG(); 322 } 323 324 #ifdef DRMDEBUG 325 DRM_INFO("Loading %s Microcode\n", chip_name); 326 #endif 327 328 snprintf(fw_name, sizeof(fw_name), "radeon-%s_pfp", chip_name); 329 err = loadfirmware(fw_name, &rdev->pfp_fw, &rdev->pfp_fw_size); 330 if (err) 331 goto out; 332 if (rdev->pfp_fw_size != pfp_req_size) { 333 DRM_ERROR( 334 "si_cp: Bogus length %zu in firmware \"%s\"\n", 335 rdev->pfp_fw_size, fw_name); 336 err = -EINVAL; 337 goto out; 338 } 339 340 snprintf(fw_name, sizeof(fw_name), "radeon-%s_me", chip_name); 341 err = loadfirmware(fw_name, &rdev->me_fw, &rdev->me_fw_size); 342 if (err) 343 goto out; 344 if (rdev->me_fw_size != me_req_size) { 345 DRM_ERROR( 346 "si_cp: Bogus length %zu in firmware \"%s\"\n", 347 rdev->me_fw_size, fw_name); 348 err = -EINVAL; 349 } 350 351 snprintf(fw_name, sizeof(fw_name), "radeon-%s_ce", chip_name); 352 err = loadfirmware(fw_name, &rdev->ce_fw, &rdev->ce_fw_size); 353 if (err) 354 goto out; 355 if (rdev->ce_fw_size != ce_req_size) { 356 DRM_ERROR( 357 "si_cp: Bogus length %zu in firmware \"%s\"\n", 358 rdev->ce_fw_size, fw_name); 359 err = -EINVAL; 360 } 361 362 snprintf(fw_name, sizeof(fw_name), "radeon-%s_rlc", rlc_chip_name); 363 err = loadfirmware(fw_name, &rdev->rlc_fw, &rdev->rlc_fw_size); 364 if (err) 365 goto out; 366 if (rdev->rlc_fw_size != rlc_req_size) { 367 DRM_ERROR( 368 "si_rlc: Bogus length %zu in firmware \"%s\"\n", 369 rdev->rlc_fw_size, fw_name); 370 err = -EINVAL; 371 } 372 373 snprintf(fw_name, sizeof(fw_name), "radeon-%s_mc", chip_name); 374 err = loadfirmware(fw_name, &rdev->mc_fw, &rdev->mc_fw_size); 375 if (err) 376 goto out; 377 if (rdev->mc_fw_size != mc_req_size) { 378 DRM_ERROR( 379 "si_mc: Bogus length %zu in firmware \"%s\"\n", 380 rdev->mc_fw_size, fw_name); 381 err = -EINVAL; 382 } 383 384 out: 385 if (err) { 386 if (err != -EINVAL) 387 DRM_ERROR( 388 "si_cp: Failed to load firmware \"%s\"\n", 389 fw_name); 390 if (rdev->pfp_fw) { 391 free(rdev->pfp_fw, M_DEVBUF, 0); 392 rdev->pfp_fw = NULL; 393 } 394 if (rdev->me_fw) { 395 free(rdev->pfp_fw, M_DEVBUF, 0); 396 rdev->me_fw = NULL; 397 } 398 if (rdev->ce_fw) { 399 free(rdev->ce_fw, M_DEVBUF, 0); 400 rdev->ce_fw = NULL; 401 } 402 if (rdev->rlc_fw) { 403 free(rdev->rlc_fw, M_DEVBUF, 0); 404 rdev->rlc_fw = NULL; 405 } 406 if (rdev->mc_fw) { 407 free(rdev->mc_fw, M_DEVBUF, 0); 408 rdev->mc_fw = NULL; 409 } 410 } 411 return err; 412 } 413 414 /* watermark setup */ 415 static u32 dce6_line_buffer_adjust(struct radeon_device *rdev, 416 struct radeon_crtc *radeon_crtc, 417 struct drm_display_mode *mode, 418 struct drm_display_mode *other_mode) 419 { 420 u32 tmp, buffer_alloc, i; 421 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; 422 /* 423 * Line Buffer Setup 424 * There are 3 line buffers, each one shared by 2 display controllers. 425 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 426 * the display controllers. The paritioning is done via one of four 427 * preset allocations specified in bits 21:20: 428 * 0 - half lb 429 * 2 - whole lb, other crtc must be disabled 430 */ 431 /* this can get tricky if we have two large displays on a paired group 432 * of crtcs. Ideally for multiple large displays we'd assign them to 433 * non-linked crtcs for maximum line buffer allocation. 434 */ 435 if (radeon_crtc->base.enabled && mode) { 436 if (other_mode) { 437 tmp = 0; /* 1/2 */ 438 buffer_alloc = 1; 439 } else { 440 tmp = 2; /* whole */ 441 buffer_alloc = 2; 442 } 443 } else { 444 tmp = 0; 445 buffer_alloc = 0; 446 } 447 448 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, 449 DC_LB_MEMORY_CONFIG(tmp)); 450 451 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 452 DMIF_BUFFERS_ALLOCATED(buffer_alloc)); 453 for (i = 0; i < rdev->usec_timeout; i++) { 454 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 455 DMIF_BUFFERS_ALLOCATED_COMPLETED) 456 break; 457 udelay(1); 458 } 459 460 if (radeon_crtc->base.enabled && mode) { 461 switch (tmp) { 462 case 0: 463 default: 464 return 4096 * 2; 465 case 2: 466 return 8192 * 2; 467 } 468 } 469 470 /* controller not enabled, so no lb used */ 471 return 0; 472 } 473 474 static u32 si_get_number_of_dram_channels(struct radeon_device *rdev) 475 { 476 u32 tmp = RREG32(MC_SHARED_CHMAP); 477 478 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 479 case 0: 480 default: 481 return 1; 482 case 1: 483 return 2; 484 case 2: 485 return 4; 486 case 3: 487 return 8; 488 case 4: 489 return 3; 490 case 5: 491 return 6; 492 case 6: 493 return 10; 494 case 7: 495 return 12; 496 case 8: 497 return 16; 498 } 499 } 500 501 struct dce6_wm_params { 502 u32 dram_channels; /* number of dram channels */ 503 u32 yclk; /* bandwidth per dram data pin in kHz */ 504 u32 sclk; /* engine clock in kHz */ 505 u32 disp_clk; /* display clock in kHz */ 506 u32 src_width; /* viewport width */ 507 u32 active_time; /* active display time in ns */ 508 u32 blank_time; /* blank time in ns */ 509 bool interlaced; /* mode is interlaced */ 510 fixed20_12 vsc; /* vertical scale ratio */ 511 u32 num_heads; /* number of active crtcs */ 512 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 513 u32 lb_size; /* line buffer allocated to pipe */ 514 u32 vtaps; /* vertical scaler taps */ 515 }; 516 517 static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm) 518 { 519 /* Calculate raw DRAM Bandwidth */ 520 fixed20_12 dram_efficiency; /* 0.7 */ 521 fixed20_12 yclk, dram_channels, bandwidth; 522 fixed20_12 a; 523 524 a.full = dfixed_const(1000); 525 yclk.full = dfixed_const(wm->yclk); 526 yclk.full = dfixed_div(yclk, a); 527 dram_channels.full = dfixed_const(wm->dram_channels * 4); 528 a.full = dfixed_const(10); 529 dram_efficiency.full = dfixed_const(7); 530 dram_efficiency.full = dfixed_div(dram_efficiency, a); 531 bandwidth.full = dfixed_mul(dram_channels, yclk); 532 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 533 534 return dfixed_trunc(bandwidth); 535 } 536 537 static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm) 538 { 539 /* Calculate DRAM Bandwidth and the part allocated to display. */ 540 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 541 fixed20_12 yclk, dram_channels, bandwidth; 542 fixed20_12 a; 543 544 a.full = dfixed_const(1000); 545 yclk.full = dfixed_const(wm->yclk); 546 yclk.full = dfixed_div(yclk, a); 547 dram_channels.full = dfixed_const(wm->dram_channels * 4); 548 a.full = dfixed_const(10); 549 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 550 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 551 bandwidth.full = dfixed_mul(dram_channels, yclk); 552 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 553 554 return dfixed_trunc(bandwidth); 555 } 556 557 static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm) 558 { 559 /* Calculate the display Data return Bandwidth */ 560 fixed20_12 return_efficiency; /* 0.8 */ 561 fixed20_12 sclk, bandwidth; 562 fixed20_12 a; 563 564 a.full = dfixed_const(1000); 565 sclk.full = dfixed_const(wm->sclk); 566 sclk.full = dfixed_div(sclk, a); 567 a.full = dfixed_const(10); 568 return_efficiency.full = dfixed_const(8); 569 return_efficiency.full = dfixed_div(return_efficiency, a); 570 a.full = dfixed_const(32); 571 bandwidth.full = dfixed_mul(a, sclk); 572 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 573 574 return dfixed_trunc(bandwidth); 575 } 576 577 static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm) 578 { 579 return 32; 580 } 581 582 static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm) 583 { 584 /* Calculate the DMIF Request Bandwidth */ 585 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 586 fixed20_12 disp_clk, sclk, bandwidth; 587 fixed20_12 a, b1, b2; 588 u32 min_bandwidth; 589 590 a.full = dfixed_const(1000); 591 disp_clk.full = dfixed_const(wm->disp_clk); 592 disp_clk.full = dfixed_div(disp_clk, a); 593 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2); 594 b1.full = dfixed_mul(a, disp_clk); 595 596 a.full = dfixed_const(1000); 597 sclk.full = dfixed_const(wm->sclk); 598 sclk.full = dfixed_div(sclk, a); 599 a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm)); 600 b2.full = dfixed_mul(a, sclk); 601 602 a.full = dfixed_const(10); 603 disp_clk_request_efficiency.full = dfixed_const(8); 604 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 605 606 min_bandwidth = min(dfixed_trunc(b1), dfixed_trunc(b2)); 607 608 a.full = dfixed_const(min_bandwidth); 609 bandwidth.full = dfixed_mul(a, disp_clk_request_efficiency); 610 611 return dfixed_trunc(bandwidth); 612 } 613 614 static u32 dce6_available_bandwidth(struct dce6_wm_params *wm) 615 { 616 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 617 u32 dram_bandwidth = dce6_dram_bandwidth(wm); 618 u32 data_return_bandwidth = dce6_data_return_bandwidth(wm); 619 u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm); 620 621 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 622 } 623 624 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm) 625 { 626 /* Calculate the display mode Average Bandwidth 627 * DisplayMode should contain the source and destination dimensions, 628 * timing, etc. 629 */ 630 fixed20_12 bpp; 631 fixed20_12 line_time; 632 fixed20_12 src_width; 633 fixed20_12 bandwidth; 634 fixed20_12 a; 635 636 a.full = dfixed_const(1000); 637 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 638 line_time.full = dfixed_div(line_time, a); 639 bpp.full = dfixed_const(wm->bytes_per_pixel); 640 src_width.full = dfixed_const(wm->src_width); 641 bandwidth.full = dfixed_mul(src_width, bpp); 642 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 643 bandwidth.full = dfixed_div(bandwidth, line_time); 644 645 return dfixed_trunc(bandwidth); 646 } 647 648 static u32 dce6_latency_watermark(struct dce6_wm_params *wm) 649 { 650 /* First calcualte the latency in ns */ 651 u32 mc_latency = 2000; /* 2000 ns. */ 652 u32 available_bandwidth = dce6_available_bandwidth(wm); 653 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 654 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 655 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 656 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 657 (wm->num_heads * cursor_line_pair_return_time); 658 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 659 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 660 u32 tmp, dmif_size = 12288; 661 fixed20_12 a, b, c; 662 663 if (wm->num_heads == 0) 664 return 0; 665 666 a.full = dfixed_const(2); 667 b.full = dfixed_const(1); 668 if ((wm->vsc.full > a.full) || 669 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 670 (wm->vtaps >= 5) || 671 ((wm->vsc.full >= a.full) && wm->interlaced)) 672 max_src_lines_per_dst_line = 4; 673 else 674 max_src_lines_per_dst_line = 2; 675 676 a.full = dfixed_const(available_bandwidth); 677 b.full = dfixed_const(wm->num_heads); 678 a.full = dfixed_div(a, b); 679 680 b.full = dfixed_const(mc_latency + 512); 681 c.full = dfixed_const(wm->disp_clk); 682 b.full = dfixed_div(b, c); 683 684 c.full = dfixed_const(dmif_size); 685 b.full = dfixed_div(c, b); 686 687 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 688 689 b.full = dfixed_const(1000); 690 c.full = dfixed_const(wm->disp_clk); 691 b.full = dfixed_div(c, b); 692 c.full = dfixed_const(wm->bytes_per_pixel); 693 b.full = dfixed_mul(b, c); 694 695 lb_fill_bw = min(tmp, dfixed_trunc(b)); 696 697 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 698 b.full = dfixed_const(1000); 699 c.full = dfixed_const(lb_fill_bw); 700 b.full = dfixed_div(c, b); 701 a.full = dfixed_div(a, b); 702 line_fill_time = dfixed_trunc(a); 703 704 if (line_fill_time < wm->active_time) 705 return latency; 706 else 707 return latency + (line_fill_time - wm->active_time); 708 709 } 710 711 static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 712 { 713 if (dce6_average_bandwidth(wm) <= 714 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) 715 return true; 716 else 717 return false; 718 }; 719 720 static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 721 { 722 if (dce6_average_bandwidth(wm) <= 723 (dce6_available_bandwidth(wm) / wm->num_heads)) 724 return true; 725 else 726 return false; 727 }; 728 729 static bool dce6_check_latency_hiding(struct dce6_wm_params *wm) 730 { 731 u32 lb_partitions = wm->lb_size / wm->src_width; 732 u32 line_time = wm->active_time + wm->blank_time; 733 u32 latency_tolerant_lines; 734 u32 latency_hiding; 735 fixed20_12 a; 736 737 a.full = dfixed_const(1); 738 if (wm->vsc.full > a.full) 739 latency_tolerant_lines = 1; 740 else { 741 if (lb_partitions <= (wm->vtaps + 1)) 742 latency_tolerant_lines = 1; 743 else 744 latency_tolerant_lines = 2; 745 } 746 747 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 748 749 if (dce6_latency_watermark(wm) <= latency_hiding) 750 return true; 751 else 752 return false; 753 } 754 755 static void dce6_program_watermarks(struct radeon_device *rdev, 756 struct radeon_crtc *radeon_crtc, 757 u32 lb_size, u32 num_heads) 758 { 759 struct drm_display_mode *mode = &radeon_crtc->base.mode; 760 struct dce6_wm_params wm; 761 u32 pixel_period; 762 u32 line_time = 0; 763 u32 latency_watermark_a = 0, latency_watermark_b = 0; 764 u32 priority_a_mark = 0, priority_b_mark = 0; 765 u32 priority_a_cnt = PRIORITY_OFF; 766 u32 priority_b_cnt = PRIORITY_OFF; 767 u32 tmp, arb_control3; 768 fixed20_12 a, b, c; 769 770 if (radeon_crtc->base.enabled && num_heads && mode) { 771 pixel_period = 1000000 / (u32)mode->clock; 772 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 773 priority_a_cnt = 0; 774 priority_b_cnt = 0; 775 776 wm.yclk = rdev->pm.current_mclk * 10; 777 wm.sclk = rdev->pm.current_sclk * 10; 778 wm.disp_clk = mode->clock; 779 wm.src_width = mode->crtc_hdisplay; 780 wm.active_time = mode->crtc_hdisplay * pixel_period; 781 wm.blank_time = line_time - wm.active_time; 782 wm.interlaced = false; 783 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 784 wm.interlaced = true; 785 wm.vsc = radeon_crtc->vsc; 786 wm.vtaps = 1; 787 if (radeon_crtc->rmx_type != RMX_OFF) 788 wm.vtaps = 2; 789 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */ 790 wm.lb_size = lb_size; 791 if (rdev->family == CHIP_ARUBA) 792 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev); 793 else 794 wm.dram_channels = si_get_number_of_dram_channels(rdev); 795 wm.num_heads = num_heads; 796 797 /* set for high clocks */ 798 latency_watermark_a = min(dce6_latency_watermark(&wm), (u32)65535); 799 /* set for low clocks */ 800 /* wm.yclk = low clk; wm.sclk = low clk */ 801 latency_watermark_b = min(dce6_latency_watermark(&wm), (u32)65535); 802 803 /* possibly force display priority to high */ 804 /* should really do this at mode validation time... */ 805 if (!dce6_average_bandwidth_vs_dram_bandwidth_for_display(&wm) || 806 !dce6_average_bandwidth_vs_available_bandwidth(&wm) || 807 !dce6_check_latency_hiding(&wm) || 808 (rdev->disp_priority == 2)) { 809 DRM_DEBUG_KMS("force priority to high\n"); 810 priority_a_cnt |= PRIORITY_ALWAYS_ON; 811 priority_b_cnt |= PRIORITY_ALWAYS_ON; 812 } 813 814 a.full = dfixed_const(1000); 815 b.full = dfixed_const(mode->clock); 816 b.full = dfixed_div(b, a); 817 c.full = dfixed_const(latency_watermark_a); 818 c.full = dfixed_mul(c, b); 819 c.full = dfixed_mul(c, radeon_crtc->hsc); 820 c.full = dfixed_div(c, a); 821 a.full = dfixed_const(16); 822 c.full = dfixed_div(c, a); 823 priority_a_mark = dfixed_trunc(c); 824 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 825 826 a.full = dfixed_const(1000); 827 b.full = dfixed_const(mode->clock); 828 b.full = dfixed_div(b, a); 829 c.full = dfixed_const(latency_watermark_b); 830 c.full = dfixed_mul(c, b); 831 c.full = dfixed_mul(c, radeon_crtc->hsc); 832 c.full = dfixed_div(c, a); 833 a.full = dfixed_const(16); 834 c.full = dfixed_div(c, a); 835 priority_b_mark = dfixed_trunc(c); 836 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 837 } 838 839 /* select wm A */ 840 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 841 tmp = arb_control3; 842 tmp &= ~LATENCY_WATERMARK_MASK(3); 843 tmp |= LATENCY_WATERMARK_MASK(1); 844 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 845 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 846 (LATENCY_LOW_WATERMARK(latency_watermark_a) | 847 LATENCY_HIGH_WATERMARK(line_time))); 848 /* select wm B */ 849 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); 850 tmp &= ~LATENCY_WATERMARK_MASK(3); 851 tmp |= LATENCY_WATERMARK_MASK(2); 852 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); 853 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, 854 (LATENCY_LOW_WATERMARK(latency_watermark_b) | 855 LATENCY_HIGH_WATERMARK(line_time))); 856 /* restore original selection */ 857 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); 858 859 /* write the priority marks */ 860 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); 861 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); 862 863 } 864 865 void dce6_bandwidth_update(struct radeon_device *rdev) 866 { 867 struct drm_display_mode *mode0 = NULL; 868 struct drm_display_mode *mode1 = NULL; 869 u32 num_heads = 0, lb_size; 870 int i; 871 872 radeon_update_display_priority(rdev); 873 874 for (i = 0; i < rdev->num_crtc; i++) { 875 if (rdev->mode_info.crtcs[i]->base.enabled) 876 num_heads++; 877 } 878 for (i = 0; i < rdev->num_crtc; i += 2) { 879 mode0 = &rdev->mode_info.crtcs[i]->base.mode; 880 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; 881 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); 882 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); 883 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); 884 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); 885 } 886 } 887 888 /* 889 * Core functions 890 */ 891 static void si_tiling_mode_table_init(struct radeon_device *rdev) 892 { 893 const u32 num_tile_mode_states = 32; 894 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; 895 896 switch (rdev->config.si.mem_row_size_in_kb) { 897 case 1: 898 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB; 899 break; 900 case 2: 901 default: 902 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB; 903 break; 904 case 4: 905 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB; 906 break; 907 } 908 909 if ((rdev->family == CHIP_TAHITI) || 910 (rdev->family == CHIP_PITCAIRN)) { 911 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 912 switch (reg_offset) { 913 case 0: /* non-AA compressed depth or any compressed stencil */ 914 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 915 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 916 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 918 NUM_BANKS(ADDR_SURF_16_BANK) | 919 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 920 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 921 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 922 break; 923 case 1: /* 2xAA/4xAA compressed depth only */ 924 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 925 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 926 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 928 NUM_BANKS(ADDR_SURF_16_BANK) | 929 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 930 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 931 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 932 break; 933 case 2: /* 8xAA compressed depth only */ 934 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 935 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 936 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 938 NUM_BANKS(ADDR_SURF_16_BANK) | 939 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 940 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 941 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 942 break; 943 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 944 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 945 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 946 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 947 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 948 NUM_BANKS(ADDR_SURF_16_BANK) | 949 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 950 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 951 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 952 break; 953 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 954 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 955 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 956 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 957 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 958 NUM_BANKS(ADDR_SURF_16_BANK) | 959 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 960 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 961 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 962 break; 963 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 964 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 965 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 966 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 967 TILE_SPLIT(split_equal_to_row_size) | 968 NUM_BANKS(ADDR_SURF_16_BANK) | 969 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 970 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 971 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 972 break; 973 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 974 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 975 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 976 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 977 TILE_SPLIT(split_equal_to_row_size) | 978 NUM_BANKS(ADDR_SURF_16_BANK) | 979 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 980 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 981 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 982 break; 983 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 984 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 985 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 986 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 987 TILE_SPLIT(split_equal_to_row_size) | 988 NUM_BANKS(ADDR_SURF_16_BANK) | 989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 992 break; 993 case 8: /* 1D and 1D Array Surfaces */ 994 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 995 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 996 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 997 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 998 NUM_BANKS(ADDR_SURF_16_BANK) | 999 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1000 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1001 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1002 break; 1003 case 9: /* Displayable maps. */ 1004 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1005 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1006 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1007 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1008 NUM_BANKS(ADDR_SURF_16_BANK) | 1009 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1010 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1011 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1012 break; 1013 case 10: /* Display 8bpp. */ 1014 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1015 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1016 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1017 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1018 NUM_BANKS(ADDR_SURF_16_BANK) | 1019 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1022 break; 1023 case 11: /* Display 16bpp. */ 1024 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1025 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1026 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1028 NUM_BANKS(ADDR_SURF_16_BANK) | 1029 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1032 break; 1033 case 12: /* Display 32bpp. */ 1034 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1035 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1036 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1037 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1038 NUM_BANKS(ADDR_SURF_16_BANK) | 1039 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1040 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1041 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1042 break; 1043 case 13: /* Thin. */ 1044 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1045 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1046 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1047 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1048 NUM_BANKS(ADDR_SURF_16_BANK) | 1049 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1050 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1051 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1052 break; 1053 case 14: /* Thin 8 bpp. */ 1054 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1055 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1056 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1057 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1058 NUM_BANKS(ADDR_SURF_16_BANK) | 1059 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1060 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1061 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1062 break; 1063 case 15: /* Thin 16 bpp. */ 1064 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1065 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1066 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1067 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1068 NUM_BANKS(ADDR_SURF_16_BANK) | 1069 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1070 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1071 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1072 break; 1073 case 16: /* Thin 32 bpp. */ 1074 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1075 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1076 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1077 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1078 NUM_BANKS(ADDR_SURF_16_BANK) | 1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1082 break; 1083 case 17: /* Thin 64 bpp. */ 1084 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1085 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1087 TILE_SPLIT(split_equal_to_row_size) | 1088 NUM_BANKS(ADDR_SURF_16_BANK) | 1089 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1090 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1091 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1092 break; 1093 case 21: /* 8 bpp PRT. */ 1094 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1095 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1097 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1098 NUM_BANKS(ADDR_SURF_16_BANK) | 1099 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1102 break; 1103 case 22: /* 16 bpp PRT */ 1104 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1105 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1106 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1107 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1108 NUM_BANKS(ADDR_SURF_16_BANK) | 1109 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1110 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1111 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1112 break; 1113 case 23: /* 32 bpp PRT */ 1114 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1115 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1116 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1117 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1118 NUM_BANKS(ADDR_SURF_16_BANK) | 1119 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1122 break; 1123 case 24: /* 64 bpp PRT */ 1124 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1125 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1126 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1127 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1128 NUM_BANKS(ADDR_SURF_16_BANK) | 1129 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1130 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1131 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1132 break; 1133 case 25: /* 128 bpp PRT */ 1134 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1135 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1136 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1137 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1138 NUM_BANKS(ADDR_SURF_8_BANK) | 1139 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1140 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1141 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1142 break; 1143 default: 1144 gb_tile_moden = 0; 1145 break; 1146 } 1147 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1148 } 1149 } else if (rdev->family == CHIP_VERDE) { 1150 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1151 switch (reg_offset) { 1152 case 0: /* non-AA compressed depth or any compressed stencil */ 1153 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1154 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1155 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1156 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1157 NUM_BANKS(ADDR_SURF_16_BANK) | 1158 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1159 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1160 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1161 break; 1162 case 1: /* 2xAA/4xAA compressed depth only */ 1163 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1164 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1165 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1166 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1167 NUM_BANKS(ADDR_SURF_16_BANK) | 1168 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1171 break; 1172 case 2: /* 8xAA compressed depth only */ 1173 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1174 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1175 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1176 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1177 NUM_BANKS(ADDR_SURF_16_BANK) | 1178 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1179 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1180 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1181 break; 1182 case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */ 1183 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1184 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1185 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1186 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | 1187 NUM_BANKS(ADDR_SURF_16_BANK) | 1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1191 break; 1192 case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ 1193 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1194 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1195 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1197 NUM_BANKS(ADDR_SURF_16_BANK) | 1198 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1199 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1200 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1201 break; 1202 case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ 1203 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1204 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1205 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1206 TILE_SPLIT(split_equal_to_row_size) | 1207 NUM_BANKS(ADDR_SURF_16_BANK) | 1208 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1209 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1210 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1211 break; 1212 case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ 1213 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1214 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1215 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1216 TILE_SPLIT(split_equal_to_row_size) | 1217 NUM_BANKS(ADDR_SURF_16_BANK) | 1218 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1219 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1220 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1221 break; 1222 case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */ 1223 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1224 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) | 1225 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1226 TILE_SPLIT(split_equal_to_row_size) | 1227 NUM_BANKS(ADDR_SURF_16_BANK) | 1228 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1231 break; 1232 case 8: /* 1D and 1D Array Surfaces */ 1233 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | 1234 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1235 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1237 NUM_BANKS(ADDR_SURF_16_BANK) | 1238 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1239 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1240 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1241 break; 1242 case 9: /* Displayable maps. */ 1243 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1244 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1245 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1246 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1247 NUM_BANKS(ADDR_SURF_16_BANK) | 1248 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1249 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1250 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1251 break; 1252 case 10: /* Display 8bpp. */ 1253 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1254 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1255 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1256 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1257 NUM_BANKS(ADDR_SURF_16_BANK) | 1258 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1259 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1260 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1261 break; 1262 case 11: /* Display 16bpp. */ 1263 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1264 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1265 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1267 NUM_BANKS(ADDR_SURF_16_BANK) | 1268 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1271 break; 1272 case 12: /* Display 32bpp. */ 1273 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1274 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | 1275 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1276 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1277 NUM_BANKS(ADDR_SURF_16_BANK) | 1278 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1279 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1280 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1281 break; 1282 case 13: /* Thin. */ 1283 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | 1284 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1285 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | 1287 NUM_BANKS(ADDR_SURF_16_BANK) | 1288 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1289 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1290 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1291 break; 1292 case 14: /* Thin 8 bpp. */ 1293 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1294 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1295 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1296 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1297 NUM_BANKS(ADDR_SURF_16_BANK) | 1298 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1299 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1300 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1301 break; 1302 case 15: /* Thin 16 bpp. */ 1303 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1304 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1305 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1306 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1307 NUM_BANKS(ADDR_SURF_16_BANK) | 1308 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1309 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1310 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1311 break; 1312 case 16: /* Thin 32 bpp. */ 1313 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1314 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1315 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1316 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1317 NUM_BANKS(ADDR_SURF_16_BANK) | 1318 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1319 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1320 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1321 break; 1322 case 17: /* Thin 64 bpp. */ 1323 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1324 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1325 PIPE_CONFIG(ADDR_SURF_P4_8x16) | 1326 TILE_SPLIT(split_equal_to_row_size) | 1327 NUM_BANKS(ADDR_SURF_16_BANK) | 1328 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1329 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1330 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1331 break; 1332 case 21: /* 8 bpp PRT. */ 1333 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1334 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1335 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1336 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1337 NUM_BANKS(ADDR_SURF_16_BANK) | 1338 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | 1339 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1340 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1341 break; 1342 case 22: /* 16 bpp PRT */ 1343 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1344 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1345 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1346 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1347 NUM_BANKS(ADDR_SURF_16_BANK) | 1348 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1349 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | 1350 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)); 1351 break; 1352 case 23: /* 32 bpp PRT */ 1353 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1354 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1355 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1356 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | 1357 NUM_BANKS(ADDR_SURF_16_BANK) | 1358 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1359 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | 1360 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1361 break; 1362 case 24: /* 64 bpp PRT */ 1363 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1364 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1365 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1366 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | 1367 NUM_BANKS(ADDR_SURF_16_BANK) | 1368 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1369 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1370 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)); 1371 break; 1372 case 25: /* 128 bpp PRT */ 1373 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | 1374 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) | 1375 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) | 1376 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) | 1377 NUM_BANKS(ADDR_SURF_8_BANK) | 1378 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | 1379 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | 1380 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)); 1381 break; 1382 default: 1383 gb_tile_moden = 0; 1384 break; 1385 } 1386 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1387 } 1388 } else 1389 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); 1390 } 1391 1392 static void si_select_se_sh(struct radeon_device *rdev, 1393 u32 se_num, u32 sh_num) 1394 { 1395 u32 data = INSTANCE_BROADCAST_WRITES; 1396 1397 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 1398 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 1399 else if (se_num == 0xffffffff) 1400 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 1401 else if (sh_num == 0xffffffff) 1402 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num); 1403 else 1404 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); 1405 WREG32(GRBM_GFX_INDEX, data); 1406 } 1407 1408 static u32 si_create_bitmask(u32 bit_width) 1409 { 1410 u32 i, mask = 0; 1411 1412 for (i = 0; i < bit_width; i++) { 1413 mask <<= 1; 1414 mask |= 1; 1415 } 1416 return mask; 1417 } 1418 1419 static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh) 1420 { 1421 u32 data, mask; 1422 1423 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG); 1424 if (data & 1) 1425 data &= INACTIVE_CUS_MASK; 1426 else 1427 data = 0; 1428 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG); 1429 1430 data >>= INACTIVE_CUS_SHIFT; 1431 1432 mask = si_create_bitmask(cu_per_sh); 1433 1434 return ~data & mask; 1435 } 1436 1437 static void si_setup_spi(struct radeon_device *rdev, 1438 u32 se_num, u32 sh_per_se, 1439 u32 cu_per_sh) 1440 { 1441 int i, j, k; 1442 u32 data, mask, active_cu; 1443 1444 for (i = 0; i < se_num; i++) { 1445 for (j = 0; j < sh_per_se; j++) { 1446 si_select_se_sh(rdev, i, j); 1447 data = RREG32(SPI_STATIC_THREAD_MGMT_3); 1448 active_cu = si_get_cu_enabled(rdev, cu_per_sh); 1449 1450 mask = 1; 1451 for (k = 0; k < 16; k++) { 1452 mask <<= k; 1453 if (active_cu & mask) { 1454 data &= ~mask; 1455 WREG32(SPI_STATIC_THREAD_MGMT_3, data); 1456 break; 1457 } 1458 } 1459 } 1460 } 1461 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1462 } 1463 1464 static u32 si_get_rb_disabled(struct radeon_device *rdev, 1465 u32 max_rb_num_per_se, 1466 u32 sh_per_se) 1467 { 1468 u32 data, mask; 1469 1470 data = RREG32(CC_RB_BACKEND_DISABLE); 1471 if (data & 1) 1472 data &= BACKEND_DISABLE_MASK; 1473 else 1474 data = 0; 1475 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); 1476 1477 data >>= BACKEND_DISABLE_SHIFT; 1478 1479 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se); 1480 1481 return data & mask; 1482 } 1483 1484 static void si_setup_rb(struct radeon_device *rdev, 1485 u32 se_num, u32 sh_per_se, 1486 u32 max_rb_num_per_se) 1487 { 1488 int i, j; 1489 u32 data, mask; 1490 u32 disabled_rbs = 0; 1491 u32 enabled_rbs = 0; 1492 1493 for (i = 0; i < se_num; i++) { 1494 for (j = 0; j < sh_per_se; j++) { 1495 si_select_se_sh(rdev, i, j); 1496 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se); 1497 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); 1498 } 1499 } 1500 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1501 1502 mask = 1; 1503 for (i = 0; i < max_rb_num_per_se * se_num; i++) { 1504 if (!(disabled_rbs & mask)) 1505 enabled_rbs |= mask; 1506 mask <<= 1; 1507 } 1508 1509 rdev->config.si.backend_enable_mask = enabled_rbs; 1510 1511 for (i = 0; i < se_num; i++) { 1512 si_select_se_sh(rdev, i, 0xffffffff); 1513 data = 0; 1514 for (j = 0; j < sh_per_se; j++) { 1515 switch (enabled_rbs & 3) { 1516 case 1: 1517 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2); 1518 break; 1519 case 2: 1520 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2); 1521 break; 1522 case 3: 1523 default: 1524 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2); 1525 break; 1526 } 1527 enabled_rbs >>= 2; 1528 } 1529 WREG32(PA_SC_RASTER_CONFIG, data); 1530 } 1531 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 1532 } 1533 1534 static void si_gpu_init(struct radeon_device *rdev) 1535 { 1536 u32 gb_addr_config = 0; 1537 u32 mc_shared_chmap, mc_arb_ramcfg; 1538 u32 sx_debug_1; 1539 u32 hdp_host_path_cntl; 1540 u32 tmp; 1541 int i, j; 1542 1543 switch (rdev->family) { 1544 case CHIP_TAHITI: 1545 rdev->config.si.max_shader_engines = 2; 1546 rdev->config.si.max_tile_pipes = 12; 1547 rdev->config.si.max_cu_per_sh = 8; 1548 rdev->config.si.max_sh_per_se = 2; 1549 rdev->config.si.max_backends_per_se = 4; 1550 rdev->config.si.max_texture_channel_caches = 12; 1551 rdev->config.si.max_gprs = 256; 1552 rdev->config.si.max_gs_threads = 32; 1553 rdev->config.si.max_hw_contexts = 8; 1554 1555 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1556 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1557 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1558 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1559 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1560 break; 1561 case CHIP_PITCAIRN: 1562 rdev->config.si.max_shader_engines = 2; 1563 rdev->config.si.max_tile_pipes = 8; 1564 rdev->config.si.max_cu_per_sh = 5; 1565 rdev->config.si.max_sh_per_se = 2; 1566 rdev->config.si.max_backends_per_se = 4; 1567 rdev->config.si.max_texture_channel_caches = 8; 1568 rdev->config.si.max_gprs = 256; 1569 rdev->config.si.max_gs_threads = 32; 1570 rdev->config.si.max_hw_contexts = 8; 1571 1572 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1573 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1574 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1575 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1576 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN; 1577 break; 1578 case CHIP_VERDE: 1579 default: 1580 rdev->config.si.max_shader_engines = 1; 1581 rdev->config.si.max_tile_pipes = 4; 1582 rdev->config.si.max_cu_per_sh = 5; 1583 rdev->config.si.max_sh_per_se = 2; 1584 rdev->config.si.max_backends_per_se = 4; 1585 rdev->config.si.max_texture_channel_caches = 4; 1586 rdev->config.si.max_gprs = 256; 1587 rdev->config.si.max_gs_threads = 32; 1588 rdev->config.si.max_hw_contexts = 8; 1589 1590 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; 1591 rdev->config.si.sc_prim_fifo_size_backend = 0x40; 1592 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1593 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1594 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1595 break; 1596 } 1597 1598 /* Initialize HDP */ 1599 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1600 WREG32((0x2c14 + j), 0x00000000); 1601 WREG32((0x2c18 + j), 0x00000000); 1602 WREG32((0x2c1c + j), 0x00000000); 1603 WREG32((0x2c20 + j), 0x00000000); 1604 WREG32((0x2c24 + j), 0x00000000); 1605 } 1606 1607 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1608 1609 evergreen_fix_pci_max_read_req_size(rdev); 1610 1611 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 1612 1613 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1614 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1615 1616 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; 1617 rdev->config.si.mem_max_burst_length_bytes = 256; 1618 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1619 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1620 if (rdev->config.si.mem_row_size_in_kb > 4) 1621 rdev->config.si.mem_row_size_in_kb = 4; 1622 /* XXX use MC settings? */ 1623 rdev->config.si.shader_engine_tile_size = 32; 1624 rdev->config.si.num_gpus = 1; 1625 rdev->config.si.multi_gpu_tile_size = 64; 1626 1627 /* fix up row size */ 1628 gb_addr_config &= ~ROW_SIZE_MASK; 1629 switch (rdev->config.si.mem_row_size_in_kb) { 1630 case 1: 1631 default: 1632 gb_addr_config |= ROW_SIZE(0); 1633 break; 1634 case 2: 1635 gb_addr_config |= ROW_SIZE(1); 1636 break; 1637 case 4: 1638 gb_addr_config |= ROW_SIZE(2); 1639 break; 1640 } 1641 1642 /* setup tiling info dword. gb_addr_config is not adequate since it does 1643 * not have bank info, so create a custom tiling dword. 1644 * bits 3:0 num_pipes 1645 * bits 7:4 num_banks 1646 * bits 11:8 group_size 1647 * bits 15:12 row_size 1648 */ 1649 rdev->config.si.tile_config = 0; 1650 switch (rdev->config.si.num_tile_pipes) { 1651 case 1: 1652 rdev->config.si.tile_config |= (0 << 0); 1653 break; 1654 case 2: 1655 rdev->config.si.tile_config |= (1 << 0); 1656 break; 1657 case 4: 1658 rdev->config.si.tile_config |= (2 << 0); 1659 break; 1660 case 8: 1661 default: 1662 /* XXX what about 12? */ 1663 rdev->config.si.tile_config |= (3 << 0); 1664 break; 1665 } 1666 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 1667 case 0: /* four banks */ 1668 rdev->config.si.tile_config |= 0 << 4; 1669 break; 1670 case 1: /* eight banks */ 1671 rdev->config.si.tile_config |= 1 << 4; 1672 break; 1673 case 2: /* sixteen banks */ 1674 default: 1675 rdev->config.si.tile_config |= 2 << 4; 1676 break; 1677 } 1678 rdev->config.si.tile_config |= 1679 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1680 rdev->config.si.tile_config |= 1681 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1682 1683 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1684 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1685 WREG32(DMIF_ADDR_CALC, gb_addr_config); 1686 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1687 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); 1688 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); 1689 1690 si_tiling_mode_table_init(rdev); 1691 1692 si_setup_rb(rdev, rdev->config.si.max_shader_engines, 1693 rdev->config.si.max_sh_per_se, 1694 rdev->config.si.max_backends_per_se); 1695 1696 si_setup_spi(rdev, rdev->config.si.max_shader_engines, 1697 rdev->config.si.max_sh_per_se, 1698 rdev->config.si.max_cu_per_sh); 1699 1700 1701 /* set HW defaults for 3D engine */ 1702 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1703 ROQ_IB2_START(0x2b))); 1704 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); 1705 1706 sx_debug_1 = RREG32(SX_DEBUG_1); 1707 WREG32(SX_DEBUG_1, sx_debug_1); 1708 1709 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); 1710 1711 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | 1712 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | 1713 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | 1714 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); 1715 1716 WREG32(VGT_NUM_INSTANCES, 1); 1717 1718 WREG32(CP_PERFMON_CNTL, 0); 1719 1720 WREG32(SQ_CONFIG, 0); 1721 1722 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 1723 FORCE_EOV_MAX_REZ_CNT(255))); 1724 1725 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | 1726 AUTO_INVLD_EN(ES_AND_GS_AUTO)); 1727 1728 WREG32(VGT_GS_VERTEX_REUSE, 16); 1729 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1730 1731 WREG32(CB_PERFCOUNTER0_SELECT0, 0); 1732 WREG32(CB_PERFCOUNTER0_SELECT1, 0); 1733 WREG32(CB_PERFCOUNTER1_SELECT0, 0); 1734 WREG32(CB_PERFCOUNTER1_SELECT1, 0); 1735 WREG32(CB_PERFCOUNTER2_SELECT0, 0); 1736 WREG32(CB_PERFCOUNTER2_SELECT1, 0); 1737 WREG32(CB_PERFCOUNTER3_SELECT0, 0); 1738 WREG32(CB_PERFCOUNTER3_SELECT1, 0); 1739 1740 tmp = RREG32(HDP_MISC_CNTL); 1741 tmp |= HDP_FLUSH_INVALIDATE_CACHE; 1742 WREG32(HDP_MISC_CNTL, tmp); 1743 1744 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1745 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1746 1747 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); 1748 1749 udelay(50); 1750 } 1751 1752 /* 1753 * GPU scratch registers helpers function. 1754 */ 1755 static void si_scratch_init(struct radeon_device *rdev) 1756 { 1757 int i; 1758 1759 rdev->scratch.num_reg = 7; 1760 rdev->scratch.reg_base = SCRATCH_REG0; 1761 for (i = 0; i < rdev->scratch.num_reg; i++) { 1762 rdev->scratch.free[i] = true; 1763 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 1764 } 1765 } 1766 1767 void si_fence_ring_emit(struct radeon_device *rdev, 1768 struct radeon_fence *fence) 1769 { 1770 struct radeon_ring *ring = &rdev->ring[fence->ring]; 1771 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 1772 1773 /* flush read cache over gart */ 1774 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1775 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1776 radeon_ring_write(ring, 0); 1777 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1778 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1779 PACKET3_TC_ACTION_ENA | 1780 PACKET3_SH_KCACHE_ACTION_ENA | 1781 PACKET3_SH_ICACHE_ACTION_ENA); 1782 radeon_ring_write(ring, 0xFFFFFFFF); 1783 radeon_ring_write(ring, 0); 1784 radeon_ring_write(ring, 10); /* poll interval */ 1785 /* EVENT_WRITE_EOP - flush caches, send int */ 1786 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 1787 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5)); 1788 radeon_ring_write(ring, addr & 0xffffffff); 1789 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 1790 radeon_ring_write(ring, fence->seq); 1791 radeon_ring_write(ring, 0); 1792 } 1793 1794 /* 1795 * IB stuff 1796 */ 1797 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1798 { 1799 struct radeon_ring *ring = &rdev->ring[ib->ring]; 1800 u32 header; 1801 1802 if (ib->is_const_ib) { 1803 /* set switch buffer packet before const IB */ 1804 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 1805 radeon_ring_write(ring, 0); 1806 1807 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); 1808 } else { 1809 u32 next_rptr; 1810 if (ring->rptr_save_reg) { 1811 next_rptr = ring->wptr + 3 + 4 + 8; 1812 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1813 radeon_ring_write(ring, ((ring->rptr_save_reg - 1814 PACKET3_SET_CONFIG_REG_START) >> 2)); 1815 radeon_ring_write(ring, next_rptr); 1816 } else if (rdev->wb.enabled) { 1817 next_rptr = ring->wptr + 5 + 4 + 8; 1818 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 1819 radeon_ring_write(ring, (1 << 8)); 1820 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 1821 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 1822 radeon_ring_write(ring, next_rptr); 1823 } 1824 1825 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 1826 } 1827 1828 radeon_ring_write(ring, header); 1829 radeon_ring_write(ring, 1830 #ifdef __BIG_ENDIAN 1831 (2 << 0) | 1832 #endif 1833 (ib->gpu_addr & 0xFFFFFFFC)); 1834 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); 1835 radeon_ring_write(ring, ib->length_dw | 1836 (ib->vm ? (ib->vm->id << 24) : 0)); 1837 1838 if (!ib->is_const_ib) { 1839 /* flush read cache over gart for this vmid */ 1840 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1841 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); 1842 radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); 1843 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 1844 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA | 1845 PACKET3_TC_ACTION_ENA | 1846 PACKET3_SH_KCACHE_ACTION_ENA | 1847 PACKET3_SH_ICACHE_ACTION_ENA); 1848 radeon_ring_write(ring, 0xFFFFFFFF); 1849 radeon_ring_write(ring, 0); 1850 radeon_ring_write(ring, 10); /* poll interval */ 1851 } 1852 } 1853 1854 /* 1855 * CP. 1856 */ 1857 static void si_cp_enable(struct radeon_device *rdev, bool enable) 1858 { 1859 if (enable) 1860 WREG32(CP_ME_CNTL, 0); 1861 else { 1862 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1863 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); 1864 WREG32(SCRATCH_UMSK, 0); 1865 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1866 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 1867 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 1868 } 1869 udelay(50); 1870 } 1871 1872 static int si_cp_load_microcode(struct radeon_device *rdev) 1873 { 1874 const __be32 *fw_data; 1875 int i; 1876 1877 if (!rdev->me_fw || !rdev->pfp_fw) 1878 return -EINVAL; 1879 1880 si_cp_enable(rdev, false); 1881 1882 /* PFP */ 1883 fw_data = (const __be32 *)rdev->pfp_fw; 1884 WREG32(CP_PFP_UCODE_ADDR, 0); 1885 for (i = 0; i < SI_PFP_UCODE_SIZE; i++) 1886 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 1887 WREG32(CP_PFP_UCODE_ADDR, 0); 1888 1889 /* CE */ 1890 fw_data = (const __be32 *)rdev->ce_fw; 1891 WREG32(CP_CE_UCODE_ADDR, 0); 1892 for (i = 0; i < SI_CE_UCODE_SIZE; i++) 1893 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); 1894 WREG32(CP_CE_UCODE_ADDR, 0); 1895 1896 /* ME */ 1897 fw_data = (const __be32 *)rdev->me_fw; 1898 WREG32(CP_ME_RAM_WADDR, 0); 1899 for (i = 0; i < SI_PM4_UCODE_SIZE; i++) 1900 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 1901 WREG32(CP_ME_RAM_WADDR, 0); 1902 1903 WREG32(CP_PFP_UCODE_ADDR, 0); 1904 WREG32(CP_CE_UCODE_ADDR, 0); 1905 WREG32(CP_ME_RAM_WADDR, 0); 1906 WREG32(CP_ME_RAM_RADDR, 0); 1907 return 0; 1908 } 1909 1910 static int si_cp_start(struct radeon_device *rdev) 1911 { 1912 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1913 int r, i; 1914 1915 r = radeon_ring_lock(rdev, ring, 7 + 4); 1916 if (r) { 1917 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1918 return r; 1919 } 1920 /* init the CP */ 1921 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1922 radeon_ring_write(ring, 0x1); 1923 radeon_ring_write(ring, 0x0); 1924 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); 1925 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1926 radeon_ring_write(ring, 0); 1927 radeon_ring_write(ring, 0); 1928 1929 /* init the CE partitions */ 1930 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 1931 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 1932 radeon_ring_write(ring, 0xc000); 1933 radeon_ring_write(ring, 0xe000); 1934 radeon_ring_unlock_commit(rdev, ring); 1935 1936 si_cp_enable(rdev, true); 1937 1938 r = radeon_ring_lock(rdev, ring, si_default_size + 10); 1939 if (r) { 1940 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1941 return r; 1942 } 1943 1944 /* setup clear context state */ 1945 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1946 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1947 1948 for (i = 0; i < si_default_size; i++) 1949 radeon_ring_write(ring, si_default_state[i]); 1950 1951 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1952 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 1953 1954 /* set clear context state */ 1955 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 1956 radeon_ring_write(ring, 0); 1957 1958 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 1959 radeon_ring_write(ring, 0x00000316); 1960 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1961 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ 1962 1963 radeon_ring_unlock_commit(rdev, ring); 1964 1965 for (i = RADEON_RING_TYPE_GFX_INDEX; i <= CAYMAN_RING_TYPE_CP2_INDEX; ++i) { 1966 ring = &rdev->ring[i]; 1967 r = radeon_ring_lock(rdev, ring, 2); 1968 1969 /* clear the compute context state */ 1970 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); 1971 radeon_ring_write(ring, 0); 1972 1973 radeon_ring_unlock_commit(rdev, ring); 1974 } 1975 1976 return 0; 1977 } 1978 1979 static void si_cp_fini(struct radeon_device *rdev) 1980 { 1981 struct radeon_ring *ring; 1982 si_cp_enable(rdev, false); 1983 1984 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1985 radeon_ring_fini(rdev, ring); 1986 radeon_scratch_free(rdev, ring->rptr_save_reg); 1987 1988 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 1989 radeon_ring_fini(rdev, ring); 1990 radeon_scratch_free(rdev, ring->rptr_save_reg); 1991 1992 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 1993 radeon_ring_fini(rdev, ring); 1994 radeon_scratch_free(rdev, ring->rptr_save_reg); 1995 } 1996 1997 static int si_cp_resume(struct radeon_device *rdev) 1998 { 1999 struct radeon_ring *ring; 2000 u32 tmp; 2001 u32 rb_bufsz; 2002 int r; 2003 2004 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */ 2005 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP | 2006 SOFT_RESET_PA | 2007 SOFT_RESET_VGT | 2008 SOFT_RESET_SPI | 2009 SOFT_RESET_SX)); 2010 RREG32(GRBM_SOFT_RESET); 2011 mdelay(15); 2012 WREG32(GRBM_SOFT_RESET, 0); 2013 RREG32(GRBM_SOFT_RESET); 2014 2015 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2016 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); 2017 2018 /* Set the write pointer delay */ 2019 WREG32(CP_RB_WPTR_DELAY, 0); 2020 2021 WREG32(CP_DEBUG, 0); 2022 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2023 2024 /* ring 0 - compute and gfx */ 2025 /* Set ring buffer size */ 2026 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2027 rb_bufsz = drm_order(ring->ring_size / 8); 2028 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2029 #ifdef __BIG_ENDIAN 2030 tmp |= BUF_SWAP_32BIT; 2031 #endif 2032 WREG32(CP_RB0_CNTL, tmp); 2033 2034 /* Initialize the ring buffer's read and write pointers */ 2035 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 2036 ring->wptr = 0; 2037 WREG32(CP_RB0_WPTR, ring->wptr); 2038 2039 /* set the wb address whether it's enabled or not */ 2040 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 2041 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2042 2043 if (rdev->wb.enabled) 2044 WREG32(SCRATCH_UMSK, 0xff); 2045 else { 2046 tmp |= RB_NO_UPDATE; 2047 WREG32(SCRATCH_UMSK, 0); 2048 } 2049 2050 mdelay(1); 2051 WREG32(CP_RB0_CNTL, tmp); 2052 2053 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); 2054 2055 ring->rptr = RREG32(CP_RB0_RPTR); 2056 2057 /* ring1 - compute only */ 2058 /* Set ring buffer size */ 2059 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 2060 rb_bufsz = drm_order(ring->ring_size / 8); 2061 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2062 #ifdef __BIG_ENDIAN 2063 tmp |= BUF_SWAP_32BIT; 2064 #endif 2065 WREG32(CP_RB1_CNTL, tmp); 2066 2067 /* Initialize the ring buffer's read and write pointers */ 2068 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 2069 ring->wptr = 0; 2070 WREG32(CP_RB1_WPTR, ring->wptr); 2071 2072 /* set the wb address whether it's enabled or not */ 2073 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); 2074 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); 2075 2076 mdelay(1); 2077 WREG32(CP_RB1_CNTL, tmp); 2078 2079 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); 2080 2081 ring->rptr = RREG32(CP_RB1_RPTR); 2082 2083 /* ring2 - compute only */ 2084 /* Set ring buffer size */ 2085 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 2086 rb_bufsz = drm_order(ring->ring_size / 8); 2087 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2088 #ifdef __BIG_ENDIAN 2089 tmp |= BUF_SWAP_32BIT; 2090 #endif 2091 WREG32(CP_RB2_CNTL, tmp); 2092 2093 /* Initialize the ring buffer's read and write pointers */ 2094 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 2095 ring->wptr = 0; 2096 WREG32(CP_RB2_WPTR, ring->wptr); 2097 2098 /* set the wb address whether it's enabled or not */ 2099 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); 2100 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); 2101 2102 mdelay(1); 2103 WREG32(CP_RB2_CNTL, tmp); 2104 2105 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); 2106 2107 ring->rptr = RREG32(CP_RB2_RPTR); 2108 2109 /* start the rings */ 2110 si_cp_start(rdev); 2111 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; 2112 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; 2113 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; 2114 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 2115 if (r) { 2116 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 2117 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2118 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2119 return r; 2120 } 2121 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); 2122 if (r) { 2123 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; 2124 } 2125 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); 2126 if (r) { 2127 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; 2128 } 2129 2130 return 0; 2131 } 2132 2133 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2134 { 2135 u32 srbm_status; 2136 u32 grbm_status, grbm_status2; 2137 u32 grbm_status_se0, grbm_status_se1; 2138 2139 srbm_status = RREG32(SRBM_STATUS); 2140 grbm_status = RREG32(GRBM_STATUS); 2141 grbm_status2 = RREG32(GRBM_STATUS2); 2142 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2143 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2144 if (!(grbm_status & GUI_ACTIVE)) { 2145 radeon_ring_lockup_update(ring); 2146 return false; 2147 } 2148 /* force CP activities */ 2149 radeon_ring_force_activity(rdev, ring); 2150 return radeon_ring_test_lockup(rdev, ring); 2151 } 2152 2153 static void si_gpu_soft_reset_gfx(struct radeon_device *rdev) 2154 { 2155 u32 grbm_reset = 0; 2156 2157 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2158 return; 2159 2160 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2161 RREG32(GRBM_STATUS)); 2162 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", 2163 RREG32(GRBM_STATUS2)); 2164 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2165 RREG32(GRBM_STATUS_SE0)); 2166 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2167 RREG32(GRBM_STATUS_SE1)); 2168 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2169 RREG32(SRBM_STATUS)); 2170 2171 /* Disable CP parsing/prefetching */ 2172 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 2173 2174 /* reset all the gfx blocks */ 2175 grbm_reset = (SOFT_RESET_CP | 2176 SOFT_RESET_CB | 2177 SOFT_RESET_DB | 2178 SOFT_RESET_GDS | 2179 SOFT_RESET_PA | 2180 SOFT_RESET_SC | 2181 SOFT_RESET_BCI | 2182 SOFT_RESET_SPI | 2183 SOFT_RESET_SX | 2184 SOFT_RESET_TC | 2185 SOFT_RESET_TA | 2186 SOFT_RESET_VGT | 2187 SOFT_RESET_IA); 2188 2189 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); 2190 WREG32(GRBM_SOFT_RESET, grbm_reset); 2191 (void)RREG32(GRBM_SOFT_RESET); 2192 udelay(50); 2193 WREG32(GRBM_SOFT_RESET, 0); 2194 (void)RREG32(GRBM_SOFT_RESET); 2195 2196 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2197 RREG32(GRBM_STATUS)); 2198 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n", 2199 RREG32(GRBM_STATUS2)); 2200 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", 2201 RREG32(GRBM_STATUS_SE0)); 2202 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", 2203 RREG32(GRBM_STATUS_SE1)); 2204 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", 2205 RREG32(SRBM_STATUS)); 2206 } 2207 2208 static void si_gpu_soft_reset_dma(struct radeon_device *rdev) 2209 { 2210 u32 tmp; 2211 2212 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2213 return; 2214 2215 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2216 RREG32(DMA_STATUS_REG)); 2217 2218 /* dma0 */ 2219 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 2220 tmp &= ~DMA_RB_ENABLE; 2221 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); 2222 2223 /* dma1 */ 2224 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 2225 tmp &= ~DMA_RB_ENABLE; 2226 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); 2227 2228 /* Reset dma */ 2229 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); 2230 RREG32(SRBM_SOFT_RESET); 2231 udelay(50); 2232 WREG32(SRBM_SOFT_RESET, 0); 2233 2234 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2235 RREG32(DMA_STATUS_REG)); 2236 } 2237 2238 static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 2239 { 2240 struct evergreen_mc_save save; 2241 2242 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2243 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); 2244 2245 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2246 reset_mask &= ~RADEON_RESET_DMA; 2247 2248 if (reset_mask == 0) 2249 return 0; 2250 2251 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 2252 2253 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 2254 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 2255 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 2256 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 2257 2258 evergreen_mc_stop(rdev, &save); 2259 if (radeon_mc_wait_for_idle(rdev)) { 2260 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2261 } 2262 2263 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 2264 si_gpu_soft_reset_gfx(rdev); 2265 2266 if (reset_mask & RADEON_RESET_DMA) 2267 si_gpu_soft_reset_dma(rdev); 2268 2269 /* Wait a little for things to settle down */ 2270 udelay(50); 2271 2272 evergreen_mc_resume(rdev, &save); 2273 return 0; 2274 } 2275 2276 int si_asic_reset(struct radeon_device *rdev) 2277 { 2278 return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 2279 RADEON_RESET_COMPUTE | 2280 RADEON_RESET_DMA)); 2281 } 2282 2283 /* MC */ 2284 static void si_mc_program(struct radeon_device *rdev) 2285 { 2286 struct evergreen_mc_save save; 2287 u32 tmp; 2288 int i, j; 2289 2290 /* Initialize HDP */ 2291 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 2292 WREG32((0x2c14 + j), 0x00000000); 2293 WREG32((0x2c18 + j), 0x00000000); 2294 WREG32((0x2c1c + j), 0x00000000); 2295 WREG32((0x2c20 + j), 0x00000000); 2296 WREG32((0x2c24 + j), 0x00000000); 2297 } 2298 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 2299 2300 evergreen_mc_stop(rdev, &save); 2301 if (radeon_mc_wait_for_idle(rdev)) { 2302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2303 } 2304 /* Lockout access through VGA aperture*/ 2305 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 2306 /* Update configuration */ 2307 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 2308 rdev->mc.vram_start >> 12); 2309 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 2310 rdev->mc.vram_end >> 12); 2311 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 2312 rdev->vram_scratch.gpu_addr >> 12); 2313 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 2314 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 2315 WREG32(MC_VM_FB_LOCATION, tmp); 2316 /* XXX double check these! */ 2317 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 2318 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); 2319 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 2320 WREG32(MC_VM_AGP_BASE, 0); 2321 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 2322 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 2323 if (radeon_mc_wait_for_idle(rdev)) { 2324 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2325 } 2326 evergreen_mc_resume(rdev, &save); 2327 /* we need to own VRAM, so turn off the VGA renderer here 2328 * to stop it overwriting our objects */ 2329 rv515_vga_render_disable(rdev); 2330 } 2331 2332 /* SI MC address space is 40 bits */ 2333 static void si_vram_location(struct radeon_device *rdev, 2334 struct radeon_mc *mc, u64 base) 2335 { 2336 mc->vram_start = base; 2337 if (mc->mc_vram_size > (0xFFFFFFFFFFULL - base + 1)) { 2338 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 2339 mc->real_vram_size = mc->aper_size; 2340 mc->mc_vram_size = mc->aper_size; 2341 } 2342 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 2343 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 2344 mc->mc_vram_size >> 20, mc->vram_start, 2345 mc->vram_end, mc->real_vram_size >> 20); 2346 } 2347 2348 static void si_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 2349 { 2350 u64 size_af, size_bf; 2351 2352 size_af = ((0xFFFFFFFFFFULL - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 2353 size_bf = mc->vram_start & ~mc->gtt_base_align; 2354 if (size_bf > size_af) { 2355 if (mc->gtt_size > size_bf) { 2356 dev_warn(rdev->dev, "limiting GTT\n"); 2357 mc->gtt_size = size_bf; 2358 } 2359 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 2360 } else { 2361 if (mc->gtt_size > size_af) { 2362 dev_warn(rdev->dev, "limiting GTT\n"); 2363 mc->gtt_size = size_af; 2364 } 2365 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 2366 } 2367 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 2368 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 2369 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 2370 } 2371 2372 void 2373 si_vram_gtt_location(struct radeon_device *rdev, 2374 struct radeon_mc *mc) 2375 { 2376 if (mc->mc_vram_size > 0xFFC0000000ULL) { 2377 /* leave room for at least 1024M GTT */ 2378 dev_warn(rdev->dev, "limiting VRAM\n"); 2379 mc->real_vram_size = 0xFFC0000000ULL; 2380 mc->mc_vram_size = 0xFFC0000000ULL; 2381 } 2382 si_vram_location(rdev, &rdev->mc, 0); 2383 rdev->mc.gtt_base_align = 0; 2384 si_gtt_location(rdev, mc); 2385 } 2386 2387 static int si_mc_init(struct radeon_device *rdev) 2388 { 2389 u32 tmp; 2390 int chansize, numchan; 2391 2392 /* Get VRAM informations */ 2393 rdev->mc.vram_is_ddr = true; 2394 tmp = RREG32(MC_ARB_RAMCFG); 2395 if (tmp & CHANSIZE_OVERRIDE) { 2396 chansize = 16; 2397 } else if (tmp & CHANSIZE_MASK) { 2398 chansize = 64; 2399 } else { 2400 chansize = 32; 2401 } 2402 tmp = RREG32(MC_SHARED_CHMAP); 2403 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 2404 case 0: 2405 default: 2406 numchan = 1; 2407 break; 2408 case 1: 2409 numchan = 2; 2410 break; 2411 case 2: 2412 numchan = 4; 2413 break; 2414 case 3: 2415 numchan = 8; 2416 break; 2417 case 4: 2418 numchan = 3; 2419 break; 2420 case 5: 2421 numchan = 6; 2422 break; 2423 case 6: 2424 numchan = 10; 2425 break; 2426 case 7: 2427 numchan = 12; 2428 break; 2429 case 8: 2430 numchan = 16; 2431 break; 2432 } 2433 rdev->mc.vram_width = numchan * chansize; 2434 /* Could aper size report 0 ? */ 2435 rdev->mc.aper_base = rdev->fb_aper_offset; 2436 rdev->mc.aper_size = rdev->fb_aper_size; 2437 /* size in MB on si */ 2438 tmp = RREG32(CONFIG_MEMSIZE); 2439 /* some boards may have garbage in the upper 16 bits */ 2440 if (tmp & 0xffff0000) { 2441 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); 2442 if (tmp & 0xffff) 2443 tmp &= 0xffff; 2444 } 2445 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL; 2446 rdev->mc.real_vram_size = rdev->mc.mc_vram_size; 2447 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2448 si_vram_gtt_location(rdev, &rdev->mc); 2449 radeon_update_bandwidth_info(rdev); 2450 2451 return 0; 2452 } 2453 2454 /* 2455 * GART 2456 */ 2457 void si_pcie_gart_tlb_flush(struct radeon_device *rdev) 2458 { 2459 /* flush hdp cache */ 2460 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 2461 2462 /* bits 0-15 are the VM contexts0-15 */ 2463 WREG32(VM_INVALIDATE_REQUEST, 1); 2464 } 2465 2466 static int si_pcie_gart_enable(struct radeon_device *rdev) 2467 { 2468 int r, i; 2469 2470 if (rdev->gart.robj == NULL) { 2471 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 2472 return -EINVAL; 2473 } 2474 r = radeon_gart_table_vram_pin(rdev); 2475 if (r) 2476 return r; 2477 radeon_gart_restore(rdev); 2478 /* Setup TLB control */ 2479 WREG32(MC_VM_MX_L1_TLB_CNTL, 2480 (0xA << 7) | 2481 ENABLE_L1_TLB | 2482 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2483 ENABLE_ADVANCED_DRIVER_MODEL | 2484 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2485 /* Setup L2 cache */ 2486 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | 2487 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2488 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2489 EFFECTIVE_L2_QUEUE_SIZE(7) | 2490 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2491 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); 2492 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2493 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2494 /* setup context0 */ 2495 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 2496 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 2497 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 2498 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 2499 (u32)(rdev->dummy_page.addr >> 12)); 2500 WREG32(VM_CONTEXT0_CNTL2, 0); 2501 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 2502 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)); 2503 2504 WREG32(0x15D4, 0); 2505 WREG32(0x15D8, 0); 2506 WREG32(0x15DC, 0); 2507 2508 /* empty context1-15 */ 2509 /* set vm size, must be a multiple of 4 */ 2510 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 2511 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn); 2512 /* Assign the pt base to something valid for now; the pts used for 2513 * the VMs are determined by the application and setup and assigned 2514 * on the fly in the vm part of radeon_gart.c 2515 */ 2516 for (i = 1; i < 16; i++) { 2517 if (i < 8) 2518 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 2519 rdev->gart.table_addr >> 12); 2520 else 2521 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), 2522 rdev->gart.table_addr >> 12); 2523 } 2524 2525 /* enable context1-15 */ 2526 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 2527 (u32)(rdev->dummy_page.addr >> 12)); 2528 WREG32(VM_CONTEXT1_CNTL2, 4); 2529 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | 2530 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2531 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2532 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2533 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT | 2534 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT | 2535 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT | 2536 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT | 2537 VALID_PROTECTION_FAULT_ENABLE_DEFAULT | 2538 READ_PROTECTION_FAULT_ENABLE_INTERRUPT | 2539 READ_PROTECTION_FAULT_ENABLE_DEFAULT | 2540 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT | 2541 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT); 2542 2543 si_pcie_gart_tlb_flush(rdev); 2544 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 2545 (unsigned)(rdev->mc.gtt_size >> 20), 2546 (unsigned long long)rdev->gart.table_addr); 2547 rdev->gart.ready = true; 2548 return 0; 2549 } 2550 2551 static void si_pcie_gart_disable(struct radeon_device *rdev) 2552 { 2553 /* Disable all tables */ 2554 WREG32(VM_CONTEXT0_CNTL, 0); 2555 WREG32(VM_CONTEXT1_CNTL, 0); 2556 /* Setup TLB control */ 2557 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | 2558 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); 2559 /* Setup L2 cache */ 2560 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 2561 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE | 2562 EFFECTIVE_L2_QUEUE_SIZE(7) | 2563 CONTEXT1_IDENTITY_ACCESS_MODE(1)); 2564 WREG32(VM_L2_CNTL2, 0); 2565 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | 2566 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); 2567 radeon_gart_table_vram_unpin(rdev); 2568 } 2569 2570 static void si_pcie_gart_fini(struct radeon_device *rdev) 2571 { 2572 si_pcie_gart_disable(rdev); 2573 radeon_gart_table_vram_free(rdev); 2574 radeon_gart_fini(rdev); 2575 } 2576 2577 /* vm parser */ 2578 static bool si_vm_reg_valid(u32 reg) 2579 { 2580 /* context regs are fine */ 2581 if (reg >= 0x28000) 2582 return true; 2583 2584 /* check config regs */ 2585 switch (reg) { 2586 case GRBM_GFX_INDEX: 2587 case CP_STRMOUT_CNTL: 2588 case VGT_VTX_VECT_EJECT_REG: 2589 case VGT_CACHE_INVALIDATION: 2590 case VGT_ESGS_RING_SIZE: 2591 case VGT_GSVS_RING_SIZE: 2592 case VGT_GS_VERTEX_REUSE: 2593 case VGT_PRIMITIVE_TYPE: 2594 case VGT_INDEX_TYPE: 2595 case VGT_NUM_INDICES: 2596 case VGT_NUM_INSTANCES: 2597 case VGT_TF_RING_SIZE: 2598 case VGT_HS_OFFCHIP_PARAM: 2599 case VGT_TF_MEMORY_BASE: 2600 case PA_CL_ENHANCE: 2601 case PA_SU_LINE_STIPPLE_VALUE: 2602 case PA_SC_LINE_STIPPLE_STATE: 2603 case PA_SC_ENHANCE: 2604 case SQC_CACHES: 2605 case SPI_STATIC_THREAD_MGMT_1: 2606 case SPI_STATIC_THREAD_MGMT_2: 2607 case SPI_STATIC_THREAD_MGMT_3: 2608 case SPI_PS_MAX_WAVE_ID: 2609 case SPI_CONFIG_CNTL: 2610 case SPI_CONFIG_CNTL_1: 2611 case TA_CNTL_AUX: 2612 return true; 2613 default: 2614 DRM_ERROR("Invalid register 0x%x in CS\n", reg); 2615 return false; 2616 } 2617 } 2618 2619 static int si_vm_packet3_ce_check(struct radeon_device *rdev, 2620 u32 *ib, struct radeon_cs_packet *pkt) 2621 { 2622 switch (pkt->opcode) { 2623 case PACKET3_NOP: 2624 case PACKET3_SET_BASE: 2625 case PACKET3_SET_CE_DE_COUNTERS: 2626 case PACKET3_LOAD_CONST_RAM: 2627 case PACKET3_WRITE_CONST_RAM: 2628 case PACKET3_WRITE_CONST_RAM_OFFSET: 2629 case PACKET3_DUMP_CONST_RAM: 2630 case PACKET3_INCREMENT_CE_COUNTER: 2631 case PACKET3_WAIT_ON_DE_COUNTER: 2632 case PACKET3_CE_WRITE: 2633 break; 2634 default: 2635 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode); 2636 return -EINVAL; 2637 } 2638 return 0; 2639 } 2640 2641 static int si_vm_packet3_cp_dma_check(u32 *ib, u32 idx) 2642 { 2643 u32 start_reg, reg, i; 2644 u32 command = ib[idx + 4]; 2645 u32 info = ib[idx + 1]; 2646 u32 idx_value = ib[idx]; 2647 if (command & PACKET3_CP_DMA_CMD_SAS) { 2648 /* src address space is register */ 2649 if (((info & 0x60000000) >> 29) == 0) { 2650 start_reg = idx_value << 2; 2651 if (command & PACKET3_CP_DMA_CMD_SAIC) { 2652 reg = start_reg; 2653 if (!si_vm_reg_valid(reg)) { 2654 DRM_ERROR("CP DMA Bad SRC register\n"); 2655 return -EINVAL; 2656 } 2657 } else { 2658 for (i = 0; i < (command & 0x1fffff); i++) { 2659 reg = start_reg + (4 * i); 2660 if (!si_vm_reg_valid(reg)) { 2661 DRM_ERROR("CP DMA Bad SRC register\n"); 2662 return -EINVAL; 2663 } 2664 } 2665 } 2666 } 2667 } 2668 if (command & PACKET3_CP_DMA_CMD_DAS) { 2669 /* dst address space is register */ 2670 if (((info & 0x00300000) >> 20) == 0) { 2671 start_reg = ib[idx + 2]; 2672 if (command & PACKET3_CP_DMA_CMD_DAIC) { 2673 reg = start_reg; 2674 if (!si_vm_reg_valid(reg)) { 2675 DRM_ERROR("CP DMA Bad DST register\n"); 2676 return -EINVAL; 2677 } 2678 } else { 2679 for (i = 0; i < (command & 0x1fffff); i++) { 2680 reg = start_reg + (4 * i); 2681 if (!si_vm_reg_valid(reg)) { 2682 DRM_ERROR("CP DMA Bad DST register\n"); 2683 return -EINVAL; 2684 } 2685 } 2686 } 2687 } 2688 } 2689 return 0; 2690 } 2691 2692 static int si_vm_packet3_gfx_check(struct radeon_device *rdev, 2693 u32 *ib, struct radeon_cs_packet *pkt) 2694 { 2695 int r; 2696 u32 idx = pkt->idx + 1; 2697 u32 idx_value = ib[idx]; 2698 u32 start_reg, end_reg, reg, i; 2699 2700 switch (pkt->opcode) { 2701 case PACKET3_NOP: 2702 case PACKET3_SET_BASE: 2703 case PACKET3_CLEAR_STATE: 2704 case PACKET3_INDEX_BUFFER_SIZE: 2705 case PACKET3_DISPATCH_DIRECT: 2706 case PACKET3_DISPATCH_INDIRECT: 2707 case PACKET3_ALLOC_GDS: 2708 case PACKET3_WRITE_GDS_RAM: 2709 case PACKET3_ATOMIC_GDS: 2710 case PACKET3_ATOMIC: 2711 case PACKET3_OCCLUSION_QUERY: 2712 case PACKET3_SET_PREDICATION: 2713 case PACKET3_COND_EXEC: 2714 case PACKET3_PRED_EXEC: 2715 case PACKET3_DRAW_INDIRECT: 2716 case PACKET3_DRAW_INDEX_INDIRECT: 2717 case PACKET3_INDEX_BASE: 2718 case PACKET3_DRAW_INDEX_2: 2719 case PACKET3_CONTEXT_CONTROL: 2720 case PACKET3_INDEX_TYPE: 2721 case PACKET3_DRAW_INDIRECT_MULTI: 2722 case PACKET3_DRAW_INDEX_AUTO: 2723 case PACKET3_DRAW_INDEX_IMMD: 2724 case PACKET3_NUM_INSTANCES: 2725 case PACKET3_DRAW_INDEX_MULTI_AUTO: 2726 case PACKET3_STRMOUT_BUFFER_UPDATE: 2727 case PACKET3_DRAW_INDEX_OFFSET_2: 2728 case PACKET3_DRAW_INDEX_MULTI_ELEMENT: 2729 case PACKET3_DRAW_INDEX_INDIRECT_MULTI: 2730 case PACKET3_MPEG_INDEX: 2731 case PACKET3_WAIT_REG_MEM: 2732 case PACKET3_MEM_WRITE: 2733 case PACKET3_PFP_SYNC_ME: 2734 case PACKET3_SURFACE_SYNC: 2735 case PACKET3_EVENT_WRITE: 2736 case PACKET3_EVENT_WRITE_EOP: 2737 case PACKET3_EVENT_WRITE_EOS: 2738 case PACKET3_SET_CONTEXT_REG: 2739 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2740 case PACKET3_SET_SH_REG: 2741 case PACKET3_SET_SH_REG_OFFSET: 2742 case PACKET3_INCREMENT_DE_COUNTER: 2743 case PACKET3_WAIT_ON_CE_COUNTER: 2744 case PACKET3_WAIT_ON_AVAIL_BUFFER: 2745 case PACKET3_ME_WRITE: 2746 break; 2747 case PACKET3_COPY_DATA: 2748 if ((idx_value & 0xf00) == 0) { 2749 reg = ib[idx + 3] * 4; 2750 if (!si_vm_reg_valid(reg)) 2751 return -EINVAL; 2752 } 2753 break; 2754 case PACKET3_WRITE_DATA: 2755 if ((idx_value & 0xf00) == 0) { 2756 start_reg = ib[idx + 1] * 4; 2757 if (idx_value & 0x10000) { 2758 if (!si_vm_reg_valid(start_reg)) 2759 return -EINVAL; 2760 } else { 2761 for (i = 0; i < (pkt->count - 2); i++) { 2762 reg = start_reg + (4 * i); 2763 if (!si_vm_reg_valid(reg)) 2764 return -EINVAL; 2765 } 2766 } 2767 } 2768 break; 2769 case PACKET3_COND_WRITE: 2770 if (idx_value & 0x100) { 2771 reg = ib[idx + 5] * 4; 2772 if (!si_vm_reg_valid(reg)) 2773 return -EINVAL; 2774 } 2775 break; 2776 case PACKET3_COPY_DW: 2777 if (idx_value & 0x2) { 2778 reg = ib[idx + 3] * 4; 2779 if (!si_vm_reg_valid(reg)) 2780 return -EINVAL; 2781 } 2782 break; 2783 case PACKET3_SET_CONFIG_REG: 2784 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; 2785 end_reg = 4 * pkt->count + start_reg - 4; 2786 if ((start_reg < PACKET3_SET_CONFIG_REG_START) || 2787 (start_reg >= PACKET3_SET_CONFIG_REG_END) || 2788 (end_reg >= PACKET3_SET_CONFIG_REG_END)) { 2789 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); 2790 return -EINVAL; 2791 } 2792 for (i = 0; i < pkt->count; i++) { 2793 reg = start_reg + (4 * i); 2794 if (!si_vm_reg_valid(reg)) 2795 return -EINVAL; 2796 } 2797 break; 2798 case PACKET3_CP_DMA: 2799 r = si_vm_packet3_cp_dma_check(ib, idx); 2800 if (r) 2801 return r; 2802 break; 2803 default: 2804 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); 2805 return -EINVAL; 2806 } 2807 return 0; 2808 } 2809 2810 static int si_vm_packet3_compute_check(struct radeon_device *rdev, 2811 u32 *ib, struct radeon_cs_packet *pkt) 2812 { 2813 int r; 2814 u32 idx = pkt->idx + 1; 2815 u32 idx_value = ib[idx]; 2816 u32 start_reg, reg, i; 2817 2818 switch (pkt->opcode) { 2819 case PACKET3_NOP: 2820 case PACKET3_SET_BASE: 2821 case PACKET3_CLEAR_STATE: 2822 case PACKET3_DISPATCH_DIRECT: 2823 case PACKET3_DISPATCH_INDIRECT: 2824 case PACKET3_ALLOC_GDS: 2825 case PACKET3_WRITE_GDS_RAM: 2826 case PACKET3_ATOMIC_GDS: 2827 case PACKET3_ATOMIC: 2828 case PACKET3_OCCLUSION_QUERY: 2829 case PACKET3_SET_PREDICATION: 2830 case PACKET3_COND_EXEC: 2831 case PACKET3_PRED_EXEC: 2832 case PACKET3_CONTEXT_CONTROL: 2833 case PACKET3_STRMOUT_BUFFER_UPDATE: 2834 case PACKET3_WAIT_REG_MEM: 2835 case PACKET3_MEM_WRITE: 2836 case PACKET3_PFP_SYNC_ME: 2837 case PACKET3_SURFACE_SYNC: 2838 case PACKET3_EVENT_WRITE: 2839 case PACKET3_EVENT_WRITE_EOP: 2840 case PACKET3_EVENT_WRITE_EOS: 2841 case PACKET3_SET_CONTEXT_REG: 2842 case PACKET3_SET_CONTEXT_REG_INDIRECT: 2843 case PACKET3_SET_SH_REG: 2844 case PACKET3_SET_SH_REG_OFFSET: 2845 case PACKET3_INCREMENT_DE_COUNTER: 2846 case PACKET3_WAIT_ON_CE_COUNTER: 2847 case PACKET3_WAIT_ON_AVAIL_BUFFER: 2848 case PACKET3_ME_WRITE: 2849 break; 2850 case PACKET3_COPY_DATA: 2851 if ((idx_value & 0xf00) == 0) { 2852 reg = ib[idx + 3] * 4; 2853 if (!si_vm_reg_valid(reg)) 2854 return -EINVAL; 2855 } 2856 break; 2857 case PACKET3_WRITE_DATA: 2858 if ((idx_value & 0xf00) == 0) { 2859 start_reg = ib[idx + 1] * 4; 2860 if (idx_value & 0x10000) { 2861 if (!si_vm_reg_valid(start_reg)) 2862 return -EINVAL; 2863 } else { 2864 for (i = 0; i < (pkt->count - 2); i++) { 2865 reg = start_reg + (4 * i); 2866 if (!si_vm_reg_valid(reg)) 2867 return -EINVAL; 2868 } 2869 } 2870 } 2871 break; 2872 case PACKET3_COND_WRITE: 2873 if (idx_value & 0x100) { 2874 reg = ib[idx + 5] * 4; 2875 if (!si_vm_reg_valid(reg)) 2876 return -EINVAL; 2877 } 2878 break; 2879 case PACKET3_COPY_DW: 2880 if (idx_value & 0x2) { 2881 reg = ib[idx + 3] * 4; 2882 if (!si_vm_reg_valid(reg)) 2883 return -EINVAL; 2884 } 2885 break; 2886 case PACKET3_CP_DMA: 2887 r = si_vm_packet3_cp_dma_check(ib, idx); 2888 if (r) 2889 return r; 2890 break; 2891 default: 2892 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode); 2893 return -EINVAL; 2894 } 2895 return 0; 2896 } 2897 2898 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 2899 { 2900 int ret = 0; 2901 u32 idx = 0; 2902 struct radeon_cs_packet pkt; 2903 2904 do { 2905 pkt.idx = idx; 2906 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 2907 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 2908 pkt.one_reg_wr = 0; 2909 switch (pkt.type) { 2910 case PACKET_TYPE0: 2911 dev_err(rdev->dev, "Packet0 not allowed!\n"); 2912 ret = -EINVAL; 2913 break; 2914 case PACKET_TYPE2: 2915 idx += 1; 2916 break; 2917 case PACKET_TYPE3: 2918 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 2919 if (ib->is_const_ib) 2920 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); 2921 else { 2922 switch (ib->ring) { 2923 case RADEON_RING_TYPE_GFX_INDEX: 2924 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt); 2925 break; 2926 case CAYMAN_RING_TYPE_CP1_INDEX: 2927 case CAYMAN_RING_TYPE_CP2_INDEX: 2928 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt); 2929 break; 2930 default: 2931 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring); 2932 ret = -EINVAL; 2933 break; 2934 } 2935 } 2936 idx += pkt.count + 2; 2937 break; 2938 default: 2939 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); 2940 ret = -EINVAL; 2941 break; 2942 } 2943 if (ret) 2944 break; 2945 } while (idx < ib->length_dw); 2946 2947 return ret; 2948 } 2949 2950 /* 2951 * vm 2952 */ 2953 int si_vm_init(struct radeon_device *rdev) 2954 { 2955 /* number of VMs */ 2956 rdev->vm_manager.nvm = 16; 2957 /* base offset of vram pages */ 2958 rdev->vm_manager.vram_base_offset = 0; 2959 2960 return 0; 2961 } 2962 2963 void si_vm_fini(struct radeon_device *rdev) 2964 { 2965 } 2966 2967 /** 2968 * si_vm_set_page - update the page tables using the CP 2969 * 2970 * @rdev: radeon_device pointer 2971 * @pe: addr of the page entry 2972 * @addr: dst addr to write into pe 2973 * @count: number of page entries to update 2974 * @incr: increase next addr by incr bytes 2975 * @flags: access flags 2976 * 2977 * Update the page tables using the CP (cayman-si). 2978 */ 2979 void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 2980 uint64_t addr, unsigned count, 2981 uint32_t incr, uint32_t flags) 2982 { 2983 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index]; 2984 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 2985 uint64_t value; 2986 unsigned ndw; 2987 2988 if (rdev->asic->vm.pt_ring_index == RADEON_RING_TYPE_GFX_INDEX) { 2989 while (count) { 2990 ndw = 2 + count * 2; 2991 if (ndw > 0x3FFE) 2992 ndw = 0x3FFE; 2993 2994 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw)); 2995 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 2996 WRITE_DATA_DST_SEL(1))); 2997 radeon_ring_write(ring, pe); 2998 radeon_ring_write(ring, upper_32_bits(pe)); 2999 for (; ndw > 2; ndw -= 2, --count, pe += 8) { 3000 if (flags & RADEON_VM_PAGE_SYSTEM) { 3001 value = radeon_vm_map_gart(rdev, addr); 3002 value &= 0xFFFFFFFFFFFFF000ULL; 3003 } else if (flags & RADEON_VM_PAGE_VALID) { 3004 value = addr; 3005 } else { 3006 value = 0; 3007 } 3008 addr += incr; 3009 value |= r600_flags; 3010 radeon_ring_write(ring, value); 3011 radeon_ring_write(ring, upper_32_bits(value)); 3012 } 3013 } 3014 } else { 3015 /* DMA */ 3016 if (flags & RADEON_VM_PAGE_SYSTEM) { 3017 while (count) { 3018 ndw = count * 2; 3019 if (ndw > 0xFFFFE) 3020 ndw = 0xFFFFE; 3021 3022 /* for non-physically contiguous pages (system) */ 3023 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw)); 3024 radeon_ring_write(ring, pe); 3025 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3026 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 3027 if (flags & RADEON_VM_PAGE_SYSTEM) { 3028 value = radeon_vm_map_gart(rdev, addr); 3029 value &= 0xFFFFFFFFFFFFF000ULL; 3030 } else if (flags & RADEON_VM_PAGE_VALID) { 3031 value = addr; 3032 } else { 3033 value = 0; 3034 } 3035 addr += incr; 3036 value |= r600_flags; 3037 radeon_ring_write(ring, value); 3038 radeon_ring_write(ring, upper_32_bits(value)); 3039 } 3040 } 3041 } else { 3042 while (count) { 3043 ndw = count * 2; 3044 if (ndw > 0xFFFFE) 3045 ndw = 0xFFFFE; 3046 3047 if (flags & RADEON_VM_PAGE_VALID) 3048 value = addr; 3049 else 3050 value = 0; 3051 /* for physically contiguous pages (vram) */ 3052 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw)); 3053 radeon_ring_write(ring, pe); /* dst addr */ 3054 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3055 radeon_ring_write(ring, r600_flags); /* mask */ 3056 radeon_ring_write(ring, 0); 3057 radeon_ring_write(ring, value); /* value */ 3058 radeon_ring_write(ring, upper_32_bits(value)); 3059 radeon_ring_write(ring, incr); /* increment size */ 3060 radeon_ring_write(ring, 0); 3061 pe += ndw * 4; 3062 addr += (ndw / 2) * incr; 3063 count -= ndw / 2; 3064 } 3065 } 3066 } 3067 } 3068 3069 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3070 { 3071 struct radeon_ring *ring = &rdev->ring[ridx]; 3072 3073 if (vm == NULL) 3074 return; 3075 3076 /* write new base address */ 3077 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3078 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3079 WRITE_DATA_DST_SEL(0))); 3080 3081 if (vm->id < 8) { 3082 radeon_ring_write(ring, 3083 (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); 3084 } else { 3085 radeon_ring_write(ring, 3086 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); 3087 } 3088 radeon_ring_write(ring, 0); 3089 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3090 3091 /* flush hdp cache */ 3092 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3093 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3094 WRITE_DATA_DST_SEL(0))); 3095 radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); 3096 radeon_ring_write(ring, 0); 3097 radeon_ring_write(ring, 0x1); 3098 3099 /* bits 0-15 are the VM contexts0-15 */ 3100 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3101 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3102 WRITE_DATA_DST_SEL(0))); 3103 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); 3104 radeon_ring_write(ring, 0); 3105 radeon_ring_write(ring, 1 << vm->id); 3106 3107 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 3108 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 3109 radeon_ring_write(ring, 0x0); 3110 } 3111 3112 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) 3113 { 3114 struct radeon_ring *ring = &rdev->ring[ridx]; 3115 3116 if (vm == NULL) 3117 return; 3118 3119 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3120 if (vm->id < 8) { 3121 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2)); 3122 } else { 3123 radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2)); 3124 } 3125 radeon_ring_write(ring, vm->pd_gpu_addr >> 12); 3126 3127 /* flush hdp cache */ 3128 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3129 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); 3130 radeon_ring_write(ring, 1); 3131 3132 /* bits 0-7 are the VM contexts0-7 */ 3133 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); 3134 radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); 3135 radeon_ring_write(ring, 1 << vm->id); 3136 } 3137 3138 /* 3139 * RLC 3140 */ 3141 void si_rlc_fini(struct radeon_device *rdev) 3142 { 3143 int r; 3144 3145 /* save restore block */ 3146 if (rdev->rlc.save_restore_obj) { 3147 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3148 if (unlikely(r != 0)) 3149 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); 3150 radeon_bo_unpin(rdev->rlc.save_restore_obj); 3151 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3152 3153 radeon_bo_unref(&rdev->rlc.save_restore_obj); 3154 rdev->rlc.save_restore_obj = NULL; 3155 } 3156 3157 /* clear state block */ 3158 if (rdev->rlc.clear_state_obj) { 3159 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3160 if (unlikely(r != 0)) 3161 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); 3162 radeon_bo_unpin(rdev->rlc.clear_state_obj); 3163 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3164 3165 radeon_bo_unref(&rdev->rlc.clear_state_obj); 3166 rdev->rlc.clear_state_obj = NULL; 3167 } 3168 } 3169 3170 int si_rlc_init(struct radeon_device *rdev) 3171 { 3172 int r; 3173 3174 /* save restore block */ 3175 if (rdev->rlc.save_restore_obj == NULL) { 3176 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3177 RADEON_GEM_DOMAIN_VRAM, NULL, 3178 &rdev->rlc.save_restore_obj); 3179 if (r) { 3180 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); 3181 return r; 3182 } 3183 } 3184 3185 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); 3186 if (unlikely(r != 0)) { 3187 si_rlc_fini(rdev); 3188 return r; 3189 } 3190 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, 3191 &rdev->rlc.save_restore_gpu_addr); 3192 radeon_bo_unreserve(rdev->rlc.save_restore_obj); 3193 if (r) { 3194 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); 3195 si_rlc_fini(rdev); 3196 return r; 3197 } 3198 3199 /* clear state block */ 3200 if (rdev->rlc.clear_state_obj == NULL) { 3201 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 3202 RADEON_GEM_DOMAIN_VRAM, NULL, 3203 &rdev->rlc.clear_state_obj); 3204 if (r) { 3205 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); 3206 si_rlc_fini(rdev); 3207 return r; 3208 } 3209 } 3210 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); 3211 if (unlikely(r != 0)) { 3212 si_rlc_fini(rdev); 3213 return r; 3214 } 3215 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, 3216 &rdev->rlc.clear_state_gpu_addr); 3217 radeon_bo_unreserve(rdev->rlc.clear_state_obj); 3218 if (r) { 3219 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); 3220 si_rlc_fini(rdev); 3221 return r; 3222 } 3223 3224 return 0; 3225 } 3226 3227 static void si_rlc_stop(struct radeon_device *rdev) 3228 { 3229 WREG32(RLC_CNTL, 0); 3230 } 3231 3232 void 3233 si_rlc_start(struct radeon_device *rdev) 3234 { 3235 WREG32(RLC_CNTL, RLC_ENABLE); 3236 } 3237 3238 static int si_rlc_resume(struct radeon_device *rdev) 3239 { 3240 u32 i; 3241 const __be32 *fw_data; 3242 3243 if (!rdev->rlc_fw) 3244 return -EINVAL; 3245 3246 si_rlc_stop(rdev); 3247 3248 WREG32(RLC_RL_BASE, 0); 3249 WREG32(RLC_RL_SIZE, 0); 3250 WREG32(RLC_LB_CNTL, 0); 3251 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); 3252 WREG32(RLC_LB_CNTR_INIT, 0); 3253 3254 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3255 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3256 3257 WREG32(RLC_MC_CNTL, 0); 3258 WREG32(RLC_UCODE_CNTL, 0); 3259 3260 fw_data = (const __be32 *)rdev->rlc_fw; 3261 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) { 3262 WREG32(RLC_UCODE_ADDR, i); 3263 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3264 } 3265 WREG32(RLC_UCODE_ADDR, 0); 3266 3267 si_rlc_start(rdev); 3268 3269 return 0; 3270 } 3271 3272 static void si_enable_interrupts(struct radeon_device *rdev) 3273 { 3274 u32 ih_cntl = RREG32(IH_CNTL); 3275 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3276 3277 ih_cntl |= ENABLE_INTR; 3278 ih_rb_cntl |= IH_RB_ENABLE; 3279 WREG32(IH_CNTL, ih_cntl); 3280 WREG32(IH_RB_CNTL, ih_rb_cntl); 3281 rdev->ih.enabled = true; 3282 } 3283 3284 static void si_disable_interrupts(struct radeon_device *rdev) 3285 { 3286 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3287 u32 ih_cntl = RREG32(IH_CNTL); 3288 3289 ih_rb_cntl &= ~IH_RB_ENABLE; 3290 ih_cntl &= ~ENABLE_INTR; 3291 WREG32(IH_RB_CNTL, ih_rb_cntl); 3292 WREG32(IH_CNTL, ih_cntl); 3293 /* set rptr, wptr to 0 */ 3294 WREG32(IH_RB_RPTR, 0); 3295 WREG32(IH_RB_WPTR, 0); 3296 rdev->ih.enabled = false; 3297 rdev->ih.rptr = 0; 3298 } 3299 3300 static void si_disable_interrupt_state(struct radeon_device *rdev) 3301 { 3302 u32 tmp; 3303 3304 WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3305 WREG32(CP_INT_CNTL_RING1, 0); 3306 WREG32(CP_INT_CNTL_RING2, 0); 3307 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3308 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); 3309 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3310 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 3311 WREG32(GRBM_INT_CNTL, 0); 3312 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3313 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3314 if (rdev->num_crtc >= 4) { 3315 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3316 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3317 } 3318 if (rdev->num_crtc >= 6) { 3319 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3320 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3321 } 3322 3323 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3324 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3325 if (rdev->num_crtc >= 4) { 3326 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3327 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3328 } 3329 if (rdev->num_crtc >= 6) { 3330 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3331 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3332 } 3333 3334 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3335 3336 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3337 WREG32(DC_HPD1_INT_CONTROL, tmp); 3338 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3339 WREG32(DC_HPD2_INT_CONTROL, tmp); 3340 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3341 WREG32(DC_HPD3_INT_CONTROL, tmp); 3342 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3343 WREG32(DC_HPD4_INT_CONTROL, tmp); 3344 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3345 WREG32(DC_HPD5_INT_CONTROL, tmp); 3346 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3347 WREG32(DC_HPD6_INT_CONTROL, tmp); 3348 3349 } 3350 3351 static int si_irq_init(struct radeon_device *rdev) 3352 { 3353 int ret = 0; 3354 int rb_bufsz; 3355 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3356 3357 /* allocate ring */ 3358 ret = r600_ih_ring_alloc(rdev); 3359 if (ret) 3360 return ret; 3361 3362 /* disable irqs */ 3363 si_disable_interrupts(rdev); 3364 3365 /* init rlc */ 3366 ret = si_rlc_resume(rdev); 3367 if (ret) { 3368 r600_ih_ring_fini(rdev); 3369 return ret; 3370 } 3371 3372 /* setup interrupt control */ 3373 /* set dummy read address to ring address */ 3374 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3375 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3376 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3377 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3378 */ 3379 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3380 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3381 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3382 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3383 3384 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3385 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3386 3387 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3388 IH_WPTR_OVERFLOW_CLEAR | 3389 (rb_bufsz << 1)); 3390 3391 if (rdev->wb.enabled) 3392 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3393 3394 /* set the writeback address whether it's enabled or not */ 3395 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3396 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3397 3398 WREG32(IH_RB_CNTL, ih_rb_cntl); 3399 3400 /* set rptr, wptr to 0 */ 3401 WREG32(IH_RB_RPTR, 0); 3402 WREG32(IH_RB_WPTR, 0); 3403 3404 /* Default settings for IH_CNTL (disabled at first) */ 3405 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); 3406 /* RPTR_REARM only works if msi's are enabled */ 3407 if (rdev->msi_enabled) 3408 ih_cntl |= RPTR_REARM; 3409 WREG32(IH_CNTL, ih_cntl); 3410 3411 /* force the active interrupt state to all disabled */ 3412 si_disable_interrupt_state(rdev); 3413 3414 #ifdef notyet 3415 pci_set_master(rdev->pdev); 3416 #endif 3417 3418 /* enable irqs */ 3419 si_enable_interrupts(rdev); 3420 3421 return ret; 3422 } 3423 3424 int si_irq_set(struct radeon_device *rdev) 3425 { 3426 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3427 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; 3428 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 3429 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 3430 u32 grbm_int_cntl = 0; 3431 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; 3432 u32 dma_cntl, dma_cntl1; 3433 3434 if (!rdev->irq.installed) { 3435 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3436 return -EINVAL; 3437 } 3438 /* don't enable anything if the ih is disabled */ 3439 if (!rdev->ih.enabled) { 3440 si_disable_interrupts(rdev); 3441 /* force the active interrupt state to all disabled */ 3442 si_disable_interrupt_state(rdev); 3443 return 0; 3444 } 3445 3446 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3447 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3448 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3449 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3450 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3451 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3452 3453 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; 3454 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 3455 3456 /* enable CP interrupts on all rings */ 3457 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3458 DRM_DEBUG("si_irq_set: sw int gfx\n"); 3459 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3460 } 3461 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { 3462 DRM_DEBUG("si_irq_set: sw int cp1\n"); 3463 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; 3464 } 3465 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { 3466 DRM_DEBUG("si_irq_set: sw int cp2\n"); 3467 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; 3468 } 3469 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3470 DRM_DEBUG("si_irq_set: sw int dma\n"); 3471 dma_cntl |= TRAP_ENABLE; 3472 } 3473 3474 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { 3475 DRM_DEBUG("si_irq_set: sw int dma1\n"); 3476 dma_cntl1 |= TRAP_ENABLE; 3477 } 3478 if (rdev->irq.crtc_vblank_int[0] || 3479 atomic_read(&rdev->irq.pflip[0])) { 3480 DRM_DEBUG("si_irq_set: vblank 0\n"); 3481 crtc1 |= VBLANK_INT_MASK; 3482 } 3483 if (rdev->irq.crtc_vblank_int[1] || 3484 atomic_read(&rdev->irq.pflip[1])) { 3485 DRM_DEBUG("si_irq_set: vblank 1\n"); 3486 crtc2 |= VBLANK_INT_MASK; 3487 } 3488 if (rdev->irq.crtc_vblank_int[2] || 3489 atomic_read(&rdev->irq.pflip[2])) { 3490 DRM_DEBUG("si_irq_set: vblank 2\n"); 3491 crtc3 |= VBLANK_INT_MASK; 3492 } 3493 if (rdev->irq.crtc_vblank_int[3] || 3494 atomic_read(&rdev->irq.pflip[3])) { 3495 DRM_DEBUG("si_irq_set: vblank 3\n"); 3496 crtc4 |= VBLANK_INT_MASK; 3497 } 3498 if (rdev->irq.crtc_vblank_int[4] || 3499 atomic_read(&rdev->irq.pflip[4])) { 3500 DRM_DEBUG("si_irq_set: vblank 4\n"); 3501 crtc5 |= VBLANK_INT_MASK; 3502 } 3503 if (rdev->irq.crtc_vblank_int[5] || 3504 atomic_read(&rdev->irq.pflip[5])) { 3505 DRM_DEBUG("si_irq_set: vblank 5\n"); 3506 crtc6 |= VBLANK_INT_MASK; 3507 } 3508 if (rdev->irq.hpd[0]) { 3509 DRM_DEBUG("si_irq_set: hpd 1\n"); 3510 hpd1 |= DC_HPDx_INT_EN; 3511 } 3512 if (rdev->irq.hpd[1]) { 3513 DRM_DEBUG("si_irq_set: hpd 2\n"); 3514 hpd2 |= DC_HPDx_INT_EN; 3515 } 3516 if (rdev->irq.hpd[2]) { 3517 DRM_DEBUG("si_irq_set: hpd 3\n"); 3518 hpd3 |= DC_HPDx_INT_EN; 3519 } 3520 if (rdev->irq.hpd[3]) { 3521 DRM_DEBUG("si_irq_set: hpd 4\n"); 3522 hpd4 |= DC_HPDx_INT_EN; 3523 } 3524 if (rdev->irq.hpd[4]) { 3525 DRM_DEBUG("si_irq_set: hpd 5\n"); 3526 hpd5 |= DC_HPDx_INT_EN; 3527 } 3528 if (rdev->irq.hpd[5]) { 3529 DRM_DEBUG("si_irq_set: hpd 6\n"); 3530 hpd6 |= DC_HPDx_INT_EN; 3531 } 3532 3533 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); 3534 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); 3535 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); 3536 3537 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); 3538 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); 3539 3540 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3541 3542 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 3543 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 3544 if (rdev->num_crtc >= 4) { 3545 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 3546 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 3547 } 3548 if (rdev->num_crtc >= 6) { 3549 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 3550 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 3551 } 3552 3553 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); 3554 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); 3555 if (rdev->num_crtc >= 4) { 3556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); 3557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); 3558 } 3559 if (rdev->num_crtc >= 6) { 3560 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); 3561 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); 3562 } 3563 3564 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3565 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3566 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3567 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3568 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3569 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3570 3571 return 0; 3572 } 3573 3574 static inline void si_irq_ack(struct radeon_device *rdev) 3575 { 3576 u32 tmp; 3577 3578 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3579 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3580 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 3581 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 3582 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 3583 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 3584 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); 3585 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); 3586 if (rdev->num_crtc >= 4) { 3587 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); 3588 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); 3589 } 3590 if (rdev->num_crtc >= 6) { 3591 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); 3592 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); 3593 } 3594 3595 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) 3596 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3597 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) 3598 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3599 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) 3600 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 3601 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) 3602 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 3603 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) 3604 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 3605 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) 3606 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 3607 3608 if (rdev->num_crtc >= 4) { 3609 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) 3610 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3611 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) 3612 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3613 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 3614 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 3615 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 3616 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 3617 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 3618 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 3619 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 3620 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 3621 } 3622 3623 if (rdev->num_crtc >= 6) { 3624 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) 3625 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3626 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) 3627 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); 3628 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 3629 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 3630 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 3631 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 3632 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 3633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 3634 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 3635 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 3636 } 3637 3638 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3639 tmp = RREG32(DC_HPD1_INT_CONTROL); 3640 tmp |= DC_HPDx_INT_ACK; 3641 WREG32(DC_HPD1_INT_CONTROL, tmp); 3642 } 3643 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3644 tmp = RREG32(DC_HPD2_INT_CONTROL); 3645 tmp |= DC_HPDx_INT_ACK; 3646 WREG32(DC_HPD2_INT_CONTROL, tmp); 3647 } 3648 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3649 tmp = RREG32(DC_HPD3_INT_CONTROL); 3650 tmp |= DC_HPDx_INT_ACK; 3651 WREG32(DC_HPD3_INT_CONTROL, tmp); 3652 } 3653 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3654 tmp = RREG32(DC_HPD4_INT_CONTROL); 3655 tmp |= DC_HPDx_INT_ACK; 3656 WREG32(DC_HPD4_INT_CONTROL, tmp); 3657 } 3658 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3659 tmp = RREG32(DC_HPD5_INT_CONTROL); 3660 tmp |= DC_HPDx_INT_ACK; 3661 WREG32(DC_HPD5_INT_CONTROL, tmp); 3662 } 3663 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3664 tmp = RREG32(DC_HPD5_INT_CONTROL); 3665 tmp |= DC_HPDx_INT_ACK; 3666 WREG32(DC_HPD6_INT_CONTROL, tmp); 3667 } 3668 } 3669 3670 static void si_irq_disable(struct radeon_device *rdev) 3671 { 3672 si_disable_interrupts(rdev); 3673 /* Wait and acknowledge irq */ 3674 mdelay(1); 3675 si_irq_ack(rdev); 3676 si_disable_interrupt_state(rdev); 3677 } 3678 3679 static void si_irq_suspend(struct radeon_device *rdev) 3680 { 3681 si_irq_disable(rdev); 3682 si_rlc_stop(rdev); 3683 } 3684 3685 static void si_irq_fini(struct radeon_device *rdev) 3686 { 3687 si_irq_suspend(rdev); 3688 r600_ih_ring_fini(rdev); 3689 } 3690 3691 static inline u32 si_get_ih_wptr(struct radeon_device *rdev) 3692 { 3693 u32 wptr, tmp; 3694 3695 if (rdev->wb.enabled) 3696 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3697 else 3698 wptr = RREG32(IH_RB_WPTR); 3699 3700 if (wptr & RB_OVERFLOW) { 3701 /* When a ring buffer overflow happen start parsing interrupt 3702 * from the last not overwritten vector (wptr + 16). Hopefully 3703 * this should allow us to catchup. 3704 */ 3705 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3706 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3707 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3708 tmp = RREG32(IH_RB_CNTL); 3709 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3710 WREG32(IH_RB_CNTL, tmp); 3711 } 3712 return (wptr & rdev->ih.ptr_mask); 3713 } 3714 3715 /* SI IV Ring 3716 * Each IV ring entry is 128 bits: 3717 * [7:0] - interrupt source id 3718 * [31:8] - reserved 3719 * [59:32] - interrupt source data 3720 * [63:60] - reserved 3721 * [71:64] - RINGID 3722 * [79:72] - VMID 3723 * [127:80] - reserved 3724 */ 3725 int si_irq_process(struct radeon_device *rdev) 3726 { 3727 u32 wptr; 3728 u32 rptr; 3729 u32 src_id, src_data, ring_id; 3730 u32 ring_index; 3731 bool queue_hotplug = false; 3732 3733 if (!rdev->ih.enabled || rdev->shutdown) 3734 return (0); 3735 3736 wptr = si_get_ih_wptr(rdev); 3737 3738 if (wptr == rdev->ih.rptr) 3739 return (0); 3740 restart_ih: 3741 /* is somebody else already processing irqs? */ 3742 if (atomic_xchg(&rdev->ih.lock, 1)) 3743 return (0); 3744 3745 rptr = rdev->ih.rptr; 3746 DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3747 3748 /* Order reading of wptr vs. reading of IH ring data */ 3749 DRM_READMEMORYBARRIER(); 3750 3751 /* display interrupts */ 3752 si_irq_ack(rdev); 3753 3754 while (rptr != wptr) { 3755 /* wptr/rptr are in bytes! */ 3756 ring_index = rptr / 4; 3757 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3758 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3759 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; 3760 3761 switch (src_id) { 3762 case 1: /* D1 vblank/vline */ 3763 switch (src_data) { 3764 case 0: /* D1 vblank */ 3765 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { 3766 if (rdev->irq.crtc_vblank_int[0]) { 3767 drm_handle_vblank(rdev->ddev, 0); 3768 rdev->pm.vblank_sync = true; 3769 wakeup(&rdev->irq.vblank_queue); 3770 } 3771 if (atomic_read(&rdev->irq.pflip[0])) 3772 radeon_crtc_handle_flip(rdev, 0); 3773 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3774 DRM_DEBUG("IH: D1 vblank\n"); 3775 } 3776 break; 3777 case 1: /* D1 vline */ 3778 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { 3779 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3780 DRM_DEBUG("IH: D1 vline\n"); 3781 } 3782 break; 3783 default: 3784 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3785 break; 3786 } 3787 break; 3788 case 2: /* D2 vblank/vline */ 3789 switch (src_data) { 3790 case 0: /* D2 vblank */ 3791 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 3792 if (rdev->irq.crtc_vblank_int[1]) { 3793 drm_handle_vblank(rdev->ddev, 1); 3794 rdev->pm.vblank_sync = true; 3795 wakeup(&rdev->irq.vblank_queue); 3796 } 3797 if (atomic_read(&rdev->irq.pflip[1])) 3798 radeon_crtc_handle_flip(rdev, 1); 3799 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 3800 DRM_DEBUG("IH: D2 vblank\n"); 3801 } 3802 break; 3803 case 1: /* D2 vline */ 3804 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { 3805 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 3806 DRM_DEBUG("IH: D2 vline\n"); 3807 } 3808 break; 3809 default: 3810 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3811 break; 3812 } 3813 break; 3814 case 3: /* D3 vblank/vline */ 3815 switch (src_data) { 3816 case 0: /* D3 vblank */ 3817 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 3818 if (rdev->irq.crtc_vblank_int[2]) { 3819 drm_handle_vblank(rdev->ddev, 2); 3820 rdev->pm.vblank_sync = true; 3821 wakeup(&rdev->irq.vblank_queue); 3822 } 3823 if (atomic_read(&rdev->irq.pflip[2])) 3824 radeon_crtc_handle_flip(rdev, 2); 3825 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 3826 DRM_DEBUG("IH: D3 vblank\n"); 3827 } 3828 break; 3829 case 1: /* D3 vline */ 3830 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 3831 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 3832 DRM_DEBUG("IH: D3 vline\n"); 3833 } 3834 break; 3835 default: 3836 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3837 break; 3838 } 3839 break; 3840 case 4: /* D4 vblank/vline */ 3841 switch (src_data) { 3842 case 0: /* D4 vblank */ 3843 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 3844 if (rdev->irq.crtc_vblank_int[3]) { 3845 drm_handle_vblank(rdev->ddev, 3); 3846 rdev->pm.vblank_sync = true; 3847 wakeup(&rdev->irq.vblank_queue); 3848 } 3849 if (atomic_read(&rdev->irq.pflip[3])) 3850 radeon_crtc_handle_flip(rdev, 3); 3851 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 3852 DRM_DEBUG("IH: D4 vblank\n"); 3853 } 3854 break; 3855 case 1: /* D4 vline */ 3856 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 3857 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 3858 DRM_DEBUG("IH: D4 vline\n"); 3859 } 3860 break; 3861 default: 3862 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3863 break; 3864 } 3865 break; 3866 case 5: /* D5 vblank/vline */ 3867 switch (src_data) { 3868 case 0: /* D5 vblank */ 3869 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 3870 if (rdev->irq.crtc_vblank_int[4]) { 3871 drm_handle_vblank(rdev->ddev, 4); 3872 rdev->pm.vblank_sync = true; 3873 wakeup(&rdev->irq.vblank_queue); 3874 } 3875 if (atomic_read(&rdev->irq.pflip[4])) 3876 radeon_crtc_handle_flip(rdev, 4); 3877 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 3878 DRM_DEBUG("IH: D5 vblank\n"); 3879 } 3880 break; 3881 case 1: /* D5 vline */ 3882 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 3883 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 3884 DRM_DEBUG("IH: D5 vline\n"); 3885 } 3886 break; 3887 default: 3888 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3889 break; 3890 } 3891 break; 3892 case 6: /* D6 vblank/vline */ 3893 switch (src_data) { 3894 case 0: /* D6 vblank */ 3895 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 3896 if (rdev->irq.crtc_vblank_int[5]) { 3897 drm_handle_vblank(rdev->ddev, 5); 3898 rdev->pm.vblank_sync = true; 3899 wakeup(&rdev->irq.vblank_queue); 3900 } 3901 if (atomic_read(&rdev->irq.pflip[5])) 3902 radeon_crtc_handle_flip(rdev, 5); 3903 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 3904 DRM_DEBUG("IH: D6 vblank\n"); 3905 } 3906 break; 3907 case 1: /* D6 vline */ 3908 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 3909 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 3910 DRM_DEBUG("IH: D6 vline\n"); 3911 } 3912 break; 3913 default: 3914 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3915 break; 3916 } 3917 break; 3918 case 42: /* HPD hotplug */ 3919 switch (src_data) { 3920 case 0: 3921 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { 3922 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; 3923 queue_hotplug = true; 3924 DRM_DEBUG("IH: HPD1\n"); 3925 } 3926 break; 3927 case 1: 3928 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { 3929 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; 3930 queue_hotplug = true; 3931 DRM_DEBUG("IH: HPD2\n"); 3932 } 3933 break; 3934 case 2: 3935 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { 3936 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 3937 queue_hotplug = true; 3938 DRM_DEBUG("IH: HPD3\n"); 3939 } 3940 break; 3941 case 3: 3942 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { 3943 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 3944 queue_hotplug = true; 3945 DRM_DEBUG("IH: HPD4\n"); 3946 } 3947 break; 3948 case 4: 3949 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { 3950 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 3951 queue_hotplug = true; 3952 DRM_DEBUG("IH: HPD5\n"); 3953 } 3954 break; 3955 case 5: 3956 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { 3957 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 3958 queue_hotplug = true; 3959 DRM_DEBUG("IH: HPD6\n"); 3960 } 3961 break; 3962 default: 3963 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3964 break; 3965 } 3966 break; 3967 case 146: 3968 case 147: 3969 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); 3970 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 3971 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 3972 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 3973 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 3974 /* reset addr and status */ 3975 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); 3976 break; 3977 case 176: /* RINGID0 CP_INT */ 3978 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3979 break; 3980 case 177: /* RINGID1 CP_INT */ 3981 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 3982 break; 3983 case 178: /* RINGID2 CP_INT */ 3984 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 3985 break; 3986 case 181: /* CP EOP event */ 3987 DRM_DEBUG("IH: CP EOP\n"); 3988 switch (ring_id) { 3989 case 0: 3990 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 3991 break; 3992 case 1: 3993 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 3994 break; 3995 case 2: 3996 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 3997 break; 3998 } 3999 break; 4000 case 224: /* DMA trap event */ 4001 DRM_DEBUG("IH: DMA trap\n"); 4002 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4003 break; 4004 case 233: /* GUI IDLE */ 4005 DRM_DEBUG("IH: GUI idle\n"); 4006 break; 4007 case 244: /* DMA trap event */ 4008 DRM_DEBUG("IH: DMA1 trap\n"); 4009 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4010 break; 4011 default: 4012 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4013 break; 4014 } 4015 4016 /* wptr/rptr are in bytes! */ 4017 rptr += 16; 4018 rptr &= rdev->ih.ptr_mask; 4019 } 4020 if (queue_hotplug) 4021 task_add(systq, &rdev->hotplug_task); 4022 rdev->ih.rptr = rptr; 4023 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4024 atomic_set(&rdev->ih.lock, 0); 4025 4026 /* make sure wptr hasn't changed while processing */ 4027 wptr = si_get_ih_wptr(rdev); 4028 if (wptr != rptr) 4029 goto restart_ih; 4030 4031 return (1); 4032 } 4033 4034 /** 4035 * si_copy_dma - copy pages using the DMA engine 4036 * 4037 * @rdev: radeon_device pointer 4038 * @src_offset: src GPU address 4039 * @dst_offset: dst GPU address 4040 * @num_gpu_pages: number of GPU pages to xfer 4041 * @fence: radeon fence object 4042 * 4043 * Copy GPU paging using the DMA engine (SI). 4044 * Used by the radeon ttm implementation to move pages if 4045 * registered as the asic copy callback. 4046 */ 4047 int si_copy_dma(struct radeon_device *rdev, 4048 uint64_t src_offset, uint64_t dst_offset, 4049 unsigned num_gpu_pages, 4050 struct radeon_fence **fence) 4051 { 4052 struct radeon_semaphore *sem = NULL; 4053 int ring_index = rdev->asic->copy.dma_ring_index; 4054 struct radeon_ring *ring = &rdev->ring[ring_index]; 4055 u32 size_in_bytes, cur_size_in_bytes; 4056 int i, num_loops; 4057 int r = 0; 4058 4059 r = radeon_semaphore_create(rdev, &sem); 4060 if (r) { 4061 DRM_ERROR("radeon: moving bo (%d).\n", r); 4062 return r; 4063 } 4064 4065 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); 4066 num_loops = howmany(size_in_bytes, 0xfffff); 4067 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11); 4068 if (r) { 4069 DRM_ERROR("radeon: moving bo (%d).\n", r); 4070 radeon_semaphore_free(rdev, &sem, NULL); 4071 return r; 4072 } 4073 4074 if (radeon_fence_need_sync(*fence, ring->idx)) { 4075 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 4076 ring->idx); 4077 radeon_fence_note_sync(*fence, ring->idx); 4078 } else { 4079 radeon_semaphore_free(rdev, &sem, NULL); 4080 } 4081 4082 for (i = 0; i < num_loops; i++) { 4083 cur_size_in_bytes = size_in_bytes; 4084 if (cur_size_in_bytes > 0xFFFFF) 4085 cur_size_in_bytes = 0xFFFFF; 4086 size_in_bytes -= cur_size_in_bytes; 4087 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 1, 0, 0, cur_size_in_bytes)); 4088 radeon_ring_write(ring, dst_offset & 0xffffffff); 4089 radeon_ring_write(ring, src_offset & 0xffffffff); 4090 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 4091 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); 4092 src_offset += cur_size_in_bytes; 4093 dst_offset += cur_size_in_bytes; 4094 } 4095 4096 r = radeon_fence_emit(rdev, fence, ring->idx); 4097 if (r) { 4098 radeon_ring_unlock_undo(rdev, ring); 4099 return r; 4100 } 4101 4102 radeon_ring_unlock_commit(rdev, ring); 4103 radeon_semaphore_free(rdev, &sem, *fence); 4104 4105 return r; 4106 } 4107 4108 /* 4109 * startup/shutdown callbacks 4110 */ 4111 static int si_startup(struct radeon_device *rdev) 4112 { 4113 struct radeon_ring *ring; 4114 int r; 4115 4116 si_mc_program(rdev); 4117 4118 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || 4119 !rdev->rlc_fw || !rdev->mc_fw) { 4120 r = si_init_microcode(rdev); 4121 if (r) { 4122 DRM_ERROR("Failed to load firmware!\n"); 4123 return r; 4124 } 4125 } 4126 4127 r = si_mc_load_microcode(rdev); 4128 if (r) { 4129 DRM_ERROR("Failed to load MC firmware!\n"); 4130 return r; 4131 } 4132 4133 r = r600_vram_scratch_init(rdev); 4134 if (r) 4135 return r; 4136 4137 r = si_pcie_gart_enable(rdev); 4138 if (r) 4139 return r; 4140 si_gpu_init(rdev); 4141 4142 #if 0 4143 r = evergreen_blit_init(rdev); 4144 if (r) { 4145 r600_blit_fini(rdev); 4146 rdev->asic->copy = NULL; 4147 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 4148 } 4149 #endif 4150 /* allocate rlc buffers */ 4151 r = si_rlc_init(rdev); 4152 if (r) { 4153 DRM_ERROR("Failed to init rlc BOs!\n"); 4154 return r; 4155 } 4156 4157 /* allocate wb buffer */ 4158 r = radeon_wb_init(rdev); 4159 if (r) 4160 return r; 4161 4162 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 4163 if (r) { 4164 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4165 return r; 4166 } 4167 4168 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); 4169 if (r) { 4170 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4171 return r; 4172 } 4173 4174 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); 4175 if (r) { 4176 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 4177 return r; 4178 } 4179 4180 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 4181 if (r) { 4182 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4183 return r; 4184 } 4185 4186 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); 4187 if (r) { 4188 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 4189 return r; 4190 } 4191 4192 /* Enable IRQ */ 4193 if (!rdev->irq.installed) { 4194 r = radeon_irq_kms_init(rdev); 4195 if (r) 4196 return r; 4197 } 4198 4199 r = si_irq_init(rdev); 4200 if (r) { 4201 DRM_ERROR("radeon: IH init failed (%d).\n", r); 4202 radeon_irq_kms_fini(rdev); 4203 return r; 4204 } 4205 si_irq_set(rdev); 4206 4207 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4208 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 4209 CP_RB0_RPTR, CP_RB0_WPTR, 4210 0, 0xfffff, RADEON_CP_PACKET2); 4211 if (r) 4212 return r; 4213 4214 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4215 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, 4216 CP_RB1_RPTR, CP_RB1_WPTR, 4217 0, 0xfffff, RADEON_CP_PACKET2); 4218 if (r) 4219 return r; 4220 4221 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4222 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, 4223 CP_RB2_RPTR, CP_RB2_WPTR, 4224 0, 0xfffff, RADEON_CP_PACKET2); 4225 if (r) 4226 return r; 4227 4228 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4229 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 4230 DMA_RB_RPTR + DMA0_REGISTER_OFFSET, 4231 DMA_RB_WPTR + DMA0_REGISTER_OFFSET, 4232 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4233 if (r) 4234 return r; 4235 4236 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4237 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, 4238 DMA_RB_RPTR + DMA1_REGISTER_OFFSET, 4239 DMA_RB_WPTR + DMA1_REGISTER_OFFSET, 4240 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); 4241 if (r) 4242 return r; 4243 4244 r = si_cp_load_microcode(rdev); 4245 if (r) 4246 return r; 4247 r = si_cp_resume(rdev); 4248 if (r) 4249 return r; 4250 4251 r = cayman_dma_resume(rdev); 4252 if (r) 4253 return r; 4254 4255 r = radeon_ib_pool_init(rdev); 4256 if (r) { 4257 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 4258 return r; 4259 } 4260 4261 r = radeon_vm_manager_init(rdev); 4262 if (r) { 4263 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); 4264 return r; 4265 } 4266 4267 return 0; 4268 } 4269 4270 int si_resume(struct radeon_device *rdev) 4271 { 4272 int r; 4273 4274 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw, 4275 * posting will perform necessary task to bring back GPU into good 4276 * shape. 4277 */ 4278 /* post card */ 4279 atom_asic_init(rdev->mode_info.atom_context); 4280 4281 rdev->accel_working = true; 4282 r = si_startup(rdev); 4283 if (r) { 4284 DRM_ERROR("si startup failed on resume\n"); 4285 rdev->accel_working = false; 4286 return r; 4287 } 4288 4289 return r; 4290 4291 } 4292 4293 int si_suspend(struct radeon_device *rdev) 4294 { 4295 radeon_vm_manager_fini(rdev); 4296 si_cp_enable(rdev, false); 4297 cayman_dma_stop(rdev); 4298 si_irq_suspend(rdev); 4299 radeon_wb_disable(rdev); 4300 si_pcie_gart_disable(rdev); 4301 return 0; 4302 } 4303 4304 /* Plan is to move initialization in that function and use 4305 * helper function so that radeon_device_init pretty much 4306 * do nothing more than calling asic specific function. This 4307 * should also allow to remove a bunch of callback function 4308 * like vram_info. 4309 */ 4310 int si_init(struct radeon_device *rdev) 4311 { 4312 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4313 int r; 4314 4315 /* Read BIOS */ 4316 if (!radeon_get_bios(rdev)) { 4317 if (ASIC_IS_AVIVO(rdev)) 4318 return -EINVAL; 4319 } 4320 /* Must be an ATOMBIOS */ 4321 if (!rdev->is_atom_bios) { 4322 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); 4323 return -EINVAL; 4324 } 4325 r = radeon_atombios_init(rdev); 4326 if (r) 4327 return r; 4328 4329 /* Post card if necessary */ 4330 if (!radeon_card_posted(rdev)) { 4331 if (!rdev->bios) { 4332 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 4333 return -EINVAL; 4334 } 4335 DRM_INFO("GPU not posted. posting now...\n"); 4336 atom_asic_init(rdev->mode_info.atom_context); 4337 } 4338 /* Initialize scratch registers */ 4339 si_scratch_init(rdev); 4340 /* Initialize surface registers */ 4341 radeon_surface_init(rdev); 4342 /* Initialize clocks */ 4343 radeon_get_clock_info(rdev->ddev); 4344 4345 /* Fence driver */ 4346 r = radeon_fence_driver_init(rdev); 4347 if (r) 4348 return r; 4349 4350 /* initialize memory controller */ 4351 r = si_mc_init(rdev); 4352 if (r) 4353 return r; 4354 /* Memory manager */ 4355 r = radeon_bo_init(rdev); 4356 if (r) 4357 return r; 4358 4359 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 4360 ring->ring_obj = NULL; 4361 r600_ring_init(rdev, ring, 1024 * 1024); 4362 4363 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; 4364 ring->ring_obj = NULL; 4365 r600_ring_init(rdev, ring, 1024 * 1024); 4366 4367 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; 4368 ring->ring_obj = NULL; 4369 r600_ring_init(rdev, ring, 1024 * 1024); 4370 4371 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 4372 ring->ring_obj = NULL; 4373 r600_ring_init(rdev, ring, 64 * 1024); 4374 4375 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; 4376 ring->ring_obj = NULL; 4377 r600_ring_init(rdev, ring, 64 * 1024); 4378 4379 rdev->ih.ring_obj = NULL; 4380 r600_ih_ring_init(rdev, 64 * 1024); 4381 4382 r = r600_pcie_gart_init(rdev); 4383 if (r) 4384 return r; 4385 4386 rdev->accel_working = true; 4387 r = si_startup(rdev); 4388 if (r) { 4389 dev_err(rdev->dev, "disabling GPU acceleration\n"); 4390 si_cp_fini(rdev); 4391 cayman_dma_fini(rdev); 4392 si_irq_fini(rdev); 4393 si_rlc_fini(rdev); 4394 radeon_wb_fini(rdev); 4395 radeon_ib_pool_fini(rdev); 4396 radeon_vm_manager_fini(rdev); 4397 radeon_irq_kms_fini(rdev); 4398 si_pcie_gart_fini(rdev); 4399 rdev->accel_working = false; 4400 } 4401 4402 /* Don't start up if the MC ucode is missing. 4403 * The default clocks and voltages before the MC ucode 4404 * is loaded are not suffient for advanced operations. 4405 */ 4406 if (!rdev->mc_fw) { 4407 DRM_ERROR("radeon: MC ucode required for NI+.\n"); 4408 return -EINVAL; 4409 } 4410 4411 return 0; 4412 } 4413 4414 void si_fini(struct radeon_device *rdev) 4415 { 4416 #if 0 4417 r600_blit_fini(rdev); 4418 #endif 4419 si_cp_fini(rdev); 4420 cayman_dma_fini(rdev); 4421 si_irq_fini(rdev); 4422 si_rlc_fini(rdev); 4423 radeon_wb_fini(rdev); 4424 radeon_vm_manager_fini(rdev); 4425 radeon_ib_pool_fini(rdev); 4426 radeon_irq_kms_fini(rdev); 4427 si_pcie_gart_fini(rdev); 4428 r600_vram_scratch_fini(rdev); 4429 radeon_gem_fini(rdev); 4430 radeon_fence_driver_fini(rdev); 4431 radeon_bo_fini(rdev); 4432 radeon_atombios_fini(rdev); 4433 kfree(rdev->bios); 4434 rdev->bios = NULL; 4435 } 4436 4437 /** 4438 * si_get_gpu_clock - return GPU clock counter snapshot 4439 * 4440 * @rdev: radeon_device pointer 4441 * 4442 * Fetches a GPU clock counter snapshot (SI). 4443 * Returns the 64 bit clock counter snapshot. 4444 */ 4445 uint64_t si_get_gpu_clock(struct radeon_device *rdev) 4446 { 4447 uint64_t clock; 4448 4449 rw_enter_write(&rdev->gpu_clock_rwlock); 4450 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4451 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4452 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4453 rw_exit_write(&rdev->gpu_clock_rwlock); 4454 return clock; 4455 } 4456