1 /* $OpenBSD: rs690.c,v 1.5 2015/02/11 07:01:37 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include "rs690d.h" 34 35 int rs690_mc_wait_for_idle(struct radeon_device *rdev) 36 { 37 unsigned i; 38 uint32_t tmp; 39 40 for (i = 0; i < rdev->usec_timeout; i++) { 41 /* read MC_STATUS */ 42 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS); 43 if (G_000090_MC_SYSTEM_IDLE(tmp)) 44 return 0; 45 udelay(1); 46 } 47 return -1; 48 } 49 50 static void rs690_gpu_init(struct radeon_device *rdev) 51 { 52 /* FIXME: is this correct ? */ 53 r420_pipes_init(rdev); 54 if (rs690_mc_wait_for_idle(rdev)) { 55 printk(KERN_WARNING "Failed to wait MC idle while " 56 "programming pipes. Bad things might happen.\n"); 57 } 58 } 59 60 union igp_info { 61 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 62 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2; 63 }; 64 65 void rs690_pm_info(struct radeon_device *rdev) 66 { 67 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 68 union igp_info *info; 69 uint16_t data_offset; 70 uint8_t frev, crev; 71 fixed20_12 tmp; 72 73 if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL, 74 &frev, &crev, &data_offset)) { 75 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset); 76 77 /* Get various system informations from bios */ 78 switch (crev) { 79 case 1: 80 tmp.full = dfixed_const(100); 81 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info.ulBootUpMemoryClock)); 82 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 83 if (le16_to_cpu(info->info.usK8MemoryClock)) 84 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock)); 85 else if (rdev->clock.default_mclk) { 86 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 87 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 88 } else 89 rdev->pm.igp_system_mclk.full = dfixed_const(400); 90 rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock)); 91 rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth); 92 break; 93 case 2: 94 tmp.full = dfixed_const(100); 95 rdev->pm.igp_sideport_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpSidePortClock)); 96 rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp); 97 if (le32_to_cpu(info->info_v2.ulBootUpUMAClock)) 98 rdev->pm.igp_system_mclk.full = dfixed_const(le32_to_cpu(info->info_v2.ulBootUpUMAClock)); 99 else if (rdev->clock.default_mclk) 100 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk); 101 else 102 rdev->pm.igp_system_mclk.full = dfixed_const(66700); 103 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp); 104 rdev->pm.igp_ht_link_clk.full = dfixed_const(le32_to_cpu(info->info_v2.ulHTLinkFreq)); 105 rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp); 106 rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth)); 107 break; 108 default: 109 /* We assume the slower possible clock ie worst case */ 110 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 111 rdev->pm.igp_system_mclk.full = dfixed_const(200); 112 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 113 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 114 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 115 break; 116 } 117 } else { 118 /* We assume the slower possible clock ie worst case */ 119 rdev->pm.igp_sideport_mclk.full = dfixed_const(200); 120 rdev->pm.igp_system_mclk.full = dfixed_const(200); 121 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000); 122 rdev->pm.igp_ht_link_width.full = dfixed_const(8); 123 DRM_ERROR("No integrated system info for your GPU, using safe default\n"); 124 } 125 /* Compute various bandwidth */ 126 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */ 127 tmp.full = dfixed_const(4); 128 rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp); 129 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8 130 * = ht_clk * ht_width / 5 131 */ 132 tmp.full = dfixed_const(5); 133 rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk, 134 rdev->pm.igp_ht_link_width); 135 rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp); 136 if (tmp.full < rdev->pm.max_bandwidth.full) { 137 /* HT link is a limiting factor */ 138 rdev->pm.max_bandwidth.full = tmp.full; 139 } 140 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7 141 * = (sideport_clk * 14) / 10 142 */ 143 tmp.full = dfixed_const(14); 144 rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp); 145 tmp.full = dfixed_const(10); 146 rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp); 147 } 148 149 static void rs690_mc_init(struct radeon_device *rdev) 150 { 151 u64 base; 152 153 rs400_gart_adjust_size(rdev); 154 rdev->mc.vram_is_ddr = true; 155 rdev->mc.vram_width = 128; 156 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 157 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 158 rdev->mc.aper_base = rdev->fb_aper_offset; 159 rdev->mc.aper_size = rdev->fb_aper_size; 160 rdev->mc.visible_vram_size = rdev->mc.aper_size; 161 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION); 162 base = G_000100_MC_FB_START(base) << 16; 163 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 164 /* Some boards seem to be configured for 128MB of sideport memory, 165 * but really only have 64MB. Just skip the sideport and use 166 * UMA memory. 167 */ 168 if (rdev->mc.igp_sideport_enabled && 169 (rdev->mc.real_vram_size == (384 * 1024 * 1024))) { 170 base += 128 * 1024 * 1024; 171 rdev->mc.real_vram_size -= 128 * 1024 * 1024; 172 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 173 } 174 175 rs690_pm_info(rdev); 176 radeon_vram_location(rdev, &rdev->mc, base); 177 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; 178 radeon_gtt_location(rdev, &rdev->mc); 179 radeon_update_bandwidth_info(rdev); 180 } 181 182 void rs690_line_buffer_adjust(struct radeon_device *rdev, 183 struct drm_display_mode *mode1, 184 struct drm_display_mode *mode2) 185 { 186 u32 tmp; 187 188 /* 189 * Line Buffer Setup 190 * There is a single line buffer shared by both display controllers. 191 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between 192 * the display controllers. The paritioning can either be done 193 * manually or via one of four preset allocations specified in bits 1:0: 194 * 0 - line buffer is divided in half and shared between crtc 195 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4 196 * 2 - D1 gets the whole buffer 197 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4 198 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual 199 * allocation mode. In manual allocation mode, D1 always starts at 0, 200 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1. 201 */ 202 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT; 203 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE; 204 /* auto */ 205 if (mode1 && mode2) { 206 if (mode1->hdisplay > mode2->hdisplay) { 207 if (mode1->hdisplay > 2560) 208 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q; 209 else 210 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 211 } else if (mode2->hdisplay > mode1->hdisplay) { 212 if (mode2->hdisplay > 2560) 213 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 214 else 215 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 216 } else 217 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF; 218 } else if (mode1) { 219 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY; 220 } else if (mode2) { 221 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q; 222 } 223 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp); 224 } 225 226 struct rs690_watermark { 227 u32 lb_request_fifo_depth; 228 fixed20_12 num_line_pair; 229 fixed20_12 estimated_width; 230 fixed20_12 worst_case_latency; 231 fixed20_12 consumption_rate; 232 fixed20_12 active_time; 233 fixed20_12 dbpp; 234 fixed20_12 priority_mark_max; 235 fixed20_12 priority_mark; 236 fixed20_12 sclk; 237 }; 238 239 static void rs690_crtc_bandwidth_compute(struct radeon_device *rdev, 240 struct radeon_crtc *crtc, 241 struct rs690_watermark *wm) 242 { 243 struct drm_display_mode *mode = &crtc->base.mode; 244 fixed20_12 a, b, c; 245 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width; 246 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency; 247 248 if (!crtc->base.enabled) { 249 /* FIXME: wouldn't it better to set priority mark to maximum */ 250 wm->lb_request_fifo_depth = 4; 251 return; 252 } 253 254 if (crtc->vsc.full > dfixed_const(2)) 255 wm->num_line_pair.full = dfixed_const(2); 256 else 257 wm->num_line_pair.full = dfixed_const(1); 258 259 b.full = dfixed_const(mode->crtc_hdisplay); 260 c.full = dfixed_const(256); 261 a.full = dfixed_div(b, c); 262 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); 263 request_fifo_depth.full = dfixed_ceil(request_fifo_depth); 264 if (a.full < dfixed_const(4)) { 265 wm->lb_request_fifo_depth = 4; 266 } else { 267 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); 268 } 269 270 /* Determine consumption rate 271 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000) 272 * vtaps = number of vertical taps, 273 * vsc = vertical scaling ratio, defined as source/destination 274 * hsc = horizontal scaling ration, defined as source/destination 275 */ 276 a.full = dfixed_const(mode->clock); 277 b.full = dfixed_const(1000); 278 a.full = dfixed_div(a, b); 279 pclk.full = dfixed_div(b, a); 280 if (crtc->rmx_type != RMX_OFF) { 281 b.full = dfixed_const(2); 282 if (crtc->vsc.full > b.full) 283 b.full = crtc->vsc.full; 284 b.full = dfixed_mul(b, crtc->hsc); 285 c.full = dfixed_const(2); 286 b.full = dfixed_div(b, c); 287 consumption_time.full = dfixed_div(pclk, b); 288 } else { 289 consumption_time.full = pclk.full; 290 } 291 a.full = dfixed_const(1); 292 wm->consumption_rate.full = dfixed_div(a, consumption_time); 293 294 295 /* Determine line time 296 * LineTime = total time for one line of displayhtotal 297 * LineTime = total number of horizontal pixels 298 * pclk = pixel clock period(ns) 299 */ 300 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 301 line_time.full = dfixed_mul(a, pclk); 302 303 /* Determine active time 304 * ActiveTime = time of active region of display within one line, 305 * hactive = total number of horizontal active pixels 306 * htotal = total number of horizontal pixels 307 */ 308 a.full = dfixed_const(crtc->base.mode.crtc_htotal); 309 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 310 wm->active_time.full = dfixed_mul(line_time, b); 311 wm->active_time.full = dfixed_div(wm->active_time, a); 312 313 /* Maximun bandwidth is the minimun bandwidth of all component */ 314 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth; 315 if (rdev->mc.igp_sideport_enabled) { 316 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full && 317 rdev->pm.sideport_bandwidth.full) 318 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth; 319 read_delay_latency.full = dfixed_const(370 * 800 * 1000); 320 read_delay_latency.full = dfixed_div(read_delay_latency, 321 rdev->pm.igp_sideport_mclk); 322 } else { 323 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full && 324 rdev->pm.k8_bandwidth.full) 325 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth; 326 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full && 327 rdev->pm.ht_bandwidth.full) 328 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth; 329 read_delay_latency.full = dfixed_const(5000); 330 } 331 332 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */ 333 a.full = dfixed_const(16); 334 rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a); 335 a.full = dfixed_const(1000); 336 rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk); 337 /* Determine chunk time 338 * ChunkTime = the time it takes the DCP to send one chunk of data 339 * to the LB which consists of pipeline delay and inter chunk gap 340 * sclk = system clock(ns) 341 */ 342 a.full = dfixed_const(256 * 13); 343 chunk_time.full = dfixed_mul(rdev->pm.sclk, a); 344 a.full = dfixed_const(10); 345 chunk_time.full = dfixed_div(chunk_time, a); 346 347 /* Determine the worst case latency 348 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines) 349 * WorstCaseLatency = worst case time from urgent to when the MC starts 350 * to return data 351 * READ_DELAY_IDLE_MAX = constant of 1us 352 * ChunkTime = time it takes the DCP to send one chunk of data to the LB 353 * which consists of pipeline delay and inter chunk gap 354 */ 355 if (dfixed_trunc(wm->num_line_pair) > 1) { 356 a.full = dfixed_const(3); 357 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 358 wm->worst_case_latency.full += read_delay_latency.full; 359 } else { 360 a.full = dfixed_const(2); 361 wm->worst_case_latency.full = dfixed_mul(a, chunk_time); 362 wm->worst_case_latency.full += read_delay_latency.full; 363 } 364 365 /* Determine the tolerable latency 366 * TolerableLatency = Any given request has only 1 line time 367 * for the data to be returned 368 * LBRequestFifoDepth = Number of chunk requests the LB can 369 * put into the request FIFO for a display 370 * LineTime = total time for one line of display 371 * ChunkTime = the time it takes the DCP to send one chunk 372 * of data to the LB which consists of 373 * pipeline delay and inter chunk gap 374 */ 375 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { 376 tolerable_latency.full = line_time.full; 377 } else { 378 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); 379 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full; 380 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time); 381 tolerable_latency.full = line_time.full - tolerable_latency.full; 382 } 383 /* We assume worst case 32bits (4 bytes) */ 384 wm->dbpp.full = dfixed_const(4 * 8); 385 386 /* Determine the maximum priority mark 387 * width = viewport width in pixels 388 */ 389 a.full = dfixed_const(16); 390 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); 391 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); 392 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); 393 394 /* Determine estimated width */ 395 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; 396 estimated_width.full = dfixed_div(estimated_width, consumption_time); 397 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) { 398 wm->priority_mark.full = dfixed_const(10); 399 } else { 400 a.full = dfixed_const(16); 401 wm->priority_mark.full = dfixed_div(estimated_width, a); 402 wm->priority_mark.full = dfixed_ceil(wm->priority_mark); 403 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; 404 } 405 } 406 407 void rs690_bandwidth_update(struct radeon_device *rdev) 408 { 409 struct drm_display_mode *mode0 = NULL; 410 struct drm_display_mode *mode1 = NULL; 411 struct rs690_watermark wm0; 412 struct rs690_watermark wm1; 413 u32 tmp; 414 u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 415 u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1); 416 fixed20_12 priority_mark02, priority_mark12, fill_rate; 417 fixed20_12 a, b; 418 419 radeon_update_display_priority(rdev); 420 421 if (rdev->mode_info.crtcs[0]->base.enabled) 422 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 423 if (rdev->mode_info.crtcs[1]->base.enabled) 424 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 425 /* 426 * Set display0/1 priority up in the memory controller for 427 * modes if the user specifies HIGH for displaypriority 428 * option. 429 */ 430 if ((rdev->disp_priority == 2) && 431 ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) { 432 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER); 433 tmp &= C_000104_MC_DISP0R_INIT_LAT; 434 tmp &= C_000104_MC_DISP1R_INIT_LAT; 435 if (mode0) 436 tmp |= S_000104_MC_DISP0R_INIT_LAT(1); 437 if (mode1) 438 tmp |= S_000104_MC_DISP1R_INIT_LAT(1); 439 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); 440 } 441 rs690_line_buffer_adjust(rdev, mode0, mode1); 442 443 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) 444 WREG32(R_006C9C_DCP_CONTROL, 0); 445 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 446 WREG32(R_006C9C_DCP_CONTROL, 2); 447 448 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0); 449 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1); 450 451 tmp = (wm0.lb_request_fifo_depth - 1); 452 tmp |= (wm1.lb_request_fifo_depth - 1) << 16; 453 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp); 454 455 if (mode0 && mode1) { 456 if (dfixed_trunc(wm0.dbpp) > 64) 457 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 458 else 459 a.full = wm0.num_line_pair.full; 460 if (dfixed_trunc(wm1.dbpp) > 64) 461 b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 462 else 463 b.full = wm1.num_line_pair.full; 464 a.full += b.full; 465 fill_rate.full = dfixed_div(wm0.sclk, a); 466 if (wm0.consumption_rate.full > fill_rate.full) { 467 b.full = wm0.consumption_rate.full - fill_rate.full; 468 b.full = dfixed_mul(b, wm0.active_time); 469 a.full = dfixed_mul(wm0.worst_case_latency, 470 wm0.consumption_rate); 471 a.full = a.full + b.full; 472 b.full = dfixed_const(16 * 1000); 473 priority_mark02.full = dfixed_div(a, b); 474 } else { 475 a.full = dfixed_mul(wm0.worst_case_latency, 476 wm0.consumption_rate); 477 b.full = dfixed_const(16 * 1000); 478 priority_mark02.full = dfixed_div(a, b); 479 } 480 if (wm1.consumption_rate.full > fill_rate.full) { 481 b.full = wm1.consumption_rate.full - fill_rate.full; 482 b.full = dfixed_mul(b, wm1.active_time); 483 a.full = dfixed_mul(wm1.worst_case_latency, 484 wm1.consumption_rate); 485 a.full = a.full + b.full; 486 b.full = dfixed_const(16 * 1000); 487 priority_mark12.full = dfixed_div(a, b); 488 } else { 489 a.full = dfixed_mul(wm1.worst_case_latency, 490 wm1.consumption_rate); 491 b.full = dfixed_const(16 * 1000); 492 priority_mark12.full = dfixed_div(a, b); 493 } 494 if (wm0.priority_mark.full > priority_mark02.full) 495 priority_mark02.full = wm0.priority_mark.full; 496 if (dfixed_trunc(priority_mark02) < 0) 497 priority_mark02.full = 0; 498 if (wm0.priority_mark_max.full > priority_mark02.full) 499 priority_mark02.full = wm0.priority_mark_max.full; 500 if (wm1.priority_mark.full > priority_mark12.full) 501 priority_mark12.full = wm1.priority_mark.full; 502 if (dfixed_trunc(priority_mark12) < 0) 503 priority_mark12.full = 0; 504 if (wm1.priority_mark_max.full > priority_mark12.full) 505 priority_mark12.full = wm1.priority_mark_max.full; 506 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 507 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 508 if (rdev->disp_priority == 2) { 509 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 510 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 511 } 512 } else if (mode0) { 513 if (dfixed_trunc(wm0.dbpp) > 64) 514 a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair); 515 else 516 a.full = wm0.num_line_pair.full; 517 fill_rate.full = dfixed_div(wm0.sclk, a); 518 if (wm0.consumption_rate.full > fill_rate.full) { 519 b.full = wm0.consumption_rate.full - fill_rate.full; 520 b.full = dfixed_mul(b, wm0.active_time); 521 a.full = dfixed_mul(wm0.worst_case_latency, 522 wm0.consumption_rate); 523 a.full = a.full + b.full; 524 b.full = dfixed_const(16 * 1000); 525 priority_mark02.full = dfixed_div(a, b); 526 } else { 527 a.full = dfixed_mul(wm0.worst_case_latency, 528 wm0.consumption_rate); 529 b.full = dfixed_const(16 * 1000); 530 priority_mark02.full = dfixed_div(a, b); 531 } 532 if (wm0.priority_mark.full > priority_mark02.full) 533 priority_mark02.full = wm0.priority_mark.full; 534 if (dfixed_trunc(priority_mark02) < 0) 535 priority_mark02.full = 0; 536 if (wm0.priority_mark_max.full > priority_mark02.full) 537 priority_mark02.full = wm0.priority_mark_max.full; 538 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02); 539 if (rdev->disp_priority == 2) 540 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 541 } else if (mode1) { 542 if (dfixed_trunc(wm1.dbpp) > 64) 543 a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair); 544 else 545 a.full = wm1.num_line_pair.full; 546 fill_rate.full = dfixed_div(wm1.sclk, a); 547 if (wm1.consumption_rate.full > fill_rate.full) { 548 b.full = wm1.consumption_rate.full - fill_rate.full; 549 b.full = dfixed_mul(b, wm1.active_time); 550 a.full = dfixed_mul(wm1.worst_case_latency, 551 wm1.consumption_rate); 552 a.full = a.full + b.full; 553 b.full = dfixed_const(16 * 1000); 554 priority_mark12.full = dfixed_div(a, b); 555 } else { 556 a.full = dfixed_mul(wm1.worst_case_latency, 557 wm1.consumption_rate); 558 b.full = dfixed_const(16 * 1000); 559 priority_mark12.full = dfixed_div(a, b); 560 } 561 if (wm1.priority_mark.full > priority_mark12.full) 562 priority_mark12.full = wm1.priority_mark.full; 563 if (dfixed_trunc(priority_mark12) < 0) 564 priority_mark12.full = 0; 565 if (wm1.priority_mark_max.full > priority_mark12.full) 566 priority_mark12.full = wm1.priority_mark_max.full; 567 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12); 568 if (rdev->disp_priority == 2) 569 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 570 } 571 572 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 573 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 574 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 575 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 576 } 577 578 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg) 579 { 580 uint32_t r; 581 582 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg)); 583 r = RREG32(R_00007C_MC_DATA); 584 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR); 585 return r; 586 } 587 588 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 589 { 590 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) | 591 S_000078_MC_IND_WR_EN(1)); 592 WREG32(R_00007C_MC_DATA, v); 593 WREG32(R_000078_MC_INDEX, 0x7F); 594 } 595 596 static void rs690_mc_program(struct radeon_device *rdev) 597 { 598 struct rv515_mc_save save; 599 600 /* Stops all mc clients */ 601 rv515_mc_stop(rdev, &save); 602 603 /* Wait for mc idle */ 604 if (rs690_mc_wait_for_idle(rdev)) 605 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 606 /* Program MC, should be a 32bits limited address space */ 607 WREG32_MC(R_000100_MCCFG_FB_LOCATION, 608 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) | 609 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16)); 610 WREG32(R_000134_HDP_FB_LOCATION, 611 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 612 613 rv515_mc_resume(rdev, &save); 614 } 615 616 static int rs690_startup(struct radeon_device *rdev) 617 { 618 int r; 619 620 rs690_mc_program(rdev); 621 /* Resume clock */ 622 rv515_clock_startup(rdev); 623 /* Initialize GPU configuration (# pipes, ...) */ 624 rs690_gpu_init(rdev); 625 /* Initialize GART (initialize after TTM so we can allocate 626 * memory through TTM but finalize after TTM) */ 627 r = rs400_gart_enable(rdev); 628 if (r) 629 return r; 630 631 /* allocate wb buffer */ 632 r = radeon_wb_init(rdev); 633 if (r) 634 return r; 635 636 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 637 if (r) { 638 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 639 return r; 640 } 641 642 /* Enable IRQ */ 643 if (!rdev->irq.installed) { 644 r = radeon_irq_kms_init(rdev); 645 if (r) 646 return r; 647 } 648 649 rs600_irq_set(rdev); 650 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 651 /* 1M ring buffer */ 652 r = r100_cp_init(rdev, 1024 * 1024); 653 if (r) { 654 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 655 return r; 656 } 657 658 r = radeon_ib_pool_init(rdev); 659 if (r) { 660 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 661 return r; 662 } 663 664 r = r600_audio_init(rdev); 665 if (r) { 666 dev_err(rdev->dev, "failed initializing audio\n"); 667 return r; 668 } 669 670 return 0; 671 } 672 673 int rs690_resume(struct radeon_device *rdev) 674 { 675 int r; 676 677 /* Make sur GART are not working */ 678 rs400_gart_disable(rdev); 679 /* Resume clock before doing reset */ 680 rv515_clock_startup(rdev); 681 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 682 if (radeon_asic_reset(rdev)) { 683 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 684 RREG32(R_000E40_RBBM_STATUS), 685 RREG32(R_0007C0_CP_STAT)); 686 } 687 /* post */ 688 atom_asic_init(rdev->mode_info.atom_context); 689 /* Resume clock after posting */ 690 rv515_clock_startup(rdev); 691 /* Initialize surface registers */ 692 radeon_surface_init(rdev); 693 694 rdev->accel_working = true; 695 r = rs690_startup(rdev); 696 if (r) { 697 rdev->accel_working = false; 698 } 699 return r; 700 } 701 702 int rs690_suspend(struct radeon_device *rdev) 703 { 704 r600_audio_fini(rdev); 705 r100_cp_disable(rdev); 706 radeon_wb_disable(rdev); 707 rs600_irq_disable(rdev); 708 rs400_gart_disable(rdev); 709 return 0; 710 } 711 712 void rs690_fini(struct radeon_device *rdev) 713 { 714 r600_audio_fini(rdev); 715 r100_cp_fini(rdev); 716 radeon_wb_fini(rdev); 717 radeon_ib_pool_fini(rdev); 718 radeon_gem_fini(rdev); 719 rs400_gart_fini(rdev); 720 radeon_irq_kms_fini(rdev); 721 radeon_fence_driver_fini(rdev); 722 radeon_bo_fini(rdev); 723 radeon_atombios_fini(rdev); 724 kfree(rdev->bios); 725 rdev->bios = NULL; 726 } 727 728 int rs690_init(struct radeon_device *rdev) 729 { 730 int r; 731 732 /* Disable VGA */ 733 rv515_vga_render_disable(rdev); 734 /* Initialize scratch registers */ 735 radeon_scratch_init(rdev); 736 /* Initialize surface registers */ 737 radeon_surface_init(rdev); 738 /* restore some register to sane defaults */ 739 r100_restore_sanity(rdev); 740 /* TODO: disable VGA need to use VGA request */ 741 /* BIOS*/ 742 if (!radeon_get_bios(rdev)) { 743 if (ASIC_IS_AVIVO(rdev)) 744 return -EINVAL; 745 } 746 if (rdev->is_atom_bios) { 747 r = radeon_atombios_init(rdev); 748 if (r) 749 return r; 750 } else { 751 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 752 return -EINVAL; 753 } 754 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 755 if (radeon_asic_reset(rdev)) { 756 dev_warn(rdev->dev, 757 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 758 RREG32(R_000E40_RBBM_STATUS), 759 RREG32(R_0007C0_CP_STAT)); 760 } 761 /* check if cards are posted or not */ 762 if (radeon_boot_test_post_card(rdev) == false) 763 return -EINVAL; 764 765 /* Initialize clocks */ 766 radeon_get_clock_info(rdev->ddev); 767 /* initialize memory controller */ 768 rs690_mc_init(rdev); 769 rv515_debugfs(rdev); 770 /* Fence driver */ 771 r = radeon_fence_driver_init(rdev); 772 if (r) 773 return r; 774 /* Memory manager */ 775 r = radeon_bo_init(rdev); 776 if (r) 777 return r; 778 r = rs400_gart_init(rdev); 779 if (r) 780 return r; 781 rs600_set_safe_registers(rdev); 782 783 rdev->accel_working = true; 784 r = rs690_startup(rdev); 785 if (r) { 786 /* Somethings want wront with the accel init stop accel */ 787 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 788 r100_cp_fini(rdev); 789 radeon_wb_fini(rdev); 790 radeon_ib_pool_fini(rdev); 791 rs400_gart_fini(rdev); 792 radeon_irq_kms_fini(rdev); 793 rdev->accel_working = false; 794 } 795 return 0; 796 } 797