1 /* $OpenBSD: rs600d.h,v 1.1 2013/08/12 04:11:53 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #ifndef __RS600D_H__ 30 #define __RS600D_H__ 31 32 /* Registers */ 33 #define R_000040_GEN_INT_CNTL 0x000040 34 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 35 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 36 #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF 37 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 38 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 39 #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF 40 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 41 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 42 #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 43 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 44 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 45 #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 46 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 47 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 48 #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 49 #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 50 #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 51 #define C_000040_I2C_INT_EN 0xFFFDFFFF 52 #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 53 #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 54 #define C_000040_GUI_IDLE 0xFFF7FFFF 55 #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 56 #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 57 #define C_000040_VIPH_INT_EN 0xFEFFFFFF 58 #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 59 #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 60 #define C_000040_SW_INT_EN 0xFDFFFFFF 61 #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 62 #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 63 #define C_000040_GEYSERVILLE 0xF7FFFFFF 64 #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 65 #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 66 #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 67 #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 68 #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 69 #define C_000040_DVI_I2C_INT 0xDFFFFFFF 70 #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 71 #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 72 #define C_000040_GUIDMA 0xBFFFFFFF 73 #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 74 #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 75 #define C_000040_VIDDMA 0x7FFFFFFF 76 #define R_000044_GEN_INT_STATUS 0x000044 77 #define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0) 78 #define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1) 79 #define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE 80 #define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1) 81 #define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1) 82 #define C_000044_VGA_INT_STAT 0xFFFFFFFD 83 #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 84 #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 85 #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 86 #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 87 #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 88 #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 89 #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 90 #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 91 #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 92 #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 93 #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 94 #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 95 #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 96 #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 97 #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 98 #define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16) 99 #define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1) 100 #define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF 101 #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 102 #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 103 #define C_000044_I2C_INT 0xFFFDFFFF 104 #define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18) 105 #define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1) 106 #define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF 107 #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 108 #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 109 #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 110 #define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20) 111 #define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1) 112 #define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF 113 #define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21) 114 #define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1) 115 #define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF 116 #define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22) 117 #define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1) 118 #define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF 119 #define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23) 120 #define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1) 121 #define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF 122 #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 123 #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 124 #define C_000044_VIPH_INT 0xFEFFFFFF 125 #define S_000044_SW_INT(x) (((x) & 0x1) << 25) 126 #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 127 #define C_000044_SW_INT 0xFDFFFFFF 128 #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 129 #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 130 #define C_000044_SW_INT_SET 0xFBFFFFFF 131 #define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27) 132 #define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1) 133 #define C_000044_IDCT_INT_STAT 0xF7FFFFFF 134 #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 135 #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 136 #define C_000044_GUIDMA_STAT 0xBFFFFFFF 137 #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 138 #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 139 #define C_000044_VIDDMA_STAT 0x7FFFFFFF 140 #define R_00004C_BUS_CNTL 0x00004C 141 #define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14) 142 #define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1) 143 #define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF 144 #define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20) 145 #define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1) 146 #define C_00004C_BUS_MSI_REARM 0xFFEFFFFF 147 #define R_000070_MC_IND_INDEX 0x000070 148 #define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0) 149 #define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF) 150 #define C_000070_MC_IND_ADDR 0xFFFF0000 151 #define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16) 152 #define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1) 153 #define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF 154 #define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17) 155 #define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1) 156 #define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF 157 #define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18) 158 #define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1) 159 #define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF 160 #define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19) 161 #define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1) 162 #define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF 163 #define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20) 164 #define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1) 165 #define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF 166 #define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21) 167 #define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1) 168 #define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF 169 #define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22) 170 #define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1) 171 #define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF 172 #define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23) 173 #define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1) 174 #define C_000070_MC_IND_WR_EN 0xFF7FFFFF 175 #define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24) 176 #define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1) 177 #define C_000070_MC_IND_RD_INV 0xFEFFFFFF 178 #define R_000074_MC_IND_DATA 0x000074 179 #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) 180 #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) 181 #define C_000074_MC_IND_DATA 0x00000000 182 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 183 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 184 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 185 #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 186 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 187 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 188 #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 189 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 190 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 191 #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 192 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 193 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 194 #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 195 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 196 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 197 #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 198 #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 199 #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 200 #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 201 #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 202 #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 203 #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 204 #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 205 #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 206 #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 207 #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 208 #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 209 #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 210 #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 211 #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 212 #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 213 #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 214 #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 215 #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 216 #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 217 #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 218 #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 219 #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 220 #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 221 #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 222 #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 223 #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 224 #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 225 #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 226 #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 227 #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 228 #define R_000134_HDP_FB_LOCATION 0x000134 229 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) 230 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) 231 #define C_000134_HDP_FB_START 0xFFFF0000 232 #define R_0007C0_CP_STAT 0x0007C0 233 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 234 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 235 #define C_0007C0_MRU_BUSY 0xFFFFFFFE 236 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 237 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 238 #define C_0007C0_MWU_BUSY 0xFFFFFFFD 239 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 240 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 241 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 242 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 243 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 244 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 245 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 246 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 247 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 248 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 249 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 250 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 251 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 252 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 253 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 254 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 255 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 256 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 257 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 258 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 259 #define C_0007C0_CSI_BUSY 0xFFFFDFFF 260 #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 261 #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 262 #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 263 #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 264 #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 265 #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 266 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 267 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 268 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 269 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 270 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 271 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 272 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 273 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 274 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 275 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 276 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 277 #define C_0007C0_CP_BUSY 0x7FFFFFFF 278 #define R_000E40_RBBM_STATUS 0x000E40 279 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 280 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 281 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 282 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 283 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 284 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 285 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 286 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 287 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 288 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 289 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 290 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 291 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 292 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 293 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 294 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 295 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 296 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 297 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 298 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 299 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 300 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 301 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 302 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 303 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 304 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 305 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 306 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 307 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 308 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 309 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 310 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 311 #define C_000E40_E2_BUSY 0xFFFDFFFF 312 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 313 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 314 #define C_000E40_RB2D_BUSY 0xFFFBFFFF 315 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 316 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 317 #define C_000E40_RB3D_BUSY 0xFFF7FFFF 318 #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 319 #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 320 #define C_000E40_VAP_BUSY 0xFFEFFFFF 321 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 322 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 323 #define C_000E40_RE_BUSY 0xFFDFFFFF 324 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 325 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 326 #define C_000E40_TAM_BUSY 0xFFBFFFFF 327 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 328 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 329 #define C_000E40_TDM_BUSY 0xFF7FFFFF 330 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 331 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 332 #define C_000E40_PB_BUSY 0xFEFFFFFF 333 #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 334 #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 335 #define C_000E40_TIM_BUSY 0xFDFFFFFF 336 #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 337 #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 338 #define C_000E40_GA_BUSY 0xFBFFFFFF 339 #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 340 #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 341 #define C_000E40_CBA2D_BUSY 0xF7FFFFFF 342 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 343 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 344 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 345 #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4 346 #define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 347 #define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 348 #define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000 349 #define R_006534_D1MODE_VBLANK_STATUS 0x006534 350 #define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 351 #define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 352 #define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE 353 #define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 354 #define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 355 #define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF 356 #define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 357 #define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 358 #define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF 359 #define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 360 #define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 361 #define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF 362 #define R_006540_DxMODE_INT_MASK 0x006540 363 #define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0) 364 #define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1) 365 #define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE 366 #define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4) 367 #define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1) 368 #define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF 369 #define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8) 370 #define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1) 371 #define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF 372 #define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12) 373 #define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1) 374 #define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF 375 #define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30) 376 #define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1) 377 #define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF 378 #define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31) 379 #define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1) 380 #define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF 381 #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4 382 #define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 383 #define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 384 #define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000 385 #define R_006D34_D2MODE_VBLANK_STATUS 0x006D34 386 #define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 387 #define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 388 #define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE 389 #define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 390 #define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 391 #define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF 392 #define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 393 #define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 394 #define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF 395 #define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 396 #define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 397 #define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF 398 #define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC 399 #define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4) 400 #define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1) 401 #define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF 402 #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) 403 #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) 404 #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF 405 #define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16) 406 #define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1) 407 #define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF 408 #define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17) 409 #define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1) 410 #define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF 411 #define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18) 412 #define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1) 413 #define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF 414 #define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19) 415 #define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1) 416 #define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF 417 #define R_007828_DACA_AUTODETECT_CONTROL 0x007828 418 #define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 419 #define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 420 #define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC 421 #define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 422 #define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 423 #define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 424 #define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 425 #define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 426 #define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF 427 #define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838 428 #define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 429 #define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE 430 #define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 431 #define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 432 #define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF 433 #define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28 434 #define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 435 #define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 436 #define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC 437 #define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 438 #define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 439 #define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 440 #define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 441 #define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 442 #define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF 443 #define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38 444 #define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 445 #define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE 446 #define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 447 #define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 448 #define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF 449 #define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00 450 #define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0) 451 #define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1) 452 #define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE 453 #define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04 454 #define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0) 455 #define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1) 456 #define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE 457 #define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1) 458 #define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1) 459 #define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD 460 #define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08 461 #define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0) 462 #define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE 463 #define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8) 464 #define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1) 465 #define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF 466 #define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16) 467 #define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1) 468 #define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF 469 #define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10 470 #define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0) 471 #define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1) 472 #define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE 473 #define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14 474 #define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0) 475 #define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1) 476 #define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE 477 #define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1) 478 #define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1) 479 #define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD 480 #define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18 481 #define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0) 482 #define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE 483 #define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8) 484 #define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1) 485 #define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF 486 #define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16) 487 #define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1) 488 #define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF 489 #define R_007404_HDMI0_STATUS 0x007404 490 #define S_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) & 0x1) << 28) 491 #define G_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) >> 28) & 0x1) 492 #define C_007404_HDMI0_AZ_FORMAT_WTRIG 0xEFFFFFFF 493 #define S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) & 0x1) << 29) 494 #define G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) >> 29) & 0x1) 495 #define C_007404_HDMI0_AZ_FORMAT_WTRIG_INT 0xDFFFFFFF 496 #define R_007408_HDMI0_AUDIO_PACKET_CONTROL 0x007408 497 #define S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) & 0x1) << 28) 498 #define G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) >> 28) & 0x1) 499 #define C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK 0xEFFFFFFF 500 #define S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) & 0x1) << 29) 501 #define G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) >> 29) & 0x1) 502 #define C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK 0xDFFFFFFF 503 504 /* MC registers */ 505 #define R_000000_MC_STATUS 0x000000 506 #define S_000000_MC_IDLE(x) (((x) & 0x1) << 0) 507 #define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1) 508 #define C_000000_MC_IDLE 0xFFFFFFFE 509 #define R_000004_MC_FB_LOCATION 0x000004 510 #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) 511 #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 512 #define C_000004_MC_FB_START 0xFFFF0000 513 #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 514 #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 515 #define C_000004_MC_FB_TOP 0x0000FFFF 516 #define R_000005_MC_AGP_LOCATION 0x000005 517 #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 518 #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 519 #define C_000005_MC_AGP_START 0xFFFF0000 520 #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 521 #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 522 #define C_000005_MC_AGP_TOP 0x0000FFFF 523 #define R_000006_AGP_BASE 0x000006 524 #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 525 #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 526 #define C_000006_AGP_BASE_ADDR 0x00000000 527 #define R_000007_AGP_BASE_2 0x000007 528 #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 529 #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 530 #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 531 #define R_000009_MC_CNTL1 0x000009 532 #define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26) 533 #define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1) 534 #define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF 535 /* FIXME don't know the various field size need feedback from AMD */ 536 #define R_000100_MC_PT0_CNTL 0x000100 537 #define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0) 538 #define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1) 539 #define C_000100_ENABLE_PT 0xFFFFFFFE 540 #define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15) 541 #define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7) 542 #define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF 543 #define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21) 544 #define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7) 545 #define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF 546 #define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28) 547 #define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1) 548 #define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF 549 #define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29) 550 #define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1) 551 #define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF 552 #define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102 553 #define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0) 554 #define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1) 555 #define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE 556 #define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1) 557 #define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3) 558 #define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9 559 #define V_000102_PAGE_TABLE_FLAT 0 560 /* R600 documentation suggest that this should be a number of pages */ 561 #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112 562 #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114 563 #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C 564 #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C 565 #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C 566 #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C 567 #define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C 568 #define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0) 569 #define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1) 570 #define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE 571 #define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1) 572 #define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1) 573 #define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD 574 #define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8) 575 #define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3) 576 #define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF 577 #define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0 578 #define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1 579 #define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2 580 #define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3 581 #define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10) 582 #define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1) 583 #define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF 584 #define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0 585 #define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1 586 #define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11) 587 #define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7) 588 #define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF 589 #define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14) 590 #define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1) 591 #define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF 592 #define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15) 593 #define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7) 594 #define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF 595 #define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20) 596 #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) 597 #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF 598 599 #define R_006548_D1MODE_PRIORITY_A_CNT 0x006548 600 #define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 601 #define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 602 #define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000 603 #define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 604 #define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 605 #define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF 606 #define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 607 #define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 608 #define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 609 #define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 610 #define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 611 #define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 612 #define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C 613 #define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 614 #define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 615 #define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000 616 #define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 617 #define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 618 #define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF 619 #define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 620 #define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 621 #define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 622 #define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 623 #define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 624 #define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 625 #define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48 626 #define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 627 #define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 628 #define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000 629 #define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 630 #define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 631 #define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF 632 #define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 633 #define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 634 #define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 635 #define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 636 #define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 637 #define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 638 #define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C 639 #define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 640 #define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 641 #define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000 642 #define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 643 #define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 644 #define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF 645 #define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 646 #define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 647 #define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 648 #define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 649 #define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 650 #define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 651 652 /* PLL regs */ 653 #define GENERAL_PWRMGT 0x8 654 #define GLOBAL_PWRMGT_EN (1 << 0) 655 #define MOBILE_SU (1 << 2) 656 #define DYN_PWRMGT_SCLK_LENGTH 0xc 657 #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) 658 #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) 659 #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) 660 #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) 661 #define POWER_D1_SCLK_HILEN(x) ((x) << 16) 662 #define POWER_D1_SCLK_LOLEN(x) ((x) << 20) 663 #define STATIC_SCREEN_HILEN(x) ((x) << 24) 664 #define STATIC_SCREEN_LOLEN(x) ((x) << 28) 665 #define DYN_SCLK_VOL_CNTL 0xe 666 #define IO_CG_VOLTAGE_DROP (1 << 0) 667 #define VOLTAGE_DROP_SYNC (1 << 2) 668 #define VOLTAGE_DELAY_SEL(x) ((x) << 3) 669 #define HDP_DYN_CNTL 0x10 670 #define HDP_FORCEON (1 << 0) 671 #define MC_HOST_DYN_CNTL 0x1e 672 #define MC_HOST_FORCEON (1 << 0) 673 #define DYN_BACKBIAS_CNTL 0x29 674 #define IO_CG_BACKBIAS_EN (1 << 0) 675 676 /* mmreg */ 677 #define DOUT_POWER_MANAGEMENT_CNTL 0x7ee0 678 #define PWRDN_WAIT_BUSY_OFF (1 << 0) 679 #define PWRDN_WAIT_PWRSEQ_OFF (1 << 4) 680 #define PWRDN_WAIT_PPLL_OFF (1 << 8) 681 #define PWRUP_WAIT_PPLL_ON (1 << 12) 682 #define PWRUP_WAIT_MEM_INIT_DONE (1 << 16) 683 #define PM_ASSERT_RESET (1 << 20) 684 #define PM_PWRDN_PPLL (1 << 24) 685 686 #endif 687