1 /* $OpenBSD: rs600.c,v 1.8 2015/04/06 05:35:29 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 /* RS600 / Radeon X1250/X1270 integrated GPU 30 * 31 * This file gather function specific to RS600 which is the IGP of 32 * the X1250/X1270 family supporting intel CPU (while RS690/RS740 33 * is the X1250/X1270 supporting AMD CPU). The display engine are 34 * the avivo one, bios is an atombios, 3D block are the one of the 35 * R4XX family. The GART is different from the RS400 one and is very 36 * close to the one of the R600 family (R600 likely being an evolution 37 * of the RS600 GART block). 38 */ 39 #include <dev/pci/drm/drmP.h> 40 #include "radeon.h" 41 #include "radeon_asic.h" 42 #include "atom.h" 43 #include "rs600d.h" 44 45 #include "rs600_reg_safe.h" 46 47 static void rs600_gpu_init(struct radeon_device *rdev); 48 int rs600_mc_wait_for_idle(struct radeon_device *rdev); 49 50 static const u32 crtc_offsets[2] = 51 { 52 0, 53 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 54 }; 55 56 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) 57 { 58 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 59 return true; 60 else 61 return false; 62 } 63 64 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) 65 { 66 u32 pos1, pos2; 67 68 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 69 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); 70 71 if (pos1 != pos2) 72 return true; 73 else 74 return false; 75 } 76 77 /** 78 * avivo_wait_for_vblank - vblank wait asic callback. 79 * 80 * @rdev: radeon_device pointer 81 * @crtc: crtc to wait for vblank on 82 * 83 * Wait for vblank on the requested crtc (r5xx-r7xx). 84 */ 85 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 86 { 87 unsigned i = 0; 88 89 if (crtc >= rdev->num_crtc) 90 return; 91 92 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) 93 return; 94 95 /* depending on when we hit vblank, we may be close to active; if so, 96 * wait for another frame. 97 */ 98 while (avivo_is_in_vblank(rdev, crtc)) { 99 if (i++ % 100 == 0) { 100 if (!avivo_is_counter_moving(rdev, crtc)) 101 break; 102 } 103 } 104 105 while (!avivo_is_in_vblank(rdev, crtc)) { 106 if (i++ % 100 == 0) { 107 if (!avivo_is_counter_moving(rdev, crtc)) 108 break; 109 } 110 } 111 } 112 113 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc) 114 { 115 /* enable the pflip int */ 116 radeon_irq_kms_pflip_irq_get(rdev, crtc); 117 } 118 119 void rs600_post_page_flip(struct radeon_device *rdev, int crtc) 120 { 121 /* disable the pflip int */ 122 radeon_irq_kms_pflip_irq_put(rdev, crtc); 123 } 124 125 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 126 { 127 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 128 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); 129 int i; 130 131 /* Lock the graphics update lock */ 132 tmp |= AVIVO_D1GRPH_UPDATE_LOCK; 133 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 134 135 /* update the scanout addresses */ 136 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 137 (u32)crtc_base); 138 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 139 (u32)crtc_base); 140 141 /* Wait for update_pending to go high. */ 142 for (i = 0; i < rdev->usec_timeout; i++) { 143 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) 144 break; 145 udelay(1); 146 } 147 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 148 149 /* Unlock the lock, so double-buffering can take place inside vblank */ 150 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; 151 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); 152 153 /* Return current update_pending status: */ 154 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; 155 } 156 157 void rs600_pm_misc(struct radeon_device *rdev) 158 { 159 int requested_index = rdev->pm.requested_power_state_index; 160 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 161 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 162 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl; 163 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl; 164 165 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 166 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 167 tmp = RREG32(voltage->gpio.reg); 168 if (voltage->active_high) 169 tmp |= voltage->gpio.mask; 170 else 171 tmp &= ~(voltage->gpio.mask); 172 WREG32(voltage->gpio.reg, tmp); 173 if (voltage->delay) 174 udelay(voltage->delay); 175 } else { 176 tmp = RREG32(voltage->gpio.reg); 177 if (voltage->active_high) 178 tmp &= ~voltage->gpio.mask; 179 else 180 tmp |= voltage->gpio.mask; 181 WREG32(voltage->gpio.reg, tmp); 182 if (voltage->delay) 183 udelay(voltage->delay); 184 } 185 } else if (voltage->type == VOLTAGE_VDDC) 186 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); 187 188 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH); 189 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf); 190 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf); 191 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 192 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) { 193 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2); 194 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2); 195 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) { 196 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4); 197 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4); 198 } 199 } else { 200 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1); 201 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1); 202 } 203 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); 204 205 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL); 206 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 207 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP; 208 if (voltage->delay) { 209 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC; 210 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay); 211 } else 212 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC; 213 } else 214 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP; 215 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); 216 217 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL); 218 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 219 hdp_dyn_cntl &= ~HDP_FORCEON; 220 else 221 hdp_dyn_cntl |= HDP_FORCEON; 222 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); 223 #if 0 224 /* mc_host_dyn seems to cause hangs from time to time */ 225 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL); 226 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN) 227 mc_host_dyn_cntl &= ~MC_HOST_FORCEON; 228 else 229 mc_host_dyn_cntl |= MC_HOST_FORCEON; 230 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); 231 #endif 232 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL); 233 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN) 234 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN; 235 else 236 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN; 237 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); 238 239 /* set pcie lanes */ 240 if ((rdev->flags & RADEON_IS_PCIE) && 241 !(rdev->flags & RADEON_IS_IGP) && 242 rdev->asic->pm.set_pcie_lanes && 243 (ps->pcie_lanes != 244 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 245 radeon_set_pcie_lanes(rdev, 246 ps->pcie_lanes); 247 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes); 248 } 249 } 250 251 void rs600_pm_prepare(struct radeon_device *rdev) 252 { 253 struct drm_device *ddev = rdev->ddev; 254 struct drm_crtc *crtc; 255 struct radeon_crtc *radeon_crtc; 256 u32 tmp; 257 258 /* disable any active CRTCs */ 259 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 260 radeon_crtc = to_radeon_crtc(crtc); 261 if (radeon_crtc->enabled) { 262 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 263 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 264 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 265 } 266 } 267 } 268 269 void rs600_pm_finish(struct radeon_device *rdev) 270 { 271 struct drm_device *ddev = rdev->ddev; 272 struct drm_crtc *crtc; 273 struct radeon_crtc *radeon_crtc; 274 u32 tmp; 275 276 /* enable any active CRTCs */ 277 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 278 radeon_crtc = to_radeon_crtc(crtc); 279 if (radeon_crtc->enabled) { 280 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset); 281 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 282 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); 283 } 284 } 285 } 286 287 /* hpd for digital panel detect/disconnect */ 288 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 289 { 290 u32 tmp; 291 bool connected = false; 292 293 switch (hpd) { 294 case RADEON_HPD_1: 295 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS); 296 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp)) 297 connected = true; 298 break; 299 case RADEON_HPD_2: 300 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS); 301 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp)) 302 connected = true; 303 break; 304 default: 305 break; 306 } 307 return connected; 308 } 309 310 void rs600_hpd_set_polarity(struct radeon_device *rdev, 311 enum radeon_hpd_id hpd) 312 { 313 u32 tmp; 314 bool connected = rs600_hpd_sense(rdev, hpd); 315 316 switch (hpd) { 317 case RADEON_HPD_1: 318 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 319 if (connected) 320 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 321 else 322 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1); 323 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 324 break; 325 case RADEON_HPD_2: 326 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 327 if (connected) 328 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 329 else 330 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1); 331 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 332 break; 333 default: 334 break; 335 } 336 } 337 338 void rs600_hpd_init(struct radeon_device *rdev) 339 { 340 struct drm_device *dev = rdev->ddev; 341 struct drm_connector *connector; 342 unsigned enable = 0; 343 344 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 345 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 346 switch (radeon_connector->hpd.hpd) { 347 case RADEON_HPD_1: 348 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 349 S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); 350 break; 351 case RADEON_HPD_2: 352 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 353 S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); 354 break; 355 default: 356 break; 357 } 358 enable |= 1 << radeon_connector->hpd.hpd; 359 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 360 } 361 radeon_irq_kms_enable_hpd(rdev, enable); 362 } 363 364 void rs600_hpd_fini(struct radeon_device *rdev) 365 { 366 struct drm_device *dev = rdev->ddev; 367 struct drm_connector *connector; 368 unsigned disable = 0; 369 370 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 371 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 372 switch (radeon_connector->hpd.hpd) { 373 case RADEON_HPD_1: 374 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, 375 S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); 376 break; 377 case RADEON_HPD_2: 378 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, 379 S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); 380 break; 381 default: 382 break; 383 } 384 disable |= 1 << radeon_connector->hpd.hpd; 385 } 386 radeon_irq_kms_disable_hpd(rdev, disable); 387 } 388 389 int rs600_asic_reset(struct radeon_device *rdev) 390 { 391 struct rv515_mc_save save; 392 u32 status, tmp; 393 int ret = 0; 394 395 status = RREG32(R_000E40_RBBM_STATUS); 396 if (!G_000E40_GUI_ACTIVE(status)) { 397 return 0; 398 } 399 /* Stops all mc clients */ 400 rv515_mc_stop(rdev, &save); 401 status = RREG32(R_000E40_RBBM_STATUS); 402 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 403 /* stop CP */ 404 WREG32(RADEON_CP_CSQ_CNTL, 0); 405 tmp = RREG32(RADEON_CP_RB_CNTL); 406 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 407 WREG32(RADEON_CP_RB_RPTR_WR, 0); 408 WREG32(RADEON_CP_RB_WPTR, 0); 409 WREG32(RADEON_CP_RB_CNTL, tmp); 410 #ifdef notyet 411 pci_save_state(rdev->pdev); 412 /* disable bus mastering */ 413 pci_clear_master(rdev->pdev); 414 #endif 415 mdelay(1); 416 /* reset GA+VAP */ 417 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 418 S_0000F0_SOFT_RESET_GA(1)); 419 RREG32(R_0000F0_RBBM_SOFT_RESET); 420 mdelay(500); 421 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 422 mdelay(1); 423 status = RREG32(R_000E40_RBBM_STATUS); 424 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 425 /* reset CP */ 426 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 427 RREG32(R_0000F0_RBBM_SOFT_RESET); 428 mdelay(500); 429 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 430 mdelay(1); 431 status = RREG32(R_000E40_RBBM_STATUS); 432 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 433 /* reset MC */ 434 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); 435 RREG32(R_0000F0_RBBM_SOFT_RESET); 436 mdelay(500); 437 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 438 mdelay(1); 439 status = RREG32(R_000E40_RBBM_STATUS); 440 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 441 /* restore PCI & busmastering */ 442 #ifdef notyet 443 pci_restore_state(rdev->pdev); 444 #endif 445 /* Check if GPU is idle */ 446 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 447 dev_err(rdev->dev, "failed to reset GPU\n"); 448 ret = -1; 449 } else 450 dev_info(rdev->dev, "GPU reset succeed\n"); 451 rv515_mc_resume(rdev, &save); 452 return ret; 453 } 454 455 /* 456 * GART. 457 */ 458 void rs600_gart_tlb_flush(struct radeon_device *rdev) 459 { 460 uint32_t tmp; 461 462 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 463 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 464 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 465 466 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 467 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1); 468 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 469 470 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 471 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE; 472 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); 473 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 474 } 475 476 static int rs600_gart_init(struct radeon_device *rdev) 477 { 478 int r; 479 480 if (rdev->gart.robj) { 481 WARN(1, "RS600 GART already initialized\n"); 482 return 0; 483 } 484 /* Initialize common gart structure */ 485 r = radeon_gart_init(rdev); 486 if (r) { 487 return r; 488 } 489 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 490 return radeon_gart_table_vram_alloc(rdev); 491 } 492 493 static int rs600_gart_enable(struct radeon_device *rdev) 494 { 495 u32 tmp; 496 int r, i; 497 498 if (rdev->gart.robj == NULL) { 499 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 500 return -EINVAL; 501 } 502 r = radeon_gart_table_vram_pin(rdev); 503 if (r) 504 return r; 505 radeon_gart_restore(rdev); 506 /* Enable bus master */ 507 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 508 WREG32(RADEON_BUS_CNTL, tmp); 509 /* FIXME: setup default page */ 510 WREG32_MC(R_000100_MC_PT0_CNTL, 511 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | 512 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6))); 513 514 for (i = 0; i < 19; i++) { 515 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, 516 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) | 517 S_00016C_SYSTEM_ACCESS_MODE_MASK( 518 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) | 519 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS( 520 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) | 521 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) | 522 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) | 523 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3)); 524 } 525 /* enable first context */ 526 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, 527 S_000102_ENABLE_PAGE_TABLE(1) | 528 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT)); 529 530 /* disable all other contexts */ 531 for (i = 1; i < 8; i++) 532 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); 533 534 /* setup the page table */ 535 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 536 rdev->gart.table_addr); 537 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); 538 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); 539 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 540 541 /* System context maps to VRAM space */ 542 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); 543 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); 544 545 /* enable page tables */ 546 tmp = RREG32_MC(R_000100_MC_PT0_CNTL); 547 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); 548 tmp = RREG32_MC(R_000009_MC_CNTL1); 549 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); 550 rs600_gart_tlb_flush(rdev); 551 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 552 (unsigned)(rdev->mc.gtt_size >> 20), 553 (unsigned long long)rdev->gart.table_addr); 554 rdev->gart.ready = true; 555 return 0; 556 } 557 558 static void rs600_gart_disable(struct radeon_device *rdev) 559 { 560 u32 tmp; 561 562 /* FIXME: disable out of gart access */ 563 WREG32_MC(R_000100_MC_PT0_CNTL, 0); 564 tmp = RREG32_MC(R_000009_MC_CNTL1); 565 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); 566 radeon_gart_table_vram_unpin(rdev); 567 } 568 569 static void rs600_gart_fini(struct radeon_device *rdev) 570 { 571 radeon_gart_fini(rdev); 572 rs600_gart_disable(rdev); 573 radeon_gart_table_vram_free(rdev); 574 } 575 576 #define R600_PTE_VALID (1 << 0) 577 #define R600_PTE_SYSTEM (1 << 1) 578 #define R600_PTE_SNOOPED (1 << 2) 579 #define R600_PTE_READABLE (1 << 5) 580 #define R600_PTE_WRITEABLE (1 << 6) 581 582 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 583 { 584 volatile uint64_t *ptr = rdev->gart.ptr; 585 586 if (i < 0 || i > rdev->gart.num_gpu_pages) { 587 return -EINVAL; 588 } 589 addr = addr & 0xFFFFFFFFFFFFF000ULL; 590 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 591 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 592 ptr += i; 593 *ptr = addr; 594 return 0; 595 } 596 597 int rs600_irq_set(struct radeon_device *rdev) 598 { 599 uint32_t tmp = 0; 600 uint32_t mode_int = 0; 601 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) & 602 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 603 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 604 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 605 u32 hdmi0; 606 if (ASIC_IS_DCE2(rdev)) 607 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 608 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 609 else 610 hdmi0 = 0; 611 612 if (!rdev->irq.installed) { 613 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 614 WREG32(R_000040_GEN_INT_CNTL, 0); 615 return -EINVAL; 616 } 617 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 618 tmp |= S_000040_SW_INT_EN(1); 619 } 620 if (rdev->irq.crtc_vblank_int[0] || 621 atomic_read(&rdev->irq.pflip[0])) { 622 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1); 623 } 624 if (rdev->irq.crtc_vblank_int[1] || 625 atomic_read(&rdev->irq.pflip[1])) { 626 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1); 627 } 628 if (rdev->irq.hpd[0]) { 629 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1); 630 } 631 if (rdev->irq.hpd[1]) { 632 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 633 } 634 if (rdev->irq.afmt[0]) { 635 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 636 } 637 WREG32(R_000040_GEN_INT_CNTL, tmp); 638 WREG32(R_006540_DxMODE_INT_MASK, mode_int); 639 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 640 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 641 if (ASIC_IS_DCE2(rdev)) 642 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 643 return 0; 644 } 645 646 static inline u32 rs600_irq_ack(struct radeon_device *rdev) 647 { 648 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS); 649 uint32_t irq_mask = S_000044_SW_INT(1); 650 u32 tmp; 651 652 if (G_000044_DISPLAY_INT_STAT(irqs)) { 653 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); 654 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 655 WREG32(R_006534_D1MODE_VBLANK_STATUS, 656 S_006534_D1MODE_VBLANK_ACK(1)); 657 } 658 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 659 WREG32(R_006D34_D2MODE_VBLANK_STATUS, 660 S_006D34_D2MODE_VBLANK_ACK(1)); 661 } 662 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 663 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL); 664 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1); 665 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 666 } 667 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 668 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL); 669 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1); 670 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 671 } 672 } else { 673 rdev->irq.stat_regs.r500.disp_int = 0; 674 } 675 676 if (ASIC_IS_DCE2(rdev)) { 677 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & 678 S_007404_HDMI0_AZ_FORMAT_WTRIG(1); 679 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 680 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL); 681 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1); 682 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp); 683 } 684 } else 685 rdev->irq.stat_regs.r500.hdmi0_status = 0; 686 687 if (irqs) { 688 WREG32(R_000044_GEN_INT_STATUS, irqs); 689 } 690 return irqs & irq_mask; 691 } 692 693 void rs600_irq_disable(struct radeon_device *rdev) 694 { 695 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) & 696 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1); 697 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 698 WREG32(R_000040_GEN_INT_CNTL, 0); 699 WREG32(R_006540_DxMODE_INT_MASK, 0); 700 /* Wait and acknowledge irq */ 701 mdelay(1); 702 rs600_irq_ack(rdev); 703 } 704 705 int rs600_irq_process(struct radeon_device *rdev) 706 { 707 u32 status, msi_rearm; 708 bool queue_hotplug = false; 709 bool queue_hdmi = false; 710 711 status = rs600_irq_ack(rdev); 712 if (!status && 713 !rdev->irq.stat_regs.r500.disp_int && 714 !rdev->irq.stat_regs.r500.hdmi0_status) { 715 return IRQ_NONE; 716 } 717 while (status || 718 rdev->irq.stat_regs.r500.disp_int || 719 rdev->irq.stat_regs.r500.hdmi0_status) { 720 /* SW interrupt */ 721 if (G_000044_SW_INT(status)) { 722 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 723 } 724 /* Vertical blank interrupts */ 725 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 726 if (rdev->irq.crtc_vblank_int[0]) { 727 drm_handle_vblank(rdev->ddev, 0); 728 rdev->pm.vblank_sync = true; 729 wake_up(&rdev->irq.vblank_queue); 730 } 731 if (atomic_read(&rdev->irq.pflip[0])) 732 radeon_crtc_handle_flip(rdev, 0); 733 } 734 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 735 if (rdev->irq.crtc_vblank_int[1]) { 736 drm_handle_vblank(rdev->ddev, 1); 737 rdev->pm.vblank_sync = true; 738 wake_up(&rdev->irq.vblank_queue); 739 } 740 if (atomic_read(&rdev->irq.pflip[1])) 741 radeon_crtc_handle_flip(rdev, 1); 742 } 743 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 744 queue_hotplug = true; 745 DRM_DEBUG("HPD1\n"); 746 } 747 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { 748 queue_hotplug = true; 749 DRM_DEBUG("HPD2\n"); 750 } 751 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { 752 queue_hdmi = true; 753 DRM_DEBUG("HDMI0\n"); 754 } 755 status = rs600_irq_ack(rdev); 756 } 757 if (queue_hotplug) 758 task_add(systq, &rdev->hotplug_task); 759 if (queue_hdmi) 760 task_add(systq, &rdev->audio_task); 761 if (rdev->msi_enabled) { 762 switch (rdev->family) { 763 case CHIP_RS600: 764 case CHIP_RS690: 765 case CHIP_RS740: 766 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; 767 WREG32(RADEON_BUS_CNTL, msi_rearm); 768 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); 769 break; 770 default: 771 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 772 break; 773 } 774 } 775 return IRQ_HANDLED; 776 } 777 778 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) 779 { 780 if (crtc == 0) 781 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT); 782 else 783 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT); 784 } 785 786 int rs600_mc_wait_for_idle(struct radeon_device *rdev) 787 { 788 unsigned i; 789 790 for (i = 0; i < rdev->usec_timeout; i++) { 791 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS))) 792 return 0; 793 udelay(1); 794 } 795 return -1; 796 } 797 798 static void rs600_gpu_init(struct radeon_device *rdev) 799 { 800 r420_pipes_init(rdev); 801 /* Wait for mc idle */ 802 if (rs600_mc_wait_for_idle(rdev)) 803 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 804 } 805 806 static void rs600_mc_init(struct radeon_device *rdev) 807 { 808 u64 base; 809 810 rdev->mc.aper_base = rdev->fb_aper_offset; 811 rdev->mc.aper_size = rdev->fb_aper_size; 812 rdev->mc.vram_is_ddr = true; 813 rdev->mc.vram_width = 128; 814 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 815 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 816 rdev->mc.visible_vram_size = rdev->mc.aper_size; 817 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 818 base = RREG32_MC(R_000004_MC_FB_LOCATION); 819 base = G_000004_MC_FB_START(base) << 16; 820 radeon_vram_location(rdev, &rdev->mc, base); 821 rdev->mc.gtt_base_align = 0; 822 radeon_gtt_location(rdev, &rdev->mc); 823 radeon_update_bandwidth_info(rdev); 824 } 825 826 void rs600_bandwidth_update(struct radeon_device *rdev) 827 { 828 struct drm_display_mode *mode0 = NULL; 829 struct drm_display_mode *mode1 = NULL; 830 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt; 831 /* FIXME: implement full support */ 832 833 radeon_update_display_priority(rdev); 834 835 if (rdev->mode_info.crtcs[0]->base.enabled) 836 mode0 = &rdev->mode_info.crtcs[0]->base.mode; 837 if (rdev->mode_info.crtcs[1]->base.enabled) 838 mode1 = &rdev->mode_info.crtcs[1]->base.mode; 839 840 rs690_line_buffer_adjust(rdev, mode0, mode1); 841 842 if (rdev->disp_priority == 2) { 843 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT); 844 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT); 845 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1); 846 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1); 847 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt); 848 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt); 849 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt); 850 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt); 851 } 852 } 853 854 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) 855 { 856 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 857 S_000070_MC_IND_CITF_ARB0(1)); 858 return RREG32(R_000074_MC_IND_DATA); 859 } 860 861 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 862 { 863 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) | 864 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1)); 865 WREG32(R_000074_MC_IND_DATA, v); 866 } 867 868 static void rs600_debugfs(struct radeon_device *rdev) 869 { 870 if (r100_debugfs_rbbm_init(rdev)) 871 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 872 } 873 874 void rs600_set_safe_registers(struct radeon_device *rdev) 875 { 876 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; 877 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); 878 } 879 880 static void rs600_mc_program(struct radeon_device *rdev) 881 { 882 struct rv515_mc_save save; 883 884 /* Stops all mc clients */ 885 rv515_mc_stop(rdev, &save); 886 887 /* Wait for mc idle */ 888 if (rs600_mc_wait_for_idle(rdev)) 889 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 890 891 /* FIXME: What does AGP means for such chipset ? */ 892 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); 893 WREG32_MC(R_000006_AGP_BASE, 0); 894 WREG32_MC(R_000007_AGP_BASE_2, 0); 895 /* Program MC */ 896 WREG32_MC(R_000004_MC_FB_LOCATION, 897 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 898 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 899 WREG32(R_000134_HDP_FB_LOCATION, 900 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 901 902 rv515_mc_resume(rdev, &save); 903 } 904 905 static int rs600_startup(struct radeon_device *rdev) 906 { 907 int r; 908 909 rs600_mc_program(rdev); 910 /* Resume clock */ 911 rv515_clock_startup(rdev); 912 /* Initialize GPU configuration (# pipes, ...) */ 913 rs600_gpu_init(rdev); 914 /* Initialize GART (initialize after TTM so we can allocate 915 * memory through TTM but finalize after TTM) */ 916 r = rs600_gart_enable(rdev); 917 if (r) 918 return r; 919 920 /* allocate wb buffer */ 921 r = radeon_wb_init(rdev); 922 if (r) 923 return r; 924 925 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 926 if (r) { 927 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 928 return r; 929 } 930 931 /* Enable IRQ */ 932 if (!rdev->irq.installed) { 933 r = radeon_irq_kms_init(rdev); 934 if (r) 935 return r; 936 } 937 938 rs600_irq_set(rdev); 939 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 940 /* 1M ring buffer */ 941 r = r100_cp_init(rdev, 1024 * 1024); 942 if (r) { 943 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 944 return r; 945 } 946 947 r = radeon_ib_pool_init(rdev); 948 if (r) { 949 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 950 return r; 951 } 952 953 r = r600_audio_init(rdev); 954 if (r) { 955 dev_err(rdev->dev, "failed initializing audio\n"); 956 return r; 957 } 958 959 return 0; 960 } 961 962 int rs600_resume(struct radeon_device *rdev) 963 { 964 int r; 965 966 /* Make sur GART are not working */ 967 rs600_gart_disable(rdev); 968 /* Resume clock before doing reset */ 969 rv515_clock_startup(rdev); 970 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 971 if (radeon_asic_reset(rdev)) { 972 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 973 RREG32(R_000E40_RBBM_STATUS), 974 RREG32(R_0007C0_CP_STAT)); 975 } 976 /* post */ 977 atom_asic_init(rdev->mode_info.atom_context); 978 /* Resume clock after posting */ 979 rv515_clock_startup(rdev); 980 /* Initialize surface registers */ 981 radeon_surface_init(rdev); 982 983 rdev->accel_working = true; 984 r = rs600_startup(rdev); 985 if (r) { 986 rdev->accel_working = false; 987 } 988 return r; 989 } 990 991 int rs600_suspend(struct radeon_device *rdev) 992 { 993 r600_audio_fini(rdev); 994 r100_cp_disable(rdev); 995 radeon_wb_disable(rdev); 996 rs600_irq_disable(rdev); 997 rs600_gart_disable(rdev); 998 return 0; 999 } 1000 1001 void rs600_fini(struct radeon_device *rdev) 1002 { 1003 r600_audio_fini(rdev); 1004 r100_cp_fini(rdev); 1005 radeon_wb_fini(rdev); 1006 radeon_ib_pool_fini(rdev); 1007 radeon_gem_fini(rdev); 1008 rs600_gart_fini(rdev); 1009 radeon_irq_kms_fini(rdev); 1010 radeon_fence_driver_fini(rdev); 1011 radeon_bo_fini(rdev); 1012 radeon_atombios_fini(rdev); 1013 kfree(rdev->bios); 1014 rdev->bios = NULL; 1015 } 1016 1017 int rs600_init(struct radeon_device *rdev) 1018 { 1019 int r; 1020 1021 /* Disable VGA */ 1022 rv515_vga_render_disable(rdev); 1023 /* Initialize scratch registers */ 1024 radeon_scratch_init(rdev); 1025 /* Initialize surface registers */ 1026 radeon_surface_init(rdev); 1027 /* restore some register to sane defaults */ 1028 r100_restore_sanity(rdev); 1029 /* BIOS */ 1030 if (!radeon_get_bios(rdev)) { 1031 if (ASIC_IS_AVIVO(rdev)) 1032 return -EINVAL; 1033 } 1034 if (rdev->is_atom_bios) { 1035 r = radeon_atombios_init(rdev); 1036 if (r) 1037 return r; 1038 } else { 1039 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); 1040 return -EINVAL; 1041 } 1042 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1043 if (radeon_asic_reset(rdev)) { 1044 dev_warn(rdev->dev, 1045 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1046 RREG32(R_000E40_RBBM_STATUS), 1047 RREG32(R_0007C0_CP_STAT)); 1048 } 1049 /* check if cards are posted or not */ 1050 if (radeon_boot_test_post_card(rdev) == false) 1051 return -EINVAL; 1052 1053 /* Initialize clocks */ 1054 radeon_get_clock_info(rdev->ddev); 1055 /* initialize memory controller */ 1056 rs600_mc_init(rdev); 1057 rs600_debugfs(rdev); 1058 /* Fence driver */ 1059 r = radeon_fence_driver_init(rdev); 1060 if (r) 1061 return r; 1062 /* Memory manager */ 1063 r = radeon_bo_init(rdev); 1064 if (r) 1065 return r; 1066 r = rs600_gart_init(rdev); 1067 if (r) 1068 return r; 1069 rs600_set_safe_registers(rdev); 1070 1071 rdev->accel_working = true; 1072 r = rs600_startup(rdev); 1073 if (r) { 1074 /* Somethings want wront with the accel init stop accel */ 1075 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1076 r100_cp_fini(rdev); 1077 radeon_wb_fini(rdev); 1078 radeon_ib_pool_fini(rdev); 1079 rs600_gart_fini(rdev); 1080 radeon_irq_kms_fini(rdev); 1081 rdev->accel_working = false; 1082 } 1083 return 0; 1084 } 1085