1 /* $OpenBSD: radeon_pm.c,v 1.14 2015/09/23 23:12:12 kettenis Exp $ */ 2 /* 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: Rafał Miłecki <zajec5@gmail.com> 22 * Alex Deucher <alexdeucher@gmail.com> 23 */ 24 #include <dev/pci/drm/drmP.h> 25 #include "radeon.h" 26 #include "avivod.h" 27 #include "atom.h" 28 29 #define RADEON_IDLE_LOOP_MS 100 30 #define RADEON_RECLOCK_DELAY_MS 200 31 #define RADEON_WAIT_VBLANK_TIMEOUT 200 32 33 #ifdef DRMDEBUG 34 static const char *radeon_pm_state_type_name[5] = { 35 "", 36 "Powersave", 37 "Battery", 38 "Balanced", 39 "Performance", 40 }; 41 #endif 42 43 static void radeon_dynpm_idle_work_handler(struct work_struct *work); 44 static int radeon_debugfs_pm_init(struct radeon_device *rdev); 45 static bool radeon_pm_in_vbl(struct radeon_device *rdev); 46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 47 static void radeon_pm_update_profile(struct radeon_device *rdev); 48 static void radeon_pm_set_clocks(struct radeon_device *rdev); 49 50 int radeon_pm_get_type_index(struct radeon_device *rdev, 51 enum radeon_pm_state_type ps_type, 52 int instance) 53 { 54 int i; 55 int found_instance = -1; 56 57 for (i = 0; i < rdev->pm.num_power_states; i++) { 58 if (rdev->pm.power_state[i].type == ps_type) { 59 found_instance++; 60 if (found_instance == instance) 61 return i; 62 } 63 } 64 /* return default if no match */ 65 return rdev->pm.default_power_state_index; 66 } 67 68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 69 { 70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 71 if (rdev->pm.profile == PM_PROFILE_AUTO) { 72 mutex_lock(&rdev->pm.mutex); 73 radeon_pm_update_profile(rdev); 74 radeon_pm_set_clocks(rdev); 75 mutex_unlock(&rdev->pm.mutex); 76 } 77 } 78 } 79 80 static void radeon_pm_update_profile(struct radeon_device *rdev) 81 { 82 switch (rdev->pm.profile) { 83 case PM_PROFILE_DEFAULT: 84 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 85 break; 86 case PM_PROFILE_AUTO: 87 if (power_supply_is_system_supplied() > 0) { 88 if (rdev->pm.active_crtc_count > 1) 89 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 90 else 91 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 92 } else { 93 if (rdev->pm.active_crtc_count > 1) 94 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 95 else 96 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 97 } 98 break; 99 case PM_PROFILE_LOW: 100 if (rdev->pm.active_crtc_count > 1) 101 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 102 else 103 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 104 break; 105 case PM_PROFILE_MID: 106 if (rdev->pm.active_crtc_count > 1) 107 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 108 else 109 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 110 break; 111 case PM_PROFILE_HIGH: 112 if (rdev->pm.active_crtc_count > 1) 113 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 114 else 115 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 116 break; 117 } 118 119 if (rdev->pm.active_crtc_count == 0) { 120 rdev->pm.requested_power_state_index = 121 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 122 rdev->pm.requested_clock_mode_index = 123 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 124 } else { 125 rdev->pm.requested_power_state_index = 126 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 127 rdev->pm.requested_clock_mode_index = 128 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 129 } 130 } 131 132 static void radeon_unmap_vram_bos(struct radeon_device *rdev) 133 { 134 struct radeon_bo *bo, *n; 135 136 if (list_empty(&rdev->gem.objects)) 137 return; 138 139 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 140 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 141 ttm_bo_unmap_virtual(&bo->tbo); 142 } 143 } 144 145 static void radeon_sync_with_vblank(struct radeon_device *rdev) 146 { 147 if (rdev->pm.active_crtcs) { 148 rdev->pm.vblank_sync = false; 149 tsleep(&rdev->irq.vblank_queue, PZERO, "rdnsvb", 150 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 151 } 152 } 153 154 static void radeon_set_power_state(struct radeon_device *rdev) 155 { 156 u32 sclk, mclk; 157 bool misc_after = false; 158 159 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 160 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 161 return; 162 163 if (radeon_gui_idle(rdev)) { 164 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 165 clock_info[rdev->pm.requested_clock_mode_index].sclk; 166 if (sclk > rdev->pm.default_sclk) 167 sclk = rdev->pm.default_sclk; 168 169 /* starting with BTC, there is one state that is used for both 170 * MH and SH. Difference is that we always use the high clock index for 171 * mclk and vddci. 172 */ 173 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 174 (rdev->family >= CHIP_BARTS) && 175 rdev->pm.active_crtc_count && 176 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 177 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 178 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 179 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 180 else 181 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 182 clock_info[rdev->pm.requested_clock_mode_index].mclk; 183 184 if (mclk > rdev->pm.default_mclk) 185 mclk = rdev->pm.default_mclk; 186 187 /* upvolt before raising clocks, downvolt after lowering clocks */ 188 if (sclk < rdev->pm.current_sclk) 189 misc_after = true; 190 191 radeon_sync_with_vblank(rdev); 192 193 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 194 if (!radeon_pm_in_vbl(rdev)) 195 return; 196 } 197 198 radeon_pm_prepare(rdev); 199 200 if (!misc_after) 201 /* voltage, pcie lanes, etc.*/ 202 radeon_pm_misc(rdev); 203 204 /* set engine clock */ 205 if (sclk != rdev->pm.current_sclk) { 206 radeon_pm_debug_check_in_vbl(rdev, false); 207 radeon_set_engine_clock(rdev, sclk); 208 radeon_pm_debug_check_in_vbl(rdev, true); 209 rdev->pm.current_sclk = sclk; 210 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 211 } 212 213 /* set memory clock */ 214 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 215 radeon_pm_debug_check_in_vbl(rdev, false); 216 radeon_set_memory_clock(rdev, mclk); 217 radeon_pm_debug_check_in_vbl(rdev, true); 218 rdev->pm.current_mclk = mclk; 219 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 220 } 221 222 if (misc_after) 223 /* voltage, pcie lanes, etc.*/ 224 radeon_pm_misc(rdev); 225 226 radeon_pm_finish(rdev); 227 228 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 229 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 230 } else 231 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 232 } 233 234 static void radeon_pm_set_clocks(struct radeon_device *rdev) 235 { 236 int i, r; 237 238 /* no need to take locks, etc. if nothing's going to change */ 239 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 240 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 241 return; 242 243 mutex_lock(&rdev->ddev->struct_mutex); 244 down_write(&rdev->pm.mclk_lock); 245 mutex_lock(&rdev->ring_lock); 246 247 /* wait for the rings to drain */ 248 for (i = 0; i < RADEON_NUM_RINGS; i++) { 249 struct radeon_ring *ring = &rdev->ring[i]; 250 if (!ring->ready) { 251 continue; 252 } 253 r = radeon_fence_wait_empty_locked(rdev, i); 254 if (r) { 255 /* needs a GPU reset dont reset here */ 256 mutex_unlock(&rdev->ring_lock); 257 up_write(&rdev->pm.mclk_lock); 258 mutex_unlock(&rdev->ddev->struct_mutex); 259 return; 260 } 261 } 262 263 radeon_unmap_vram_bos(rdev); 264 265 if (rdev->irq.installed) { 266 for (i = 0; i < rdev->num_crtc; i++) { 267 if (rdev->pm.active_crtcs & (1 << i)) { 268 rdev->pm.req_vblank |= (1 << i); 269 drm_vblank_get(rdev->ddev, i); 270 } 271 } 272 } 273 274 radeon_set_power_state(rdev); 275 276 if (rdev->irq.installed) { 277 for (i = 0; i < rdev->num_crtc; i++) { 278 if (rdev->pm.req_vblank & (1 << i)) { 279 rdev->pm.req_vblank &= ~(1 << i); 280 drm_vblank_put(rdev->ddev, i); 281 } 282 } 283 } 284 285 /* update display watermarks based on new power state */ 286 radeon_update_bandwidth_info(rdev); 287 if (rdev->pm.active_crtc_count) 288 radeon_bandwidth_update(rdev); 289 290 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 291 292 mutex_unlock(&rdev->ring_lock); 293 up_write(&rdev->pm.mclk_lock); 294 mutex_unlock(&rdev->ddev->struct_mutex); 295 } 296 297 static void radeon_pm_print_states(struct radeon_device *rdev) 298 { 299 int i, j; 300 struct radeon_power_state *power_state; 301 struct radeon_pm_clock_info *clock_info; 302 303 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 304 for (i = 0; i < rdev->pm.num_power_states; i++) { 305 power_state = &rdev->pm.power_state[i]; 306 DRM_DEBUG_DRIVER("State %d: %s\n", i, 307 radeon_pm_state_type_name[power_state->type]); 308 if (i == rdev->pm.default_power_state_index) 309 DRM_DEBUG_DRIVER("\tDefault"); 310 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 311 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 312 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 313 DRM_DEBUG_DRIVER("\tSingle display only\n"); 314 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 315 for (j = 0; j < power_state->num_clock_modes; j++) { 316 clock_info = &(power_state->clock_info[j]); 317 if (rdev->flags & RADEON_IS_IGP) 318 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 319 j, 320 clock_info->sclk * 10); 321 else 322 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 323 j, 324 clock_info->sclk * 10, 325 clock_info->mclk * 10, 326 clock_info->voltage.voltage); 327 } 328 } 329 } 330 331 #ifdef notyet 332 static ssize_t radeon_get_pm_profile(struct device *dev, 333 struct device_attribute *attr, 334 char *buf) 335 { 336 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 337 struct radeon_device *rdev = ddev->dev_private; 338 int cp = rdev->pm.profile; 339 340 return snprintf(buf, PAGE_SIZE, "%s\n", 341 (cp == PM_PROFILE_AUTO) ? "auto" : 342 (cp == PM_PROFILE_LOW) ? "low" : 343 (cp == PM_PROFILE_MID) ? "mid" : 344 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 345 } 346 347 static ssize_t radeon_set_pm_profile(struct device *dev, 348 struct device_attribute *attr, 349 const char *buf, 350 size_t count) 351 { 352 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 353 struct radeon_device *rdev = ddev->dev_private; 354 355 mutex_lock(&rdev->pm.mutex); 356 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 357 if (strncmp("default", buf, strlen("default")) == 0) 358 rdev->pm.profile = PM_PROFILE_DEFAULT; 359 else if (strncmp("auto", buf, strlen("auto")) == 0) 360 rdev->pm.profile = PM_PROFILE_AUTO; 361 else if (strncmp("low", buf, strlen("low")) == 0) 362 rdev->pm.profile = PM_PROFILE_LOW; 363 else if (strncmp("mid", buf, strlen("mid")) == 0) 364 rdev->pm.profile = PM_PROFILE_MID; 365 else if (strncmp("high", buf, strlen("high")) == 0) 366 rdev->pm.profile = PM_PROFILE_HIGH; 367 else { 368 count = -EINVAL; 369 goto fail; 370 } 371 radeon_pm_update_profile(rdev); 372 radeon_pm_set_clocks(rdev); 373 } else 374 count = -EINVAL; 375 376 fail: 377 mutex_unlock(&rdev->pm.mutex); 378 379 return count; 380 } 381 382 static ssize_t radeon_get_pm_method(struct device *dev, 383 struct device_attribute *attr, 384 char *buf) 385 { 386 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 387 struct radeon_device *rdev = ddev->dev_private; 388 int pm = rdev->pm.pm_method; 389 390 return snprintf(buf, PAGE_SIZE, "%s\n", 391 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile"); 392 } 393 394 static ssize_t radeon_set_pm_method(struct device *dev, 395 struct device_attribute *attr, 396 const char *buf, 397 size_t count) 398 { 399 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 400 struct radeon_device *rdev = ddev->dev_private; 401 402 403 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 404 mutex_lock(&rdev->pm.mutex); 405 rdev->pm.pm_method = PM_METHOD_DYNPM; 406 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 407 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 408 mutex_unlock(&rdev->pm.mutex); 409 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 410 mutex_lock(&rdev->pm.mutex); 411 /* disable dynpm */ 412 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 413 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 414 rdev->pm.pm_method = PM_METHOD_PROFILE; 415 mutex_unlock(&rdev->pm.mutex); 416 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 417 } else { 418 count = -EINVAL; 419 goto fail; 420 } 421 radeon_pm_compute_clocks(rdev); 422 fail: 423 return count; 424 } 425 426 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 427 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 428 #endif /* notyet */ 429 430 #ifdef notyet 431 static ssize_t radeon_hwmon_show_temp(struct device *dev, 432 struct device_attribute *attr, 433 char *buf) 434 { 435 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); 436 struct radeon_device *rdev = ddev->dev_private; 437 int temp; 438 439 switch (rdev->pm.int_thermal_type) { 440 case THERMAL_TYPE_RV6XX: 441 temp = rv6xx_get_temp(rdev); 442 break; 443 case THERMAL_TYPE_RV770: 444 temp = rv770_get_temp(rdev); 445 break; 446 case THERMAL_TYPE_EVERGREEN: 447 case THERMAL_TYPE_NI: 448 temp = evergreen_get_temp(rdev); 449 break; 450 case THERMAL_TYPE_SUMO: 451 temp = sumo_get_temp(rdev); 452 break; 453 case THERMAL_TYPE_SI: 454 temp = si_get_temp(rdev); 455 break; 456 default: 457 temp = 0; 458 break; 459 } 460 461 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 462 } 463 464 static ssize_t radeon_hwmon_show_name(struct device *dev, 465 struct device_attribute *attr, 466 char *buf) 467 { 468 return sprintf(buf, "radeon\n"); 469 } 470 471 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 472 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0); 473 474 static struct attribute *hwmon_attributes[] = { 475 &sensor_dev_attr_temp1_input.dev_attr.attr, 476 &sensor_dev_attr_name.dev_attr.attr, 477 NULL 478 }; 479 480 static const struct attribute_group hwmon_attrgroup = { 481 .attrs = hwmon_attributes, 482 }; 483 #endif 484 485 static int radeon_hwmon_init(struct radeon_device *rdev) 486 { 487 int err = 0; 488 489 rdev->pm.int_hwmon_dev = NULL; 490 491 switch (rdev->pm.int_thermal_type) { 492 case THERMAL_TYPE_RV6XX: 493 case THERMAL_TYPE_RV770: 494 case THERMAL_TYPE_EVERGREEN: 495 case THERMAL_TYPE_NI: 496 case THERMAL_TYPE_SUMO: 497 case THERMAL_TYPE_SI: 498 /* No support for TN yet */ 499 if (rdev->family == CHIP_ARUBA) 500 return err; 501 #ifdef notyet 502 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 503 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 504 err = PTR_ERR(rdev->pm.int_hwmon_dev); 505 dev_err(rdev->dev, 506 "Unable to register hwmon device: %d\n", err); 507 break; 508 } 509 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev); 510 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj, 511 &hwmon_attrgroup); 512 if (err) { 513 dev_err(rdev->dev, 514 "Unable to create hwmon sysfs file: %d\n", err); 515 hwmon_device_unregister(rdev->dev); 516 } 517 break; 518 #endif 519 default: 520 break; 521 } 522 523 return err; 524 } 525 526 static void radeon_hwmon_fini(struct radeon_device *rdev) 527 { 528 printf("%s stub\n", __func__); 529 #ifdef notyet 530 if (rdev->pm.int_hwmon_dev) { 531 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup); 532 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 533 } 534 #endif 535 } 536 537 void radeon_pm_suspend(struct radeon_device *rdev) 538 { 539 mutex_lock(&rdev->pm.mutex); 540 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 541 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 542 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 543 } 544 mutex_unlock(&rdev->pm.mutex); 545 546 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 547 } 548 549 void radeon_pm_resume(struct radeon_device *rdev) 550 { 551 /* set up the default clocks if the MC ucode is loaded */ 552 if ((rdev->family >= CHIP_BARTS) && 553 (rdev->family <= CHIP_CAYMAN) && 554 rdev->mc_fw) { 555 if (rdev->pm.default_vddc) 556 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 557 SET_VOLTAGE_TYPE_ASIC_VDDC); 558 if (rdev->pm.default_vddci) 559 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 560 SET_VOLTAGE_TYPE_ASIC_VDDCI); 561 if (rdev->pm.default_sclk) 562 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 563 if (rdev->pm.default_mclk) 564 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 565 } 566 /* asic init will reset the default power state */ 567 mutex_lock(&rdev->pm.mutex); 568 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 569 rdev->pm.current_clock_mode_index = 0; 570 rdev->pm.current_sclk = rdev->pm.default_sclk; 571 rdev->pm.current_mclk = rdev->pm.default_mclk; 572 if (rdev->pm.power_state) { 573 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 574 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 575 } 576 if (rdev->pm.pm_method == PM_METHOD_DYNPM 577 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 578 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 579 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 580 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 581 } 582 mutex_unlock(&rdev->pm.mutex); 583 radeon_pm_compute_clocks(rdev); 584 } 585 586 int radeon_pm_init(struct radeon_device *rdev) 587 { 588 int ret; 589 590 /* default to profile method */ 591 rdev->pm.pm_method = PM_METHOD_PROFILE; 592 rdev->pm.profile = PM_PROFILE_DEFAULT; 593 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 594 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 595 rdev->pm.dynpm_can_upclock = true; 596 rdev->pm.dynpm_can_downclock = true; 597 rdev->pm.default_sclk = rdev->clock.default_sclk; 598 rdev->pm.default_mclk = rdev->clock.default_mclk; 599 rdev->pm.current_sclk = rdev->clock.default_sclk; 600 rdev->pm.current_mclk = rdev->clock.default_mclk; 601 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 602 603 if (rdev->bios) { 604 if (rdev->is_atom_bios) 605 radeon_atombios_get_power_modes(rdev); 606 else 607 radeon_combios_get_power_modes(rdev); 608 radeon_pm_print_states(rdev); 609 radeon_pm_init_profile(rdev); 610 /* set up the default clocks if the MC ucode is loaded */ 611 if ((rdev->family >= CHIP_BARTS) && 612 (rdev->family <= CHIP_CAYMAN) && 613 rdev->mc_fw) { 614 if (rdev->pm.default_vddc) 615 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 616 SET_VOLTAGE_TYPE_ASIC_VDDC); 617 if (rdev->pm.default_vddci) 618 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 619 SET_VOLTAGE_TYPE_ASIC_VDDCI); 620 if (rdev->pm.default_sclk) 621 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 622 if (rdev->pm.default_mclk) 623 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 624 } 625 } 626 627 /* set up the internal thermal sensor if applicable */ 628 ret = radeon_hwmon_init(rdev); 629 if (ret) 630 return ret; 631 632 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 633 634 if (rdev->pm.num_power_states > 1) { 635 #ifdef notyet 636 /* where's the best place to put these? */ 637 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 638 if (ret) 639 DRM_ERROR("failed to create device file for power profile\n"); 640 ret = device_create_file(rdev->dev, &dev_attr_power_method); 641 if (ret) 642 DRM_ERROR("failed to create device file for power method\n"); 643 #endif 644 if (radeon_debugfs_pm_init(rdev)) { 645 DRM_ERROR("Failed to register debugfs file for PM!\n"); 646 } 647 648 #ifdef DRMDEBUG 649 DRM_INFO("radeon: power management initialized\n"); 650 #endif 651 } 652 653 return 0; 654 } 655 656 void radeon_pm_fini(struct radeon_device *rdev) 657 { 658 if (rdev->pm.num_power_states > 1) { 659 mutex_lock(&rdev->pm.mutex); 660 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 661 rdev->pm.profile = PM_PROFILE_DEFAULT; 662 radeon_pm_update_profile(rdev); 663 radeon_pm_set_clocks(rdev); 664 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 665 /* reset default clocks */ 666 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 667 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 668 radeon_pm_set_clocks(rdev); 669 } 670 mutex_unlock(&rdev->pm.mutex); 671 672 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 673 674 #ifdef notyet 675 device_remove_file(rdev->dev, &dev_attr_power_profile); 676 device_remove_file(rdev->dev, &dev_attr_power_method); 677 #endif 678 } 679 680 if (rdev->pm.power_state) 681 kfree(rdev->pm.power_state); 682 683 radeon_hwmon_fini(rdev); 684 } 685 686 void radeon_pm_compute_clocks(struct radeon_device *rdev) 687 { 688 struct drm_device *ddev = rdev->ddev; 689 struct drm_crtc *crtc; 690 struct radeon_crtc *radeon_crtc; 691 692 if (rdev->pm.num_power_states < 2) 693 return; 694 695 mutex_lock(&rdev->pm.mutex); 696 697 rdev->pm.active_crtcs = 0; 698 rdev->pm.active_crtc_count = 0; 699 list_for_each_entry(crtc, 700 &ddev->mode_config.crtc_list, head) { 701 radeon_crtc = to_radeon_crtc(crtc); 702 if (radeon_crtc->enabled) { 703 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 704 rdev->pm.active_crtc_count++; 705 } 706 } 707 708 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 709 radeon_pm_update_profile(rdev); 710 radeon_pm_set_clocks(rdev); 711 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 712 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 713 if (rdev->pm.active_crtc_count > 1) { 714 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 715 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 716 717 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 718 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 719 radeon_pm_get_dynpm_state(rdev); 720 radeon_pm_set_clocks(rdev); 721 722 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 723 } 724 } else if (rdev->pm.active_crtc_count == 1) { 725 /* TODO: Increase clocks if needed for current mode */ 726 727 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 728 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 729 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 730 radeon_pm_get_dynpm_state(rdev); 731 radeon_pm_set_clocks(rdev); 732 733 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 734 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 735 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 736 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 737 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 738 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 739 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 740 } 741 } else { /* count == 0 */ 742 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 743 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 744 745 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 746 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 747 radeon_pm_get_dynpm_state(rdev); 748 radeon_pm_set_clocks(rdev); 749 } 750 } 751 } 752 } 753 754 mutex_unlock(&rdev->pm.mutex); 755 } 756 757 static bool radeon_pm_in_vbl(struct radeon_device *rdev) 758 { 759 int crtc, vpos, hpos, vbl_status; 760 bool in_vbl = true; 761 762 /* Iterate over all active crtc's. All crtc's must be in vblank, 763 * otherwise return in_vbl == false. 764 */ 765 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 766 if (rdev->pm.active_crtcs & (1 << crtc)) { 767 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL); 768 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 769 !(vbl_status & DRM_SCANOUTPOS_INVBL)) 770 in_vbl = false; 771 } 772 } 773 774 return in_vbl; 775 } 776 777 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 778 { 779 #ifdef DRMDEBUG 780 u32 stat_crtc = 0; 781 #endif 782 bool in_vbl = radeon_pm_in_vbl(rdev); 783 784 if (in_vbl == false) 785 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 786 finish ? "exit" : "entry"); 787 return in_vbl; 788 } 789 790 static void radeon_dynpm_idle_work_handler(struct work_struct *work) 791 { 792 struct radeon_device *rdev; 793 int resched; 794 rdev = container_of(work, struct radeon_device, 795 pm.dynpm_idle_work.work); 796 797 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 798 mutex_lock(&rdev->pm.mutex); 799 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 800 int not_processed = 0; 801 int i; 802 803 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 804 struct radeon_ring *ring = &rdev->ring[i]; 805 806 if (ring->ready) { 807 not_processed += radeon_fence_count_emitted(rdev, i); 808 if (not_processed >= 3) 809 break; 810 } 811 } 812 813 if (not_processed >= 3) { /* should upclock */ 814 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 815 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 816 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 817 rdev->pm.dynpm_can_upclock) { 818 rdev->pm.dynpm_planned_action = 819 DYNPM_ACTION_UPCLOCK; 820 rdev->pm.dynpm_action_timeout = jiffies + 821 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 822 } 823 } else if (not_processed == 0) { /* should downclock */ 824 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 825 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 826 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 827 rdev->pm.dynpm_can_downclock) { 828 rdev->pm.dynpm_planned_action = 829 DYNPM_ACTION_DOWNCLOCK; 830 rdev->pm.dynpm_action_timeout = jiffies + 831 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 832 } 833 } 834 835 /* Note, radeon_pm_set_clocks is called with static_switch set 836 * to false since we want to wait for vbl to avoid flicker. 837 */ 838 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 839 jiffies > rdev->pm.dynpm_action_timeout) { 840 radeon_pm_get_dynpm_state(rdev); 841 radeon_pm_set_clocks(rdev); 842 } 843 844 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 845 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 846 } 847 mutex_unlock(&rdev->pm.mutex); 848 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 849 } 850 851 /* 852 * Debugfs info 853 */ 854 #if defined(CONFIG_DEBUG_FS) 855 856 static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 857 { 858 struct drm_info_node *node = (struct drm_info_node *) m->private; 859 struct drm_device *dev = node->minor->dev; 860 struct radeon_device *rdev = dev->dev_private; 861 862 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 863 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 864 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 865 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 866 else 867 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 868 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 869 if (rdev->asic->pm.get_memory_clock) 870 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 871 if (rdev->pm.current_vddc) 872 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 873 if (rdev->asic->pm.get_pcie_lanes) 874 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 875 876 return 0; 877 } 878 879 static struct drm_info_list radeon_pm_info_list[] = { 880 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 881 }; 882 #endif 883 884 static int radeon_debugfs_pm_init(struct radeon_device *rdev) 885 { 886 #if defined(CONFIG_DEBUG_FS) 887 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 888 #else 889 return 0; 890 #endif 891 } 892