1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 #include <linux/list.h> 33 #include <linux/slab.h> 34 #include <drm/drmP.h> 35 #include <drm/radeon_drm.h> 36 #include <drm/drm_cache.h> 37 #include "radeon.h" 38 #include "radeon_trace.h" 39 40 41 int radeon_ttm_init(struct radeon_device *rdev); 42 void radeon_ttm_fini(struct radeon_device *rdev); 43 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 44 45 /* 46 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 47 * function are calling it. 48 */ 49 50 static void radeon_update_memory_usage(struct radeon_bo *bo, 51 unsigned mem_type, int sign) 52 { 53 struct radeon_device *rdev = bo->rdev; 54 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT; 55 56 switch (mem_type) { 57 case TTM_PL_TT: 58 if (sign > 0) 59 atomic64_add(size, &rdev->gtt_usage); 60 else 61 atomic64_sub(size, &rdev->gtt_usage); 62 break; 63 case TTM_PL_VRAM: 64 if (sign > 0) 65 atomic64_add(size, &rdev->vram_usage); 66 else 67 atomic64_sub(size, &rdev->vram_usage); 68 break; 69 } 70 } 71 72 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 73 { 74 struct radeon_bo *bo; 75 76 bo = container_of(tbo, struct radeon_bo, tbo); 77 78 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1); 79 80 mutex_lock(&bo->rdev->gem.mutex); 81 list_del_init(&bo->list); 82 mutex_unlock(&bo->rdev->gem.mutex); 83 radeon_bo_clear_surface_reg(bo); 84 WARN_ON_ONCE(!list_empty(&bo->va)); 85 #ifdef notyet 86 if (bo->gem_base.import_attach) 87 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg); 88 #endif 89 drm_gem_object_release(&bo->gem_base); 90 pool_put(&bo->rdev->ddev->objpl, bo); 91 } 92 93 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 94 { 95 if (bo->destroy == &radeon_ttm_bo_destroy) 96 return true; 97 return false; 98 } 99 100 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 101 { 102 u32 c = 0, i; 103 104 rbo->placement.placement = rbo->placements; 105 rbo->placement.busy_placement = rbo->placements; 106 if (domain & RADEON_GEM_DOMAIN_VRAM) { 107 /* Try placing BOs which don't need CPU access outside of the 108 * CPU accessible part of VRAM 109 */ 110 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && 111 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { 112 rbo->placements[c].fpfn = 113 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 114 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 115 TTM_PL_FLAG_UNCACHED | 116 TTM_PL_FLAG_VRAM; 117 } 118 119 rbo->placements[c].fpfn = 0; 120 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 121 TTM_PL_FLAG_UNCACHED | 122 TTM_PL_FLAG_VRAM; 123 } 124 125 if (domain & RADEON_GEM_DOMAIN_GTT) { 126 if (rbo->flags & RADEON_GEM_GTT_UC) { 127 rbo->placements[c].fpfn = 0; 128 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 129 TTM_PL_FLAG_TT; 130 131 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 132 (rbo->rdev->flags & RADEON_IS_AGP)) { 133 rbo->placements[c].fpfn = 0; 134 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 135 TTM_PL_FLAG_UNCACHED | 136 TTM_PL_FLAG_TT; 137 } else { 138 rbo->placements[c].fpfn = 0; 139 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 140 TTM_PL_FLAG_TT; 141 } 142 } 143 144 if (domain & RADEON_GEM_DOMAIN_CPU) { 145 if (rbo->flags & RADEON_GEM_GTT_UC) { 146 rbo->placements[c].fpfn = 0; 147 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | 148 TTM_PL_FLAG_SYSTEM; 149 150 } else if ((rbo->flags & RADEON_GEM_GTT_WC) || 151 rbo->rdev->flags & RADEON_IS_AGP) { 152 rbo->placements[c].fpfn = 0; 153 rbo->placements[c++].flags = TTM_PL_FLAG_WC | 154 TTM_PL_FLAG_UNCACHED | 155 TTM_PL_FLAG_SYSTEM; 156 } else { 157 rbo->placements[c].fpfn = 0; 158 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | 159 TTM_PL_FLAG_SYSTEM; 160 } 161 } 162 if (!c) { 163 rbo->placements[c].fpfn = 0; 164 rbo->placements[c++].flags = TTM_PL_MASK_CACHING | 165 TTM_PL_FLAG_SYSTEM; 166 } 167 168 rbo->placement.num_placement = c; 169 rbo->placement.num_busy_placement = c; 170 171 for (i = 0; i < c; ++i) { 172 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 173 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 174 !rbo->placements[i].fpfn) 175 rbo->placements[i].lpfn = 176 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 177 else 178 rbo->placements[i].lpfn = 0; 179 } 180 } 181 182 int radeon_bo_create(struct radeon_device *rdev, 183 unsigned long size, int byte_align, bool kernel, 184 u32 domain, u32 flags, struct sg_table *sg, 185 struct reservation_object *resv, 186 struct radeon_bo **bo_ptr) 187 { 188 struct radeon_bo *bo; 189 enum ttm_bo_type type; 190 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 191 size_t acc_size; 192 int r; 193 194 size = PAGE_ALIGN(size); 195 196 if (kernel) { 197 type = ttm_bo_type_kernel; 198 } else if (sg) { 199 type = ttm_bo_type_sg; 200 } else { 201 type = ttm_bo_type_device; 202 } 203 *bo_ptr = NULL; 204 205 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 206 sizeof(struct radeon_bo)); 207 208 bo = pool_get(&rdev->ddev->objpl, PR_WAITOK | PR_ZERO); 209 if (bo == NULL) 210 return -ENOMEM; 211 drm_gem_private_object_init(rdev->ddev, &bo->gem_base, size); 212 bo->rdev = rdev; 213 bo->surface_reg = -1; 214 INIT_LIST_HEAD(&bo->list); 215 INIT_LIST_HEAD(&bo->va); 216 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 217 RADEON_GEM_DOMAIN_GTT | 218 RADEON_GEM_DOMAIN_CPU); 219 220 bo->flags = flags; 221 /* PCI GART is always snooped */ 222 if (!(rdev->flags & RADEON_IS_PCIE)) 223 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 224 225 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx 226 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 227 */ 228 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) 229 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 230 231 #ifdef CONFIG_X86_32 232 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 233 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 234 */ 235 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 236 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 237 /* Don't try to enable write-combining when it can't work, or things 238 * may be slow 239 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 240 */ 241 #ifndef CONFIG_COMPILE_TEST 242 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 243 thanks to write-combining 244 #endif 245 246 if (bo->flags & RADEON_GEM_GTT_WC) 247 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 248 "better performance thanks to write-combining\n"); 249 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 250 #else 251 /* For architectures that don't support WC memory, 252 * mask out the WC flag from the BO 253 */ 254 if (!drm_arch_can_wc_memory()) 255 bo->flags &= ~RADEON_GEM_GTT_WC; 256 #endif 257 258 radeon_ttm_placement_from_domain(bo, domain); 259 /* Kernel allocation are uninterruptible */ 260 down_read(&rdev->pm.mclk_lock); 261 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type, 262 &bo->placement, page_align, !kernel, acc_size, 263 sg, resv, &radeon_ttm_bo_destroy); 264 up_read(&rdev->pm.mclk_lock); 265 if (unlikely(r != 0)) { 266 return r; 267 } 268 *bo_ptr = bo; 269 270 trace_radeon_bo_create(bo); 271 272 return 0; 273 } 274 275 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 276 { 277 bool is_iomem; 278 int r; 279 280 if (bo->kptr) { 281 if (ptr) { 282 *ptr = bo->kptr; 283 } 284 return 0; 285 } 286 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 287 if (r) { 288 return r; 289 } 290 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 291 if (ptr) { 292 *ptr = bo->kptr; 293 } 294 radeon_bo_check_tiling(bo, 0, 0); 295 return 0; 296 } 297 298 void radeon_bo_kunmap(struct radeon_bo *bo) 299 { 300 if (bo->kptr == NULL) 301 return; 302 bo->kptr = NULL; 303 radeon_bo_check_tiling(bo, 0, 0); 304 ttm_bo_kunmap(&bo->kmap); 305 } 306 307 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 308 { 309 if (bo == NULL) 310 return NULL; 311 312 ttm_bo_get(&bo->tbo); 313 return bo; 314 } 315 316 void radeon_bo_unref(struct radeon_bo **bo) 317 { 318 struct ttm_buffer_object *tbo; 319 struct radeon_device *rdev; 320 321 if ((*bo) == NULL) 322 return; 323 rdev = (*bo)->rdev; 324 tbo = &((*bo)->tbo); 325 ttm_bo_put(tbo); 326 *bo = NULL; 327 } 328 329 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 330 u64 *gpu_addr) 331 { 332 struct ttm_operation_ctx ctx = { false, false }; 333 int r, i; 334 335 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm)) 336 return -EPERM; 337 338 if (bo->pin_count) { 339 bo->pin_count++; 340 if (gpu_addr) 341 *gpu_addr = radeon_bo_gpu_offset(bo); 342 343 if (max_offset != 0) { 344 u64 domain_start; 345 346 if (domain == RADEON_GEM_DOMAIN_VRAM) 347 domain_start = bo->rdev->mc.vram_start; 348 else 349 domain_start = bo->rdev->mc.gtt_start; 350 WARN_ON_ONCE(max_offset < 351 (radeon_bo_gpu_offset(bo) - domain_start)); 352 } 353 354 return 0; 355 } 356 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) { 357 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */ 358 return -EINVAL; 359 } 360 361 radeon_ttm_placement_from_domain(bo, domain); 362 for (i = 0; i < bo->placement.num_placement; i++) { 363 /* force to pin into visible video ram */ 364 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 365 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 366 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 367 bo->placements[i].lpfn = 368 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 369 else 370 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; 371 372 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 373 } 374 375 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 376 if (likely(r == 0)) { 377 bo->pin_count = 1; 378 if (gpu_addr != NULL) 379 *gpu_addr = radeon_bo_gpu_offset(bo); 380 if (domain == RADEON_GEM_DOMAIN_VRAM) 381 bo->rdev->vram_pin_size += radeon_bo_size(bo); 382 else 383 bo->rdev->gart_pin_size += radeon_bo_size(bo); 384 } else { 385 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 386 } 387 return r; 388 } 389 390 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 391 { 392 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 393 } 394 395 int radeon_bo_unpin(struct radeon_bo *bo) 396 { 397 struct ttm_operation_ctx ctx = { false, false }; 398 int r, i; 399 400 if (!bo->pin_count) { 401 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo); 402 return 0; 403 } 404 bo->pin_count--; 405 if (bo->pin_count) 406 return 0; 407 for (i = 0; i < bo->placement.num_placement; i++) { 408 bo->placements[i].lpfn = 0; 409 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 410 } 411 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 412 if (likely(r == 0)) { 413 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 414 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 415 else 416 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 417 } else { 418 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo); 419 } 420 return r; 421 } 422 423 int radeon_bo_evict_vram(struct radeon_device *rdev) 424 { 425 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 426 if (0 && (rdev->flags & RADEON_IS_IGP)) { 427 if (rdev->mc.igp_sideport_enabled == false) 428 /* Useless to evict on IGP chips */ 429 return 0; 430 } 431 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 432 } 433 434 void radeon_bo_force_delete(struct radeon_device *rdev) 435 { 436 struct radeon_bo *bo, *n; 437 438 if (list_empty(&rdev->gem.objects)) { 439 return; 440 } 441 dev_err(rdev->dev, "Userspace still has active objects !\n"); 442 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 443 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 444 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 445 *((unsigned long *)&bo->gem_base.refcount)); 446 mutex_lock(&bo->rdev->gem.mutex); 447 list_del_init(&bo->list); 448 mutex_unlock(&bo->rdev->gem.mutex); 449 /* this should unref the ttm bo */ 450 drm_gem_object_put_unlocked(&bo->gem_base); 451 } 452 } 453 454 int radeon_bo_init(struct radeon_device *rdev) 455 { 456 paddr_t start, end; 457 458 #ifdef __linux__ 459 /* reserve PAT memory space to WC for VRAM */ 460 arch_io_reserve_memtype_wc(rdev->mc.aper_base, 461 rdev->mc.aper_size); 462 #endif 463 464 /* Add an MTRR for the VRAM */ 465 if (!rdev->fastfb_working) { 466 #ifdef __linux__ 467 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 468 rdev->mc.aper_size); 469 #else 470 drm_mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, DRM_MTRR_WC); 471 /* fake a 'cookie', seems to be unused? */ 472 rdev->mc.vram_mtrr = 1; 473 #endif 474 } 475 476 start = atop(bus_space_mmap(rdev->memt, rdev->mc.aper_base, 0, 0, 0)); 477 end = start + atop(rdev->mc.aper_size); 478 uvm_page_physload(start, end, start, end, PHYSLOAD_DEVICE); 479 480 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 481 rdev->mc.mc_vram_size >> 20, 482 (unsigned long long)rdev->mc.aper_size >> 20); 483 DRM_INFO("RAM width %dbits %cDR\n", 484 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 485 return radeon_ttm_init(rdev); 486 } 487 488 void radeon_bo_fini(struct radeon_device *rdev) 489 { 490 radeon_ttm_fini(rdev); 491 #ifdef __linux__ 492 arch_phys_wc_del(rdev->mc.vram_mtrr); 493 arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size); 494 #else 495 drm_mtrr_del(0, rdev->mc.aper_base, rdev->mc.aper_size, DRM_MTRR_WC); 496 #endif 497 } 498 499 /* Returns how many bytes TTM can move per IB. 500 */ 501 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 502 { 503 u64 real_vram_size = rdev->mc.real_vram_size; 504 u64 vram_usage = atomic64_read(&rdev->vram_usage); 505 506 /* This function is based on the current VRAM usage. 507 * 508 * - If all of VRAM is free, allow relocating the number of bytes that 509 * is equal to 1/4 of the size of VRAM for this IB. 510 511 * - If more than one half of VRAM is occupied, only allow relocating 512 * 1 MB of data for this IB. 513 * 514 * - From 0 to one half of used VRAM, the threshold decreases 515 * linearly. 516 * __________________ 517 * 1/4 of -|\ | 518 * VRAM | \ | 519 * | \ | 520 * | \ | 521 * | \ | 522 * | \ | 523 * | \ | 524 * | \________|1 MB 525 * |----------------| 526 * VRAM 0 % 100 % 527 * used used 528 * 529 * Note: It's a threshold, not a limit. The threshold must be crossed 530 * for buffer relocations to stop, so any buffer of an arbitrary size 531 * can be moved as long as the threshold isn't crossed before 532 * the relocation takes place. We don't want to disable buffer 533 * relocations completely. 534 * 535 * The idea is that buffers should be placed in VRAM at creation time 536 * and TTM should only do a minimum number of relocations during 537 * command submission. In practice, you need to submit at least 538 * a dozen IBs to move all buffers to VRAM if they are in GTT. 539 * 540 * Also, things can get pretty crazy under memory pressure and actual 541 * VRAM usage can change a lot, so playing safe even at 50% does 542 * consistently increase performance. 543 */ 544 545 u64 half_vram = real_vram_size >> 1; 546 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 547 u64 bytes_moved_threshold = half_free_vram >> 1; 548 return max(bytes_moved_threshold, 1024*1024ull); 549 } 550 551 int radeon_bo_list_validate(struct radeon_device *rdev, 552 struct ww_acquire_ctx *ticket, 553 struct list_head *head, int ring) 554 { 555 struct ttm_operation_ctx ctx = { true, false }; 556 struct radeon_bo_list *lobj; 557 struct list_head duplicates; 558 int r; 559 u64 bytes_moved = 0, initial_bytes_moved; 560 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 561 562 INIT_LIST_HEAD(&duplicates); 563 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); 564 if (unlikely(r != 0)) { 565 return r; 566 } 567 568 list_for_each_entry(lobj, head, tv.head) { 569 struct radeon_bo *bo = lobj->robj; 570 if (!bo->pin_count) { 571 u32 domain = lobj->preferred_domains; 572 u32 allowed = lobj->allowed_domains; 573 u32 current_domain = 574 radeon_mem_type_to_domain(bo->tbo.mem.mem_type); 575 576 /* Check if this buffer will be moved and don't move it 577 * if we have moved too many buffers for this IB already. 578 * 579 * Note that this allows moving at least one buffer of 580 * any size, because it doesn't take the current "bo" 581 * into account. We don't want to disallow buffer moves 582 * completely. 583 */ 584 if ((allowed & current_domain) != 0 && 585 (domain & current_domain) == 0 && /* will be moved */ 586 bytes_moved > bytes_moved_threshold) { 587 /* don't move it */ 588 domain = current_domain; 589 } 590 591 retry: 592 radeon_ttm_placement_from_domain(bo, domain); 593 if (ring == R600_RING_TYPE_UVD_INDEX) 594 radeon_uvd_force_into_uvd_segment(bo, allowed); 595 596 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 597 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 598 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 599 initial_bytes_moved; 600 601 if (unlikely(r)) { 602 if (r != -ERESTARTSYS && 603 domain != lobj->allowed_domains) { 604 domain = lobj->allowed_domains; 605 goto retry; 606 } 607 ttm_eu_backoff_reservation(ticket, head); 608 return r; 609 } 610 } 611 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 612 lobj->tiling_flags = bo->tiling_flags; 613 } 614 615 list_for_each_entry(lobj, &duplicates, tv.head) { 616 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); 617 lobj->tiling_flags = lobj->robj->tiling_flags; 618 } 619 620 return 0; 621 } 622 623 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 624 { 625 struct radeon_device *rdev = bo->rdev; 626 struct radeon_surface_reg *reg; 627 struct radeon_bo *old_object; 628 int steal; 629 int i; 630 631 #ifdef notyet 632 lockdep_assert_held(&bo->tbo.resv->lock.base); 633 #endif 634 635 if (!bo->tiling_flags) 636 return 0; 637 638 if (bo->surface_reg >= 0) { 639 reg = &rdev->surface_regs[bo->surface_reg]; 640 i = bo->surface_reg; 641 goto out; 642 } 643 644 steal = -1; 645 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 646 647 reg = &rdev->surface_regs[i]; 648 if (!reg->bo) 649 break; 650 651 old_object = reg->bo; 652 if (old_object->pin_count == 0) 653 steal = i; 654 } 655 656 /* if we are all out */ 657 if (i == RADEON_GEM_MAX_SURFACES) { 658 if (steal == -1) 659 return -ENOMEM; 660 /* find someone with a surface reg and nuke their BO */ 661 reg = &rdev->surface_regs[steal]; 662 old_object = reg->bo; 663 /* blow away the mapping */ 664 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 665 ttm_bo_unmap_virtual(&old_object->tbo); 666 old_object->surface_reg = -1; 667 i = steal; 668 } 669 670 bo->surface_reg = i; 671 reg->bo = bo; 672 673 out: 674 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 675 bo->tbo.mem.start << PAGE_SHIFT, 676 bo->tbo.num_pages << PAGE_SHIFT); 677 return 0; 678 } 679 680 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 681 { 682 struct radeon_device *rdev = bo->rdev; 683 struct radeon_surface_reg *reg; 684 685 if (bo->surface_reg == -1) 686 return; 687 688 reg = &rdev->surface_regs[bo->surface_reg]; 689 radeon_clear_surface_reg(rdev, bo->surface_reg); 690 691 reg->bo = NULL; 692 bo->surface_reg = -1; 693 } 694 695 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 696 uint32_t tiling_flags, uint32_t pitch) 697 { 698 struct radeon_device *rdev = bo->rdev; 699 int r; 700 701 if (rdev->family >= CHIP_CEDAR) { 702 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 703 704 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 705 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 706 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 707 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 708 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 709 switch (bankw) { 710 case 0: 711 case 1: 712 case 2: 713 case 4: 714 case 8: 715 break; 716 default: 717 return -EINVAL; 718 } 719 switch (bankh) { 720 case 0: 721 case 1: 722 case 2: 723 case 4: 724 case 8: 725 break; 726 default: 727 return -EINVAL; 728 } 729 switch (mtaspect) { 730 case 0: 731 case 1: 732 case 2: 733 case 4: 734 case 8: 735 break; 736 default: 737 return -EINVAL; 738 } 739 if (tilesplit > 6) { 740 return -EINVAL; 741 } 742 if (stilesplit > 6) { 743 return -EINVAL; 744 } 745 } 746 r = radeon_bo_reserve(bo, false); 747 if (unlikely(r != 0)) 748 return r; 749 bo->tiling_flags = tiling_flags; 750 bo->pitch = pitch; 751 radeon_bo_unreserve(bo); 752 return 0; 753 } 754 755 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 756 uint32_t *tiling_flags, 757 uint32_t *pitch) 758 { 759 #ifdef notyet 760 lockdep_assert_held(&bo->tbo.resv->lock.base); 761 #endif 762 763 if (tiling_flags) 764 *tiling_flags = bo->tiling_flags; 765 if (pitch) 766 *pitch = bo->pitch; 767 } 768 769 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 770 bool force_drop) 771 { 772 #ifdef notyet 773 if (!force_drop) 774 lockdep_assert_held(&bo->tbo.resv->lock.base); 775 #endif 776 777 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 778 return 0; 779 780 if (force_drop) { 781 radeon_bo_clear_surface_reg(bo); 782 return 0; 783 } 784 785 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) { 786 if (!has_moved) 787 return 0; 788 789 if (bo->surface_reg >= 0) 790 radeon_bo_clear_surface_reg(bo); 791 return 0; 792 } 793 794 if ((bo->surface_reg >= 0) && !has_moved) 795 return 0; 796 797 return radeon_bo_get_surface_reg(bo); 798 } 799 800 void radeon_bo_move_notify(struct ttm_buffer_object *bo, 801 bool evict, 802 struct ttm_mem_reg *new_mem) 803 { 804 struct radeon_bo *rbo; 805 806 if (!radeon_ttm_bo_is_radeon_bo(bo)) 807 return; 808 809 rbo = container_of(bo, struct radeon_bo, tbo); 810 radeon_bo_check_tiling(rbo, 0, 1); 811 radeon_vm_bo_invalidate(rbo->rdev, rbo); 812 813 /* update statistics */ 814 if (!new_mem) 815 return; 816 817 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); 818 radeon_update_memory_usage(rbo, new_mem->mem_type, 1); 819 } 820 821 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 822 { 823 struct ttm_operation_ctx ctx = { false, false }; 824 struct radeon_device *rdev; 825 struct radeon_bo *rbo; 826 unsigned long offset, size, lpfn; 827 int i, r; 828 829 if (!radeon_ttm_bo_is_radeon_bo(bo)) 830 return 0; 831 rbo = container_of(bo, struct radeon_bo, tbo); 832 radeon_bo_check_tiling(rbo, 0, 0); 833 rdev = rbo->rdev; 834 if (bo->mem.mem_type != TTM_PL_VRAM) 835 return 0; 836 837 size = bo->mem.num_pages << PAGE_SHIFT; 838 offset = bo->mem.start << PAGE_SHIFT; 839 if ((offset + size) <= rdev->mc.visible_vram_size) 840 return 0; 841 842 /* Can't move a pinned BO to visible VRAM */ 843 if (rbo->pin_count > 0) 844 return -EINVAL; 845 846 /* hurrah the memory is not visible ! */ 847 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 848 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 849 for (i = 0; i < rbo->placement.num_placement; i++) { 850 /* Force into visible VRAM */ 851 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && 852 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) 853 rbo->placements[i].lpfn = lpfn; 854 } 855 r = ttm_bo_validate(bo, &rbo->placement, &ctx); 856 if (unlikely(r == -ENOMEM)) { 857 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 858 return ttm_bo_validate(bo, &rbo->placement, &ctx); 859 } else if (unlikely(r != 0)) { 860 return r; 861 } 862 863 offset = bo->mem.start << PAGE_SHIFT; 864 /* this should never happen */ 865 if ((offset + size) > rdev->mc.visible_vram_size) 866 return -EINVAL; 867 868 return 0; 869 } 870 871 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait) 872 { 873 int r; 874 875 r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL); 876 if (unlikely(r != 0)) 877 return r; 878 if (mem_type) 879 *mem_type = bo->tbo.mem.mem_type; 880 881 r = ttm_bo_wait(&bo->tbo, true, no_wait); 882 ttm_bo_unreserve(&bo->tbo); 883 return r; 884 } 885 886 /** 887 * radeon_bo_fence - add fence to buffer object 888 * 889 * @bo: buffer object in question 890 * @fence: fence to add 891 * @shared: true if fence should be added shared 892 * 893 */ 894 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 895 bool shared) 896 { 897 struct reservation_object *resv = bo->tbo.resv; 898 899 if (shared) 900 reservation_object_add_shared_fence(resv, &fence->base); 901 else 902 reservation_object_add_excl_fence(resv, &fence->base); 903 } 904