1 /* $OpenBSD: radeon_mode.h,v 1.3 2015/09/23 23:12:12 kettenis Exp $ */ 2 /* 3 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 4 * VA Linux Systems Inc., Fremont, California. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Original Authors: 26 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 27 * 28 * Kernel port Author: Dave Airlie 29 */ 30 31 #ifndef RADEON_MODE_H 32 #define RADEON_MODE_H 33 34 #include <dev/pci/drm/drm_crtc.h> 35 #include <dev/pci/drm/drm_edid.h> 36 #include <dev/pci/drm/drm_dp_helper.h> 37 #include <dev/pci/drm/drm_fixed.h> 38 #include <dev/pci/drm/drm_crtc_helper.h> 39 40 struct radeon_bo; 41 struct radeon_device; 42 43 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) 44 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) 45 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 46 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 47 48 enum radeon_rmx_type { 49 RMX_OFF, 50 RMX_FULL, 51 RMX_CENTER, 52 RMX_ASPECT 53 }; 54 55 enum radeon_tv_std { 56 TV_STD_NTSC, 57 TV_STD_PAL, 58 TV_STD_PAL_M, 59 TV_STD_PAL_60, 60 TV_STD_NTSC_J, 61 TV_STD_SCART_PAL, 62 TV_STD_SECAM, 63 TV_STD_PAL_CN, 64 TV_STD_PAL_N, 65 }; 66 67 enum radeon_underscan_type { 68 UNDERSCAN_OFF, 69 UNDERSCAN_ON, 70 UNDERSCAN_AUTO, 71 }; 72 73 enum radeon_hpd_id { 74 RADEON_HPD_1 = 0, 75 RADEON_HPD_2, 76 RADEON_HPD_3, 77 RADEON_HPD_4, 78 RADEON_HPD_5, 79 RADEON_HPD_6, 80 RADEON_HPD_NONE = 0xff, 81 }; 82 83 #define RADEON_MAX_I2C_BUS 16 84 85 /* radeon gpio-based i2c 86 * 1. "mask" reg and bits 87 * grabs the gpio pins for software use 88 * 0=not held 1=held 89 * 2. "a" reg and bits 90 * output pin value 91 * 0=low 1=high 92 * 3. "en" reg and bits 93 * sets the pin direction 94 * 0=input 1=output 95 * 4. "y" reg and bits 96 * input pin value 97 * 0=low 1=high 98 */ 99 struct radeon_i2c_bus_rec { 100 bool valid; 101 /* id used by atom */ 102 uint8_t i2c_id; 103 /* id used by atom */ 104 enum radeon_hpd_id hpd; 105 /* can be used with hw i2c engine */ 106 bool hw_capable; 107 /* uses multi-media i2c engine */ 108 bool mm_i2c; 109 /* regs and bits */ 110 uint32_t mask_clk_reg; 111 uint32_t mask_data_reg; 112 uint32_t a_clk_reg; 113 uint32_t a_data_reg; 114 uint32_t en_clk_reg; 115 uint32_t en_data_reg; 116 uint32_t y_clk_reg; 117 uint32_t y_data_reg; 118 uint32_t mask_clk_mask; 119 uint32_t mask_data_mask; 120 uint32_t a_clk_mask; 121 uint32_t a_data_mask; 122 uint32_t en_clk_mask; 123 uint32_t en_data_mask; 124 uint32_t y_clk_mask; 125 uint32_t y_data_mask; 126 }; 127 128 struct radeon_tmds_pll { 129 uint32_t freq; 130 uint32_t value; 131 }; 132 133 #define RADEON_MAX_BIOS_CONNECTOR 16 134 135 /* pll flags */ 136 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 137 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 138 #define RADEON_PLL_USE_REF_DIV (1 << 2) 139 #define RADEON_PLL_LEGACY (1 << 3) 140 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 141 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 142 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 143 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 144 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 145 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 146 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 147 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 148 #define RADEON_PLL_USE_POST_DIV (1 << 12) 149 #define RADEON_PLL_IS_LCD (1 << 13) 150 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 151 152 struct radeon_pll { 153 /* reference frequency */ 154 uint32_t reference_freq; 155 156 /* fixed dividers */ 157 uint32_t reference_div; 158 uint32_t post_div; 159 160 /* pll in/out limits */ 161 uint32_t pll_in_min; 162 uint32_t pll_in_max; 163 uint32_t pll_out_min; 164 uint32_t pll_out_max; 165 uint32_t lcd_pll_out_min; 166 uint32_t lcd_pll_out_max; 167 uint32_t best_vco; 168 169 /* divider limits */ 170 uint32_t min_ref_div; 171 uint32_t max_ref_div; 172 uint32_t min_post_div; 173 uint32_t max_post_div; 174 uint32_t min_feedback_div; 175 uint32_t max_feedback_div; 176 uint32_t min_frac_feedback_div; 177 uint32_t max_frac_feedback_div; 178 179 /* flags for the current clock */ 180 uint32_t flags; 181 182 /* pll id */ 183 uint32_t id; 184 }; 185 186 struct radeon_i2c_chan { 187 struct i2c_controller adapter; 188 struct drm_device *dev; 189 union { 190 struct i2c_algo_dp_aux_data dp; 191 } algo; 192 struct radeon_i2c_bus_rec rec; 193 }; 194 195 /* mostly for macs, but really any system without connector tables */ 196 enum radeon_connector_table { 197 CT_NONE = 0, 198 CT_GENERIC, 199 CT_IBOOK, 200 CT_POWERBOOK_EXTERNAL, 201 CT_POWERBOOK_INTERNAL, 202 CT_POWERBOOK_VGA, 203 CT_MINI_EXTERNAL, 204 CT_MINI_INTERNAL, 205 CT_IMAC_G5_ISIGHT, 206 CT_EMAC, 207 CT_RN50_POWER, 208 CT_MAC_X800, 209 CT_MAC_G5_9600, 210 CT_SAM440EP, 211 CT_MAC_G4_SILVER 212 }; 213 214 enum radeon_dvo_chip { 215 DVO_SIL164, 216 DVO_SIL1178, 217 }; 218 219 struct radeon_fbdev; 220 221 struct radeon_afmt { 222 bool enabled; 223 int offset; 224 bool last_buffer_filled_status; 225 int id; 226 }; 227 228 struct radeon_mode_info { 229 struct atom_context *atom_context; 230 struct card_info *atom_card_info; 231 enum radeon_connector_table connector_table; 232 bool mode_config_initialized; 233 struct radeon_crtc *crtcs[6]; 234 struct radeon_afmt *afmt[6]; 235 /* DVI-I properties */ 236 struct drm_property *coherent_mode_property; 237 /* DAC enable load detect */ 238 struct drm_property *load_detect_property; 239 /* TV standard */ 240 struct drm_property *tv_std_property; 241 /* legacy TMDS PLL detect */ 242 struct drm_property *tmds_pll_property; 243 /* underscan */ 244 struct drm_property *underscan_property; 245 struct drm_property *underscan_hborder_property; 246 struct drm_property *underscan_vborder_property; 247 /* hardcoded DFP edid from BIOS */ 248 struct edid *bios_hardcoded_edid; 249 int bios_hardcoded_edid_size; 250 251 /* pointer to fbdev info structure */ 252 struct radeon_fbdev *rfbdev; 253 /* firmware flags */ 254 u16 firmware_flags; 255 /* pointer to backlight encoder */ 256 struct radeon_encoder *bl_encoder; 257 }; 258 259 #define RADEON_MAX_BL_LEVEL 0xFF 260 261 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 262 263 struct radeon_backlight_privdata { 264 struct radeon_encoder *encoder; 265 uint8_t negative; 266 }; 267 268 #endif 269 270 #define MAX_H_CODE_TIMING_LEN 32 271 #define MAX_V_CODE_TIMING_LEN 32 272 273 /* need to store these as reading 274 back code tables is excessive */ 275 struct radeon_tv_regs { 276 uint32_t tv_uv_adr; 277 uint32_t timing_cntl; 278 uint32_t hrestart; 279 uint32_t vrestart; 280 uint32_t frestart; 281 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN]; 282 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN]; 283 }; 284 285 struct radeon_atom_ss { 286 uint16_t percentage; 287 uint8_t type; 288 uint16_t step; 289 uint8_t delay; 290 uint8_t range; 291 uint8_t refdiv; 292 /* asic_ss */ 293 uint16_t rate; 294 uint16_t amount; 295 }; 296 297 struct radeon_crtc { 298 struct drm_crtc base; 299 int crtc_id; 300 u16 lut_r[256], lut_g[256], lut_b[256]; 301 bool enabled; 302 bool can_tile; 303 bool in_mode_set; 304 uint32_t crtc_offset; 305 struct drm_gem_object *cursor_bo; 306 uint64_t cursor_addr; 307 int cursor_width; 308 int cursor_height; 309 uint32_t legacy_display_base_addr; 310 uint32_t legacy_cursor_offset; 311 enum radeon_rmx_type rmx_type; 312 u8 h_border; 313 u8 v_border; 314 fixed20_12 vsc; 315 fixed20_12 hsc; 316 struct drm_display_mode native_mode; 317 int pll_id; 318 /* page flipping */ 319 struct radeon_unpin_work *unpin_work; 320 int deferred_flip_completion; 321 /* pll sharing */ 322 struct radeon_atom_ss ss; 323 bool ss_enabled; 324 u32 adjusted_clock; 325 int bpc; 326 u32 pll_reference_div; 327 u32 pll_post_div; 328 u32 pll_flags; 329 struct drm_encoder *encoder; 330 struct drm_connector *connector; 331 }; 332 333 struct radeon_encoder_primary_dac { 334 /* legacy primary dac */ 335 uint32_t ps2_pdac_adj; 336 }; 337 338 struct radeon_encoder_lvds { 339 /* legacy lvds */ 340 uint16_t panel_vcc_delay; 341 uint8_t panel_pwr_delay; 342 uint8_t panel_digon_delay; 343 uint8_t panel_blon_delay; 344 uint16_t panel_ref_divider; 345 uint8_t panel_post_divider; 346 uint16_t panel_fb_divider; 347 bool use_bios_dividers; 348 uint32_t lvds_gen_cntl; 349 /* panel mode */ 350 struct drm_display_mode native_mode; 351 struct backlight_device *bl_dev; 352 int dpms_mode; 353 uint8_t backlight_level; 354 }; 355 356 struct radeon_encoder_tv_dac { 357 /* legacy tv dac */ 358 uint32_t ps2_tvdac_adj; 359 uint32_t ntsc_tvdac_adj; 360 uint32_t pal_tvdac_adj; 361 362 int h_pos; 363 int v_pos; 364 int h_size; 365 int supported_tv_stds; 366 bool tv_on; 367 enum radeon_tv_std tv_std; 368 struct radeon_tv_regs tv; 369 }; 370 371 struct radeon_encoder_int_tmds { 372 /* legacy int tmds */ 373 struct radeon_tmds_pll tmds_pll[4]; 374 }; 375 376 struct radeon_encoder_ext_tmds { 377 /* tmds over dvo */ 378 struct radeon_i2c_chan *i2c_bus; 379 uint8_t slave_addr; 380 enum radeon_dvo_chip dvo_chip; 381 }; 382 383 /* spread spectrum */ 384 struct radeon_encoder_atom_dig { 385 bool linkb; 386 /* atom dig */ 387 bool coherent_mode; 388 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 389 /* atom lvds/edp */ 390 uint32_t lcd_misc; 391 uint16_t panel_pwr_delay; 392 uint32_t lcd_ss_id; 393 /* panel mode */ 394 struct drm_display_mode native_mode; 395 struct backlight_device *bl_dev; 396 int dpms_mode; 397 uint8_t backlight_level; 398 int panel_mode; 399 struct radeon_afmt *afmt; 400 }; 401 402 struct radeon_encoder_atom_dac { 403 enum radeon_tv_std tv_std; 404 }; 405 406 struct radeon_encoder { 407 struct drm_encoder base; 408 uint32_t encoder_enum; 409 uint32_t encoder_id; 410 uint32_t devices; 411 uint32_t active_device; 412 uint32_t flags; 413 uint32_t pixel_clock; 414 enum radeon_rmx_type rmx_type; 415 enum radeon_underscan_type underscan_type; 416 uint32_t underscan_hborder; 417 uint32_t underscan_vborder; 418 struct drm_display_mode native_mode; 419 void *enc_priv; 420 int audio_polling_active; 421 bool is_ext_encoder; 422 u16 caps; 423 }; 424 425 struct radeon_connector_atom_dig { 426 uint32_t igp_lane_info; 427 /* displayport */ 428 struct radeon_i2c_chan *dp_i2c_bus; 429 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 430 u8 dp_sink_type; 431 int dp_clock; 432 int dp_lane_count; 433 bool edp_on; 434 }; 435 436 struct radeon_gpio_rec { 437 bool valid; 438 u8 id; 439 u32 reg; 440 u32 mask; 441 }; 442 443 struct radeon_hpd { 444 enum radeon_hpd_id hpd; 445 u8 plugged_state; 446 struct radeon_gpio_rec gpio; 447 }; 448 449 struct radeon_router { 450 u32 router_id; 451 struct radeon_i2c_bus_rec i2c_info; 452 u8 i2c_addr; 453 /* i2c mux */ 454 bool ddc_valid; 455 u8 ddc_mux_type; 456 u8 ddc_mux_control_pin; 457 u8 ddc_mux_state; 458 /* clock/data mux */ 459 bool cd_valid; 460 u8 cd_mux_type; 461 u8 cd_mux_control_pin; 462 u8 cd_mux_state; 463 }; 464 465 struct radeon_connector { 466 struct drm_connector base; 467 uint32_t connector_id; 468 uint32_t devices; 469 struct radeon_i2c_chan *ddc_bus; 470 /* some systems have an hdmi and vga port with a shared ddc line */ 471 bool shared_ddc; 472 bool use_digital; 473 /* we need to mind the EDID between detect 474 and get modes due to analog/digital/tvencoder */ 475 struct edid *edid; 476 void *con_priv; 477 bool dac_load_detect; 478 bool detected_by_load; /* if the connection status was determined by load */ 479 uint16_t connector_object_id; 480 struct radeon_hpd hpd; 481 struct radeon_router router; 482 struct radeon_i2c_chan *router_bus; 483 }; 484 485 struct radeon_framebuffer { 486 struct drm_framebuffer base; 487 struct drm_gem_object *obj; 488 }; 489 490 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 491 ((em) == ATOM_ENCODER_MODE_DP_MST)) 492 493 extern enum radeon_tv_std 494 radeon_combios_get_tv_info(struct radeon_device *rdev); 495 extern enum radeon_tv_std 496 radeon_atombios_get_tv_info(struct radeon_device *rdev); 497 498 extern struct drm_connector * 499 radeon_get_connector_for_encoder(struct drm_encoder *encoder); 500 extern struct drm_connector * 501 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder); 502 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder, 503 u32 pixel_clock); 504 505 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 506 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); 507 extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector); 508 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector); 509 extern int radeon_get_monitor_bpc(struct drm_connector *connector); 510 511 extern void radeon_connector_hotplug(struct drm_connector *connector); 512 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector, 513 struct drm_display_mode *mode); 514 extern void radeon_dp_set_link_config(struct drm_connector *connector, 515 const struct drm_display_mode *mode); 516 extern void radeon_dp_link_train(struct drm_encoder *encoder, 517 struct drm_connector *connector); 518 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector); 519 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector); 520 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector); 521 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, 522 struct drm_connector *connector); 523 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); 524 extern void radeon_atom_encoder_init(struct radeon_device *rdev); 525 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev); 526 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, 527 int action, uint8_t lane_num, 528 uint8_t lane_set); 529 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder); 530 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder); 531 extern int radeon_dp_i2c_aux_ch(struct i2c_controller *adapter, int mode, 532 u8 write_byte, u8 *read_byte); 533 534 extern void radeon_i2c_init(struct radeon_device *rdev); 535 extern void radeon_i2c_fini(struct radeon_device *rdev); 536 extern void radeon_combios_i2c_init(struct radeon_device *rdev); 537 extern void radeon_atombios_i2c_init(struct radeon_device *rdev); 538 extern void radeon_i2c_add(struct radeon_device *rdev, 539 struct radeon_i2c_bus_rec *rec, 540 const char *name); 541 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 542 struct radeon_i2c_bus_rec *i2c_bus); 543 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, 544 struct radeon_i2c_bus_rec *rec, 545 const char *name); 546 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 547 struct radeon_i2c_bus_rec *rec, 548 const char *name); 549 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); 550 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 551 u8 slave_addr, 552 u8 addr, 553 u8 *val); 554 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c, 555 u8 slave_addr, 556 u8 addr, 557 u8 val); 558 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector); 559 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector); 560 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux); 561 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); 562 563 extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); 564 565 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev, 566 struct radeon_atom_ss *ss, 567 int id); 568 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev, 569 struct radeon_atom_ss *ss, 570 int id, u32 clock); 571 572 extern void radeon_compute_pll_legacy(struct radeon_pll *pll, 573 uint64_t freq, 574 uint32_t *dot_clock_p, 575 uint32_t *fb_div_p, 576 uint32_t *frac_fb_div_p, 577 uint32_t *ref_div_p, 578 uint32_t *post_div_p); 579 580 extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 581 u32 freq, 582 u32 *dot_clock_p, 583 u32 *fb_div_p, 584 u32 *frac_fb_div_p, 585 u32 *ref_div_p, 586 u32 *post_div_p); 587 588 extern void radeon_setup_encoder_clones(struct drm_device *dev); 589 590 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); 591 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); 592 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); 593 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); 594 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); 595 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action); 596 extern void atombios_digital_setup(struct drm_encoder *encoder, int action); 597 extern int atombios_get_encoder_mode(struct drm_encoder *encoder); 598 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action); 599 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder); 600 601 extern void radeon_crtc_load_lut(struct drm_crtc *crtc); 602 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 603 struct drm_framebuffer *old_fb); 604 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 605 struct drm_framebuffer *fb, 606 int x, int y, 607 enum mode_set_atomic state); 608 extern int atombios_crtc_mode_set(struct drm_crtc *crtc, 609 struct drm_display_mode *mode, 610 struct drm_display_mode *adjusted_mode, 611 int x, int y, 612 struct drm_framebuffer *old_fb); 613 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); 614 615 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 616 struct drm_framebuffer *old_fb); 617 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc, 618 struct drm_framebuffer *fb, 619 int x, int y, 620 enum mode_set_atomic state); 621 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc, 622 struct drm_framebuffer *fb, 623 int x, int y, int atomic); 624 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 625 struct drm_file *file_priv, 626 uint32_t handle, 627 uint32_t width, 628 uint32_t height); 629 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, 630 int x, int y); 631 632 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, 633 unsigned int flags, 634 int *vpos, int *hpos, ktime_t *stime, 635 ktime_t *etime); 636 637 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev); 638 extern struct edid * 639 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev); 640 extern bool radeon_atom_get_clock_info(struct drm_device *dev); 641 extern bool radeon_combios_get_clock_info(struct drm_device *dev); 642 extern struct radeon_encoder_atom_dig * 643 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); 644 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 645 struct radeon_encoder_int_tmds *tmds); 646 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 647 struct radeon_encoder_int_tmds *tmds); 648 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 649 struct radeon_encoder_int_tmds *tmds); 650 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 651 struct radeon_encoder_ext_tmds *tmds); 652 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 653 struct radeon_encoder_ext_tmds *tmds); 654 extern struct radeon_encoder_primary_dac * 655 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); 656 extern struct radeon_encoder_tv_dac * 657 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); 658 extern struct radeon_encoder_lvds * 659 radeon_combios_get_lvds_info(struct radeon_encoder *encoder); 660 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); 661 extern struct radeon_encoder_tv_dac * 662 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); 663 extern struct radeon_encoder_primary_dac * 664 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); 665 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder); 666 extern void radeon_external_tmds_setup(struct drm_encoder *encoder); 667 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); 668 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); 669 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); 670 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); 671 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev); 672 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev); 673 extern void 674 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 675 extern void 676 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 677 extern void 678 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); 679 extern void 680 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); 681 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 682 u16 blue, int regno); 683 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 684 u16 *blue, int regno); 685 int radeon_framebuffer_init(struct drm_device *dev, 686 struct radeon_framebuffer *rfb, 687 struct drm_mode_fb_cmd2 *mode_cmd, 688 struct drm_gem_object *obj); 689 690 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 691 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); 692 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); 693 void radeon_atombios_init_crtc(struct drm_device *dev, 694 struct radeon_crtc *radeon_crtc); 695 void radeon_legacy_init_crtc(struct drm_device *dev, 696 struct radeon_crtc *radeon_crtc); 697 698 void radeon_get_clock_info(struct drm_device *dev); 699 700 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); 701 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); 702 703 void radeon_enc_destroy(struct drm_encoder *encoder); 704 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 705 void radeon_combios_asic_init(struct drm_device *dev); 706 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 707 const struct drm_display_mode *mode, 708 struct drm_display_mode *adjusted_mode); 709 void radeon_panel_mode_fixup(struct drm_encoder *encoder, 710 struct drm_display_mode *adjusted_mode); 711 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc); 712 713 /* legacy tv */ 714 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 715 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 716 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid); 717 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 718 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 719 uint32_t *ppll_div_3, uint32_t *pixclks_cntl); 720 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 721 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 722 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl); 723 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 724 struct drm_display_mode *mode, 725 struct drm_display_mode *adjusted_mode); 726 727 /* fbdev layer */ 728 int radeon_fbdev_init(struct radeon_device *rdev); 729 void radeon_fbdev_fini(struct radeon_device *rdev); 730 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); 731 int radeon_fbdev_total_size(struct radeon_device *rdev); 732 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); 733 734 void radeon_fb_output_poll_changed(struct radeon_device *rdev); 735 736 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id); 737 738 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled); 739 740 void radeondrm_burner(void *, u_int, u_int); 741 #endif 742