1 /* $OpenBSD: radeon_kms.c,v 1.48 2016/04/08 08:27:53 kettenis Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/drm/drm_fb_helper.h> 31 #include "radeon.h" 32 #include <dev/pci/drm/radeon_drm.h> 33 #include "radeon_asic.h" 34 #include <dev/pci/drm/drm_pciids.h> 35 36 /* can't include radeon_drv.h due to duplicated defines in radeon_reg.h */ 37 38 #include "vga.h" 39 40 #if NVGA > 0 41 extern int vga_console_attached; 42 #endif 43 44 #ifdef __amd64__ 45 #include "efifb.h" 46 #endif 47 48 #if NEFIFB > 0 49 #include <machine/efifbvar.h> 50 #endif 51 52 #define DRIVER_NAME "radeon" 53 #define DRIVER_DESC "ATI Radeon" 54 #define DRIVER_DATE "20080613" 55 56 #define KMS_DRIVER_MAJOR 2 57 #define KMS_DRIVER_MINOR 29 58 #define KMS_DRIVER_PATCHLEVEL 0 59 60 int radeon_driver_irq_handler_kms(void *); 61 void radeon_driver_irq_preinstall_kms(struct drm_device *); 62 int radeon_driver_irq_postinstall_kms(struct drm_device *); 63 void radeon_driver_irq_uninstall_kms(struct drm_device *d); 64 65 void radeon_gem_object_free(struct drm_gem_object *); 66 int radeon_gem_object_open(struct drm_gem_object *, struct drm_file *); 67 void radeon_gem_object_close(struct drm_gem_object *, struct drm_file *); 68 69 int radeon_driver_unload_kms(struct drm_device *); 70 int radeon_driver_load_kms(struct drm_device *, unsigned long); 71 int radeon_info_ioctl(struct drm_device *, void *, struct drm_file *); 72 int radeon_driver_firstopen_kms(struct drm_device *); 73 void radeon_driver_lastclose_kms(struct drm_device *); 74 int radeon_driver_open_kms(struct drm_device *, struct drm_file *); 75 void radeon_driver_postclose_kms(struct drm_device *, struct drm_file *); 76 void radeon_driver_preclose_kms(struct drm_device *, struct drm_file *); 77 u32 radeon_get_vblank_counter_kms(struct drm_device *, int); 78 int radeon_enable_vblank_kms(struct drm_device *, int); 79 void radeon_disable_vblank_kms(struct drm_device *, int); 80 int radeon_get_vblank_timestamp_kms(struct drm_device *, int, int *, 81 struct timeval *, unsigned); 82 83 int radeon_dma_ioctl_kms(struct drm_device *, struct drm_dma *, struct drm_file *); 84 85 int radeon_cp_init_kms(struct drm_device *, void *, struct drm_file *); 86 int radeon_cp_start_kms(struct drm_device *, void *, struct drm_file *); 87 int radeon_cp_stop_kms(struct drm_device *, void *, struct drm_file *); 88 int radeon_cp_reset_kms(struct drm_device *, void *, struct drm_file *); 89 int radeon_cp_idle_kms(struct drm_device *, void *, struct drm_file *); 90 int radeon_cp_resume_kms(struct drm_device *, void *, struct drm_file *); 91 int radeon_engine_reset_kms(struct drm_device *, void *, struct drm_file *); 92 int radeon_fullscreen_kms(struct drm_device *, void *, struct drm_file *); 93 int radeon_cp_swap_kms(struct drm_device *, void *, struct drm_file *); 94 int radeon_cp_clear_kms(struct drm_device *, void *, struct drm_file *); 95 int radeon_cp_vertex_kms(struct drm_device *, void *, struct drm_file *); 96 int radeon_cp_indices_kms(struct drm_device *, void *, struct drm_file *); 97 int radeon_cp_texture_kms(struct drm_device *, void *, struct drm_file *); 98 int radeon_cp_stipple_kms(struct drm_device *, void *, struct drm_file *); 99 int radeon_cp_indirect_kms(struct drm_device *, void *, struct drm_file *); 100 int radeon_cp_vertex2_kms(struct drm_device *, void *, struct drm_file *); 101 int radeon_cp_cmdbuf_kms(struct drm_device *, void *, struct drm_file *); 102 int radeon_cp_getparam_kms(struct drm_device *, void *, struct drm_file *); 103 int radeon_cp_flip_kms(struct drm_device *, void *, struct drm_file *); 104 int radeon_mem_alloc_kms(struct drm_device *, void *, struct drm_file *); 105 int radeon_mem_free_kms(struct drm_device *, void *, struct drm_file *); 106 int radeon_mem_init_heap_kms(struct drm_device *, void *, struct drm_file *); 107 int radeon_irq_emit_kms(struct drm_device *, void *, struct drm_file *); 108 int radeon_irq_wait_kms(struct drm_device *, void *, struct drm_file *); 109 int radeon_cp_setparam_kms(struct drm_device *, void *, struct drm_file *); 110 int radeon_surface_alloc_kms(struct drm_device *, void *, struct drm_file *); 111 int radeon_surface_free_kms(struct drm_device *, void *, struct drm_file *); 112 113 int radeondrm_probe(struct device *, void *, void *); 114 void radeondrm_attach_kms(struct device *, struct device *, void *); 115 int radeondrm_detach_kms(struct device *, int); 116 int radeondrm_activate_kms(struct device *, int); 117 void radeondrm_attachhook(struct device *); 118 int radeondrm_forcedetach(struct radeon_device *); 119 120 extern struct drm_ioctl_desc radeon_ioctls_kms[]; 121 extern int radeon_max_kms_ioctl; 122 123 struct cfattach radeondrm_ca = { 124 sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms, 125 radeondrm_detach_kms, radeondrm_activate_kms 126 }; 127 128 struct cfdriver radeondrm_cd = { 129 NULL, "radeondrm", DV_DULL 130 }; 131 132 int radeon_no_wb; 133 int radeon_modeset = 1; 134 int radeon_dynclks = -1; 135 int radeon_r4xx_atom = 0; 136 int radeon_agpmode = 0; 137 int radeon_vram_limit = 0; 138 int radeon_gart_size = 512; /* default gart size */ 139 int radeon_benchmarking = 0; 140 int radeon_testing = 0; 141 int radeon_connector_table = 0; 142 int radeon_tv = 1; 143 int radeon_audio = 0; 144 int radeon_disp_priority = 0; 145 int radeon_hw_i2c = 0; 146 int radeon_pcie_gen2 = -1; 147 int radeon_msi = -1; 148 int radeon_lockup_timeout = 10000; 149 150 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 151 module_param_named(no_wb, radeon_no_wb, int, 0444); 152 153 MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 154 module_param_named(modeset, radeon_modeset, int, 0400); 155 156 MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 157 module_param_named(dynclks, radeon_dynclks, int, 0444); 158 159 MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 160 module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 161 162 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing"); 163 module_param_named(vramlimit, radeon_vram_limit, int, 0600); 164 165 MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 166 module_param_named(agpmode, radeon_agpmode, int, 0444); 167 168 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc)"); 169 module_param_named(gartsize, radeon_gart_size, int, 0600); 170 171 MODULE_PARM_DESC(benchmark, "Run benchmark"); 172 module_param_named(benchmark, radeon_benchmarking, int, 0444); 173 174 MODULE_PARM_DESC(test, "Run tests"); 175 module_param_named(test, radeon_testing, int, 0444); 176 177 MODULE_PARM_DESC(connector_table, "Force connector table"); 178 module_param_named(connector_table, radeon_connector_table, int, 0444); 179 180 MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 181 module_param_named(tv, radeon_tv, int, 0444); 182 183 MODULE_PARM_DESC(audio, "Audio enable (1 = enable)"); 184 module_param_named(audio, radeon_audio, int, 0444); 185 186 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 187 module_param_named(disp_priority, radeon_disp_priority, int, 0444); 188 189 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 190 module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 191 192 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 193 module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 194 195 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 196 module_param_named(msi, radeon_msi, int, 0444); 197 198 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 199 module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 200 201 /* 202 * set if the mountroot hook has a fatal error 203 * such as not being able to find the firmware on newer cards 204 */ 205 int radeon_fatal_error = 0; 206 207 const struct drm_pcidev radeondrm_pciidlist[] = { 208 radeon_PCI_IDS 209 }; 210 211 static struct drm_driver_info kms_driver = { 212 .driver_features = 213 DRIVER_USE_AGP | 214 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 215 DRIVER_MODESET, 216 .buf_priv_size = 0, 217 .firstopen = radeon_driver_firstopen_kms, 218 .open = radeon_driver_open_kms, 219 .mmap = radeon_mmap, 220 #ifdef notyet 221 .preclose = radeon_driver_preclose_kms, 222 .postclose = radeon_driver_postclose_kms, 223 #endif 224 .lastclose = radeon_driver_lastclose_kms, 225 #ifdef notyet 226 .suspend = radeon_suspend_kms, 227 .resume = radeon_resume_kms, 228 #endif 229 .get_vblank_counter = radeon_get_vblank_counter_kms, 230 .enable_vblank = radeon_enable_vblank_kms, 231 .disable_vblank = radeon_disable_vblank_kms, 232 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms, 233 .get_scanout_position = radeon_get_crtc_scanoutpos, 234 #if defined(CONFIG_DEBUG_FS) 235 .debugfs_init = radeon_debugfs_init, 236 .debugfs_cleanup = radeon_debugfs_cleanup, 237 #endif 238 .irq_preinstall = radeon_driver_irq_preinstall_kms, 239 .irq_postinstall = radeon_driver_irq_postinstall_kms, 240 .irq_uninstall = radeon_driver_irq_uninstall_kms, 241 .ioctls = radeon_ioctls_kms, 242 .gem_free_object = radeon_gem_object_free, 243 .gem_open_object = radeon_gem_object_open, 244 .gem_close_object = radeon_gem_object_close, 245 .gem_size = sizeof(struct radeon_bo), 246 .dma_ioctl = radeon_dma_ioctl_kms, 247 .dumb_create = radeon_mode_dumb_create, 248 .dumb_map_offset = radeon_mode_dumb_mmap, 249 .dumb_destroy = radeon_mode_dumb_destroy, 250 #ifdef notyet 251 .fops = &radeon_driver_kms_fops, 252 253 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 254 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 255 .gem_prime_export = radeon_gem_prime_export, 256 .gem_prime_import = radeon_gem_prime_import, 257 #endif 258 259 .name = DRIVER_NAME, 260 .desc = DRIVER_DESC, 261 .date = DRIVER_DATE, 262 .major = KMS_DRIVER_MAJOR, 263 .minor = KMS_DRIVER_MINOR, 264 .patchlevel = KMS_DRIVER_PATCHLEVEL, 265 }; 266 267 int 268 radeondrm_probe(struct device *parent, void *match, void *aux) 269 { 270 if (radeon_fatal_error) 271 return 0; 272 if (drm_pciprobe(aux, radeondrm_pciidlist)) 273 return 20; 274 return 0; 275 } 276 277 /** 278 * radeon_driver_unload_kms - Main unload function for KMS. 279 * 280 * @dev: drm dev pointer 281 * 282 * This is the main unload function for KMS (all asics). 283 * It calls radeon_modeset_fini() to tear down the 284 * displays, and radeon_device_fini() to tear down 285 * the rest of the device (CP, writeback, etc.). 286 * Returns 0 on success. 287 */ 288 int 289 radeondrm_detach_kms(struct device *self, int flags) 290 { 291 struct radeon_device *rdev = (struct radeon_device *)self; 292 293 if (rdev == NULL) 294 return 0; 295 296 radeon_acpi_fini(rdev); 297 radeon_modeset_fini(rdev); 298 radeon_device_fini(rdev); 299 300 if (rdev->ddev != NULL) { 301 config_detach((struct device *)rdev->ddev, flags); 302 rdev->ddev = NULL; 303 } 304 305 pci_intr_disestablish(rdev->pc, rdev->irqh); 306 307 if (rdev->rmmio_size > 0) 308 bus_space_unmap(rdev->memt, rdev->rmmio, rdev->rmmio_size); 309 310 return 0; 311 } 312 313 int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *); 314 paddr_t radeondrm_wsmmap(void *, off_t, int); 315 int radeondrm_alloc_screen(void *, const struct wsscreen_descr *, 316 void **, int *, int *, long *); 317 void radeondrm_free_screen(void *, void *); 318 int radeondrm_show_screen(void *, void *, int, 319 void (*)(void *, int, int), void *); 320 void radeondrm_doswitch(void *); 321 #ifdef __sparc64__ 322 void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 323 #endif 324 325 struct wsscreen_descr radeondrm_stdscreen = { 326 "std", 327 0, 0, 328 0, 329 0, 0, 330 WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 331 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS 332 }; 333 334 const struct wsscreen_descr *radeondrm_scrlist[] = { 335 &radeondrm_stdscreen, 336 }; 337 338 struct wsscreen_list radeondrm_screenlist = { 339 nitems(radeondrm_scrlist), radeondrm_scrlist 340 }; 341 342 struct wsdisplay_accessops radeondrm_accessops = { 343 .ioctl = radeondrm_wsioctl, 344 .mmap = radeondrm_wsmmap, 345 .alloc_screen = radeondrm_alloc_screen, 346 .free_screen = radeondrm_free_screen, 347 .show_screen = radeondrm_show_screen, 348 .getchar = rasops_getchar, 349 .load_font = rasops_load_font, 350 .list_font = rasops_list_font, 351 .burn_screen = radeondrm_burner 352 }; 353 354 int 355 radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 356 { 357 switch (cmd) { 358 case WSDISPLAYIO_GTYPE: 359 *(int *)data = WSDISPLAY_TYPE_RADEONDRM; 360 return 0; 361 default: 362 return -1; 363 } 364 } 365 366 paddr_t 367 radeondrm_wsmmap(void *v, off_t off, int prot) 368 { 369 return (-1); 370 } 371 372 int 373 radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type, 374 void **cookiep, int *curxp, int *curyp, long *attrp) 375 { 376 return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); 377 } 378 379 void 380 radeondrm_free_screen(void *v, void *cookie) 381 { 382 return rasops_free_screen(v, cookie); 383 } 384 385 int 386 radeondrm_show_screen(void *v, void *cookie, int waitok, 387 void (*cb)(void *, int, int), void *cbarg) 388 { 389 struct rasops_info *ri = v; 390 struct radeon_device *rdev = ri->ri_hw; 391 392 if (cookie == ri->ri_active) 393 return (0); 394 395 rdev->switchcb = cb; 396 rdev->switchcbarg = cbarg; 397 rdev->switchcookie = cookie; 398 if (cb) { 399 task_add(systq, &rdev->switchtask); 400 return (EAGAIN); 401 } 402 403 radeondrm_doswitch(v); 404 405 return (0); 406 } 407 408 void 409 radeondrm_doswitch(void *v) 410 { 411 struct rasops_info *ri = v; 412 struct radeon_device *rdev = ri->ri_hw; 413 struct radeon_crtc *radeon_crtc; 414 int i, crtc; 415 416 rasops_show_screen(ri, rdev->switchcookie, 0, NULL, NULL); 417 for (crtc = 0; crtc < rdev->num_crtc; crtc++) { 418 for (i = 0; i < 256; i++) { 419 radeon_crtc = rdev->mode_info.crtcs[crtc]; 420 radeon_crtc->lut_r[i] = rasops_cmap[3 * i] << 2; 421 radeon_crtc->lut_g[i] = rasops_cmap[(3 * i) + 1] << 2; 422 radeon_crtc->lut_b[i] = rasops_cmap[(3 * i) + 2] << 2; 423 } 424 } 425 #ifdef __sparc64__ 426 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 427 #endif 428 drm_modeset_lock_all(rdev->ddev); 429 drm_fb_helper_restore_fbdev_mode((void *)rdev->mode_info.rfbdev); 430 drm_modeset_unlock_all(rdev->ddev); 431 432 if (rdev->switchcb) 433 (rdev->switchcb)(rdev->switchcbarg, 0, 0); 434 } 435 436 #ifdef __sparc64__ 437 void 438 radeondrm_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 439 { 440 struct sunfb *sf = v; 441 struct radeon_device *rdev = sf->sf_ro.ri_hw; 442 struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev; 443 u_int16_t red, green, blue; 444 struct drm_crtc *crtc; 445 int i; 446 447 for (i = 0; i < fb_helper->crtc_count; i++) { 448 crtc = fb_helper->crtc_info[i].mode_set.crtc; 449 450 red = (r << 8) | r; 451 green = (g << 8) | g; 452 blue = (b << 8) | b; 453 fb_helper->funcs->gamma_set(crtc, red, green, blue, index); 454 } 455 } 456 #endif 457 458 /** 459 * radeon_driver_load_kms - Main load function for KMS. 460 * 461 * @dev: drm dev pointer 462 * @flags: device flags 463 * 464 * This is the main load function for KMS (all asics). 465 * It calls radeon_device_init() to set up the non-display 466 * parts of the chip (asic init, CP, writeback, etc.), and 467 * radeon_modeset_init() to set up the display parts 468 * (crtcs, encoders, hotplug detect, etc.). 469 * Returns 0 on success, error on failure. 470 */ 471 void 472 radeondrm_attach_kms(struct device *parent, struct device *self, void *aux) 473 { 474 struct radeon_device *rdev = (struct radeon_device *)self; 475 struct drm_device *dev; 476 struct pci_attach_args *pa = aux; 477 const struct drm_pcidev *id_entry; 478 int is_agp; 479 pcireg_t type; 480 uint8_t iobar; 481 #if !defined(__sparc64__) 482 pcireg_t addr, mask; 483 int s; 484 #endif 485 486 #if defined(__sparc64__) || defined(__macppc__) 487 extern int fbnode; 488 #endif 489 490 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 491 PCI_PRODUCT(pa->pa_id), radeondrm_pciidlist); 492 rdev->flags = id_entry->driver_data; 493 rdev->pc = pa->pa_pc; 494 rdev->pa_tag = pa->pa_tag; 495 rdev->iot = pa->pa_iot; 496 rdev->memt = pa->pa_memt; 497 rdev->dmat = pa->pa_dmat; 498 499 #if defined(__sparc64__) || defined(__macppc__) 500 if (fbnode == PCITAG_NODE(rdev->pa_tag)) 501 rdev->console = 1; 502 #else 503 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 504 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && 505 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 506 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 507 == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { 508 rdev->console = 1; 509 #if NVGA > 0 510 vga_console_attached = 1; 511 #endif 512 } 513 #if NEFIFB > 0 514 if (efifb_is_console(pa)) { 515 rdev->console = 1; 516 efifb_cndetach(); 517 } 518 #endif 519 #endif 520 521 #define RADEON_PCI_MEM 0x10 522 #define RADEON_PCI_IO 0x14 523 #define RADEON_PCI_MMIO 0x18 524 #define RADEON_PCI_IO2 0x20 525 526 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM); 527 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 528 pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, 529 type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) { 530 printf(": can't get frambuffer info\n"); 531 return; 532 } 533 534 if (PCI_MAPREG_MEM_TYPE(type) != PCI_MAPREG_MEM_TYPE_64BIT) 535 iobar = RADEON_PCI_IO; 536 else 537 iobar = RADEON_PCI_IO2; 538 539 if (pci_mapreg_map(pa, iobar, PCI_MAPREG_TYPE_IO, 0, 540 NULL, &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0)) { 541 printf(": can't map IO space\n"); 542 return; 543 } 544 545 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MMIO); 546 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 547 pci_mapreg_map(pa, RADEON_PCI_MMIO, type, 0, NULL, 548 &rdev->rmmio, &rdev->rmmio_base, &rdev->rmmio_size, 0)) { 549 printf(": can't map mmio space\n"); 550 return; 551 } 552 553 #if !defined(__sparc64__) 554 /* 555 * Make sure we have a base address for the ROM such that we 556 * can map it later. 557 */ 558 s = splhigh(); 559 addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 560 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 561 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 562 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); 563 splx(s); 564 565 if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { 566 bus_size_t size, start, end; 567 bus_addr_t base; 568 569 size = PCI_ROM_SIZE(mask); 570 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 571 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 572 if (extent_alloc_subregion(pa->pa_memex, start, end, size, 573 size, 0, 0, 0, &base) == 0) 574 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); 575 } 576 #endif 577 578 #ifdef notyet 579 mtx_init(&rdev->swi_lock, IPL_TTY); 580 #endif 581 582 /* update BUS flag */ 583 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) { 584 rdev->flags |= RADEON_IS_AGP; 585 } else if (pci_get_capability(pa->pa_pc, pa->pa_tag, 586 PCI_CAP_PCIEXPRESS, NULL, NULL)) { 587 rdev->flags |= RADEON_IS_PCIE; 588 } else { 589 rdev->flags |= RADEON_IS_PCI; 590 } 591 592 DRM_DEBUG("%s card detected\n", 593 ((rdev->flags & RADEON_IS_AGP) ? "AGP" : 594 (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 595 596 is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, 597 NULL, NULL); 598 599 printf("\n"); 600 601 kms_driver.num_ioctls = radeon_max_kms_ioctl; 602 603 dev = (struct drm_device *)drm_attach_pci(&kms_driver, pa, is_agp, 604 rdev->console, self); 605 rdev->ddev = dev; 606 rdev->pdev = dev->pdev; 607 608 rdev->family = rdev->flags & RADEON_FAMILY_MASK; 609 if (!radeon_msi_ok(rdev)) 610 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 611 612 rdev->msi_enabled = 0; 613 if (pci_intr_map_msi(pa, &rdev->intrh) == 0) 614 rdev->msi_enabled = 1; 615 else if (pci_intr_map(pa, &rdev->intrh) != 0) { 616 printf(": couldn't map interrupt\n"); 617 return; 618 } 619 printf("%s: %s\n", rdev->dev.dv_xname, 620 pci_intr_string(pa->pa_pc, rdev->intrh)); 621 622 rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY, 623 radeon_driver_irq_handler_kms, rdev->ddev, rdev->dev.dv_xname); 624 if (rdev->irqh == NULL) { 625 printf("%s: couldn't establish interrupt\n", 626 rdev->dev.dv_xname); 627 return; 628 } 629 630 #ifdef __sparc64__ 631 { 632 struct rasops_info *ri; 633 int node, console; 634 635 node = PCITAG_NODE(pa->pa_tag); 636 console = (fbnode == node); 637 638 fb_setsize(&rdev->sf, 8, 1152, 900, node, 0); 639 640 /* 641 * The firmware sets up the framebuffer such that at starts at 642 * an offset from the start of video memory. 643 */ 644 rdev->fb_offset = 645 bus_space_read_4(rdev->memt, rdev->rmmio, RADEON_CRTC_OFFSET); 646 if (bus_space_map(rdev->memt, rdev->fb_aper_offset + rdev->fb_offset, 647 rdev->sf.sf_fbsize, BUS_SPACE_MAP_LINEAR, &rdev->memh)) { 648 printf("%s: can't map video memory\n", rdev->dev.dv_xname); 649 return; 650 } 651 652 ri = &rdev->sf.sf_ro; 653 ri->ri_bits = bus_space_vaddr(rdev->memt, rdev->memh); 654 ri->ri_hw = rdev; 655 ri->ri_updatecursor = NULL; 656 657 fbwscons_init(&rdev->sf, RI_VCONS | RI_WRONLY | RI_BSWAP, console); 658 if (console) 659 fbwscons_console_init(&rdev->sf, -1); 660 } 661 #endif 662 663 rdev->shutdown = true; 664 config_mountroot(self, radeondrm_attachhook); 665 } 666 667 int 668 radeondrm_forcedetach(struct radeon_device *rdev) 669 { 670 struct pci_softc *sc = (struct pci_softc *)rdev->dev.dv_parent; 671 pcitag_t tag = rdev->pa_tag; 672 673 #if NVGA > 0 674 if (rdev->console) 675 vga_console_attached = 0; 676 #endif 677 678 config_detach(&rdev->dev, 0); 679 return pci_probe_device(sc, tag, NULL, NULL); 680 } 681 682 void 683 radeondrm_attachhook(struct device *self) 684 { 685 struct radeon_device *rdev = (struct radeon_device *)self; 686 int r, acpi_status; 687 688 /* radeon_device_init should report only fatal error 689 * like memory allocation failure or iomapping failure, 690 * or memory manager initialization failure, it must 691 * properly initialize the GPU MC controller and permit 692 * VRAM allocation 693 */ 694 r = radeon_device_init(rdev, rdev->ddev); 695 if (r) { 696 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 697 radeon_fatal_error = 1; 698 radeondrm_forcedetach(rdev); 699 return; 700 } 701 702 /* Again modeset_init should fail only on fatal error 703 * otherwise it should provide enough functionalities 704 * for shadowfb to run 705 */ 706 r = radeon_modeset_init(rdev); 707 if (r) 708 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 709 710 /* Call ACPI methods: require modeset init 711 * but failure is not fatal 712 */ 713 if (!r) { 714 acpi_status = radeon_acpi_init(rdev); 715 if (acpi_status) 716 DRM_DEBUG("Error during ACPI methods call\n"); 717 } 718 719 { 720 struct wsemuldisplaydev_attach_args aa; 721 struct rasops_info *ri = &rdev->ro; 722 723 task_set(&rdev->switchtask, radeondrm_doswitch, ri); 724 725 if (ri->ri_bits == NULL) 726 return; 727 728 #ifdef __sparc64__ 729 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 730 #endif 731 drm_modeset_lock_all(rdev->ddev); 732 drm_fb_helper_restore_fbdev_mode((void *)rdev->mode_info.rfbdev); 733 drm_modeset_unlock_all(rdev->ddev); 734 735 #ifndef __sparc64__ 736 ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; 737 rasops_init(ri, 160, 160); 738 739 ri->ri_hw = rdev; 740 #else 741 ri = &rdev->sf.sf_ro; 742 #endif 743 744 radeondrm_stdscreen.capabilities = ri->ri_caps; 745 radeondrm_stdscreen.nrows = ri->ri_rows; 746 radeondrm_stdscreen.ncols = ri->ri_cols; 747 radeondrm_stdscreen.textops = &ri->ri_ops; 748 radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth; 749 radeondrm_stdscreen.fontheight = ri->ri_font->fontheight; 750 751 aa.console = rdev->console; 752 aa.scrdata = &radeondrm_screenlist; 753 aa.accessops = &radeondrm_accessops; 754 aa.accesscookie = ri; 755 aa.defaultscreens = 0; 756 757 if (rdev->console) { 758 long defattr; 759 760 ri->ri_ops.alloc_attr(ri->ri_active, 0, 0, 0, &defattr); 761 wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active, 762 ri->ri_ccol, ri->ri_crow, defattr); 763 } 764 765 /* 766 * Now that we've taken over the console, disable decoding of 767 * VGA legacy addresses, and opt out of arbitration. 768 */ 769 radeon_vga_set_state(rdev, false); 770 pci_disable_legacy_vga(&rdev->dev); 771 772 printf("%s: %dx%d\n", rdev->dev.dv_xname, ri->ri_width, ri->ri_height); 773 774 config_found_sm(&rdev->dev, &aa, wsemuldisplaydevprint, 775 wsemuldisplaydevsubmatch); 776 } 777 } 778 779 int 780 radeondrm_activate_kms(struct device *self, int act) 781 { 782 struct radeon_device *rdev = (struct radeon_device *)self; 783 int rv = 0; 784 785 if (rdev->ddev == NULL) 786 return (0); 787 788 switch (act) { 789 case DVACT_QUIESCE: 790 rv = config_activate_children(self, act); 791 radeon_suspend_kms(rdev->ddev); 792 break; 793 case DVACT_SUSPEND: 794 break; 795 case DVACT_RESUME: 796 break; 797 case DVACT_WAKEUP: 798 radeon_resume_kms(rdev->ddev); 799 rv = config_activate_children(self, act); 800 break; 801 } 802 803 return (rv); 804 } 805 806 /** 807 * radeon_set_filp_rights - Set filp right. 808 * 809 * @dev: drm dev pointer 810 * @owner: drm file 811 * @applier: drm file 812 * @value: value 813 * 814 * Sets the filp rights for the device (all asics). 815 */ 816 static void radeon_set_filp_rights(struct drm_device *dev, 817 struct drm_file **owner, 818 struct drm_file *applier, 819 uint32_t *value) 820 { 821 mutex_lock(&dev->struct_mutex); 822 if (*value == 1) { 823 /* wants rights */ 824 if (!*owner) 825 *owner = applier; 826 } else if (*value == 0) { 827 /* revokes rights */ 828 if (*owner == applier) 829 *owner = NULL; 830 } 831 *value = *owner == applier ? 1 : 0; 832 mutex_unlock(&dev->struct_mutex); 833 } 834 835 /* 836 * Userspace get information ioctl 837 */ 838 /** 839 * radeon_info_ioctl - answer a device specific request. 840 * 841 * @rdev: radeon device pointer 842 * @data: request object 843 * @filp: drm filp 844 * 845 * This function is used to pass device specific parameters to the userspace 846 * drivers. Examples include: pci device id, pipeline parms, tiling params, 847 * etc. (all asics). 848 * Returns 0 on success, -EINVAL on failure. 849 */ 850 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 851 { 852 struct radeon_device *rdev = dev->dev_private; 853 struct drm_radeon_info *info = data; 854 struct radeon_mode_info *minfo = &rdev->mode_info; 855 uint32_t value, *value_ptr; 856 uint64_t value64, *value_ptr64; 857 struct drm_crtc *crtc; 858 int i, found; 859 860 /* TIMESTAMP is a 64-bit value, needs special handling. */ 861 if (info->request == RADEON_INFO_TIMESTAMP) { 862 if (rdev->family >= CHIP_R600) { 863 value_ptr64 = (uint64_t*)((unsigned long)info->value); 864 if (rdev->family >= CHIP_TAHITI) { 865 value64 = si_get_gpu_clock(rdev); 866 } else { 867 value64 = r600_get_gpu_clock(rdev); 868 } 869 870 if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) { 871 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 872 return -EFAULT; 873 } 874 return 0; 875 } else { 876 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n"); 877 return -EINVAL; 878 } 879 } 880 881 value_ptr = (uint32_t *)((unsigned long)info->value); 882 if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) { 883 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__); 884 return -EFAULT; 885 } 886 887 switch (info->request) { 888 case RADEON_INFO_DEVICE_ID: 889 value = dev->pci_device; 890 break; 891 case RADEON_INFO_NUM_GB_PIPES: 892 value = rdev->num_gb_pipes; 893 break; 894 case RADEON_INFO_NUM_Z_PIPES: 895 value = rdev->num_z_pipes; 896 break; 897 case RADEON_INFO_ACCEL_WORKING: 898 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */ 899 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) 900 value = false; 901 else 902 value = rdev->accel_working; 903 break; 904 case RADEON_INFO_CRTC_FROM_ID: 905 for (i = 0, found = 0; i < rdev->num_crtc; i++) { 906 crtc = (struct drm_crtc *)minfo->crtcs[i]; 907 if (crtc && crtc->base.id == value) { 908 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 909 value = radeon_crtc->crtc_id; 910 found = 1; 911 break; 912 } 913 } 914 if (!found) { 915 DRM_DEBUG_KMS("unknown crtc id %d\n", value); 916 return -EINVAL; 917 } 918 break; 919 case RADEON_INFO_ACCEL_WORKING2: 920 value = rdev->accel_working; 921 break; 922 case RADEON_INFO_TILING_CONFIG: 923 if (rdev->family >= CHIP_TAHITI) 924 value = rdev->config.si.tile_config; 925 else if (rdev->family >= CHIP_CAYMAN) 926 value = rdev->config.cayman.tile_config; 927 else if (rdev->family >= CHIP_CEDAR) 928 value = rdev->config.evergreen.tile_config; 929 else if (rdev->family >= CHIP_RV770) 930 value = rdev->config.rv770.tile_config; 931 else if (rdev->family >= CHIP_R600) 932 value = rdev->config.r600.tile_config; 933 else { 934 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n"); 935 return -EINVAL; 936 } 937 break; 938 case RADEON_INFO_WANT_HYPERZ: 939 /* The "value" here is both an input and output parameter. 940 * If the input value is 1, filp requests hyper-z access. 941 * If the input value is 0, filp revokes its hyper-z access. 942 * 943 * When returning, the value is 1 if filp owns hyper-z access, 944 * 0 otherwise. */ 945 if (value >= 2) { 946 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value); 947 return -EINVAL; 948 } 949 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value); 950 break; 951 case RADEON_INFO_WANT_CMASK: 952 /* The same logic as Hyper-Z. */ 953 if (value >= 2) { 954 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value); 955 return -EINVAL; 956 } 957 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value); 958 break; 959 case RADEON_INFO_CLOCK_CRYSTAL_FREQ: 960 /* return clock value in KHz */ 961 value = rdev->clock.spll.reference_freq * 10; 962 break; 963 case RADEON_INFO_NUM_BACKENDS: 964 if (rdev->family >= CHIP_TAHITI) 965 value = rdev->config.si.max_backends_per_se * 966 rdev->config.si.max_shader_engines; 967 else if (rdev->family >= CHIP_CAYMAN) 968 value = rdev->config.cayman.max_backends_per_se * 969 rdev->config.cayman.max_shader_engines; 970 else if (rdev->family >= CHIP_CEDAR) 971 value = rdev->config.evergreen.max_backends; 972 else if (rdev->family >= CHIP_RV770) 973 value = rdev->config.rv770.max_backends; 974 else if (rdev->family >= CHIP_R600) 975 value = rdev->config.r600.max_backends; 976 else { 977 return -EINVAL; 978 } 979 break; 980 case RADEON_INFO_NUM_TILE_PIPES: 981 if (rdev->family >= CHIP_TAHITI) 982 value = rdev->config.si.max_tile_pipes; 983 else if (rdev->family >= CHIP_CAYMAN) 984 value = rdev->config.cayman.max_tile_pipes; 985 else if (rdev->family >= CHIP_CEDAR) 986 value = rdev->config.evergreen.max_tile_pipes; 987 else if (rdev->family >= CHIP_RV770) 988 value = rdev->config.rv770.max_tile_pipes; 989 else if (rdev->family >= CHIP_R600) 990 value = rdev->config.r600.max_tile_pipes; 991 else { 992 return -EINVAL; 993 } 994 break; 995 case RADEON_INFO_FUSION_GART_WORKING: 996 value = 1; 997 break; 998 case RADEON_INFO_BACKEND_MAP: 999 if (rdev->family >= CHIP_TAHITI) 1000 value = rdev->config.si.backend_map; 1001 else if (rdev->family >= CHIP_CAYMAN) 1002 value = rdev->config.cayman.backend_map; 1003 else if (rdev->family >= CHIP_CEDAR) 1004 value = rdev->config.evergreen.backend_map; 1005 else if (rdev->family >= CHIP_RV770) 1006 value = rdev->config.rv770.backend_map; 1007 else if (rdev->family >= CHIP_R600) 1008 value = rdev->config.r600.backend_map; 1009 else { 1010 return -EINVAL; 1011 } 1012 break; 1013 case RADEON_INFO_VA_START: 1014 /* this is where we report if vm is supported or not */ 1015 if (rdev->family < CHIP_CAYMAN) 1016 return -EINVAL; 1017 value = RADEON_VA_RESERVED_SIZE; 1018 break; 1019 case RADEON_INFO_IB_VM_MAX_SIZE: 1020 /* this is where we report if vm is supported or not */ 1021 if (rdev->family < CHIP_CAYMAN) 1022 return -EINVAL; 1023 value = RADEON_IB_VM_MAX_SIZE; 1024 break; 1025 case RADEON_INFO_MAX_PIPES: 1026 if (rdev->family >= CHIP_TAHITI) 1027 value = rdev->config.si.max_cu_per_sh; 1028 else if (rdev->family >= CHIP_CAYMAN) 1029 value = rdev->config.cayman.max_pipes_per_simd; 1030 else if (rdev->family >= CHIP_CEDAR) 1031 value = rdev->config.evergreen.max_pipes; 1032 else if (rdev->family >= CHIP_RV770) 1033 value = rdev->config.rv770.max_pipes; 1034 else if (rdev->family >= CHIP_R600) 1035 value = rdev->config.r600.max_pipes; 1036 else { 1037 return -EINVAL; 1038 } 1039 break; 1040 case RADEON_INFO_MAX_SE: 1041 if (rdev->family >= CHIP_TAHITI) 1042 value = rdev->config.si.max_shader_engines; 1043 else if (rdev->family >= CHIP_CAYMAN) 1044 value = rdev->config.cayman.max_shader_engines; 1045 else if (rdev->family >= CHIP_CEDAR) 1046 value = rdev->config.evergreen.num_ses; 1047 else 1048 value = 1; 1049 break; 1050 case RADEON_INFO_MAX_SH_PER_SE: 1051 if (rdev->family >= CHIP_TAHITI) 1052 value = rdev->config.si.max_sh_per_se; 1053 else 1054 return -EINVAL; 1055 break; 1056 case RADEON_INFO_SI_CP_DMA_COMPUTE: 1057 value = 1; 1058 break; 1059 case RADEON_INFO_SI_BACKEND_ENABLED_MASK: 1060 if (rdev->family >= CHIP_TAHITI) { 1061 value = rdev->config.si.backend_enable_mask; 1062 } else { 1063 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n"); 1064 } 1065 break; 1066 default: 1067 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 1068 return -EINVAL; 1069 } 1070 if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) { 1071 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__); 1072 return -EFAULT; 1073 } 1074 return 0; 1075 } 1076 1077 1078 /* 1079 * Outdated mess for old drm with Xorg being in charge (void function now). 1080 */ 1081 /** 1082 * radeon_driver_firstopen_kms - drm callback for first open 1083 * 1084 * @dev: drm dev pointer 1085 * 1086 * Nothing to be done for KMS (all asics). 1087 * Returns 0 on success. 1088 */ 1089 int radeon_driver_firstopen_kms(struct drm_device *dev) 1090 { 1091 return 0; 1092 } 1093 1094 /** 1095 * radeon_driver_firstopen_kms - drm callback for last close 1096 * 1097 * @dev: drm dev pointer 1098 * 1099 * Switch vga switcheroo state after last close (all asics). 1100 */ 1101 void radeon_driver_lastclose_kms(struct drm_device *dev) 1102 { 1103 struct radeon_device *rdev = dev->dev_private; 1104 struct drm_fb_helper *fb_helper = (void *)rdev->mode_info.rfbdev; 1105 1106 #ifdef __sparc64__ 1107 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 1108 #endif 1109 if (rdev->mode_info.mode_config_initialized) { 1110 drm_modeset_lock_all(dev); 1111 drm_fb_helper_restore_fbdev_mode(fb_helper); 1112 drm_modeset_unlock_all(dev); 1113 } 1114 #ifdef notyet 1115 vga_switcheroo_process_delayed_switch(); 1116 #endif 1117 } 1118 1119 /** 1120 * radeon_driver_open_kms - drm callback for open 1121 * 1122 * @dev: drm dev pointer 1123 * @file_priv: drm file 1124 * 1125 * On device open, init vm on cayman+ (all asics). 1126 * Returns 0 on success, error on failure. 1127 */ 1128 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 1129 { 1130 struct radeon_device *rdev = dev->dev_private; 1131 1132 file_priv->driver_priv = NULL; 1133 1134 /* new gpu have virtual address space support */ 1135 if (rdev->family >= CHIP_CAYMAN) { 1136 struct radeon_fpriv *fpriv; 1137 struct radeon_bo_va *bo_va; 1138 int r; 1139 1140 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 1141 if (unlikely(!fpriv)) { 1142 return -ENOMEM; 1143 } 1144 1145 radeon_vm_init(rdev, &fpriv->vm); 1146 1147 if (rdev->accel_working) { 1148 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 1149 if (r) { 1150 radeon_vm_fini(rdev, &fpriv->vm); 1151 kfree(fpriv); 1152 return r; 1153 } 1154 1155 /* map the ib pool buffer read only into 1156 * virtual address space */ 1157 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, 1158 rdev->ring_tmp_bo.bo); 1159 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, 1160 RADEON_VM_PAGE_READABLE | 1161 RADEON_VM_PAGE_SNOOPED); 1162 1163 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 1164 if (r) { 1165 radeon_vm_fini(rdev, &fpriv->vm); 1166 kfree(fpriv); 1167 return r; 1168 } 1169 } 1170 file_priv->driver_priv = fpriv; 1171 } 1172 return 0; 1173 } 1174 1175 /** 1176 * radeon_driver_postclose_kms - drm callback for post close 1177 * 1178 * @dev: drm dev pointer 1179 * @file_priv: drm file 1180 * 1181 * On device post close, tear down vm on cayman+ (all asics). 1182 */ 1183 void radeon_driver_postclose_kms(struct drm_device *dev, 1184 struct drm_file *file_priv) 1185 { 1186 struct radeon_device *rdev = dev->dev_private; 1187 1188 /* new gpu have virtual address space support */ 1189 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) { 1190 struct radeon_fpriv *fpriv = file_priv->driver_priv; 1191 struct radeon_bo_va *bo_va; 1192 int r; 1193 1194 if (rdev->accel_working) { 1195 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); 1196 if (!r) { 1197 bo_va = radeon_vm_bo_find(&fpriv->vm, 1198 rdev->ring_tmp_bo.bo); 1199 if (bo_va) 1200 radeon_vm_bo_rmv(rdev, bo_va); 1201 radeon_bo_unreserve(rdev->ring_tmp_bo.bo); 1202 } 1203 } 1204 1205 radeon_vm_fini(rdev, &fpriv->vm); 1206 kfree(fpriv); 1207 file_priv->driver_priv = NULL; 1208 } 1209 } 1210 1211 /** 1212 * radeon_driver_preclose_kms - drm callback for pre close 1213 * 1214 * @dev: drm dev pointer 1215 * @file_priv: drm file 1216 * 1217 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 1218 * (all asics). 1219 */ 1220 void radeon_driver_preclose_kms(struct drm_device *dev, 1221 struct drm_file *file_priv) 1222 { 1223 struct radeon_device *rdev = dev->dev_private; 1224 if (rdev->hyperz_filp == file_priv) 1225 rdev->hyperz_filp = NULL; 1226 if (rdev->cmask_filp == file_priv) 1227 rdev->cmask_filp = NULL; 1228 } 1229 1230 /* 1231 * VBlank related functions. 1232 */ 1233 /** 1234 * radeon_get_vblank_counter_kms - get frame count 1235 * 1236 * @dev: drm dev pointer 1237 * @crtc: crtc to get the frame count from 1238 * 1239 * Gets the frame count on the requested crtc (all asics). 1240 * Returns frame count on success, -EINVAL on failure. 1241 */ 1242 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc) 1243 { 1244 struct radeon_device *rdev = dev->dev_private; 1245 1246 if (crtc < 0 || crtc >= rdev->num_crtc) { 1247 DRM_ERROR("Invalid crtc %d\n", crtc); 1248 return -EINVAL; 1249 } 1250 1251 return radeon_get_vblank_counter(rdev, crtc); 1252 } 1253 1254 /** 1255 * radeon_enable_vblank_kms - enable vblank interrupt 1256 * 1257 * @dev: drm dev pointer 1258 * @crtc: crtc to enable vblank interrupt for 1259 * 1260 * Enable the interrupt on the requested crtc (all asics). 1261 * Returns 0 on success, -EINVAL on failure. 1262 */ 1263 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc) 1264 { 1265 struct radeon_device *rdev = dev->dev_private; 1266 unsigned long irqflags; 1267 int r; 1268 1269 if (crtc < 0 || crtc >= rdev->num_crtc) { 1270 DRM_ERROR("Invalid crtc %d\n", crtc); 1271 return -EINVAL; 1272 } 1273 1274 spin_lock_irqsave(&rdev->irq.lock, irqflags); 1275 rdev->irq.crtc_vblank_int[crtc] = true; 1276 r = radeon_irq_set(rdev); 1277 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 1278 return r; 1279 } 1280 1281 /** 1282 * radeon_disable_vblank_kms - disable vblank interrupt 1283 * 1284 * @dev: drm dev pointer 1285 * @crtc: crtc to disable vblank interrupt for 1286 * 1287 * Disable the interrupt on the requested crtc (all asics). 1288 */ 1289 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc) 1290 { 1291 struct radeon_device *rdev = dev->dev_private; 1292 unsigned long irqflags; 1293 1294 if (crtc < 0 || crtc >= rdev->num_crtc) { 1295 DRM_ERROR("Invalid crtc %d\n", crtc); 1296 return; 1297 } 1298 1299 spin_lock_irqsave(&rdev->irq.lock, irqflags); 1300 rdev->irq.crtc_vblank_int[crtc] = false; 1301 radeon_irq_set(rdev); 1302 spin_unlock_irqrestore(&rdev->irq.lock, irqflags); 1303 } 1304 1305 /** 1306 * radeon_get_vblank_timestamp_kms - get vblank timestamp 1307 * 1308 * @dev: drm dev pointer 1309 * @crtc: crtc to get the timestamp for 1310 * @max_error: max error 1311 * @vblank_time: time value 1312 * @flags: flags passed to the driver 1313 * 1314 * Gets the timestamp on the requested crtc based on the 1315 * scanout position. (all asics). 1316 * Returns postive status flags on success, negative error on failure. 1317 */ 1318 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 1319 int *max_error, 1320 struct timeval *vblank_time, 1321 unsigned flags) 1322 { 1323 struct drm_crtc *drmcrtc; 1324 struct radeon_device *rdev = dev->dev_private; 1325 1326 if (crtc < 0 || crtc >= dev->num_crtcs) { 1327 DRM_ERROR("Invalid crtc %d\n", crtc); 1328 return -EINVAL; 1329 } 1330 1331 /* Get associated drm_crtc: */ 1332 drmcrtc = &rdev->mode_info.crtcs[crtc]->base; 1333 1334 /* Helper routine in DRM core does all the work: */ 1335 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, 1336 vblank_time, flags, 1337 drmcrtc, &drmcrtc->hwmode); 1338 } 1339 1340 /* 1341 * IOCTL. 1342 */ 1343 int radeon_dma_ioctl_kms(struct drm_device *dev, struct drm_dma *d, 1344 struct drm_file *file_priv) 1345 { 1346 /* Not valid in KMS. */ 1347 return -EINVAL; 1348 } 1349 1350 #define KMS_INVALID_IOCTL(name) \ 1351 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\ 1352 { \ 1353 DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ 1354 return -EINVAL; \ 1355 } 1356 1357 /* 1358 * All these ioctls are invalid in kms world. 1359 */ 1360 KMS_INVALID_IOCTL(radeon_cp_init_kms) 1361 KMS_INVALID_IOCTL(radeon_cp_start_kms) 1362 KMS_INVALID_IOCTL(radeon_cp_stop_kms) 1363 KMS_INVALID_IOCTL(radeon_cp_reset_kms) 1364 KMS_INVALID_IOCTL(radeon_cp_idle_kms) 1365 KMS_INVALID_IOCTL(radeon_cp_resume_kms) 1366 KMS_INVALID_IOCTL(radeon_engine_reset_kms) 1367 KMS_INVALID_IOCTL(radeon_fullscreen_kms) 1368 KMS_INVALID_IOCTL(radeon_cp_swap_kms) 1369 KMS_INVALID_IOCTL(radeon_cp_clear_kms) 1370 KMS_INVALID_IOCTL(radeon_cp_vertex_kms) 1371 KMS_INVALID_IOCTL(radeon_cp_indices_kms) 1372 KMS_INVALID_IOCTL(radeon_cp_texture_kms) 1373 KMS_INVALID_IOCTL(radeon_cp_stipple_kms) 1374 KMS_INVALID_IOCTL(radeon_cp_indirect_kms) 1375 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) 1376 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) 1377 KMS_INVALID_IOCTL(radeon_cp_getparam_kms) 1378 KMS_INVALID_IOCTL(radeon_cp_flip_kms) 1379 KMS_INVALID_IOCTL(radeon_mem_alloc_kms) 1380 KMS_INVALID_IOCTL(radeon_mem_free_kms) 1381 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) 1382 KMS_INVALID_IOCTL(radeon_irq_emit_kms) 1383 KMS_INVALID_IOCTL(radeon_irq_wait_kms) 1384 KMS_INVALID_IOCTL(radeon_cp_setparam_kms) 1385 KMS_INVALID_IOCTL(radeon_surface_alloc_kms) 1386 KMS_INVALID_IOCTL(radeon_surface_free_kms) 1387 1388 1389 struct drm_ioctl_desc radeon_ioctls_kms[] = { 1390 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1391 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1392 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1393 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1394 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), 1395 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), 1396 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), 1397 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), 1398 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), 1399 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), 1400 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), 1401 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), 1402 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), 1403 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), 1404 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1405 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), 1406 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), 1407 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), 1408 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), 1409 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), 1410 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), 1411 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 1412 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), 1413 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), 1414 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), 1415 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), 1416 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), 1417 /* KMS */ 1418 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1419 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1420 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1421 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1422 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), 1423 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), 1424 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1425 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1426 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1427 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1428 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1429 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1430 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 1431 }; 1432 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); 1433