1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/console.h> 30 #include <linux/efi.h> 31 #include <linux/pci.h> 32 #include <linux/pm_runtime.h> 33 #include <linux/slab.h> 34 #include <linux/vga_switcheroo.h> 35 #include <linux/vgaarb.h> 36 37 #include <drm/drm_cache.h> 38 #include <drm/drm_crtc_helper.h> 39 #include <drm/drm_debugfs.h> 40 #include <drm/drm_device.h> 41 #include <drm/drm_file.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/radeon_drm.h> 44 45 #include "radeon_reg.h" 46 #include "radeon.h" 47 #include "atom.h" 48 49 static const char radeon_family_name[][16] = { 50 "R100", 51 "RV100", 52 "RS100", 53 "RV200", 54 "RS200", 55 "R200", 56 "RV250", 57 "RS300", 58 "RV280", 59 "R300", 60 "R350", 61 "RV350", 62 "RV380", 63 "R420", 64 "R423", 65 "RV410", 66 "RS400", 67 "RS480", 68 "RS600", 69 "RS690", 70 "RS740", 71 "RV515", 72 "R520", 73 "RV530", 74 "RV560", 75 "RV570", 76 "R580", 77 "R600", 78 "RV610", 79 "RV630", 80 "RV670", 81 "RV620", 82 "RV635", 83 "RS780", 84 "RS880", 85 "RV770", 86 "RV730", 87 "RV710", 88 "RV740", 89 "CEDAR", 90 "REDWOOD", 91 "JUNIPER", 92 "CYPRESS", 93 "HEMLOCK", 94 "PALM", 95 "SUMO", 96 "SUMO2", 97 "BARTS", 98 "TURKS", 99 "CAICOS", 100 "CAYMAN", 101 "ARUBA", 102 "TAHITI", 103 "PITCAIRN", 104 "VERDE", 105 "OLAND", 106 "HAINAN", 107 "BONAIRE", 108 "KAVERI", 109 "KABINI", 110 "HAWAII", 111 "MULLINS", 112 "LAST", 113 }; 114 115 #if defined(CONFIG_VGA_SWITCHEROO) 116 bool radeon_has_atpx_dgpu_power_cntl(void); 117 bool radeon_is_atpx_hybrid(void); 118 #else 119 static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; } 120 static inline bool radeon_is_atpx_hybrid(void) { return false; } 121 #endif 122 123 #define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 124 125 struct radeon_px_quirk { 126 u32 chip_vendor; 127 u32 chip_device; 128 u32 subsys_vendor; 129 u32 subsys_device; 130 u32 px_quirk_flags; 131 }; 132 133 static struct radeon_px_quirk radeon_px_quirk_list[] = { 134 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 135 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 136 */ 137 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 138 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 139 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 140 */ 141 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 142 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 143 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 144 */ 145 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 146 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 147 * https://bugs.freedesktop.org/show_bug.cgi?id=101491 148 */ 149 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 150 /* Asus K73TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 151 * https://bugzilla.kernel.org/show_bug.cgi?id=51381#c52 152 */ 153 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX }, 154 { 0, 0, 0, 0, 0 }, 155 }; 156 157 bool radeon_is_px(struct drm_device *dev) 158 { 159 struct radeon_device *rdev = dev->dev_private; 160 161 if (rdev->flags & RADEON_IS_PX) 162 return true; 163 return false; 164 } 165 166 static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 167 { 168 struct radeon_px_quirk *p = radeon_px_quirk_list; 169 170 /* Apply PX quirks */ 171 while (p && p->chip_device != 0) { 172 if (rdev->pdev->vendor == p->chip_vendor && 173 rdev->pdev->device == p->chip_device && 174 rdev->pdev->subsystem_vendor == p->subsys_vendor && 175 rdev->pdev->subsystem_device == p->subsys_device) { 176 rdev->px_quirk_flags = p->px_quirk_flags; 177 break; 178 } 179 ++p; 180 } 181 182 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 183 rdev->flags &= ~RADEON_IS_PX; 184 185 /* disable PX is the system doesn't support dGPU power control or hybrid gfx */ 186 if (!radeon_is_atpx_hybrid() && 187 !radeon_has_atpx_dgpu_power_cntl()) 188 rdev->flags &= ~RADEON_IS_PX; 189 } 190 191 /** 192 * radeon_program_register_sequence - program an array of registers. 193 * 194 * @rdev: radeon_device pointer 195 * @registers: pointer to the register array 196 * @array_size: size of the register array 197 * 198 * Programs an array or registers with and and or masks. 199 * This is a helper for setting golden registers. 200 */ 201 void radeon_program_register_sequence(struct radeon_device *rdev, 202 const u32 *registers, 203 const u32 array_size) 204 { 205 u32 tmp, reg, and_mask, or_mask; 206 int i; 207 208 if (array_size % 3) 209 return; 210 211 for (i = 0; i < array_size; i +=3) { 212 reg = registers[i + 0]; 213 and_mask = registers[i + 1]; 214 or_mask = registers[i + 2]; 215 216 if (and_mask == 0xffffffff) { 217 tmp = or_mask; 218 } else { 219 tmp = RREG32(reg); 220 tmp &= ~and_mask; 221 tmp |= or_mask; 222 } 223 WREG32(reg, tmp); 224 } 225 } 226 227 void radeon_pci_config_reset(struct radeon_device *rdev) 228 { 229 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 230 } 231 232 /** 233 * radeon_surface_init - Clear GPU surface registers. 234 * 235 * @rdev: radeon_device pointer 236 * 237 * Clear GPU surface registers (r1xx-r5xx). 238 */ 239 void radeon_surface_init(struct radeon_device *rdev) 240 { 241 /* FIXME: check this out */ 242 if (rdev->family < CHIP_R600) { 243 int i; 244 245 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 246 if (rdev->surface_regs[i].bo) 247 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 248 else 249 radeon_clear_surface_reg(rdev, i); 250 } 251 /* enable surfaces */ 252 WREG32(RADEON_SURFACE_CNTL, 0); 253 } 254 } 255 256 /* 257 * GPU scratch registers helpers function. 258 */ 259 /** 260 * radeon_scratch_init - Init scratch register driver information. 261 * 262 * @rdev: radeon_device pointer 263 * 264 * Init CP scratch register driver information (r1xx-r5xx) 265 */ 266 void radeon_scratch_init(struct radeon_device *rdev) 267 { 268 int i; 269 270 /* FIXME: check this out */ 271 if (rdev->family < CHIP_R300) { 272 rdev->scratch.num_reg = 5; 273 } else { 274 rdev->scratch.num_reg = 7; 275 } 276 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 277 for (i = 0; i < rdev->scratch.num_reg; i++) { 278 rdev->scratch.free[i] = true; 279 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 280 } 281 } 282 283 /** 284 * radeon_scratch_get - Allocate a scratch register 285 * 286 * @rdev: radeon_device pointer 287 * @reg: scratch register mmio offset 288 * 289 * Allocate a CP scratch register for use by the driver (all asics). 290 * Returns 0 on success or -EINVAL on failure. 291 */ 292 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 293 { 294 int i; 295 296 for (i = 0; i < rdev->scratch.num_reg; i++) { 297 if (rdev->scratch.free[i]) { 298 rdev->scratch.free[i] = false; 299 *reg = rdev->scratch.reg[i]; 300 return 0; 301 } 302 } 303 return -EINVAL; 304 } 305 306 /** 307 * radeon_scratch_free - Free a scratch register 308 * 309 * @rdev: radeon_device pointer 310 * @reg: scratch register mmio offset 311 * 312 * Free a CP scratch register allocated for use by the driver (all asics) 313 */ 314 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 315 { 316 int i; 317 318 for (i = 0; i < rdev->scratch.num_reg; i++) { 319 if (rdev->scratch.reg[i] == reg) { 320 rdev->scratch.free[i] = true; 321 return; 322 } 323 } 324 } 325 326 /* 327 * GPU doorbell aperture helpers function. 328 */ 329 /** 330 * radeon_doorbell_init - Init doorbell driver information. 331 * 332 * @rdev: radeon_device pointer 333 * 334 * Init doorbell driver information (CIK) 335 * Returns 0 on success, error on failure. 336 */ 337 static int radeon_doorbell_init(struct radeon_device *rdev) 338 { 339 /* doorbell bar mapping */ 340 #ifdef __linux__ 341 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 342 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 343 #endif 344 345 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 346 if (rdev->doorbell.num_doorbells == 0) 347 return -EINVAL; 348 349 #ifdef __linux__ 350 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 351 if (rdev->doorbell.ptr == NULL) { 352 return -ENOMEM; 353 } 354 #endif 355 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 356 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 357 358 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 359 360 return 0; 361 } 362 363 /** 364 * radeon_doorbell_fini - Tear down doorbell driver information. 365 * 366 * @rdev: radeon_device pointer 367 * 368 * Tear down doorbell driver information (CIK) 369 */ 370 static void radeon_doorbell_fini(struct radeon_device *rdev) 371 { 372 #ifdef __linux__ 373 iounmap(rdev->doorbell.ptr); 374 rdev->doorbell.ptr = NULL; 375 #else 376 if (rdev->doorbell.size > 0) 377 bus_space_unmap(rdev->memt, rdev->doorbell.bsh, 378 rdev->doorbell.size); 379 rdev->doorbell.size = 0; 380 #endif 381 } 382 383 /** 384 * radeon_doorbell_get - Allocate a doorbell entry 385 * 386 * @rdev: radeon_device pointer 387 * @doorbell: doorbell index 388 * 389 * Allocate a doorbell for use by the driver (all asics). 390 * Returns 0 on success or -EINVAL on failure. 391 */ 392 int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 393 { 394 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 395 if (offset < rdev->doorbell.num_doorbells) { 396 __set_bit(offset, rdev->doorbell.used); 397 *doorbell = offset; 398 return 0; 399 } else { 400 return -EINVAL; 401 } 402 } 403 404 /** 405 * radeon_doorbell_free - Free a doorbell entry 406 * 407 * @rdev: radeon_device pointer 408 * @doorbell: doorbell index 409 * 410 * Free a doorbell allocated for use by the driver (all asics) 411 */ 412 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 413 { 414 if (doorbell < rdev->doorbell.num_doorbells) 415 __clear_bit(doorbell, rdev->doorbell.used); 416 } 417 418 /* 419 * radeon_wb_*() 420 * Writeback is the the method by which the the GPU updates special pages 421 * in memory with the status of certain GPU events (fences, ring pointers, 422 * etc.). 423 */ 424 425 /** 426 * radeon_wb_disable - Disable Writeback 427 * 428 * @rdev: radeon_device pointer 429 * 430 * Disables Writeback (all asics). Used for suspend. 431 */ 432 void radeon_wb_disable(struct radeon_device *rdev) 433 { 434 rdev->wb.enabled = false; 435 } 436 437 /** 438 * radeon_wb_fini - Disable Writeback and free memory 439 * 440 * @rdev: radeon_device pointer 441 * 442 * Disables Writeback and frees the Writeback memory (all asics). 443 * Used at driver shutdown. 444 */ 445 void radeon_wb_fini(struct radeon_device *rdev) 446 { 447 radeon_wb_disable(rdev); 448 if (rdev->wb.wb_obj) { 449 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 450 radeon_bo_kunmap(rdev->wb.wb_obj); 451 radeon_bo_unpin(rdev->wb.wb_obj); 452 radeon_bo_unreserve(rdev->wb.wb_obj); 453 } 454 radeon_bo_unref(&rdev->wb.wb_obj); 455 rdev->wb.wb = NULL; 456 rdev->wb.wb_obj = NULL; 457 } 458 } 459 460 /** 461 * radeon_wb_init- Init Writeback driver info and allocate memory 462 * 463 * @rdev: radeon_device pointer 464 * 465 * Disables Writeback and frees the Writeback memory (all asics). 466 * Used at driver startup. 467 * Returns 0 on success or an -error on failure. 468 */ 469 int radeon_wb_init(struct radeon_device *rdev) 470 { 471 int r; 472 473 if (rdev->wb.wb_obj == NULL) { 474 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 475 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, 476 &rdev->wb.wb_obj); 477 if (r) { 478 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 479 return r; 480 } 481 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 482 if (unlikely(r != 0)) { 483 radeon_wb_fini(rdev); 484 return r; 485 } 486 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 487 &rdev->wb.gpu_addr); 488 if (r) { 489 radeon_bo_unreserve(rdev->wb.wb_obj); 490 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 491 radeon_wb_fini(rdev); 492 return r; 493 } 494 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); 495 radeon_bo_unreserve(rdev->wb.wb_obj); 496 if (r) { 497 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 498 radeon_wb_fini(rdev); 499 return r; 500 } 501 } 502 503 /* clear wb memory */ 504 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); 505 /* disable event_write fences */ 506 rdev->wb.use_event = false; 507 /* disabled via module param */ 508 if (radeon_no_wb == 1) { 509 rdev->wb.enabled = false; 510 } else { 511 if (rdev->flags & RADEON_IS_AGP) { 512 /* often unreliable on AGP */ 513 rdev->wb.enabled = false; 514 } else if (rdev->family < CHIP_R300) { 515 /* often unreliable on pre-r300 */ 516 rdev->wb.enabled = false; 517 } else { 518 rdev->wb.enabled = true; 519 /* event_write fences are only available on r600+ */ 520 if (rdev->family >= CHIP_R600) { 521 rdev->wb.use_event = true; 522 } 523 } 524 } 525 /* always use writeback/events on NI, APUs */ 526 if (rdev->family >= CHIP_PALM) { 527 rdev->wb.enabled = true; 528 rdev->wb.use_event = true; 529 } 530 531 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 532 533 return 0; 534 } 535 536 /** 537 * radeon_vram_location - try to find VRAM location 538 * @rdev: radeon device structure holding all necessary informations 539 * @mc: memory controller structure holding memory informations 540 * @base: base address at which to put VRAM 541 * 542 * Function will place try to place VRAM at base address provided 543 * as parameter (which is so far either PCI aperture address or 544 * for IGP TOM base address). 545 * 546 * If there is not enough space to fit the unvisible VRAM in the 32bits 547 * address space then we limit the VRAM size to the aperture. 548 * 549 * If we are using AGP and if the AGP aperture doesn't allow us to have 550 * room for all the VRAM than we restrict the VRAM to the PCI aperture 551 * size and print a warning. 552 * 553 * This function will never fails, worst case are limiting VRAM. 554 * 555 * Note: GTT start, end, size should be initialized before calling this 556 * function on AGP platform. 557 * 558 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 559 * this shouldn't be a problem as we are using the PCI aperture as a reference. 560 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 561 * not IGP. 562 * 563 * Note: we use mc_vram_size as on some board we need to program the mc to 564 * cover the whole aperture even if VRAM size is inferior to aperture size 565 * Novell bug 204882 + along with lots of ubuntu ones 566 * 567 * Note: when limiting vram it's safe to overwritte real_vram_size because 568 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 569 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 570 * ones) 571 * 572 * Note: IGP TOM addr should be the same as the aperture addr, we don't 573 * explicitly check for that thought. 574 * 575 * FIXME: when reducing VRAM size align new size on power of 2. 576 */ 577 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 578 { 579 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 580 581 mc->vram_start = base; 582 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 583 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 584 mc->real_vram_size = mc->aper_size; 585 mc->mc_vram_size = mc->aper_size; 586 } 587 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 588 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 589 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 590 mc->real_vram_size = mc->aper_size; 591 mc->mc_vram_size = mc->aper_size; 592 } 593 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 594 if (limit && limit < mc->real_vram_size) 595 mc->real_vram_size = limit; 596 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", 597 mc->mc_vram_size >> 20, mc->vram_start, 598 mc->vram_end, mc->real_vram_size >> 20); 599 } 600 601 /** 602 * radeon_gtt_location - try to find GTT location 603 * @rdev: radeon device structure holding all necessary informations 604 * @mc: memory controller structure holding memory informations 605 * 606 * Function will place try to place GTT before or after VRAM. 607 * 608 * If GTT size is bigger than space left then we ajust GTT size. 609 * Thus function will never fails. 610 * 611 * FIXME: when reducing GTT size align new size on power of 2. 612 */ 613 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 614 { 615 u64 size_af, size_bf; 616 617 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 618 size_bf = mc->vram_start & ~mc->gtt_base_align; 619 if (size_bf > size_af) { 620 if (mc->gtt_size > size_bf) { 621 dev_warn(rdev->dev, "limiting GTT\n"); 622 mc->gtt_size = size_bf; 623 } 624 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 625 } else { 626 if (mc->gtt_size > size_af) { 627 dev_warn(rdev->dev, "limiting GTT\n"); 628 mc->gtt_size = size_af; 629 } 630 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 631 } 632 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 633 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", 634 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 635 } 636 637 /* 638 * GPU helpers function. 639 */ 640 641 /** 642 * radeon_device_is_virtual - check if we are running is a virtual environment 643 * 644 * Check if the asic has been passed through to a VM (all asics). 645 * Used at driver startup. 646 * Returns true if virtual or false if not. 647 */ 648 bool radeon_device_is_virtual(void) 649 { 650 #ifdef CONFIG_X86 651 return (cpu_ecxfeature & CPUIDECX_HV); 652 #else 653 return false; 654 #endif 655 } 656 657 /** 658 * radeon_card_posted - check if the hw has already been initialized 659 * 660 * @rdev: radeon_device pointer 661 * 662 * Check if the asic has been initialized (all asics). 663 * Used at driver startup. 664 * Returns true if initialized or false if not. 665 */ 666 bool radeon_card_posted(struct radeon_device *rdev) 667 { 668 uint32_t reg; 669 670 /* for pass through, always force asic_init for CI */ 671 if (rdev->family >= CHIP_BONAIRE && 672 radeon_device_is_virtual()) 673 return false; 674 675 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 676 #ifdef notyet 677 if (efi_enabled(EFI_BOOT) && 678 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 679 (rdev->family < CHIP_R600)) 680 return false; 681 #endif 682 683 if (ASIC_IS_NODCE(rdev)) 684 goto check_memsize; 685 686 /* first check CRTCs */ 687 if (ASIC_IS_DCE4(rdev)) { 688 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 689 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 690 if (rdev->num_crtc >= 4) { 691 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 692 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 693 } 694 if (rdev->num_crtc >= 6) { 695 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 696 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 697 } 698 if (reg & EVERGREEN_CRTC_MASTER_EN) 699 return true; 700 } else if (ASIC_IS_AVIVO(rdev)) { 701 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 702 RREG32(AVIVO_D2CRTC_CONTROL); 703 if (reg & AVIVO_CRTC_EN) { 704 return true; 705 } 706 } else { 707 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 708 RREG32(RADEON_CRTC2_GEN_CNTL); 709 if (reg & RADEON_CRTC_EN) { 710 return true; 711 } 712 } 713 714 check_memsize: 715 /* then check MEM_SIZE, in case the crtcs are off */ 716 if (rdev->family >= CHIP_R600) 717 reg = RREG32(R600_CONFIG_MEMSIZE); 718 else 719 reg = RREG32(RADEON_CONFIG_MEMSIZE); 720 721 if (reg) 722 return true; 723 724 return false; 725 726 } 727 728 /** 729 * radeon_update_bandwidth_info - update display bandwidth params 730 * 731 * @rdev: radeon_device pointer 732 * 733 * Used when sclk/mclk are switched or display modes are set. 734 * params are used to calculate display watermarks (all asics) 735 */ 736 void radeon_update_bandwidth_info(struct radeon_device *rdev) 737 { 738 fixed20_12 a; 739 u32 sclk = rdev->pm.current_sclk; 740 u32 mclk = rdev->pm.current_mclk; 741 742 /* sclk/mclk in Mhz */ 743 a.full = dfixed_const(100); 744 rdev->pm.sclk.full = dfixed_const(sclk); 745 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 746 rdev->pm.mclk.full = dfixed_const(mclk); 747 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 748 749 if (rdev->flags & RADEON_IS_IGP) { 750 a.full = dfixed_const(16); 751 /* core_bandwidth = sclk(Mhz) * 16 */ 752 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 753 } 754 } 755 756 /** 757 * radeon_boot_test_post_card - check and possibly initialize the hw 758 * 759 * @rdev: radeon_device pointer 760 * 761 * Check if the asic is initialized and if not, attempt to initialize 762 * it (all asics). 763 * Returns true if initialized or false if not. 764 */ 765 bool radeon_boot_test_post_card(struct radeon_device *rdev) 766 { 767 if (radeon_card_posted(rdev)) 768 return true; 769 770 if (rdev->bios) { 771 DRM_INFO("GPU not posted. posting now...\n"); 772 if (rdev->is_atom_bios) 773 atom_asic_init(rdev->mode_info.atom_context); 774 else 775 radeon_combios_asic_init(rdev->ddev); 776 return true; 777 } else { 778 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 779 return false; 780 } 781 } 782 783 /** 784 * radeon_dummy_page_init - init dummy page used by the driver 785 * 786 * @rdev: radeon_device pointer 787 * 788 * Allocate the dummy page used by the driver (all asics). 789 * This dummy page is used by the driver as a filler for gart entries 790 * when pages are taken out of the GART 791 * Returns 0 on sucess, -ENOMEM on failure. 792 */ 793 int radeon_dummy_page_init(struct radeon_device *rdev) 794 { 795 if (rdev->dummy_page.dmah) 796 return 0; 797 rdev->dummy_page.dmah = drm_dmamem_alloc(rdev->dmat, PAGE_SIZE, PAGE_SIZE, 1, 798 PAGE_SIZE, 0, BUS_DMA_WAITOK); 799 if (!rdev->dummy_page.dmah) 800 return -ENOMEM; 801 rdev->dummy_page.addr = (bus_addr_t)rdev->dummy_page.dmah->map->dm_segs[0].ds_addr; 802 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 803 RADEON_GART_PAGE_DUMMY); 804 return 0; 805 } 806 807 /** 808 * radeon_dummy_page_fini - free dummy page used by the driver 809 * 810 * @rdev: radeon_device pointer 811 * 812 * Frees the dummy page used by the driver (all asics). 813 */ 814 void radeon_dummy_page_fini(struct radeon_device *rdev) 815 { 816 if (rdev->dummy_page.dmah == NULL) 817 return; 818 819 drm_dmamem_free(rdev->dmat, rdev->dummy_page.dmah); 820 rdev->dummy_page.dmah = NULL; 821 rdev->dummy_page.addr = 0; 822 } 823 824 825 /* ATOM accessor methods */ 826 /* 827 * ATOM is an interpreted byte code stored in tables in the vbios. The 828 * driver registers callbacks to access registers and the interpreter 829 * in the driver parses the tables and executes then to program specific 830 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 831 * atombios.h, and atom.c 832 */ 833 834 /** 835 * cail_pll_read - read PLL register 836 * 837 * @info: atom card_info pointer 838 * @reg: PLL register offset 839 * 840 * Provides a PLL register accessor for the atom interpreter (r4xx+). 841 * Returns the value of the PLL register. 842 */ 843 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 844 { 845 struct radeon_device *rdev = info->dev->dev_private; 846 uint32_t r; 847 848 r = rdev->pll_rreg(rdev, reg); 849 return r; 850 } 851 852 /** 853 * cail_pll_write - write PLL register 854 * 855 * @info: atom card_info pointer 856 * @reg: PLL register offset 857 * @val: value to write to the pll register 858 * 859 * Provides a PLL register accessor for the atom interpreter (r4xx+). 860 */ 861 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 862 { 863 struct radeon_device *rdev = info->dev->dev_private; 864 865 rdev->pll_wreg(rdev, reg, val); 866 } 867 868 /** 869 * cail_mc_read - read MC (Memory Controller) register 870 * 871 * @info: atom card_info pointer 872 * @reg: MC register offset 873 * 874 * Provides an MC register accessor for the atom interpreter (r4xx+). 875 * Returns the value of the MC register. 876 */ 877 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 878 { 879 struct radeon_device *rdev = info->dev->dev_private; 880 uint32_t r; 881 882 r = rdev->mc_rreg(rdev, reg); 883 return r; 884 } 885 886 /** 887 * cail_mc_write - write MC (Memory Controller) register 888 * 889 * @info: atom card_info pointer 890 * @reg: MC register offset 891 * @val: value to write to the pll register 892 * 893 * Provides a MC register accessor for the atom interpreter (r4xx+). 894 */ 895 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 896 { 897 struct radeon_device *rdev = info->dev->dev_private; 898 899 rdev->mc_wreg(rdev, reg, val); 900 } 901 902 /** 903 * cail_reg_write - write MMIO register 904 * 905 * @info: atom card_info pointer 906 * @reg: MMIO register offset 907 * @val: value to write to the pll register 908 * 909 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 910 */ 911 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 912 { 913 struct radeon_device *rdev = info->dev->dev_private; 914 915 WREG32(reg*4, val); 916 } 917 918 /** 919 * cail_reg_read - read MMIO register 920 * 921 * @info: atom card_info pointer 922 * @reg: MMIO register offset 923 * 924 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 925 * Returns the value of the MMIO register. 926 */ 927 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 928 { 929 struct radeon_device *rdev = info->dev->dev_private; 930 uint32_t r; 931 932 r = RREG32(reg*4); 933 return r; 934 } 935 936 /** 937 * cail_ioreg_write - write IO register 938 * 939 * @info: atom card_info pointer 940 * @reg: IO register offset 941 * @val: value to write to the pll register 942 * 943 * Provides a IO register accessor for the atom interpreter (r4xx+). 944 */ 945 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 946 { 947 struct radeon_device *rdev = info->dev->dev_private; 948 949 WREG32_IO(reg*4, val); 950 } 951 952 /** 953 * cail_ioreg_read - read IO register 954 * 955 * @info: atom card_info pointer 956 * @reg: IO register offset 957 * 958 * Provides an IO register accessor for the atom interpreter (r4xx+). 959 * Returns the value of the IO register. 960 */ 961 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 962 { 963 struct radeon_device *rdev = info->dev->dev_private; 964 uint32_t r; 965 966 r = RREG32_IO(reg*4); 967 return r; 968 } 969 970 /** 971 * radeon_atombios_init - init the driver info and callbacks for atombios 972 * 973 * @rdev: radeon_device pointer 974 * 975 * Initializes the driver info and register access callbacks for the 976 * ATOM interpreter (r4xx+). 977 * Returns 0 on sucess, -ENOMEM on failure. 978 * Called at driver startup. 979 */ 980 int radeon_atombios_init(struct radeon_device *rdev) 981 { 982 struct card_info *atom_card_info = 983 kzalloc(sizeof(struct card_info), GFP_KERNEL); 984 985 if (!atom_card_info) 986 return -ENOMEM; 987 988 rdev->mode_info.atom_card_info = atom_card_info; 989 atom_card_info->dev = rdev->ddev; 990 atom_card_info->reg_read = cail_reg_read; 991 atom_card_info->reg_write = cail_reg_write; 992 /* needed for iio ops */ 993 if (rdev->rio_mem_size > 0) { 994 atom_card_info->ioreg_read = cail_ioreg_read; 995 atom_card_info->ioreg_write = cail_ioreg_write; 996 } else { 997 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 998 atom_card_info->ioreg_read = cail_reg_read; 999 atom_card_info->ioreg_write = cail_reg_write; 1000 } 1001 atom_card_info->mc_read = cail_mc_read; 1002 atom_card_info->mc_write = cail_mc_write; 1003 atom_card_info->pll_read = cail_pll_read; 1004 atom_card_info->pll_write = cail_pll_write; 1005 1006 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 1007 if (!rdev->mode_info.atom_context) { 1008 radeon_atombios_fini(rdev); 1009 return -ENOMEM; 1010 } 1011 1012 rw_init(&rdev->mode_info.atom_context->mutex, "atomcon"); 1013 rw_init(&rdev->mode_info.atom_context->scratch_mutex, "atomscr"); 1014 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 1015 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 1016 return 0; 1017 } 1018 1019 /** 1020 * radeon_atombios_fini - free the driver info and callbacks for atombios 1021 * 1022 * @rdev: radeon_device pointer 1023 * 1024 * Frees the driver info and register access callbacks for the ATOM 1025 * interpreter (r4xx+). 1026 * Called at driver shutdown. 1027 */ 1028 void radeon_atombios_fini(struct radeon_device *rdev) 1029 { 1030 if (rdev->mode_info.atom_context) { 1031 kfree(rdev->mode_info.atom_context->scratch); 1032 } 1033 kfree(rdev->mode_info.atom_context); 1034 rdev->mode_info.atom_context = NULL; 1035 kfree(rdev->mode_info.atom_card_info); 1036 rdev->mode_info.atom_card_info = NULL; 1037 } 1038 1039 /* COMBIOS */ 1040 /* 1041 * COMBIOS is the bios format prior to ATOM. It provides 1042 * command tables similar to ATOM, but doesn't have a unified 1043 * parser. See radeon_combios.c 1044 */ 1045 1046 /** 1047 * radeon_combios_init - init the driver info for combios 1048 * 1049 * @rdev: radeon_device pointer 1050 * 1051 * Initializes the driver info for combios (r1xx-r3xx). 1052 * Returns 0 on sucess. 1053 * Called at driver startup. 1054 */ 1055 int radeon_combios_init(struct radeon_device *rdev) 1056 { 1057 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1058 return 0; 1059 } 1060 1061 /** 1062 * radeon_combios_fini - free the driver info for combios 1063 * 1064 * @rdev: radeon_device pointer 1065 * 1066 * Frees the driver info for combios (r1xx-r3xx). 1067 * Called at driver shutdown. 1068 */ 1069 void radeon_combios_fini(struct radeon_device *rdev) 1070 { 1071 } 1072 1073 /* if we get transitioned to only one device, take VGA back */ 1074 /** 1075 * radeon_vga_set_decode - enable/disable vga decode 1076 * 1077 * @cookie: radeon_device pointer 1078 * @state: enable/disable vga decode 1079 * 1080 * Enable/disable vga decode (all asics). 1081 * Returns VGA resource flags. 1082 */ 1083 static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1084 { 1085 STUB(); 1086 return -ENOSYS; 1087 #ifdef notyet 1088 struct radeon_device *rdev = cookie; 1089 radeon_vga_set_state(rdev, state); 1090 if (state) 1091 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1092 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1093 else 1094 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1095 #endif 1096 } 1097 1098 /** 1099 * radeon_check_pot_argument - check that argument is a power of two 1100 * 1101 * @arg: value to check 1102 * 1103 * Validates that a certain argument is a power of two (all asics). 1104 * Returns true if argument is valid. 1105 */ 1106 static bool radeon_check_pot_argument(int arg) 1107 { 1108 return (arg & (arg - 1)) == 0; 1109 } 1110 1111 /** 1112 * Determine a sensible default GART size according to ASIC family. 1113 * 1114 * @family ASIC family name 1115 */ 1116 static int radeon_gart_size_auto(enum radeon_family family) 1117 { 1118 /* default to a larger gart size on newer asics */ 1119 if (family >= CHIP_TAHITI) 1120 return 2048; 1121 else if (family >= CHIP_RV770) 1122 return 1024; 1123 else 1124 return 512; 1125 } 1126 1127 /** 1128 * radeon_check_arguments - validate module params 1129 * 1130 * @rdev: radeon_device pointer 1131 * 1132 * Validates certain module parameters and updates 1133 * the associated values used by the driver (all asics). 1134 */ 1135 static void radeon_check_arguments(struct radeon_device *rdev) 1136 { 1137 /* vramlimit must be a power of two */ 1138 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1139 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1140 radeon_vram_limit); 1141 radeon_vram_limit = 0; 1142 } 1143 1144 if (radeon_gart_size == -1) { 1145 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1146 } 1147 /* gtt size must be power of two and greater or equal to 32M */ 1148 if (radeon_gart_size < 32) { 1149 dev_warn(rdev->dev, "gart size (%d) too small\n", 1150 radeon_gart_size); 1151 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1152 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1153 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1154 radeon_gart_size); 1155 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1156 } 1157 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1158 1159 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1160 switch (radeon_agpmode) { 1161 case -1: 1162 case 0: 1163 case 1: 1164 case 2: 1165 case 4: 1166 case 8: 1167 break; 1168 default: 1169 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1170 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1171 radeon_agpmode = 0; 1172 break; 1173 } 1174 1175 if (!radeon_check_pot_argument(radeon_vm_size)) { 1176 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1177 radeon_vm_size); 1178 radeon_vm_size = 4; 1179 } 1180 1181 if (radeon_vm_size < 1) { 1182 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n", 1183 radeon_vm_size); 1184 radeon_vm_size = 4; 1185 } 1186 1187 /* 1188 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1189 */ 1190 if (radeon_vm_size > 1024) { 1191 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1192 radeon_vm_size); 1193 radeon_vm_size = 4; 1194 } 1195 1196 /* defines number of bits in page table versus page directory, 1197 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1198 * page table and the remaining bits are in the page directory */ 1199 if (radeon_vm_block_size == -1) { 1200 1201 /* Total bits covered by PD + PTs */ 1202 unsigned bits = ilog2(radeon_vm_size) + 18; 1203 1204 /* Make sure the PD is 4K in size up to 8GB address space. 1205 Above that split equal between PD and PTs */ 1206 if (radeon_vm_size <= 8) 1207 radeon_vm_block_size = bits - 9; 1208 else 1209 radeon_vm_block_size = (bits + 3) / 2; 1210 1211 } else if (radeon_vm_block_size < 9) { 1212 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1213 radeon_vm_block_size); 1214 radeon_vm_block_size = 9; 1215 } 1216 1217 if (radeon_vm_block_size > 24 || 1218 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1219 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1220 radeon_vm_block_size); 1221 radeon_vm_block_size = 9; 1222 } 1223 } 1224 1225 /** 1226 * radeon_switcheroo_set_state - set switcheroo state 1227 * 1228 * @pdev: pci dev pointer 1229 * @state: vga_switcheroo state 1230 * 1231 * Callback for the switcheroo driver. Suspends or resumes the 1232 * the asics before or after it is powered up using ACPI methods. 1233 */ 1234 #ifdef notyet 1235 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1236 { 1237 struct drm_device *dev = pci_get_drvdata(pdev); 1238 1239 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1240 return; 1241 1242 if (state == VGA_SWITCHEROO_ON) { 1243 pr_info("radeon: switched on\n"); 1244 /* don't suspend or resume card normally */ 1245 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1246 1247 radeon_resume_kms(dev, true, true); 1248 1249 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1250 drm_kms_helper_poll_enable(dev); 1251 } else { 1252 pr_info("radeon: switched off\n"); 1253 drm_kms_helper_poll_disable(dev); 1254 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1255 radeon_suspend_kms(dev, true, true, false); 1256 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1257 } 1258 } 1259 1260 /** 1261 * radeon_switcheroo_can_switch - see if switcheroo state can change 1262 * 1263 * @pdev: pci dev pointer 1264 * 1265 * Callback for the switcheroo driver. Check of the switcheroo 1266 * state can be changed. 1267 * Returns true if the state can be changed, false if not. 1268 */ 1269 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1270 { 1271 struct drm_device *dev = pci_get_drvdata(pdev); 1272 1273 /* 1274 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1275 * locking inversion with the driver load path. And the access here is 1276 * completely racy anyway. So don't bother with locking for now. 1277 */ 1278 return atomic_read(&dev->open_count) == 0; 1279 } 1280 1281 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1282 .set_gpu_state = radeon_switcheroo_set_state, 1283 .reprobe = NULL, 1284 .can_switch = radeon_switcheroo_can_switch, 1285 }; 1286 #endif 1287 1288 /** 1289 * radeon_device_init - initialize the driver 1290 * 1291 * @rdev: radeon_device pointer 1292 * @pdev: drm dev pointer 1293 * @pdev: pci dev pointer 1294 * @flags: driver flags 1295 * 1296 * Initializes the driver info and hw (all asics). 1297 * Returns 0 for success or an error on failure. 1298 * Called at driver startup. 1299 */ 1300 int radeon_device_init(struct radeon_device *rdev, 1301 struct drm_device *ddev, 1302 struct pci_dev *pdev, 1303 uint32_t flags) 1304 { 1305 int r, i; 1306 int dma_bits; 1307 bool runtime = false; 1308 1309 rdev->shutdown = false; 1310 rdev->ddev = ddev; 1311 rdev->pdev = pdev; 1312 rdev->flags = flags; 1313 rdev->family = flags & RADEON_FAMILY_MASK; 1314 rdev->is_atom_bios = false; 1315 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1316 rdev->mc.gtt_size = 512 * 1024 * 1024; 1317 rdev->accel_working = false; 1318 /* set up ring ids */ 1319 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1320 rdev->ring[i].idx = i; 1321 } 1322 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS); 1323 1324 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", 1325 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1326 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); 1327 printf("%s: %s\n", rdev->self.dv_xname, radeon_family_name[rdev->family]); 1328 1329 /* mutex initialization are all done here so we 1330 * can recall function without having locking issues */ 1331 rw_init(&rdev->ring_lock, "ring"); 1332 rw_init(&rdev->dc_hw_i2c_mutex, "dciic"); 1333 atomic_set(&rdev->ih.lock, 0); 1334 rw_init(&rdev->gem.mutex, "gem"); 1335 rw_init(&rdev->pm.mutex, "pm"); 1336 rw_init(&rdev->gpu_clock_mutex, "gpuclk"); 1337 rw_init(&rdev->srbm_mutex, "srbm"); 1338 rw_init(&rdev->pm.mclk_lock, "mclk"); 1339 rw_init(&rdev->exclusive_lock, "rdnexc"); 1340 init_waitqueue_head(&rdev->irq.vblank_queue); 1341 r = radeon_gem_init(rdev); 1342 if (r) 1343 return r; 1344 1345 radeon_check_arguments(rdev); 1346 /* Adjust VM size here. 1347 * Max GPUVM size for cayman+ is 40 bits. 1348 */ 1349 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1350 1351 /* Set asic functions */ 1352 r = radeon_asic_init(rdev); 1353 if (r) 1354 return r; 1355 1356 /* all of the newer IGP chips have an internal gart 1357 * However some rs4xx report as AGP, so remove that here. 1358 */ 1359 if ((rdev->family >= CHIP_RS400) && 1360 (rdev->flags & RADEON_IS_IGP)) { 1361 rdev->flags &= ~RADEON_IS_AGP; 1362 } 1363 1364 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1365 radeon_agp_disable(rdev); 1366 } 1367 1368 /* Set the internal MC address mask 1369 * This is the max address of the GPU's 1370 * internal address space. 1371 */ 1372 if (rdev->family >= CHIP_CAYMAN) 1373 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1374 else if (rdev->family >= CHIP_CEDAR) 1375 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1376 else 1377 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1378 1379 /* set DMA mask. 1380 * PCIE - can handle 40-bits. 1381 * IGP - can handle 40-bits 1382 * AGP - generally dma32 is safest 1383 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1384 */ 1385 dma_bits = 40; 1386 if (rdev->flags & RADEON_IS_AGP) 1387 dma_bits = 32; 1388 if ((rdev->flags & RADEON_IS_PCI) && 1389 (rdev->family <= CHIP_RS740)) 1390 dma_bits = 32; 1391 #ifdef CONFIG_PPC64 1392 if (rdev->family == CHIP_CEDAR) 1393 dma_bits = 32; 1394 #endif 1395 1396 r = dma_set_mask_and_coherent(&rdev->pdev->dev, DMA_BIT_MASK(dma_bits)); 1397 if (r) { 1398 pr_warn("radeon: No suitable DMA available\n"); 1399 return r; 1400 } 1401 rdev->need_swiotlb = drm_need_swiotlb(dma_bits); 1402 1403 /* Registers mapping */ 1404 /* TODO: block userspace mapping of io register */ 1405 mtx_init(&rdev->mmio_idx_lock, IPL_TTY); 1406 mtx_init(&rdev->smc_idx_lock, IPL_TTY); 1407 mtx_init(&rdev->pll_idx_lock, IPL_TTY); 1408 mtx_init(&rdev->mc_idx_lock, IPL_TTY); 1409 mtx_init(&rdev->pcie_idx_lock, IPL_TTY); 1410 mtx_init(&rdev->pciep_idx_lock, IPL_TTY); 1411 mtx_init(&rdev->pif_idx_lock, IPL_TTY); 1412 mtx_init(&rdev->cg_idx_lock, IPL_TTY); 1413 mtx_init(&rdev->uvd_idx_lock, IPL_TTY); 1414 mtx_init(&rdev->rcu_idx_lock, IPL_TTY); 1415 mtx_init(&rdev->didt_idx_lock, IPL_TTY); 1416 mtx_init(&rdev->end_idx_lock, IPL_TTY); 1417 #ifdef __linux__ 1418 if (rdev->family >= CHIP_BONAIRE) { 1419 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); 1420 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); 1421 } else { 1422 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1423 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1424 } 1425 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1426 if (rdev->rmmio == NULL) 1427 return -ENOMEM; 1428 #endif 1429 1430 /* doorbell bar mapping */ 1431 if (rdev->family >= CHIP_BONAIRE) 1432 radeon_doorbell_init(rdev); 1433 1434 /* io port mapping */ 1435 #ifdef linux 1436 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1437 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1438 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1439 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1440 break; 1441 } 1442 } 1443 if (rdev->rio_mem == NULL) 1444 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1445 #endif 1446 1447 if (rdev->flags & RADEON_IS_PX) 1448 radeon_device_handle_px_quirks(rdev); 1449 1450 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1451 /* this will fail for cards that aren't VGA class devices, just 1452 * ignore it */ 1453 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1454 1455 if (rdev->flags & RADEON_IS_PX) 1456 runtime = true; 1457 #ifdef notyet 1458 if (!pci_is_thunderbolt_attached(rdev->pdev)) 1459 vga_switcheroo_register_client(rdev->pdev, 1460 &radeon_switcheroo_ops, runtime); 1461 #endif 1462 if (runtime) 1463 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1464 1465 r = radeon_init(rdev); 1466 if (r) 1467 goto failed; 1468 1469 r = radeon_gem_debugfs_init(rdev); 1470 if (r) { 1471 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1472 } 1473 1474 r = radeon_mst_debugfs_init(rdev); 1475 if (r) { 1476 DRM_ERROR("registering mst debugfs failed (%d).\n", r); 1477 } 1478 1479 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1480 /* Acceleration not working on AGP card try again 1481 * with fallback to PCI or PCIE GART 1482 */ 1483 radeon_asic_reset(rdev); 1484 radeon_fini(rdev); 1485 radeon_agp_disable(rdev); 1486 r = radeon_init(rdev); 1487 if (r) 1488 goto failed; 1489 } 1490 1491 r = radeon_ib_ring_tests(rdev); 1492 if (r) 1493 DRM_ERROR("ib ring test failed (%d).\n", r); 1494 1495 /* 1496 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1497 * after the CP ring have chew one packet at least. Hence here we stop 1498 * and restart DPM after the radeon_ib_ring_tests(). 1499 */ 1500 if (rdev->pm.dpm_enabled && 1501 (rdev->pm.pm_method == PM_METHOD_DPM) && 1502 (rdev->family == CHIP_TURKS) && 1503 (rdev->flags & RADEON_IS_MOBILITY)) { 1504 mutex_lock(&rdev->pm.mutex); 1505 radeon_dpm_disable(rdev); 1506 radeon_dpm_enable(rdev); 1507 mutex_unlock(&rdev->pm.mutex); 1508 } 1509 1510 if ((radeon_testing & 1)) { 1511 if (rdev->accel_working) 1512 radeon_test_moves(rdev); 1513 else 1514 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1515 } 1516 if ((radeon_testing & 2)) { 1517 if (rdev->accel_working) 1518 radeon_test_syncing(rdev); 1519 else 1520 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1521 } 1522 if (radeon_benchmarking) { 1523 if (rdev->accel_working) 1524 radeon_benchmark(rdev, radeon_benchmarking); 1525 else 1526 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1527 } 1528 return 0; 1529 1530 failed: 1531 /* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */ 1532 if (radeon_is_px(ddev)) 1533 pm_runtime_put_noidle(ddev->dev); 1534 if (runtime) 1535 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1536 return r; 1537 } 1538 1539 /** 1540 * radeon_device_fini - tear down the driver 1541 * 1542 * @rdev: radeon_device pointer 1543 * 1544 * Tear down the driver info (all asics). 1545 * Called at driver shutdown. 1546 */ 1547 void radeon_device_fini(struct radeon_device *rdev) 1548 { 1549 DRM_INFO("radeon: finishing device.\n"); 1550 rdev->shutdown = true; 1551 /* evict vram memory */ 1552 radeon_bo_evict_vram(rdev); 1553 radeon_fini(rdev); 1554 if (!pci_is_thunderbolt_attached(rdev->pdev)) 1555 vga_switcheroo_unregister_client(rdev->pdev); 1556 if (rdev->flags & RADEON_IS_PX) 1557 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1558 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1559 #ifdef __linux__ 1560 if (rdev->rio_mem) 1561 pci_iounmap(rdev->pdev, rdev->rio_mem); 1562 rdev->rio_mem = NULL; 1563 iounmap(rdev->rmmio); 1564 rdev->rmmio = NULL; 1565 #else 1566 if (rdev->rio_mem_size > 0) 1567 bus_space_unmap(rdev->iot, rdev->rio_mem, rdev->rio_mem_size); 1568 rdev->rio_mem_size = 0; 1569 1570 if (rdev->rmmio_size > 0) 1571 bus_space_unmap(rdev->memt, rdev->rmmio_bsh, rdev->rmmio_size); 1572 rdev->rmmio_size = 0; 1573 #endif 1574 if (rdev->family >= CHIP_BONAIRE) 1575 radeon_doorbell_fini(rdev); 1576 } 1577 1578 1579 /* 1580 * Suspend & resume. 1581 */ 1582 /** 1583 * radeon_suspend_kms - initiate device suspend 1584 * 1585 * @pdev: drm dev pointer 1586 * @state: suspend state 1587 * 1588 * Puts the hw in the suspend state (all asics). 1589 * Returns 0 for success or an error on failure. 1590 * Called at driver suspend. 1591 */ 1592 int radeon_suspend_kms(struct drm_device *dev, bool suspend, 1593 bool fbcon, bool freeze) 1594 { 1595 struct radeon_device *rdev; 1596 struct drm_crtc *crtc; 1597 struct drm_connector *connector; 1598 int i, r; 1599 1600 if (dev == NULL || dev->dev_private == NULL) { 1601 return -ENODEV; 1602 } 1603 1604 rdev = dev->dev_private; 1605 if (rdev->shutdown) 1606 return 0; 1607 1608 #ifdef notyet 1609 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1610 return 0; 1611 #endif 1612 1613 drm_kms_helper_poll_disable(dev); 1614 1615 drm_modeset_lock_all(dev); 1616 /* turn off display hw */ 1617 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1618 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1619 } 1620 drm_modeset_unlock_all(dev); 1621 1622 /* unpin the front buffers and cursors */ 1623 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1624 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1625 struct drm_framebuffer *fb = crtc->primary->fb; 1626 struct radeon_bo *robj; 1627 1628 if (radeon_crtc->cursor_bo) { 1629 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1630 r = radeon_bo_reserve(robj, false); 1631 if (r == 0) { 1632 radeon_bo_unpin(robj); 1633 radeon_bo_unreserve(robj); 1634 } 1635 } 1636 1637 if (fb == NULL || fb->obj[0] == NULL) { 1638 continue; 1639 } 1640 robj = gem_to_radeon_bo(fb->obj[0]); 1641 /* don't unpin kernel fb objects */ 1642 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1643 r = radeon_bo_reserve(robj, false); 1644 if (r == 0) { 1645 radeon_bo_unpin(robj); 1646 radeon_bo_unreserve(robj); 1647 } 1648 } 1649 } 1650 /* evict vram memory */ 1651 radeon_bo_evict_vram(rdev); 1652 1653 /* wait for gpu to finish processing current batch */ 1654 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1655 r = radeon_fence_wait_empty(rdev, i); 1656 if (r) { 1657 /* delay GPU reset to resume */ 1658 radeon_fence_driver_force_completion(rdev, i); 1659 } 1660 } 1661 1662 radeon_save_bios_scratch_regs(rdev); 1663 1664 radeon_suspend(rdev); 1665 radeon_hpd_fini(rdev); 1666 /* evict remaining vram memory 1667 * This second call to evict vram is to evict the gart page table 1668 * using the CPU. 1669 */ 1670 radeon_bo_evict_vram(rdev); 1671 1672 radeon_agp_suspend(rdev); 1673 1674 pci_save_state(dev->pdev); 1675 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) { 1676 rdev->asic->asic_reset(rdev, true); 1677 pci_restore_state(dev->pdev); 1678 } else if (suspend) { 1679 /* Shut down the device */ 1680 pci_disable_device(dev->pdev); 1681 pci_set_power_state(dev->pdev, PCI_D3hot); 1682 } 1683 1684 if (fbcon) { 1685 console_lock(); 1686 radeon_fbdev_set_suspend(rdev, 1); 1687 console_unlock(); 1688 } 1689 return 0; 1690 } 1691 1692 /** 1693 * radeon_resume_kms - initiate device resume 1694 * 1695 * @pdev: drm dev pointer 1696 * 1697 * Bring the hw back to operating state (all asics). 1698 * Returns 0 for success or an error on failure. 1699 * Called at driver resume. 1700 */ 1701 int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1702 { 1703 struct drm_connector *connector; 1704 struct radeon_device *rdev = dev->dev_private; 1705 struct drm_crtc *crtc; 1706 int r; 1707 1708 #ifdef notyet 1709 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1710 return 0; 1711 #endif 1712 1713 if (fbcon) { 1714 console_lock(); 1715 } 1716 if (resume) { 1717 pci_set_power_state(dev->pdev, PCI_D0); 1718 pci_restore_state(dev->pdev); 1719 if (pci_enable_device(dev->pdev)) { 1720 if (fbcon) 1721 console_unlock(); 1722 return -1; 1723 } 1724 } 1725 /* resume AGP if in use */ 1726 radeon_agp_resume(rdev); 1727 radeon_resume(rdev); 1728 1729 r = radeon_ib_ring_tests(rdev); 1730 if (r) 1731 DRM_ERROR("ib ring test failed (%d).\n", r); 1732 1733 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1734 /* do dpm late init */ 1735 r = radeon_pm_late_init(rdev); 1736 if (r) { 1737 rdev->pm.dpm_enabled = false; 1738 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1739 } 1740 } else { 1741 /* resume old pm late */ 1742 radeon_pm_resume(rdev); 1743 } 1744 1745 radeon_restore_bios_scratch_regs(rdev); 1746 1747 /* pin cursors */ 1748 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1749 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1750 1751 if (radeon_crtc->cursor_bo) { 1752 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1753 r = radeon_bo_reserve(robj, false); 1754 if (r == 0) { 1755 /* Only 27 bit offset for legacy cursor */ 1756 r = radeon_bo_pin_restricted(robj, 1757 RADEON_GEM_DOMAIN_VRAM, 1758 ASIC_IS_AVIVO(rdev) ? 1759 0 : 1 << 27, 1760 &radeon_crtc->cursor_addr); 1761 if (r != 0) 1762 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1763 radeon_bo_unreserve(robj); 1764 } 1765 } 1766 } 1767 1768 /* init dig PHYs, disp eng pll */ 1769 if (rdev->is_atom_bios) { 1770 radeon_atom_encoder_init(rdev); 1771 radeon_atom_disp_eng_pll_init(rdev); 1772 /* turn on the BL */ 1773 if (rdev->mode_info.bl_encoder) { 1774 u8 bl_level = radeon_get_backlight_level(rdev, 1775 rdev->mode_info.bl_encoder); 1776 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1777 bl_level); 1778 } 1779 } 1780 /* reset hpd state */ 1781 radeon_hpd_init(rdev); 1782 /* blat the mode back in */ 1783 if (fbcon) { 1784 drm_helper_resume_force_mode(dev); 1785 /* turn on display hw */ 1786 drm_modeset_lock_all(dev); 1787 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1788 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1789 } 1790 drm_modeset_unlock_all(dev); 1791 } 1792 1793 drm_kms_helper_poll_enable(dev); 1794 1795 /* set the power state here in case we are a PX system or headless */ 1796 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1797 radeon_pm_compute_clocks(rdev); 1798 1799 if (fbcon) { 1800 radeon_fbdev_set_suspend(rdev, 0); 1801 console_unlock(); 1802 } 1803 1804 return 0; 1805 } 1806 1807 /** 1808 * radeon_gpu_reset - reset the asic 1809 * 1810 * @rdev: radeon device pointer 1811 * 1812 * Attempt the reset the GPU if it has hung (all asics). 1813 * Returns 0 for success or an error on failure. 1814 */ 1815 int radeon_gpu_reset(struct radeon_device *rdev) 1816 { 1817 unsigned ring_sizes[RADEON_NUM_RINGS]; 1818 uint32_t *ring_data[RADEON_NUM_RINGS]; 1819 1820 bool saved = false; 1821 1822 int i, r; 1823 int resched; 1824 1825 down_write(&rdev->exclusive_lock); 1826 1827 if (!rdev->needs_reset) { 1828 up_write(&rdev->exclusive_lock); 1829 return 0; 1830 } 1831 1832 atomic_inc(&rdev->gpu_reset_counter); 1833 1834 radeon_save_bios_scratch_regs(rdev); 1835 /* block TTM */ 1836 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1837 radeon_suspend(rdev); 1838 radeon_hpd_fini(rdev); 1839 1840 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1841 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 1842 &ring_data[i]); 1843 if (ring_sizes[i]) { 1844 saved = true; 1845 dev_info(rdev->dev, "Saved %d dwords of commands " 1846 "on ring %d.\n", ring_sizes[i], i); 1847 } 1848 } 1849 1850 r = radeon_asic_reset(rdev); 1851 if (!r) { 1852 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 1853 radeon_resume(rdev); 1854 } 1855 1856 radeon_restore_bios_scratch_regs(rdev); 1857 1858 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1859 if (!r && ring_data[i]) { 1860 radeon_ring_restore(rdev, &rdev->ring[i], 1861 ring_sizes[i], ring_data[i]); 1862 } else { 1863 radeon_fence_driver_force_completion(rdev, i); 1864 kfree(ring_data[i]); 1865 } 1866 } 1867 1868 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1869 /* do dpm late init */ 1870 r = radeon_pm_late_init(rdev); 1871 if (r) { 1872 rdev->pm.dpm_enabled = false; 1873 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1874 } 1875 } else { 1876 /* resume old pm late */ 1877 radeon_pm_resume(rdev); 1878 } 1879 1880 /* init dig PHYs, disp eng pll */ 1881 if (rdev->is_atom_bios) { 1882 radeon_atom_encoder_init(rdev); 1883 radeon_atom_disp_eng_pll_init(rdev); 1884 /* turn on the BL */ 1885 if (rdev->mode_info.bl_encoder) { 1886 u8 bl_level = radeon_get_backlight_level(rdev, 1887 rdev->mode_info.bl_encoder); 1888 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1889 bl_level); 1890 } 1891 } 1892 /* reset hpd state */ 1893 radeon_hpd_init(rdev); 1894 1895 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1896 1897 rdev->in_reset = true; 1898 rdev->needs_reset = false; 1899 1900 downgrade_write(&rdev->exclusive_lock); 1901 1902 drm_helper_resume_force_mode(rdev->ddev); 1903 1904 /* set the power state here in case we are a PX system or headless */ 1905 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1906 radeon_pm_compute_clocks(rdev); 1907 1908 if (!r) { 1909 r = radeon_ib_ring_tests(rdev); 1910 if (r && saved) 1911 r = -EAGAIN; 1912 } else { 1913 /* bad news, how to tell it to userspace ? */ 1914 dev_info(rdev->dev, "GPU reset failed\n"); 1915 } 1916 1917 rdev->needs_reset = r == -EAGAIN; 1918 rdev->in_reset = false; 1919 1920 up_read(&rdev->exclusive_lock); 1921 return r; 1922 } 1923 1924 1925 /* 1926 * Debugfs 1927 */ 1928 int radeon_debugfs_add_files(struct radeon_device *rdev, 1929 struct drm_info_list *files, 1930 unsigned nfiles) 1931 { 1932 unsigned i; 1933 1934 for (i = 0; i < rdev->debugfs_count; i++) { 1935 if (rdev->debugfs[i].files == files) { 1936 /* Already registered */ 1937 return 0; 1938 } 1939 } 1940 1941 i = rdev->debugfs_count + 1; 1942 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 1943 DRM_ERROR("Reached maximum number of debugfs components.\n"); 1944 DRM_ERROR("Report so we increase " 1945 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 1946 return -EINVAL; 1947 } 1948 rdev->debugfs[rdev->debugfs_count].files = files; 1949 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 1950 rdev->debugfs_count = i; 1951 #if defined(CONFIG_DEBUG_FS) 1952 drm_debugfs_create_files(files, nfiles, 1953 rdev->ddev->primary->debugfs_root, 1954 rdev->ddev->primary); 1955 #endif 1956 return 0; 1957 } 1958