1 /* $OpenBSD: radeon_combios.c,v 1.8 2015/04/18 14:47:35 jsg Exp $ */ 2 /* 3 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <dev/pci/drm/drmP.h> 29 #include <dev/pci/drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "atom.h" 32 33 /* from radeon_encoder.c */ 34 extern uint32_t 35 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, 36 uint8_t dac); 37 extern void radeon_link_encoder_connector(struct drm_device *dev); 38 39 /* from radeon_connector.c */ 40 extern void 41 radeon_add_legacy_connector(struct drm_device *dev, 42 uint32_t connector_id, 43 uint32_t supported_device, 44 int connector_type, 45 struct radeon_i2c_bus_rec *i2c_bus, 46 uint16_t connector_object_id, 47 struct radeon_hpd *hpd); 48 49 /* from radeon_legacy_encoder.c */ 50 extern void 51 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 52 uint32_t supported_device); 53 54 /* old legacy ATI BIOS routines */ 55 56 /* COMBIOS table offsets */ 57 enum radeon_combios_table_offset { 58 /* absolute offset tables */ 59 COMBIOS_ASIC_INIT_1_TABLE, 60 COMBIOS_BIOS_SUPPORT_TABLE, 61 COMBIOS_DAC_PROGRAMMING_TABLE, 62 COMBIOS_MAX_COLOR_DEPTH_TABLE, 63 COMBIOS_CRTC_INFO_TABLE, 64 COMBIOS_PLL_INFO_TABLE, 65 COMBIOS_TV_INFO_TABLE, 66 COMBIOS_DFP_INFO_TABLE, 67 COMBIOS_HW_CONFIG_INFO_TABLE, 68 COMBIOS_MULTIMEDIA_INFO_TABLE, 69 COMBIOS_TV_STD_PATCH_TABLE, 70 COMBIOS_LCD_INFO_TABLE, 71 COMBIOS_MOBILE_INFO_TABLE, 72 COMBIOS_PLL_INIT_TABLE, 73 COMBIOS_MEM_CONFIG_TABLE, 74 COMBIOS_SAVE_MASK_TABLE, 75 COMBIOS_HARDCODED_EDID_TABLE, 76 COMBIOS_ASIC_INIT_2_TABLE, 77 COMBIOS_CONNECTOR_INFO_TABLE, 78 COMBIOS_DYN_CLK_1_TABLE, 79 COMBIOS_RESERVED_MEM_TABLE, 80 COMBIOS_EXT_TMDS_INFO_TABLE, 81 COMBIOS_MEM_CLK_INFO_TABLE, 82 COMBIOS_EXT_DAC_INFO_TABLE, 83 COMBIOS_MISC_INFO_TABLE, 84 COMBIOS_CRT_INFO_TABLE, 85 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 86 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 87 COMBIOS_FAN_SPEED_INFO_TABLE, 88 COMBIOS_OVERDRIVE_INFO_TABLE, 89 COMBIOS_OEM_INFO_TABLE, 90 COMBIOS_DYN_CLK_2_TABLE, 91 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 92 COMBIOS_I2C_INFO_TABLE, 93 /* relative offset tables */ 94 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 95 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 96 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 97 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 98 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 99 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 100 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 101 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 102 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 103 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 104 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 105 }; 106 107 enum radeon_combios_ddc { 108 DDC_NONE_DETECTED, 109 DDC_MONID, 110 DDC_DVI, 111 DDC_VGA, 112 DDC_CRT2, 113 DDC_LCD, 114 DDC_GPIO, 115 }; 116 117 enum radeon_combios_connector { 118 CONNECTOR_NONE_LEGACY, 119 CONNECTOR_PROPRIETARY_LEGACY, 120 CONNECTOR_CRT_LEGACY, 121 CONNECTOR_DVI_I_LEGACY, 122 CONNECTOR_DVI_D_LEGACY, 123 CONNECTOR_CTV_LEGACY, 124 CONNECTOR_STV_LEGACY, 125 CONNECTOR_UNSUPPORTED_LEGACY 126 }; 127 128 const int legacy_connector_convert[] = { 129 DRM_MODE_CONNECTOR_Unknown, 130 DRM_MODE_CONNECTOR_DVID, 131 DRM_MODE_CONNECTOR_VGA, 132 DRM_MODE_CONNECTOR_DVII, 133 DRM_MODE_CONNECTOR_DVID, 134 DRM_MODE_CONNECTOR_Composite, 135 DRM_MODE_CONNECTOR_SVIDEO, 136 DRM_MODE_CONNECTOR_Unknown, 137 }; 138 139 static uint16_t combios_get_table_offset(struct drm_device *dev, 140 enum radeon_combios_table_offset table) 141 { 142 struct radeon_device *rdev = dev->dev_private; 143 int rev, size; 144 uint16_t offset = 0, check_offset; 145 146 if (!rdev->bios) 147 return 0; 148 149 switch (table) { 150 /* absolute offset tables */ 151 case COMBIOS_ASIC_INIT_1_TABLE: 152 check_offset = 0xc; 153 break; 154 case COMBIOS_BIOS_SUPPORT_TABLE: 155 check_offset = 0x14; 156 break; 157 case COMBIOS_DAC_PROGRAMMING_TABLE: 158 check_offset = 0x2a; 159 break; 160 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 161 check_offset = 0x2c; 162 break; 163 case COMBIOS_CRTC_INFO_TABLE: 164 check_offset = 0x2e; 165 break; 166 case COMBIOS_PLL_INFO_TABLE: 167 check_offset = 0x30; 168 break; 169 case COMBIOS_TV_INFO_TABLE: 170 check_offset = 0x32; 171 break; 172 case COMBIOS_DFP_INFO_TABLE: 173 check_offset = 0x34; 174 break; 175 case COMBIOS_HW_CONFIG_INFO_TABLE: 176 check_offset = 0x36; 177 break; 178 case COMBIOS_MULTIMEDIA_INFO_TABLE: 179 check_offset = 0x38; 180 break; 181 case COMBIOS_TV_STD_PATCH_TABLE: 182 check_offset = 0x3e; 183 break; 184 case COMBIOS_LCD_INFO_TABLE: 185 check_offset = 0x40; 186 break; 187 case COMBIOS_MOBILE_INFO_TABLE: 188 check_offset = 0x42; 189 break; 190 case COMBIOS_PLL_INIT_TABLE: 191 check_offset = 0x46; 192 break; 193 case COMBIOS_MEM_CONFIG_TABLE: 194 check_offset = 0x48; 195 break; 196 case COMBIOS_SAVE_MASK_TABLE: 197 check_offset = 0x4a; 198 break; 199 case COMBIOS_HARDCODED_EDID_TABLE: 200 check_offset = 0x4c; 201 break; 202 case COMBIOS_ASIC_INIT_2_TABLE: 203 check_offset = 0x4e; 204 break; 205 case COMBIOS_CONNECTOR_INFO_TABLE: 206 check_offset = 0x50; 207 break; 208 case COMBIOS_DYN_CLK_1_TABLE: 209 check_offset = 0x52; 210 break; 211 case COMBIOS_RESERVED_MEM_TABLE: 212 check_offset = 0x54; 213 break; 214 case COMBIOS_EXT_TMDS_INFO_TABLE: 215 check_offset = 0x58; 216 break; 217 case COMBIOS_MEM_CLK_INFO_TABLE: 218 check_offset = 0x5a; 219 break; 220 case COMBIOS_EXT_DAC_INFO_TABLE: 221 check_offset = 0x5c; 222 break; 223 case COMBIOS_MISC_INFO_TABLE: 224 check_offset = 0x5e; 225 break; 226 case COMBIOS_CRT_INFO_TABLE: 227 check_offset = 0x60; 228 break; 229 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 230 check_offset = 0x62; 231 break; 232 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 233 check_offset = 0x64; 234 break; 235 case COMBIOS_FAN_SPEED_INFO_TABLE: 236 check_offset = 0x66; 237 break; 238 case COMBIOS_OVERDRIVE_INFO_TABLE: 239 check_offset = 0x68; 240 break; 241 case COMBIOS_OEM_INFO_TABLE: 242 check_offset = 0x6a; 243 break; 244 case COMBIOS_DYN_CLK_2_TABLE: 245 check_offset = 0x6c; 246 break; 247 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 248 check_offset = 0x6e; 249 break; 250 case COMBIOS_I2C_INFO_TABLE: 251 check_offset = 0x70; 252 break; 253 /* relative offset tables */ 254 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 255 check_offset = 256 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 257 if (check_offset) { 258 rev = RBIOS8(check_offset); 259 if (rev > 0) { 260 check_offset = RBIOS16(check_offset + 0x3); 261 if (check_offset) 262 offset = check_offset; 263 } 264 } 265 break; 266 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 267 check_offset = 268 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 269 if (check_offset) { 270 rev = RBIOS8(check_offset); 271 if (rev > 0) { 272 check_offset = RBIOS16(check_offset + 0x5); 273 if (check_offset) 274 offset = check_offset; 275 } 276 } 277 break; 278 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 279 check_offset = 280 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 281 if (check_offset) { 282 rev = RBIOS8(check_offset); 283 if (rev > 0) { 284 check_offset = RBIOS16(check_offset + 0x7); 285 if (check_offset) 286 offset = check_offset; 287 } 288 } 289 break; 290 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 291 check_offset = 292 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 293 if (check_offset) { 294 rev = RBIOS8(check_offset); 295 if (rev == 2) { 296 check_offset = RBIOS16(check_offset + 0x9); 297 if (check_offset) 298 offset = check_offset; 299 } 300 } 301 break; 302 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 303 check_offset = 304 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 305 if (check_offset) { 306 while (RBIOS8(check_offset++)); 307 check_offset += 2; 308 if (check_offset) 309 offset = check_offset; 310 } 311 break; 312 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 313 check_offset = 314 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 315 if (check_offset) { 316 check_offset = RBIOS16(check_offset + 0x11); 317 if (check_offset) 318 offset = check_offset; 319 } 320 break; 321 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 322 check_offset = 323 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 324 if (check_offset) { 325 check_offset = RBIOS16(check_offset + 0x13); 326 if (check_offset) 327 offset = check_offset; 328 } 329 break; 330 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 331 check_offset = 332 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 333 if (check_offset) { 334 check_offset = RBIOS16(check_offset + 0x15); 335 if (check_offset) 336 offset = check_offset; 337 } 338 break; 339 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 340 check_offset = 341 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 342 if (check_offset) { 343 check_offset = RBIOS16(check_offset + 0x17); 344 if (check_offset) 345 offset = check_offset; 346 } 347 break; 348 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 349 check_offset = 350 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 351 if (check_offset) { 352 check_offset = RBIOS16(check_offset + 0x2); 353 if (check_offset) 354 offset = check_offset; 355 } 356 break; 357 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 358 check_offset = 359 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 360 if (check_offset) { 361 check_offset = RBIOS16(check_offset + 0x4); 362 if (check_offset) 363 offset = check_offset; 364 } 365 break; 366 default: 367 break; 368 } 369 370 size = RBIOS8(rdev->bios_header_start + 0x6); 371 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset < size) 372 offset = RBIOS16(rdev->bios_header_start + check_offset); 373 374 return offset; 375 } 376 377 bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 378 { 379 int edid_info, size; 380 struct edid *edid; 381 unsigned char *raw; 382 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 383 if (!edid_info) 384 return false; 385 386 raw = rdev->bios + edid_info; 387 size = EDID_LENGTH * (raw[0x7e] + 1); 388 edid = kmalloc(size, GFP_KERNEL); 389 if (edid == NULL) 390 return false; 391 392 memcpy((unsigned char *)edid, raw, size); 393 394 if (!drm_edid_is_valid(edid)) { 395 kfree(edid); 396 return false; 397 } 398 399 rdev->mode_info.bios_hardcoded_edid = edid; 400 rdev->mode_info.bios_hardcoded_edid_size = size; 401 return true; 402 } 403 404 /* this is used for atom LCDs as well */ 405 struct edid * 406 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 407 { 408 struct edid *edid; 409 410 if (rdev->mode_info.bios_hardcoded_edid) { 411 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 412 if (edid) { 413 memcpy((unsigned char *)edid, 414 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 415 rdev->mode_info.bios_hardcoded_edid_size); 416 return edid; 417 } 418 } 419 return NULL; 420 } 421 422 static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 423 enum radeon_combios_ddc ddc, 424 u32 clk_mask, 425 u32 data_mask) 426 { 427 struct radeon_i2c_bus_rec i2c; 428 int ddc_line = 0; 429 430 /* ddc id = mask reg 431 * DDC_NONE_DETECTED = none 432 * DDC_DVI = RADEON_GPIO_DVI_DDC 433 * DDC_VGA = RADEON_GPIO_VGA_DDC 434 * DDC_LCD = RADEON_GPIOPAD_MASK 435 * DDC_GPIO = RADEON_MDGPIO_MASK 436 * r1xx 437 * DDC_MONID = RADEON_GPIO_MONID 438 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 439 * r200 440 * DDC_MONID = RADEON_GPIO_MONID 441 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 442 * r300/r350 443 * DDC_MONID = RADEON_GPIO_DVI_DDC 444 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 445 * rv2xx/rv3xx 446 * DDC_MONID = RADEON_GPIO_MONID 447 * DDC_CRT2 = RADEON_GPIO_MONID 448 * rs3xx/rs4xx 449 * DDC_MONID = RADEON_GPIOPAD_MASK 450 * DDC_CRT2 = RADEON_GPIO_MONID 451 */ 452 switch (ddc) { 453 case DDC_NONE_DETECTED: 454 default: 455 ddc_line = 0; 456 break; 457 case DDC_DVI: 458 ddc_line = RADEON_GPIO_DVI_DDC; 459 break; 460 case DDC_VGA: 461 ddc_line = RADEON_GPIO_VGA_DDC; 462 break; 463 case DDC_LCD: 464 ddc_line = RADEON_GPIOPAD_MASK; 465 break; 466 case DDC_GPIO: 467 ddc_line = RADEON_MDGPIO_MASK; 468 break; 469 case DDC_MONID: 470 if (rdev->family == CHIP_RS300 || 471 rdev->family == CHIP_RS400 || 472 rdev->family == CHIP_RS480) 473 ddc_line = RADEON_GPIOPAD_MASK; 474 else if (rdev->family == CHIP_R300 || 475 rdev->family == CHIP_R350) { 476 ddc_line = RADEON_GPIO_DVI_DDC; 477 ddc = DDC_DVI; 478 } else 479 ddc_line = RADEON_GPIO_MONID; 480 break; 481 case DDC_CRT2: 482 if (rdev->family == CHIP_R200 || 483 rdev->family == CHIP_R300 || 484 rdev->family == CHIP_R350) { 485 ddc_line = RADEON_GPIO_DVI_DDC; 486 ddc = DDC_DVI; 487 } else if (rdev->family == CHIP_RS300 || 488 rdev->family == CHIP_RS400 || 489 rdev->family == CHIP_RS480) 490 ddc_line = RADEON_GPIO_MONID; 491 else if (rdev->family >= CHIP_RV350) { 492 ddc_line = RADEON_GPIO_MONID; 493 ddc = DDC_MONID; 494 } else 495 ddc_line = RADEON_GPIO_CRT2_DDC; 496 break; 497 } 498 499 if (ddc_line == RADEON_GPIOPAD_MASK) { 500 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 501 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 502 i2c.a_clk_reg = RADEON_GPIOPAD_A; 503 i2c.a_data_reg = RADEON_GPIOPAD_A; 504 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 505 i2c.en_data_reg = RADEON_GPIOPAD_EN; 506 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 507 i2c.y_data_reg = RADEON_GPIOPAD_Y; 508 } else if (ddc_line == RADEON_MDGPIO_MASK) { 509 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 510 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 511 i2c.a_clk_reg = RADEON_MDGPIO_A; 512 i2c.a_data_reg = RADEON_MDGPIO_A; 513 i2c.en_clk_reg = RADEON_MDGPIO_EN; 514 i2c.en_data_reg = RADEON_MDGPIO_EN; 515 i2c.y_clk_reg = RADEON_MDGPIO_Y; 516 i2c.y_data_reg = RADEON_MDGPIO_Y; 517 } else { 518 i2c.mask_clk_reg = ddc_line; 519 i2c.mask_data_reg = ddc_line; 520 i2c.a_clk_reg = ddc_line; 521 i2c.a_data_reg = ddc_line; 522 i2c.en_clk_reg = ddc_line; 523 i2c.en_data_reg = ddc_line; 524 i2c.y_clk_reg = ddc_line; 525 i2c.y_data_reg = ddc_line; 526 } 527 528 if (clk_mask && data_mask) { 529 /* system specific masks */ 530 i2c.mask_clk_mask = clk_mask; 531 i2c.mask_data_mask = data_mask; 532 i2c.a_clk_mask = clk_mask; 533 i2c.a_data_mask = data_mask; 534 i2c.en_clk_mask = clk_mask; 535 i2c.en_data_mask = data_mask; 536 i2c.y_clk_mask = clk_mask; 537 i2c.y_data_mask = data_mask; 538 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 539 (ddc_line == RADEON_MDGPIO_MASK)) { 540 /* default gpiopad masks */ 541 i2c.mask_clk_mask = (0x20 << 8); 542 i2c.mask_data_mask = 0x80; 543 i2c.a_clk_mask = (0x20 << 8); 544 i2c.a_data_mask = 0x80; 545 i2c.en_clk_mask = (0x20 << 8); 546 i2c.en_data_mask = 0x80; 547 i2c.y_clk_mask = (0x20 << 8); 548 i2c.y_data_mask = 0x80; 549 } else { 550 /* default masks for ddc pads */ 551 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 552 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 553 i2c.a_clk_mask = RADEON_GPIO_A_1; 554 i2c.a_data_mask = RADEON_GPIO_A_0; 555 i2c.en_clk_mask = RADEON_GPIO_EN_1; 556 i2c.en_data_mask = RADEON_GPIO_EN_0; 557 i2c.y_clk_mask = RADEON_GPIO_Y_1; 558 i2c.y_data_mask = RADEON_GPIO_Y_0; 559 } 560 561 switch (rdev->family) { 562 case CHIP_R100: 563 case CHIP_RV100: 564 case CHIP_RS100: 565 case CHIP_RV200: 566 case CHIP_RS200: 567 case CHIP_RS300: 568 switch (ddc_line) { 569 case RADEON_GPIO_DVI_DDC: 570 i2c.hw_capable = true; 571 break; 572 default: 573 i2c.hw_capable = false; 574 break; 575 } 576 break; 577 case CHIP_R200: 578 switch (ddc_line) { 579 case RADEON_GPIO_DVI_DDC: 580 case RADEON_GPIO_MONID: 581 i2c.hw_capable = true; 582 break; 583 default: 584 i2c.hw_capable = false; 585 break; 586 } 587 break; 588 case CHIP_RV250: 589 case CHIP_RV280: 590 switch (ddc_line) { 591 case RADEON_GPIO_VGA_DDC: 592 case RADEON_GPIO_DVI_DDC: 593 case RADEON_GPIO_CRT2_DDC: 594 i2c.hw_capable = true; 595 break; 596 default: 597 i2c.hw_capable = false; 598 break; 599 } 600 break; 601 case CHIP_R300: 602 case CHIP_R350: 603 switch (ddc_line) { 604 case RADEON_GPIO_VGA_DDC: 605 case RADEON_GPIO_DVI_DDC: 606 i2c.hw_capable = true; 607 break; 608 default: 609 i2c.hw_capable = false; 610 break; 611 } 612 break; 613 case CHIP_RV350: 614 case CHIP_RV380: 615 case CHIP_RS400: 616 case CHIP_RS480: 617 switch (ddc_line) { 618 case RADEON_GPIO_VGA_DDC: 619 case RADEON_GPIO_DVI_DDC: 620 i2c.hw_capable = true; 621 break; 622 case RADEON_GPIO_MONID: 623 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 624 * reliably on some pre-r4xx hardware; not sure why. 625 */ 626 i2c.hw_capable = false; 627 break; 628 default: 629 i2c.hw_capable = false; 630 break; 631 } 632 break; 633 default: 634 i2c.hw_capable = false; 635 break; 636 } 637 i2c.mm_i2c = false; 638 639 i2c.i2c_id = ddc; 640 i2c.hpd = RADEON_HPD_NONE; 641 642 if (ddc_line) 643 i2c.valid = true; 644 else 645 i2c.valid = false; 646 647 return i2c; 648 } 649 650 static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 651 { 652 struct drm_device *dev = rdev->ddev; 653 struct radeon_i2c_bus_rec i2c; 654 u16 offset; 655 u8 id, blocks, clk, data; 656 int i; 657 658 i2c.valid = false; 659 660 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 661 if (offset) { 662 blocks = RBIOS8(offset + 2); 663 for (i = 0; i < blocks; i++) { 664 id = RBIOS8(offset + 3 + (i * 5) + 0); 665 if (id == 136) { 666 clk = RBIOS8(offset + 3 + (i * 5) + 3); 667 data = RBIOS8(offset + 3 + (i * 5) + 4); 668 /* gpiopad */ 669 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 670 (1 << clk), (1 << data)); 671 break; 672 } 673 } 674 } 675 return i2c; 676 } 677 678 void radeon_combios_i2c_init(struct radeon_device *rdev) 679 { 680 struct drm_device *dev = rdev->ddev; 681 struct radeon_i2c_bus_rec i2c; 682 683 /* actual hw pads 684 * r1xx/rs2xx/rs3xx 685 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 686 * r200 687 * 0x60, 0x64, 0x68, mm 688 * r300/r350 689 * 0x60, 0x64, mm 690 * rv2xx/rv3xx/rs4xx 691 * 0x60, 0x64, 0x68, gpiopads, mm 692 */ 693 694 /* 0x60 */ 695 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 696 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 697 /* 0x64 */ 698 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 699 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 700 701 /* mm i2c */ 702 i2c.valid = true; 703 i2c.hw_capable = true; 704 i2c.mm_i2c = true; 705 i2c.i2c_id = 0xa0; 706 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 707 708 if (rdev->family == CHIP_R300 || 709 rdev->family == CHIP_R350) { 710 /* only 2 sw i2c pads */ 711 } else if (rdev->family == CHIP_RS300 || 712 rdev->family == CHIP_RS400 || 713 rdev->family == CHIP_RS480) { 714 /* 0x68 */ 715 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 716 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 717 718 /* gpiopad */ 719 i2c = radeon_combios_get_i2c_info_from_table(rdev); 720 if (i2c.valid) 721 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 722 } else if ((rdev->family == CHIP_R200) || 723 (rdev->family >= CHIP_R300)) { 724 /* 0x68 */ 725 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 726 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 727 } else { 728 /* 0x68 */ 729 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 730 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 731 /* 0x6c */ 732 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 733 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 734 } 735 } 736 737 bool radeon_combios_get_clock_info(struct drm_device *dev) 738 { 739 struct radeon_device *rdev = dev->dev_private; 740 uint16_t pll_info; 741 struct radeon_pll *p1pll = &rdev->clock.p1pll; 742 struct radeon_pll *p2pll = &rdev->clock.p2pll; 743 struct radeon_pll *spll = &rdev->clock.spll; 744 struct radeon_pll *mpll = &rdev->clock.mpll; 745 int8_t rev; 746 uint16_t sclk, mclk; 747 748 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 749 if (pll_info) { 750 rev = RBIOS8(pll_info); 751 752 /* pixel clocks */ 753 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 754 p1pll->reference_div = RBIOS16(pll_info + 0x10); 755 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 756 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 757 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 758 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 759 760 if (rev > 9) { 761 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 762 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 763 } else { 764 p1pll->pll_in_min = 40; 765 p1pll->pll_in_max = 500; 766 } 767 *p2pll = *p1pll; 768 769 /* system clock */ 770 spll->reference_freq = RBIOS16(pll_info + 0x1a); 771 spll->reference_div = RBIOS16(pll_info + 0x1c); 772 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 773 spll->pll_out_max = RBIOS32(pll_info + 0x22); 774 775 if (rev > 10) { 776 spll->pll_in_min = RBIOS32(pll_info + 0x48); 777 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 778 } else { 779 /* ??? */ 780 spll->pll_in_min = 40; 781 spll->pll_in_max = 500; 782 } 783 784 /* memory clock */ 785 mpll->reference_freq = RBIOS16(pll_info + 0x26); 786 mpll->reference_div = RBIOS16(pll_info + 0x28); 787 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 788 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 789 790 if (rev > 10) { 791 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 792 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 793 } else { 794 /* ??? */ 795 mpll->pll_in_min = 40; 796 mpll->pll_in_max = 500; 797 } 798 799 /* default sclk/mclk */ 800 sclk = RBIOS16(pll_info + 0xa); 801 mclk = RBIOS16(pll_info + 0x8); 802 if (sclk == 0) 803 sclk = 200 * 100; 804 if (mclk == 0) 805 mclk = 200 * 100; 806 807 rdev->clock.default_sclk = sclk; 808 rdev->clock.default_mclk = mclk; 809 810 if (RBIOS32(pll_info + 0x16)) 811 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 812 else 813 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 814 815 return true; 816 } 817 return false; 818 } 819 820 bool radeon_combios_sideport_present(struct radeon_device *rdev) 821 { 822 struct drm_device *dev = rdev->ddev; 823 u16 igp_info; 824 825 /* sideport is AMD only */ 826 if (rdev->family == CHIP_RS400) 827 return false; 828 829 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 830 831 if (igp_info) { 832 if (RBIOS16(igp_info + 0x4)) 833 return true; 834 } 835 return false; 836 } 837 838 static const uint32_t default_primarydac_adj[CHIP_LAST] = { 839 0x00000808, /* r100 */ 840 0x00000808, /* rv100 */ 841 0x00000808, /* rs100 */ 842 0x00000808, /* rv200 */ 843 0x00000808, /* rs200 */ 844 0x00000808, /* r200 */ 845 0x00000808, /* rv250 */ 846 0x00000000, /* rs300 */ 847 0x00000808, /* rv280 */ 848 0x00000808, /* r300 */ 849 0x00000808, /* r350 */ 850 0x00000808, /* rv350 */ 851 0x00000808, /* rv380 */ 852 0x00000808, /* r420 */ 853 0x00000808, /* r423 */ 854 0x00000808, /* rv410 */ 855 0x00000000, /* rs400 */ 856 0x00000000, /* rs480 */ 857 }; 858 859 static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 860 struct radeon_encoder_primary_dac *p_dac) 861 { 862 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 863 return; 864 } 865 866 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 867 radeon_encoder 868 *encoder) 869 { 870 struct drm_device *dev = encoder->base.dev; 871 struct radeon_device *rdev = dev->dev_private; 872 uint16_t dac_info; 873 uint8_t rev, bg, dac; 874 struct radeon_encoder_primary_dac *p_dac = NULL; 875 int found = 0; 876 877 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 878 GFP_KERNEL); 879 880 if (!p_dac) 881 return NULL; 882 883 /* check CRT table */ 884 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 885 if (dac_info) { 886 rev = RBIOS8(dac_info) & 0x3; 887 if (rev < 2) { 888 bg = RBIOS8(dac_info + 0x2) & 0xf; 889 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 890 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 891 } else { 892 bg = RBIOS8(dac_info + 0x2) & 0xf; 893 dac = RBIOS8(dac_info + 0x3) & 0xf; 894 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 895 } 896 /* if the values are zeros, use the table */ 897 if ((dac == 0) || (bg == 0)) 898 found = 0; 899 else 900 found = 1; 901 } 902 903 /* quirks */ 904 /* Radeon 7000 (RV100) */ 905 if (((dev->pdev->device == 0x5159) && 906 (dev->pdev->subsystem_vendor == 0x174B) && 907 (dev->pdev->subsystem_device == 0x7c28)) || 908 /* Radeon 9100 (R200) */ 909 ((dev->pdev->device == 0x514D) && 910 (dev->pdev->subsystem_vendor == 0x174B) && 911 (dev->pdev->subsystem_device == 0x7149))) { 912 /* vbios value is bad, use the default */ 913 found = 0; 914 } 915 916 if (!found) /* fallback to defaults */ 917 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 918 919 return p_dac; 920 } 921 922 enum radeon_tv_std 923 radeon_combios_get_tv_info(struct radeon_device *rdev) 924 { 925 struct drm_device *dev = rdev->ddev; 926 uint16_t tv_info; 927 enum radeon_tv_std tv_std = TV_STD_NTSC; 928 929 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 930 if (tv_info) { 931 if (RBIOS8(tv_info + 6) == 'T') { 932 switch (RBIOS8(tv_info + 7) & 0xf) { 933 case 1: 934 tv_std = TV_STD_NTSC; 935 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 936 break; 937 case 2: 938 tv_std = TV_STD_PAL; 939 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 940 break; 941 case 3: 942 tv_std = TV_STD_PAL_M; 943 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 944 break; 945 case 4: 946 tv_std = TV_STD_PAL_60; 947 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 948 break; 949 case 5: 950 tv_std = TV_STD_NTSC_J; 951 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 952 break; 953 case 6: 954 tv_std = TV_STD_SCART_PAL; 955 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 956 break; 957 default: 958 tv_std = TV_STD_NTSC; 959 DRM_DEBUG_KMS 960 ("Unknown TV standard; defaulting to NTSC\n"); 961 break; 962 } 963 964 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 965 case 0: 966 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 967 break; 968 case 1: 969 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 970 break; 971 case 2: 972 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 973 break; 974 case 3: 975 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 976 break; 977 default: 978 break; 979 } 980 } 981 } 982 return tv_std; 983 } 984 985 static const uint32_t default_tvdac_adj[CHIP_LAST] = { 986 0x00000000, /* r100 */ 987 0x00280000, /* rv100 */ 988 0x00000000, /* rs100 */ 989 0x00880000, /* rv200 */ 990 0x00000000, /* rs200 */ 991 0x00000000, /* r200 */ 992 0x00770000, /* rv250 */ 993 0x00290000, /* rs300 */ 994 0x00560000, /* rv280 */ 995 0x00780000, /* r300 */ 996 0x00770000, /* r350 */ 997 0x00780000, /* rv350 */ 998 0x00780000, /* rv380 */ 999 0x01080000, /* r420 */ 1000 0x01080000, /* r423 */ 1001 0x01080000, /* rv410 */ 1002 0x00780000, /* rs400 */ 1003 0x00780000, /* rs480 */ 1004 }; 1005 1006 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 1007 struct radeon_encoder_tv_dac *tv_dac) 1008 { 1009 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1010 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1011 tv_dac->ps2_tvdac_adj = 0x00880000; 1012 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1013 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1014 return; 1015 } 1016 1017 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1018 radeon_encoder 1019 *encoder) 1020 { 1021 struct drm_device *dev = encoder->base.dev; 1022 struct radeon_device *rdev = dev->dev_private; 1023 uint16_t dac_info; 1024 uint8_t rev, bg, dac; 1025 struct radeon_encoder_tv_dac *tv_dac = NULL; 1026 int found = 0; 1027 1028 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1029 if (!tv_dac) 1030 return NULL; 1031 1032 /* first check TV table */ 1033 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1034 if (dac_info) { 1035 rev = RBIOS8(dac_info + 0x3); 1036 if (rev > 4) { 1037 bg = RBIOS8(dac_info + 0xc) & 0xf; 1038 dac = RBIOS8(dac_info + 0xd) & 0xf; 1039 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1040 1041 bg = RBIOS8(dac_info + 0xe) & 0xf; 1042 dac = RBIOS8(dac_info + 0xf) & 0xf; 1043 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1044 1045 bg = RBIOS8(dac_info + 0x10) & 0xf; 1046 dac = RBIOS8(dac_info + 0x11) & 0xf; 1047 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1048 /* if the values are all zeros, use the table */ 1049 if (tv_dac->ps2_tvdac_adj) 1050 found = 1; 1051 } else if (rev > 1) { 1052 bg = RBIOS8(dac_info + 0xc) & 0xf; 1053 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1054 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1055 1056 bg = RBIOS8(dac_info + 0xd) & 0xf; 1057 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1058 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1059 1060 bg = RBIOS8(dac_info + 0xe) & 0xf; 1061 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1062 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1063 /* if the values are all zeros, use the table */ 1064 if (tv_dac->ps2_tvdac_adj) 1065 found = 1; 1066 } 1067 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1068 } 1069 if (!found) { 1070 /* then check CRT table */ 1071 dac_info = 1072 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1073 if (dac_info) { 1074 rev = RBIOS8(dac_info) & 0x3; 1075 if (rev < 2) { 1076 bg = RBIOS8(dac_info + 0x3) & 0xf; 1077 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1078 tv_dac->ps2_tvdac_adj = 1079 (bg << 16) | (dac << 20); 1080 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1081 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1082 /* if the values are all zeros, use the table */ 1083 if (tv_dac->ps2_tvdac_adj) 1084 found = 1; 1085 } else { 1086 bg = RBIOS8(dac_info + 0x4) & 0xf; 1087 dac = RBIOS8(dac_info + 0x5) & 0xf; 1088 tv_dac->ps2_tvdac_adj = 1089 (bg << 16) | (dac << 20); 1090 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1091 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1092 /* if the values are all zeros, use the table */ 1093 if (tv_dac->ps2_tvdac_adj) 1094 found = 1; 1095 } 1096 } else { 1097 DRM_INFO("No TV DAC info found in BIOS\n"); 1098 } 1099 } 1100 1101 if (!found) /* fallback to defaults */ 1102 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1103 1104 return tv_dac; 1105 } 1106 1107 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1108 radeon_device 1109 *rdev) 1110 { 1111 struct radeon_encoder_lvds *lvds = NULL; 1112 uint32_t fp_vert_stretch, fp_horz_stretch; 1113 uint32_t ppll_div_sel, ppll_val; 1114 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1115 1116 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1117 1118 if (!lvds) 1119 return NULL; 1120 1121 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1122 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1123 1124 /* These should be fail-safe defaults, fingers crossed */ 1125 lvds->panel_pwr_delay = 200; 1126 lvds->panel_vcc_delay = 2000; 1127 1128 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1129 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1130 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1131 1132 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1133 lvds->native_mode.vdisplay = 1134 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1135 RADEON_VERT_PANEL_SHIFT) + 1; 1136 else 1137 lvds->native_mode.vdisplay = 1138 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1139 1140 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1141 lvds->native_mode.hdisplay = 1142 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1143 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1144 else 1145 lvds->native_mode.hdisplay = 1146 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1147 1148 if ((lvds->native_mode.hdisplay < 640) || 1149 (lvds->native_mode.vdisplay < 480)) { 1150 lvds->native_mode.hdisplay = 640; 1151 lvds->native_mode.vdisplay = 480; 1152 } 1153 1154 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1155 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1156 if ((ppll_val & 0x000707ff) == 0x1bb) 1157 lvds->use_bios_dividers = false; 1158 else { 1159 lvds->panel_ref_divider = 1160 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1161 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1162 lvds->panel_fb_divider = ppll_val & 0x7ff; 1163 1164 if ((lvds->panel_ref_divider != 0) && 1165 (lvds->panel_fb_divider > 3)) 1166 lvds->use_bios_dividers = true; 1167 } 1168 lvds->panel_vcc_delay = 200; 1169 1170 DRM_INFO("Panel info derived from registers\n"); 1171 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1172 lvds->native_mode.vdisplay); 1173 1174 return lvds; 1175 } 1176 1177 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1178 *encoder) 1179 { 1180 struct drm_device *dev = encoder->base.dev; 1181 struct radeon_device *rdev = dev->dev_private; 1182 uint16_t lcd_info; 1183 uint32_t panel_setup; 1184 char stmp[30]; 1185 int tmp, i; 1186 struct radeon_encoder_lvds *lvds = NULL; 1187 1188 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1189 1190 if (lcd_info) { 1191 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1192 1193 if (!lvds) 1194 return NULL; 1195 1196 for (i = 0; i < 24; i++) 1197 stmp[i] = RBIOS8(lcd_info + i + 1); 1198 stmp[24] = 0; 1199 1200 DRM_INFO("Panel ID String: %s\n", stmp); 1201 1202 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1203 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1204 1205 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1206 lvds->native_mode.vdisplay); 1207 1208 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1209 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1210 1211 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1212 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1213 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1214 1215 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1216 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1217 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1218 if ((lvds->panel_ref_divider != 0) && 1219 (lvds->panel_fb_divider > 3)) 1220 lvds->use_bios_dividers = true; 1221 1222 panel_setup = RBIOS32(lcd_info + 0x39); 1223 lvds->lvds_gen_cntl = 0xff00; 1224 if (panel_setup & 0x1) 1225 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1226 1227 if ((panel_setup >> 4) & 0x1) 1228 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1229 1230 switch ((panel_setup >> 8) & 0x7) { 1231 case 0: 1232 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1233 break; 1234 case 1: 1235 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1236 break; 1237 case 2: 1238 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1239 break; 1240 default: 1241 break; 1242 } 1243 1244 if ((panel_setup >> 16) & 0x1) 1245 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1246 1247 if ((panel_setup >> 17) & 0x1) 1248 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1249 1250 if ((panel_setup >> 18) & 0x1) 1251 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1252 1253 if ((panel_setup >> 23) & 0x1) 1254 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1255 1256 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1257 1258 for (i = 0; i < 32; i++) { 1259 tmp = RBIOS16(lcd_info + 64 + i * 2); 1260 if (tmp == 0) 1261 break; 1262 1263 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1264 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1265 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1266 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1267 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1268 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1269 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1270 (RBIOS8(tmp + 23) * 8); 1271 1272 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1273 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1274 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1275 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1276 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1277 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1278 1279 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1280 lvds->native_mode.flags = 0; 1281 /* set crtc values */ 1282 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1283 1284 } 1285 } 1286 } else { 1287 DRM_INFO("No panel info found in BIOS\n"); 1288 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1289 } 1290 1291 if (lvds) 1292 encoder->native_mode = lvds->native_mode; 1293 return lvds; 1294 } 1295 1296 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1297 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1298 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1299 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1300 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1301 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1302 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1303 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1304 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1305 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1306 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1307 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1308 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1309 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1310 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1311 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1312 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1313 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1314 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1315 }; 1316 1317 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1318 struct radeon_encoder_int_tmds *tmds) 1319 { 1320 struct drm_device *dev = encoder->base.dev; 1321 struct radeon_device *rdev = dev->dev_private; 1322 int i; 1323 1324 for (i = 0; i < 4; i++) { 1325 tmds->tmds_pll[i].value = 1326 default_tmds_pll[rdev->family][i].value; 1327 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1328 } 1329 1330 return true; 1331 } 1332 1333 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1334 struct radeon_encoder_int_tmds *tmds) 1335 { 1336 struct drm_device *dev = encoder->base.dev; 1337 struct radeon_device *rdev = dev->dev_private; 1338 uint16_t tmds_info; 1339 int i, n; 1340 uint8_t ver; 1341 1342 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1343 1344 if (tmds_info) { 1345 ver = RBIOS8(tmds_info); 1346 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1347 if (ver == 3) { 1348 n = RBIOS8(tmds_info + 5) + 1; 1349 if (n > 4) 1350 n = 4; 1351 for (i = 0; i < n; i++) { 1352 tmds->tmds_pll[i].value = 1353 RBIOS32(tmds_info + i * 10 + 0x08); 1354 tmds->tmds_pll[i].freq = 1355 RBIOS16(tmds_info + i * 10 + 0x10); 1356 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1357 tmds->tmds_pll[i].freq, 1358 tmds->tmds_pll[i].value); 1359 } 1360 } else if (ver == 4) { 1361 int stride = 0; 1362 n = RBIOS8(tmds_info + 5) + 1; 1363 if (n > 4) 1364 n = 4; 1365 for (i = 0; i < n; i++) { 1366 tmds->tmds_pll[i].value = 1367 RBIOS32(tmds_info + stride + 0x08); 1368 tmds->tmds_pll[i].freq = 1369 RBIOS16(tmds_info + stride + 0x10); 1370 if (i == 0) 1371 stride += 10; 1372 else 1373 stride += 6; 1374 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1375 tmds->tmds_pll[i].freq, 1376 tmds->tmds_pll[i].value); 1377 } 1378 } 1379 } else { 1380 DRM_INFO("No TMDS info found in BIOS\n"); 1381 return false; 1382 } 1383 return true; 1384 } 1385 1386 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1387 struct radeon_encoder_ext_tmds *tmds) 1388 { 1389 struct drm_device *dev = encoder->base.dev; 1390 struct radeon_device *rdev = dev->dev_private; 1391 struct radeon_i2c_bus_rec i2c_bus; 1392 1393 /* default for macs */ 1394 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1395 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1396 1397 /* XXX some macs have duallink chips */ 1398 switch (rdev->mode_info.connector_table) { 1399 case CT_POWERBOOK_EXTERNAL: 1400 case CT_MINI_EXTERNAL: 1401 default: 1402 tmds->dvo_chip = DVO_SIL164; 1403 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1404 break; 1405 } 1406 1407 return true; 1408 } 1409 1410 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1411 struct radeon_encoder_ext_tmds *tmds) 1412 { 1413 struct drm_device *dev = encoder->base.dev; 1414 struct radeon_device *rdev = dev->dev_private; 1415 uint16_t offset; 1416 uint8_t ver; 1417 enum radeon_combios_ddc gpio; 1418 struct radeon_i2c_bus_rec i2c_bus; 1419 1420 tmds->i2c_bus = NULL; 1421 if (rdev->flags & RADEON_IS_IGP) { 1422 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1423 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1424 tmds->dvo_chip = DVO_SIL164; 1425 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1426 } else { 1427 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1428 if (offset) { 1429 ver = RBIOS8(offset); 1430 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1431 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1432 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1433 gpio = RBIOS8(offset + 4 + 3); 1434 if (gpio == DDC_LCD) { 1435 /* MM i2c */ 1436 i2c_bus.valid = true; 1437 i2c_bus.hw_capable = true; 1438 i2c_bus.mm_i2c = true; 1439 i2c_bus.i2c_id = 0xa0; 1440 } else 1441 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1442 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1443 } 1444 } 1445 1446 if (!tmds->i2c_bus) { 1447 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1448 return false; 1449 } 1450 1451 return true; 1452 } 1453 1454 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1455 { 1456 struct radeon_device *rdev = dev->dev_private; 1457 struct radeon_i2c_bus_rec ddc_i2c; 1458 struct radeon_hpd hpd; 1459 1460 rdev->mode_info.connector_table = radeon_connector_table; 1461 if (rdev->mode_info.connector_table == CT_NONE) { 1462 #ifdef __macppc__ 1463 if (of_machine_is_compatible("PowerBook3,3")) { 1464 /* powerbook with VGA */ 1465 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1466 } else if (of_machine_is_compatible("PowerBook3,4") || 1467 of_machine_is_compatible("PowerBook3,5")) { 1468 /* powerbook with internal tmds */ 1469 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1470 } else if (of_machine_is_compatible("PowerBook5,1") || 1471 of_machine_is_compatible("PowerBook5,2") || 1472 of_machine_is_compatible("PowerBook5,3") || 1473 of_machine_is_compatible("PowerBook5,4") || 1474 of_machine_is_compatible("PowerBook5,5")) { 1475 /* powerbook with external single link tmds (sil164) */ 1476 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1477 } else if (of_machine_is_compatible("PowerBook5,6")) { 1478 /* powerbook with external dual or single link tmds */ 1479 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1480 } else if (of_machine_is_compatible("PowerBook5,7") || 1481 of_machine_is_compatible("PowerBook5,8") || 1482 of_machine_is_compatible("PowerBook5,9")) { 1483 /* PowerBook6,2 ? */ 1484 /* powerbook with external dual link tmds (sil1178?) */ 1485 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1486 } else if (of_machine_is_compatible("PowerBook4,1") || 1487 of_machine_is_compatible("PowerBook4,2") || 1488 of_machine_is_compatible("PowerBook4,3") || 1489 of_machine_is_compatible("PowerBook6,3") || 1490 of_machine_is_compatible("PowerBook6,5") || 1491 of_machine_is_compatible("PowerBook6,7")) { 1492 /* ibook */ 1493 rdev->mode_info.connector_table = CT_IBOOK; 1494 } else if (of_machine_is_compatible("PowerMac3,5")) { 1495 /* PowerMac G4 Silver radeon 7500 */ 1496 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1497 } else if (of_machine_is_compatible("PowerMac4,4")) { 1498 /* emac */ 1499 rdev->mode_info.connector_table = CT_EMAC; 1500 } else if (of_machine_is_compatible("PowerMac10,1")) { 1501 /* mini with internal tmds */ 1502 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1503 } else if (of_machine_is_compatible("PowerMac10,2")) { 1504 /* mini with external tmds */ 1505 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1506 } else if (of_machine_is_compatible("PowerMac12,1")) { 1507 /* PowerMac8,1 ? */ 1508 /* imac g5 isight */ 1509 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1510 } else if ((rdev->pdev->device == 0x4a48) && 1511 (rdev->pdev->subsystem_vendor == 0x1002) && 1512 (rdev->pdev->subsystem_device == 0x4a48)) { 1513 /* Mac X800 */ 1514 rdev->mode_info.connector_table = CT_MAC_X800; 1515 } else if ((of_machine_is_compatible("PowerMac7,2") || 1516 of_machine_is_compatible("PowerMac7,3")) && 1517 (rdev->pdev->device == 0x4150) && 1518 (rdev->pdev->subsystem_vendor == 0x1002) && 1519 (rdev->pdev->subsystem_device == 0x4150)) { 1520 /* Mac G5 tower 9600 */ 1521 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1522 } else if ((rdev->pdev->device == 0x4c66) && 1523 (rdev->pdev->subsystem_vendor == 0x1002) && 1524 (rdev->pdev->subsystem_device == 0x4c66)) { 1525 /* SAM440ep RV250 embedded board */ 1526 rdev->mode_info.connector_table = CT_SAM440EP; 1527 } else 1528 #endif /* __macppc__ */ 1529 #ifdef CONFIG_PPC64 1530 if (ASIC_IS_RN50(rdev)) 1531 rdev->mode_info.connector_table = CT_RN50_POWER; 1532 else 1533 #endif 1534 rdev->mode_info.connector_table = CT_GENERIC; 1535 } 1536 1537 switch (rdev->mode_info.connector_table) { 1538 case CT_GENERIC: 1539 DRM_INFO("Connector Table: %d (generic)\n", 1540 rdev->mode_info.connector_table); 1541 /* these are the most common settings */ 1542 if (rdev->flags & RADEON_SINGLE_CRTC) { 1543 /* VGA - primary dac */ 1544 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1545 hpd.hpd = RADEON_HPD_NONE; 1546 radeon_add_legacy_encoder(dev, 1547 radeon_get_encoder_enum(dev, 1548 ATOM_DEVICE_CRT1_SUPPORT, 1549 1), 1550 ATOM_DEVICE_CRT1_SUPPORT); 1551 radeon_add_legacy_connector(dev, 0, 1552 ATOM_DEVICE_CRT1_SUPPORT, 1553 DRM_MODE_CONNECTOR_VGA, 1554 &ddc_i2c, 1555 CONNECTOR_OBJECT_ID_VGA, 1556 &hpd); 1557 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1558 /* LVDS */ 1559 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1560 hpd.hpd = RADEON_HPD_NONE; 1561 radeon_add_legacy_encoder(dev, 1562 radeon_get_encoder_enum(dev, 1563 ATOM_DEVICE_LCD1_SUPPORT, 1564 0), 1565 ATOM_DEVICE_LCD1_SUPPORT); 1566 radeon_add_legacy_connector(dev, 0, 1567 ATOM_DEVICE_LCD1_SUPPORT, 1568 DRM_MODE_CONNECTOR_LVDS, 1569 &ddc_i2c, 1570 CONNECTOR_OBJECT_ID_LVDS, 1571 &hpd); 1572 1573 /* VGA - primary dac */ 1574 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1575 hpd.hpd = RADEON_HPD_NONE; 1576 radeon_add_legacy_encoder(dev, 1577 radeon_get_encoder_enum(dev, 1578 ATOM_DEVICE_CRT1_SUPPORT, 1579 1), 1580 ATOM_DEVICE_CRT1_SUPPORT); 1581 radeon_add_legacy_connector(dev, 1, 1582 ATOM_DEVICE_CRT1_SUPPORT, 1583 DRM_MODE_CONNECTOR_VGA, 1584 &ddc_i2c, 1585 CONNECTOR_OBJECT_ID_VGA, 1586 &hpd); 1587 } else { 1588 /* DVI-I - tv dac, int tmds */ 1589 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1590 hpd.hpd = RADEON_HPD_1; 1591 radeon_add_legacy_encoder(dev, 1592 radeon_get_encoder_enum(dev, 1593 ATOM_DEVICE_DFP1_SUPPORT, 1594 0), 1595 ATOM_DEVICE_DFP1_SUPPORT); 1596 radeon_add_legacy_encoder(dev, 1597 radeon_get_encoder_enum(dev, 1598 ATOM_DEVICE_CRT2_SUPPORT, 1599 2), 1600 ATOM_DEVICE_CRT2_SUPPORT); 1601 radeon_add_legacy_connector(dev, 0, 1602 ATOM_DEVICE_DFP1_SUPPORT | 1603 ATOM_DEVICE_CRT2_SUPPORT, 1604 DRM_MODE_CONNECTOR_DVII, 1605 &ddc_i2c, 1606 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1607 &hpd); 1608 1609 /* VGA - primary dac */ 1610 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1611 hpd.hpd = RADEON_HPD_NONE; 1612 radeon_add_legacy_encoder(dev, 1613 radeon_get_encoder_enum(dev, 1614 ATOM_DEVICE_CRT1_SUPPORT, 1615 1), 1616 ATOM_DEVICE_CRT1_SUPPORT); 1617 radeon_add_legacy_connector(dev, 1, 1618 ATOM_DEVICE_CRT1_SUPPORT, 1619 DRM_MODE_CONNECTOR_VGA, 1620 &ddc_i2c, 1621 CONNECTOR_OBJECT_ID_VGA, 1622 &hpd); 1623 } 1624 1625 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1626 /* TV - tv dac */ 1627 ddc_i2c.valid = false; 1628 hpd.hpd = RADEON_HPD_NONE; 1629 radeon_add_legacy_encoder(dev, 1630 radeon_get_encoder_enum(dev, 1631 ATOM_DEVICE_TV1_SUPPORT, 1632 2), 1633 ATOM_DEVICE_TV1_SUPPORT); 1634 radeon_add_legacy_connector(dev, 2, 1635 ATOM_DEVICE_TV1_SUPPORT, 1636 DRM_MODE_CONNECTOR_SVIDEO, 1637 &ddc_i2c, 1638 CONNECTOR_OBJECT_ID_SVIDEO, 1639 &hpd); 1640 } 1641 break; 1642 case CT_IBOOK: 1643 DRM_INFO("Connector Table: %d (ibook)\n", 1644 rdev->mode_info.connector_table); 1645 /* LVDS */ 1646 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1647 hpd.hpd = RADEON_HPD_NONE; 1648 radeon_add_legacy_encoder(dev, 1649 radeon_get_encoder_enum(dev, 1650 ATOM_DEVICE_LCD1_SUPPORT, 1651 0), 1652 ATOM_DEVICE_LCD1_SUPPORT); 1653 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1654 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1655 CONNECTOR_OBJECT_ID_LVDS, 1656 &hpd); 1657 /* VGA - TV DAC */ 1658 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1659 hpd.hpd = RADEON_HPD_NONE; 1660 radeon_add_legacy_encoder(dev, 1661 radeon_get_encoder_enum(dev, 1662 ATOM_DEVICE_CRT2_SUPPORT, 1663 2), 1664 ATOM_DEVICE_CRT2_SUPPORT); 1665 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1666 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1667 CONNECTOR_OBJECT_ID_VGA, 1668 &hpd); 1669 /* TV - TV DAC */ 1670 ddc_i2c.valid = false; 1671 hpd.hpd = RADEON_HPD_NONE; 1672 radeon_add_legacy_encoder(dev, 1673 radeon_get_encoder_enum(dev, 1674 ATOM_DEVICE_TV1_SUPPORT, 1675 2), 1676 ATOM_DEVICE_TV1_SUPPORT); 1677 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1678 DRM_MODE_CONNECTOR_SVIDEO, 1679 &ddc_i2c, 1680 CONNECTOR_OBJECT_ID_SVIDEO, 1681 &hpd); 1682 break; 1683 case CT_POWERBOOK_EXTERNAL: 1684 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1685 rdev->mode_info.connector_table); 1686 /* LVDS */ 1687 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1688 hpd.hpd = RADEON_HPD_NONE; 1689 radeon_add_legacy_encoder(dev, 1690 radeon_get_encoder_enum(dev, 1691 ATOM_DEVICE_LCD1_SUPPORT, 1692 0), 1693 ATOM_DEVICE_LCD1_SUPPORT); 1694 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1695 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1696 CONNECTOR_OBJECT_ID_LVDS, 1697 &hpd); 1698 /* DVI-I - primary dac, ext tmds */ 1699 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1700 hpd.hpd = RADEON_HPD_2; /* ??? */ 1701 radeon_add_legacy_encoder(dev, 1702 radeon_get_encoder_enum(dev, 1703 ATOM_DEVICE_DFP2_SUPPORT, 1704 0), 1705 ATOM_DEVICE_DFP2_SUPPORT); 1706 radeon_add_legacy_encoder(dev, 1707 radeon_get_encoder_enum(dev, 1708 ATOM_DEVICE_CRT1_SUPPORT, 1709 1), 1710 ATOM_DEVICE_CRT1_SUPPORT); 1711 /* XXX some are SL */ 1712 radeon_add_legacy_connector(dev, 1, 1713 ATOM_DEVICE_DFP2_SUPPORT | 1714 ATOM_DEVICE_CRT1_SUPPORT, 1715 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1716 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1717 &hpd); 1718 /* TV - TV DAC */ 1719 ddc_i2c.valid = false; 1720 hpd.hpd = RADEON_HPD_NONE; 1721 radeon_add_legacy_encoder(dev, 1722 radeon_get_encoder_enum(dev, 1723 ATOM_DEVICE_TV1_SUPPORT, 1724 2), 1725 ATOM_DEVICE_TV1_SUPPORT); 1726 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1727 DRM_MODE_CONNECTOR_SVIDEO, 1728 &ddc_i2c, 1729 CONNECTOR_OBJECT_ID_SVIDEO, 1730 &hpd); 1731 break; 1732 case CT_POWERBOOK_INTERNAL: 1733 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1734 rdev->mode_info.connector_table); 1735 /* LVDS */ 1736 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1737 hpd.hpd = RADEON_HPD_NONE; 1738 radeon_add_legacy_encoder(dev, 1739 radeon_get_encoder_enum(dev, 1740 ATOM_DEVICE_LCD1_SUPPORT, 1741 0), 1742 ATOM_DEVICE_LCD1_SUPPORT); 1743 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1744 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1745 CONNECTOR_OBJECT_ID_LVDS, 1746 &hpd); 1747 /* DVI-I - primary dac, int tmds */ 1748 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1749 hpd.hpd = RADEON_HPD_1; /* ??? */ 1750 radeon_add_legacy_encoder(dev, 1751 radeon_get_encoder_enum(dev, 1752 ATOM_DEVICE_DFP1_SUPPORT, 1753 0), 1754 ATOM_DEVICE_DFP1_SUPPORT); 1755 radeon_add_legacy_encoder(dev, 1756 radeon_get_encoder_enum(dev, 1757 ATOM_DEVICE_CRT1_SUPPORT, 1758 1), 1759 ATOM_DEVICE_CRT1_SUPPORT); 1760 radeon_add_legacy_connector(dev, 1, 1761 ATOM_DEVICE_DFP1_SUPPORT | 1762 ATOM_DEVICE_CRT1_SUPPORT, 1763 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1764 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1765 &hpd); 1766 /* TV - TV DAC */ 1767 ddc_i2c.valid = false; 1768 hpd.hpd = RADEON_HPD_NONE; 1769 radeon_add_legacy_encoder(dev, 1770 radeon_get_encoder_enum(dev, 1771 ATOM_DEVICE_TV1_SUPPORT, 1772 2), 1773 ATOM_DEVICE_TV1_SUPPORT); 1774 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1775 DRM_MODE_CONNECTOR_SVIDEO, 1776 &ddc_i2c, 1777 CONNECTOR_OBJECT_ID_SVIDEO, 1778 &hpd); 1779 break; 1780 case CT_POWERBOOK_VGA: 1781 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1782 rdev->mode_info.connector_table); 1783 /* LVDS */ 1784 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1785 hpd.hpd = RADEON_HPD_NONE; 1786 radeon_add_legacy_encoder(dev, 1787 radeon_get_encoder_enum(dev, 1788 ATOM_DEVICE_LCD1_SUPPORT, 1789 0), 1790 ATOM_DEVICE_LCD1_SUPPORT); 1791 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1792 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1793 CONNECTOR_OBJECT_ID_LVDS, 1794 &hpd); 1795 /* VGA - primary dac */ 1796 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1797 hpd.hpd = RADEON_HPD_NONE; 1798 radeon_add_legacy_encoder(dev, 1799 radeon_get_encoder_enum(dev, 1800 ATOM_DEVICE_CRT1_SUPPORT, 1801 1), 1802 ATOM_DEVICE_CRT1_SUPPORT); 1803 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1804 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1805 CONNECTOR_OBJECT_ID_VGA, 1806 &hpd); 1807 /* TV - TV DAC */ 1808 ddc_i2c.valid = false; 1809 hpd.hpd = RADEON_HPD_NONE; 1810 radeon_add_legacy_encoder(dev, 1811 radeon_get_encoder_enum(dev, 1812 ATOM_DEVICE_TV1_SUPPORT, 1813 2), 1814 ATOM_DEVICE_TV1_SUPPORT); 1815 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1816 DRM_MODE_CONNECTOR_SVIDEO, 1817 &ddc_i2c, 1818 CONNECTOR_OBJECT_ID_SVIDEO, 1819 &hpd); 1820 break; 1821 case CT_MINI_EXTERNAL: 1822 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1823 rdev->mode_info.connector_table); 1824 /* DVI-I - tv dac, ext tmds */ 1825 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1826 hpd.hpd = RADEON_HPD_2; /* ??? */ 1827 radeon_add_legacy_encoder(dev, 1828 radeon_get_encoder_enum(dev, 1829 ATOM_DEVICE_DFP2_SUPPORT, 1830 0), 1831 ATOM_DEVICE_DFP2_SUPPORT); 1832 radeon_add_legacy_encoder(dev, 1833 radeon_get_encoder_enum(dev, 1834 ATOM_DEVICE_CRT2_SUPPORT, 1835 2), 1836 ATOM_DEVICE_CRT2_SUPPORT); 1837 /* XXX are any DL? */ 1838 radeon_add_legacy_connector(dev, 0, 1839 ATOM_DEVICE_DFP2_SUPPORT | 1840 ATOM_DEVICE_CRT2_SUPPORT, 1841 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1842 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1843 &hpd); 1844 /* TV - TV DAC */ 1845 ddc_i2c.valid = false; 1846 hpd.hpd = RADEON_HPD_NONE; 1847 radeon_add_legacy_encoder(dev, 1848 radeon_get_encoder_enum(dev, 1849 ATOM_DEVICE_TV1_SUPPORT, 1850 2), 1851 ATOM_DEVICE_TV1_SUPPORT); 1852 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1853 DRM_MODE_CONNECTOR_SVIDEO, 1854 &ddc_i2c, 1855 CONNECTOR_OBJECT_ID_SVIDEO, 1856 &hpd); 1857 break; 1858 case CT_MINI_INTERNAL: 1859 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1860 rdev->mode_info.connector_table); 1861 /* DVI-I - tv dac, int tmds */ 1862 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1863 hpd.hpd = RADEON_HPD_1; /* ??? */ 1864 radeon_add_legacy_encoder(dev, 1865 radeon_get_encoder_enum(dev, 1866 ATOM_DEVICE_DFP1_SUPPORT, 1867 0), 1868 ATOM_DEVICE_DFP1_SUPPORT); 1869 radeon_add_legacy_encoder(dev, 1870 radeon_get_encoder_enum(dev, 1871 ATOM_DEVICE_CRT2_SUPPORT, 1872 2), 1873 ATOM_DEVICE_CRT2_SUPPORT); 1874 radeon_add_legacy_connector(dev, 0, 1875 ATOM_DEVICE_DFP1_SUPPORT | 1876 ATOM_DEVICE_CRT2_SUPPORT, 1877 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1878 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1879 &hpd); 1880 /* TV - TV DAC */ 1881 ddc_i2c.valid = false; 1882 hpd.hpd = RADEON_HPD_NONE; 1883 radeon_add_legacy_encoder(dev, 1884 radeon_get_encoder_enum(dev, 1885 ATOM_DEVICE_TV1_SUPPORT, 1886 2), 1887 ATOM_DEVICE_TV1_SUPPORT); 1888 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1889 DRM_MODE_CONNECTOR_SVIDEO, 1890 &ddc_i2c, 1891 CONNECTOR_OBJECT_ID_SVIDEO, 1892 &hpd); 1893 break; 1894 case CT_IMAC_G5_ISIGHT: 1895 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1896 rdev->mode_info.connector_table); 1897 /* DVI-D - int tmds */ 1898 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1899 hpd.hpd = RADEON_HPD_1; /* ??? */ 1900 radeon_add_legacy_encoder(dev, 1901 radeon_get_encoder_enum(dev, 1902 ATOM_DEVICE_DFP1_SUPPORT, 1903 0), 1904 ATOM_DEVICE_DFP1_SUPPORT); 1905 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1906 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1907 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1908 &hpd); 1909 /* VGA - tv dac */ 1910 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1911 hpd.hpd = RADEON_HPD_NONE; 1912 radeon_add_legacy_encoder(dev, 1913 radeon_get_encoder_enum(dev, 1914 ATOM_DEVICE_CRT2_SUPPORT, 1915 2), 1916 ATOM_DEVICE_CRT2_SUPPORT); 1917 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1918 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1919 CONNECTOR_OBJECT_ID_VGA, 1920 &hpd); 1921 /* TV - TV DAC */ 1922 ddc_i2c.valid = false; 1923 hpd.hpd = RADEON_HPD_NONE; 1924 radeon_add_legacy_encoder(dev, 1925 radeon_get_encoder_enum(dev, 1926 ATOM_DEVICE_TV1_SUPPORT, 1927 2), 1928 ATOM_DEVICE_TV1_SUPPORT); 1929 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1930 DRM_MODE_CONNECTOR_SVIDEO, 1931 &ddc_i2c, 1932 CONNECTOR_OBJECT_ID_SVIDEO, 1933 &hpd); 1934 break; 1935 case CT_EMAC: 1936 DRM_INFO("Connector Table: %d (emac)\n", 1937 rdev->mode_info.connector_table); 1938 /* VGA - primary dac */ 1939 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1940 hpd.hpd = RADEON_HPD_NONE; 1941 radeon_add_legacy_encoder(dev, 1942 radeon_get_encoder_enum(dev, 1943 ATOM_DEVICE_CRT1_SUPPORT, 1944 1), 1945 ATOM_DEVICE_CRT1_SUPPORT); 1946 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1947 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1948 CONNECTOR_OBJECT_ID_VGA, 1949 &hpd); 1950 /* VGA - tv dac */ 1951 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1952 hpd.hpd = RADEON_HPD_NONE; 1953 radeon_add_legacy_encoder(dev, 1954 radeon_get_encoder_enum(dev, 1955 ATOM_DEVICE_CRT2_SUPPORT, 1956 2), 1957 ATOM_DEVICE_CRT2_SUPPORT); 1958 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1959 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1960 CONNECTOR_OBJECT_ID_VGA, 1961 &hpd); 1962 /* TV - TV DAC */ 1963 ddc_i2c.valid = false; 1964 hpd.hpd = RADEON_HPD_NONE; 1965 radeon_add_legacy_encoder(dev, 1966 radeon_get_encoder_enum(dev, 1967 ATOM_DEVICE_TV1_SUPPORT, 1968 2), 1969 ATOM_DEVICE_TV1_SUPPORT); 1970 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1971 DRM_MODE_CONNECTOR_SVIDEO, 1972 &ddc_i2c, 1973 CONNECTOR_OBJECT_ID_SVIDEO, 1974 &hpd); 1975 break; 1976 case CT_RN50_POWER: 1977 DRM_INFO("Connector Table: %d (rn50-power)\n", 1978 rdev->mode_info.connector_table); 1979 /* VGA - primary dac */ 1980 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1981 hpd.hpd = RADEON_HPD_NONE; 1982 radeon_add_legacy_encoder(dev, 1983 radeon_get_encoder_enum(dev, 1984 ATOM_DEVICE_CRT1_SUPPORT, 1985 1), 1986 ATOM_DEVICE_CRT1_SUPPORT); 1987 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1988 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1989 CONNECTOR_OBJECT_ID_VGA, 1990 &hpd); 1991 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1992 hpd.hpd = RADEON_HPD_NONE; 1993 radeon_add_legacy_encoder(dev, 1994 radeon_get_encoder_enum(dev, 1995 ATOM_DEVICE_CRT2_SUPPORT, 1996 2), 1997 ATOM_DEVICE_CRT2_SUPPORT); 1998 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1999 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2000 CONNECTOR_OBJECT_ID_VGA, 2001 &hpd); 2002 break; 2003 case CT_MAC_X800: 2004 DRM_INFO("Connector Table: %d (mac x800)\n", 2005 rdev->mode_info.connector_table); 2006 /* DVI - primary dac, internal tmds */ 2007 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2008 hpd.hpd = RADEON_HPD_1; /* ??? */ 2009 radeon_add_legacy_encoder(dev, 2010 radeon_get_encoder_enum(dev, 2011 ATOM_DEVICE_DFP1_SUPPORT, 2012 0), 2013 ATOM_DEVICE_DFP1_SUPPORT); 2014 radeon_add_legacy_encoder(dev, 2015 radeon_get_encoder_enum(dev, 2016 ATOM_DEVICE_CRT1_SUPPORT, 2017 1), 2018 ATOM_DEVICE_CRT1_SUPPORT); 2019 radeon_add_legacy_connector(dev, 0, 2020 ATOM_DEVICE_DFP1_SUPPORT | 2021 ATOM_DEVICE_CRT1_SUPPORT, 2022 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2023 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2024 &hpd); 2025 /* DVI - tv dac, dvo */ 2026 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2027 hpd.hpd = RADEON_HPD_2; /* ??? */ 2028 radeon_add_legacy_encoder(dev, 2029 radeon_get_encoder_enum(dev, 2030 ATOM_DEVICE_DFP2_SUPPORT, 2031 0), 2032 ATOM_DEVICE_DFP2_SUPPORT); 2033 radeon_add_legacy_encoder(dev, 2034 radeon_get_encoder_enum(dev, 2035 ATOM_DEVICE_CRT2_SUPPORT, 2036 2), 2037 ATOM_DEVICE_CRT2_SUPPORT); 2038 radeon_add_legacy_connector(dev, 1, 2039 ATOM_DEVICE_DFP2_SUPPORT | 2040 ATOM_DEVICE_CRT2_SUPPORT, 2041 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2042 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2043 &hpd); 2044 break; 2045 case CT_MAC_G5_9600: 2046 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2047 rdev->mode_info.connector_table); 2048 /* DVI - tv dac, dvo */ 2049 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2050 hpd.hpd = RADEON_HPD_1; /* ??? */ 2051 radeon_add_legacy_encoder(dev, 2052 radeon_get_encoder_enum(dev, 2053 ATOM_DEVICE_DFP2_SUPPORT, 2054 0), 2055 ATOM_DEVICE_DFP2_SUPPORT); 2056 radeon_add_legacy_encoder(dev, 2057 radeon_get_encoder_enum(dev, 2058 ATOM_DEVICE_CRT2_SUPPORT, 2059 2), 2060 ATOM_DEVICE_CRT2_SUPPORT); 2061 radeon_add_legacy_connector(dev, 0, 2062 ATOM_DEVICE_DFP2_SUPPORT | 2063 ATOM_DEVICE_CRT2_SUPPORT, 2064 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2065 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2066 &hpd); 2067 /* ADC - primary dac, internal tmds */ 2068 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2069 hpd.hpd = RADEON_HPD_2; /* ??? */ 2070 radeon_add_legacy_encoder(dev, 2071 radeon_get_encoder_enum(dev, 2072 ATOM_DEVICE_DFP1_SUPPORT, 2073 0), 2074 ATOM_DEVICE_DFP1_SUPPORT); 2075 radeon_add_legacy_encoder(dev, 2076 radeon_get_encoder_enum(dev, 2077 ATOM_DEVICE_CRT1_SUPPORT, 2078 1), 2079 ATOM_DEVICE_CRT1_SUPPORT); 2080 radeon_add_legacy_connector(dev, 1, 2081 ATOM_DEVICE_DFP1_SUPPORT | 2082 ATOM_DEVICE_CRT1_SUPPORT, 2083 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2084 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2085 &hpd); 2086 /* TV - TV DAC */ 2087 ddc_i2c.valid = false; 2088 hpd.hpd = RADEON_HPD_NONE; 2089 radeon_add_legacy_encoder(dev, 2090 radeon_get_encoder_enum(dev, 2091 ATOM_DEVICE_TV1_SUPPORT, 2092 2), 2093 ATOM_DEVICE_TV1_SUPPORT); 2094 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2095 DRM_MODE_CONNECTOR_SVIDEO, 2096 &ddc_i2c, 2097 CONNECTOR_OBJECT_ID_SVIDEO, 2098 &hpd); 2099 break; 2100 case CT_SAM440EP: 2101 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2102 rdev->mode_info.connector_table); 2103 /* LVDS */ 2104 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2105 hpd.hpd = RADEON_HPD_NONE; 2106 radeon_add_legacy_encoder(dev, 2107 radeon_get_encoder_enum(dev, 2108 ATOM_DEVICE_LCD1_SUPPORT, 2109 0), 2110 ATOM_DEVICE_LCD1_SUPPORT); 2111 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2112 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2113 CONNECTOR_OBJECT_ID_LVDS, 2114 &hpd); 2115 /* DVI-I - secondary dac, int tmds */ 2116 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2117 hpd.hpd = RADEON_HPD_1; /* ??? */ 2118 radeon_add_legacy_encoder(dev, 2119 radeon_get_encoder_enum(dev, 2120 ATOM_DEVICE_DFP1_SUPPORT, 2121 0), 2122 ATOM_DEVICE_DFP1_SUPPORT); 2123 radeon_add_legacy_encoder(dev, 2124 radeon_get_encoder_enum(dev, 2125 ATOM_DEVICE_CRT2_SUPPORT, 2126 2), 2127 ATOM_DEVICE_CRT2_SUPPORT); 2128 radeon_add_legacy_connector(dev, 1, 2129 ATOM_DEVICE_DFP1_SUPPORT | 2130 ATOM_DEVICE_CRT2_SUPPORT, 2131 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2132 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2133 &hpd); 2134 /* VGA - primary dac */ 2135 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2136 hpd.hpd = RADEON_HPD_NONE; 2137 radeon_add_legacy_encoder(dev, 2138 radeon_get_encoder_enum(dev, 2139 ATOM_DEVICE_CRT1_SUPPORT, 2140 1), 2141 ATOM_DEVICE_CRT1_SUPPORT); 2142 radeon_add_legacy_connector(dev, 2, 2143 ATOM_DEVICE_CRT1_SUPPORT, 2144 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2145 CONNECTOR_OBJECT_ID_VGA, 2146 &hpd); 2147 /* TV - TV DAC */ 2148 ddc_i2c.valid = false; 2149 hpd.hpd = RADEON_HPD_NONE; 2150 radeon_add_legacy_encoder(dev, 2151 radeon_get_encoder_enum(dev, 2152 ATOM_DEVICE_TV1_SUPPORT, 2153 2), 2154 ATOM_DEVICE_TV1_SUPPORT); 2155 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2156 DRM_MODE_CONNECTOR_SVIDEO, 2157 &ddc_i2c, 2158 CONNECTOR_OBJECT_ID_SVIDEO, 2159 &hpd); 2160 break; 2161 case CT_MAC_G4_SILVER: 2162 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2163 rdev->mode_info.connector_table); 2164 /* DVI-I - tv dac, int tmds */ 2165 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2166 hpd.hpd = RADEON_HPD_1; /* ??? */ 2167 radeon_add_legacy_encoder(dev, 2168 radeon_get_encoder_enum(dev, 2169 ATOM_DEVICE_DFP1_SUPPORT, 2170 0), 2171 ATOM_DEVICE_DFP1_SUPPORT); 2172 radeon_add_legacy_encoder(dev, 2173 radeon_get_encoder_enum(dev, 2174 ATOM_DEVICE_CRT2_SUPPORT, 2175 2), 2176 ATOM_DEVICE_CRT2_SUPPORT); 2177 radeon_add_legacy_connector(dev, 0, 2178 ATOM_DEVICE_DFP1_SUPPORT | 2179 ATOM_DEVICE_CRT2_SUPPORT, 2180 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2181 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2182 &hpd); 2183 /* VGA - primary dac */ 2184 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2185 hpd.hpd = RADEON_HPD_NONE; 2186 radeon_add_legacy_encoder(dev, 2187 radeon_get_encoder_enum(dev, 2188 ATOM_DEVICE_CRT1_SUPPORT, 2189 1), 2190 ATOM_DEVICE_CRT1_SUPPORT); 2191 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2192 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2193 CONNECTOR_OBJECT_ID_VGA, 2194 &hpd); 2195 /* TV - TV DAC */ 2196 ddc_i2c.valid = false; 2197 hpd.hpd = RADEON_HPD_NONE; 2198 radeon_add_legacy_encoder(dev, 2199 radeon_get_encoder_enum(dev, 2200 ATOM_DEVICE_TV1_SUPPORT, 2201 2), 2202 ATOM_DEVICE_TV1_SUPPORT); 2203 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2204 DRM_MODE_CONNECTOR_SVIDEO, 2205 &ddc_i2c, 2206 CONNECTOR_OBJECT_ID_SVIDEO, 2207 &hpd); 2208 break; 2209 default: 2210 DRM_INFO("Connector table: %d (invalid)\n", 2211 rdev->mode_info.connector_table); 2212 return false; 2213 } 2214 2215 radeon_link_encoder_connector(dev); 2216 2217 return true; 2218 } 2219 2220 static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2221 int bios_index, 2222 enum radeon_combios_connector 2223 *legacy_connector, 2224 struct radeon_i2c_bus_rec *ddc_i2c, 2225 struct radeon_hpd *hpd) 2226 { 2227 2228 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2229 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2230 if (dev->pdev->device == 0x515e && 2231 dev->pdev->subsystem_vendor == 0x1014) { 2232 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2233 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2234 return false; 2235 } 2236 2237 /* X300 card with extra non-existent DVI port */ 2238 if (dev->pdev->device == 0x5B60 && 2239 dev->pdev->subsystem_vendor == 0x17af && 2240 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2241 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2242 return false; 2243 } 2244 2245 return true; 2246 } 2247 2248 static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2249 { 2250 /* Acer 5102 has non-existent TV port */ 2251 if (dev->pdev->device == 0x5975 && 2252 dev->pdev->subsystem_vendor == 0x1025 && 2253 dev->pdev->subsystem_device == 0x009f) 2254 return false; 2255 2256 /* HP dc5750 has non-existent TV port */ 2257 if (dev->pdev->device == 0x5974 && 2258 dev->pdev->subsystem_vendor == 0x103c && 2259 dev->pdev->subsystem_device == 0x280a) 2260 return false; 2261 2262 /* MSI S270 has non-existent TV port */ 2263 if (dev->pdev->device == 0x5955 && 2264 dev->pdev->subsystem_vendor == 0x1462 && 2265 dev->pdev->subsystem_device == 0x0131) 2266 return false; 2267 2268 return true; 2269 } 2270 2271 static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2272 { 2273 struct radeon_device *rdev = dev->dev_private; 2274 uint32_t ext_tmds_info; 2275 2276 if (rdev->flags & RADEON_IS_IGP) { 2277 if (is_dvi_d) 2278 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2279 else 2280 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2281 } 2282 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2283 if (ext_tmds_info) { 2284 uint8_t rev = RBIOS8(ext_tmds_info); 2285 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2286 if (rev >= 3) { 2287 if (is_dvi_d) 2288 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2289 else 2290 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2291 } else { 2292 if (flags & 1) { 2293 if (is_dvi_d) 2294 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2295 else 2296 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2297 } 2298 } 2299 } 2300 if (is_dvi_d) 2301 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2302 else 2303 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2304 } 2305 2306 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2307 { 2308 struct radeon_device *rdev = dev->dev_private; 2309 uint32_t conn_info, entry, devices; 2310 uint16_t tmp, connector_object_id; 2311 enum radeon_combios_ddc ddc_type; 2312 enum radeon_combios_connector connector; 2313 int i = 0; 2314 struct radeon_i2c_bus_rec ddc_i2c; 2315 struct radeon_hpd hpd; 2316 2317 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2318 if (conn_info) { 2319 for (i = 0; i < 4; i++) { 2320 entry = conn_info + 2 + i * 2; 2321 2322 if (!RBIOS16(entry)) 2323 break; 2324 2325 tmp = RBIOS16(entry); 2326 2327 connector = (tmp >> 12) & 0xf; 2328 2329 ddc_type = (tmp >> 8) & 0xf; 2330 if (ddc_type == 5) 2331 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2332 else 2333 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2334 2335 switch (connector) { 2336 case CONNECTOR_PROPRIETARY_LEGACY: 2337 case CONNECTOR_DVI_I_LEGACY: 2338 case CONNECTOR_DVI_D_LEGACY: 2339 if ((tmp >> 4) & 0x1) 2340 hpd.hpd = RADEON_HPD_2; 2341 else 2342 hpd.hpd = RADEON_HPD_1; 2343 break; 2344 default: 2345 hpd.hpd = RADEON_HPD_NONE; 2346 break; 2347 } 2348 2349 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2350 &ddc_i2c, &hpd)) 2351 continue; 2352 2353 switch (connector) { 2354 case CONNECTOR_PROPRIETARY_LEGACY: 2355 if ((tmp >> 4) & 0x1) 2356 devices = ATOM_DEVICE_DFP2_SUPPORT; 2357 else 2358 devices = ATOM_DEVICE_DFP1_SUPPORT; 2359 radeon_add_legacy_encoder(dev, 2360 radeon_get_encoder_enum 2361 (dev, devices, 0), 2362 devices); 2363 radeon_add_legacy_connector(dev, i, devices, 2364 legacy_connector_convert 2365 [connector], 2366 &ddc_i2c, 2367 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2368 &hpd); 2369 break; 2370 case CONNECTOR_CRT_LEGACY: 2371 if (tmp & 0x1) { 2372 devices = ATOM_DEVICE_CRT2_SUPPORT; 2373 radeon_add_legacy_encoder(dev, 2374 radeon_get_encoder_enum 2375 (dev, 2376 ATOM_DEVICE_CRT2_SUPPORT, 2377 2), 2378 ATOM_DEVICE_CRT2_SUPPORT); 2379 } else { 2380 devices = ATOM_DEVICE_CRT1_SUPPORT; 2381 radeon_add_legacy_encoder(dev, 2382 radeon_get_encoder_enum 2383 (dev, 2384 ATOM_DEVICE_CRT1_SUPPORT, 2385 1), 2386 ATOM_DEVICE_CRT1_SUPPORT); 2387 } 2388 radeon_add_legacy_connector(dev, 2389 i, 2390 devices, 2391 legacy_connector_convert 2392 [connector], 2393 &ddc_i2c, 2394 CONNECTOR_OBJECT_ID_VGA, 2395 &hpd); 2396 break; 2397 case CONNECTOR_DVI_I_LEGACY: 2398 devices = 0; 2399 if (tmp & 0x1) { 2400 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2401 radeon_add_legacy_encoder(dev, 2402 radeon_get_encoder_enum 2403 (dev, 2404 ATOM_DEVICE_CRT2_SUPPORT, 2405 2), 2406 ATOM_DEVICE_CRT2_SUPPORT); 2407 } else { 2408 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2409 radeon_add_legacy_encoder(dev, 2410 radeon_get_encoder_enum 2411 (dev, 2412 ATOM_DEVICE_CRT1_SUPPORT, 2413 1), 2414 ATOM_DEVICE_CRT1_SUPPORT); 2415 } 2416 /* RV100 board with external TDMS bit mis-set. 2417 * Actually uses internal TMDS, clear the bit. 2418 */ 2419 if (dev->pdev->device == 0x5159 && 2420 dev->pdev->subsystem_vendor == 0x1014 && 2421 dev->pdev->subsystem_device == 0x029A) { 2422 tmp &= ~(1 << 4); 2423 } 2424 if ((tmp >> 4) & 0x1) { 2425 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2426 radeon_add_legacy_encoder(dev, 2427 radeon_get_encoder_enum 2428 (dev, 2429 ATOM_DEVICE_DFP2_SUPPORT, 2430 0), 2431 ATOM_DEVICE_DFP2_SUPPORT); 2432 connector_object_id = combios_check_dl_dvi(dev, 0); 2433 } else { 2434 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2435 radeon_add_legacy_encoder(dev, 2436 radeon_get_encoder_enum 2437 (dev, 2438 ATOM_DEVICE_DFP1_SUPPORT, 2439 0), 2440 ATOM_DEVICE_DFP1_SUPPORT); 2441 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2442 } 2443 radeon_add_legacy_connector(dev, 2444 i, 2445 devices, 2446 legacy_connector_convert 2447 [connector], 2448 &ddc_i2c, 2449 connector_object_id, 2450 &hpd); 2451 break; 2452 case CONNECTOR_DVI_D_LEGACY: 2453 if ((tmp >> 4) & 0x1) { 2454 devices = ATOM_DEVICE_DFP2_SUPPORT; 2455 connector_object_id = combios_check_dl_dvi(dev, 1); 2456 } else { 2457 devices = ATOM_DEVICE_DFP1_SUPPORT; 2458 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2459 } 2460 radeon_add_legacy_encoder(dev, 2461 radeon_get_encoder_enum 2462 (dev, devices, 0), 2463 devices); 2464 radeon_add_legacy_connector(dev, i, devices, 2465 legacy_connector_convert 2466 [connector], 2467 &ddc_i2c, 2468 connector_object_id, 2469 &hpd); 2470 break; 2471 case CONNECTOR_CTV_LEGACY: 2472 case CONNECTOR_STV_LEGACY: 2473 radeon_add_legacy_encoder(dev, 2474 radeon_get_encoder_enum 2475 (dev, 2476 ATOM_DEVICE_TV1_SUPPORT, 2477 2), 2478 ATOM_DEVICE_TV1_SUPPORT); 2479 radeon_add_legacy_connector(dev, i, 2480 ATOM_DEVICE_TV1_SUPPORT, 2481 legacy_connector_convert 2482 [connector], 2483 &ddc_i2c, 2484 CONNECTOR_OBJECT_ID_SVIDEO, 2485 &hpd); 2486 break; 2487 default: 2488 DRM_ERROR("Unknown connector type: %d\n", 2489 connector); 2490 continue; 2491 } 2492 2493 } 2494 } else { 2495 uint16_t tmds_info = 2496 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2497 if (tmds_info) { 2498 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2499 2500 radeon_add_legacy_encoder(dev, 2501 radeon_get_encoder_enum(dev, 2502 ATOM_DEVICE_CRT1_SUPPORT, 2503 1), 2504 ATOM_DEVICE_CRT1_SUPPORT); 2505 radeon_add_legacy_encoder(dev, 2506 radeon_get_encoder_enum(dev, 2507 ATOM_DEVICE_DFP1_SUPPORT, 2508 0), 2509 ATOM_DEVICE_DFP1_SUPPORT); 2510 2511 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2512 hpd.hpd = RADEON_HPD_1; 2513 radeon_add_legacy_connector(dev, 2514 0, 2515 ATOM_DEVICE_CRT1_SUPPORT | 2516 ATOM_DEVICE_DFP1_SUPPORT, 2517 DRM_MODE_CONNECTOR_DVII, 2518 &ddc_i2c, 2519 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2520 &hpd); 2521 } else { 2522 uint16_t crt_info = 2523 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2524 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2525 if (crt_info) { 2526 radeon_add_legacy_encoder(dev, 2527 radeon_get_encoder_enum(dev, 2528 ATOM_DEVICE_CRT1_SUPPORT, 2529 1), 2530 ATOM_DEVICE_CRT1_SUPPORT); 2531 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2532 hpd.hpd = RADEON_HPD_NONE; 2533 radeon_add_legacy_connector(dev, 2534 0, 2535 ATOM_DEVICE_CRT1_SUPPORT, 2536 DRM_MODE_CONNECTOR_VGA, 2537 &ddc_i2c, 2538 CONNECTOR_OBJECT_ID_VGA, 2539 &hpd); 2540 } else { 2541 DRM_DEBUG_KMS("No connector info found\n"); 2542 return false; 2543 } 2544 } 2545 } 2546 2547 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2548 uint16_t lcd_info = 2549 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2550 if (lcd_info) { 2551 uint16_t lcd_ddc_info = 2552 combios_get_table_offset(dev, 2553 COMBIOS_LCD_DDC_INFO_TABLE); 2554 2555 radeon_add_legacy_encoder(dev, 2556 radeon_get_encoder_enum(dev, 2557 ATOM_DEVICE_LCD1_SUPPORT, 2558 0), 2559 ATOM_DEVICE_LCD1_SUPPORT); 2560 2561 if (lcd_ddc_info) { 2562 ddc_type = RBIOS8(lcd_ddc_info + 2); 2563 switch (ddc_type) { 2564 case DDC_LCD: 2565 ddc_i2c = 2566 combios_setup_i2c_bus(rdev, 2567 DDC_LCD, 2568 RBIOS32(lcd_ddc_info + 3), 2569 RBIOS32(lcd_ddc_info + 7)); 2570 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2571 break; 2572 case DDC_GPIO: 2573 ddc_i2c = 2574 combios_setup_i2c_bus(rdev, 2575 DDC_GPIO, 2576 RBIOS32(lcd_ddc_info + 3), 2577 RBIOS32(lcd_ddc_info + 7)); 2578 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2579 break; 2580 default: 2581 ddc_i2c = 2582 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2583 break; 2584 } 2585 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2586 } else 2587 ddc_i2c.valid = false; 2588 2589 hpd.hpd = RADEON_HPD_NONE; 2590 radeon_add_legacy_connector(dev, 2591 5, 2592 ATOM_DEVICE_LCD1_SUPPORT, 2593 DRM_MODE_CONNECTOR_LVDS, 2594 &ddc_i2c, 2595 CONNECTOR_OBJECT_ID_LVDS, 2596 &hpd); 2597 } 2598 } 2599 2600 /* check TV table */ 2601 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2602 uint32_t tv_info = 2603 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2604 if (tv_info) { 2605 if (RBIOS8(tv_info + 6) == 'T') { 2606 if (radeon_apply_legacy_tv_quirks(dev)) { 2607 hpd.hpd = RADEON_HPD_NONE; 2608 ddc_i2c.valid = false; 2609 radeon_add_legacy_encoder(dev, 2610 radeon_get_encoder_enum 2611 (dev, 2612 ATOM_DEVICE_TV1_SUPPORT, 2613 2), 2614 ATOM_DEVICE_TV1_SUPPORT); 2615 radeon_add_legacy_connector(dev, 6, 2616 ATOM_DEVICE_TV1_SUPPORT, 2617 DRM_MODE_CONNECTOR_SVIDEO, 2618 &ddc_i2c, 2619 CONNECTOR_OBJECT_ID_SVIDEO, 2620 &hpd); 2621 } 2622 } 2623 } 2624 } 2625 2626 radeon_link_encoder_connector(dev); 2627 2628 return true; 2629 } 2630 2631 #ifdef DRMDEBUG 2632 static const char *thermal_controller_names[] = { 2633 "NONE", 2634 "lm63", 2635 "adm1032", 2636 }; 2637 #endif 2638 2639 void radeon_combios_get_power_modes(struct radeon_device *rdev) 2640 { 2641 struct drm_device *dev = rdev->ddev; 2642 u16 offset, misc, misc2 = 0; 2643 u8 rev, blocks, tmp; 2644 int state_index = 0; 2645 struct radeon_i2c_bus_rec i2c_bus; 2646 2647 rdev->pm.default_power_state_index = -1; 2648 2649 /* allocate 2 power states */ 2650 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); 2651 if (rdev->pm.power_state) { 2652 /* allocate 1 clock mode per state */ 2653 rdev->pm.power_state[0].clock_info = 2654 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2655 rdev->pm.power_state[1].clock_info = 2656 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL); 2657 if (!rdev->pm.power_state[0].clock_info || 2658 !rdev->pm.power_state[1].clock_info) 2659 goto pm_failed; 2660 } else 2661 goto pm_failed; 2662 2663 /* check for a thermal chip */ 2664 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2665 if (offset) { 2666 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2667 2668 rev = RBIOS8(offset); 2669 2670 if (rev == 0) { 2671 thermal_controller = RBIOS8(offset + 3); 2672 gpio = RBIOS8(offset + 4) & 0x3f; 2673 i2c_addr = RBIOS8(offset + 5); 2674 } else if (rev == 1) { 2675 thermal_controller = RBIOS8(offset + 4); 2676 gpio = RBIOS8(offset + 5) & 0x3f; 2677 i2c_addr = RBIOS8(offset + 6); 2678 } else if (rev == 2) { 2679 thermal_controller = RBIOS8(offset + 4); 2680 gpio = RBIOS8(offset + 5) & 0x3f; 2681 i2c_addr = RBIOS8(offset + 6); 2682 clk_bit = RBIOS8(offset + 0xa); 2683 data_bit = RBIOS8(offset + 0xb); 2684 } 2685 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2686 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2687 thermal_controller_names[thermal_controller], 2688 i2c_addr >> 1); 2689 if (gpio == DDC_LCD) { 2690 /* MM i2c */ 2691 i2c_bus.valid = true; 2692 i2c_bus.hw_capable = true; 2693 i2c_bus.mm_i2c = true; 2694 i2c_bus.i2c_id = 0xa0; 2695 } else if (gpio == DDC_GPIO) 2696 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2697 else 2698 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2699 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2700 #ifdef notyet 2701 if (rdev->pm.i2c_bus) { 2702 struct i2c_board_info info = { }; 2703 const char *name = thermal_controller_names[thermal_controller]; 2704 info.addr = i2c_addr >> 1; 2705 strlcpy(info.type, name, sizeof(info.type)); 2706 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2707 } 2708 #endif 2709 } 2710 } else { 2711 /* boards with a thermal chip, but no overdrive table */ 2712 2713 /* Asus 9600xt has an f75375 on the monid bus */ 2714 if ((dev->pdev->device == 0x4152) && 2715 (dev->pdev->subsystem_vendor == 0x1043) && 2716 (dev->pdev->subsystem_device == 0xc002)) { 2717 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2718 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2719 #ifdef notyet 2720 if (rdev->pm.i2c_bus) { 2721 struct i2c_board_info info = { }; 2722 const char *name = "f75375"; 2723 info.addr = 0x28; 2724 strlcpy(info.type, name, sizeof(info.type)); 2725 i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); 2726 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2727 name, info.addr); 2728 } 2729 #endif 2730 } 2731 } 2732 2733 if (rdev->flags & RADEON_IS_MOBILITY) { 2734 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2735 if (offset) { 2736 rev = RBIOS8(offset); 2737 blocks = RBIOS8(offset + 0x2); 2738 /* power mode 0 tends to be the only valid one */ 2739 rdev->pm.power_state[state_index].num_clock_modes = 1; 2740 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2741 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2742 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2743 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2744 goto default_mode; 2745 rdev->pm.power_state[state_index].type = 2746 POWER_STATE_TYPE_BATTERY; 2747 misc = RBIOS16(offset + 0x5 + 0x0); 2748 if (rev > 4) 2749 misc2 = RBIOS16(offset + 0x5 + 0xe); 2750 rdev->pm.power_state[state_index].misc = misc; 2751 rdev->pm.power_state[state_index].misc2 = misc2; 2752 if (misc & 0x4) { 2753 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2754 if (misc & 0x8) 2755 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2756 true; 2757 else 2758 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2759 false; 2760 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2761 if (rev < 6) { 2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2763 RBIOS16(offset + 0x5 + 0xb) * 4; 2764 tmp = RBIOS8(offset + 0x5 + 0xd); 2765 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2766 } else { 2767 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2768 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2769 if (entries && voltage_table_offset) { 2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2771 RBIOS16(voltage_table_offset) * 4; 2772 tmp = RBIOS8(voltage_table_offset + 0x2); 2773 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2774 } else 2775 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2776 } 2777 switch ((misc2 & 0x700) >> 8) { 2778 case 0: 2779 default: 2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2781 break; 2782 case 1: 2783 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2784 break; 2785 case 2: 2786 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2787 break; 2788 case 3: 2789 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2790 break; 2791 case 4: 2792 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2793 break; 2794 } 2795 } else 2796 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2797 if (rev > 6) 2798 rdev->pm.power_state[state_index].pcie_lanes = 2799 RBIOS8(offset + 0x5 + 0x10); 2800 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2801 state_index++; 2802 } else { 2803 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2804 } 2805 } else { 2806 /* XXX figure out some good default low power mode for desktop cards */ 2807 } 2808 2809 default_mode: 2810 /* add the default mode */ 2811 rdev->pm.power_state[state_index].type = 2812 POWER_STATE_TYPE_DEFAULT; 2813 rdev->pm.power_state[state_index].num_clock_modes = 1; 2814 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2815 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2816 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2817 if ((state_index > 0) && 2818 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2819 rdev->pm.power_state[state_index].clock_info[0].voltage = 2820 rdev->pm.power_state[0].clock_info[0].voltage; 2821 else 2822 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2823 rdev->pm.power_state[state_index].pcie_lanes = 16; 2824 rdev->pm.power_state[state_index].flags = 0; 2825 rdev->pm.default_power_state_index = state_index; 2826 rdev->pm.num_power_states = state_index + 1; 2827 2828 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2829 rdev->pm.current_clock_mode_index = 0; 2830 return; 2831 2832 pm_failed: 2833 rdev->pm.default_power_state_index = state_index; 2834 rdev->pm.num_power_states = 0; 2835 2836 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2837 rdev->pm.current_clock_mode_index = 0; 2838 } 2839 2840 void radeon_external_tmds_setup(struct drm_encoder *encoder) 2841 { 2842 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2843 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2844 2845 if (!tmds) 2846 return; 2847 2848 switch (tmds->dvo_chip) { 2849 case DVO_SIL164: 2850 /* sil 164 */ 2851 radeon_i2c_put_byte(tmds->i2c_bus, 2852 tmds->slave_addr, 2853 0x08, 0x30); 2854 radeon_i2c_put_byte(tmds->i2c_bus, 2855 tmds->slave_addr, 2856 0x09, 0x00); 2857 radeon_i2c_put_byte(tmds->i2c_bus, 2858 tmds->slave_addr, 2859 0x0a, 0x90); 2860 radeon_i2c_put_byte(tmds->i2c_bus, 2861 tmds->slave_addr, 2862 0x0c, 0x89); 2863 radeon_i2c_put_byte(tmds->i2c_bus, 2864 tmds->slave_addr, 2865 0x08, 0x3b); 2866 break; 2867 case DVO_SIL1178: 2868 /* sil 1178 - untested */ 2869 /* 2870 * 0x0f, 0x44 2871 * 0x0f, 0x4c 2872 * 0x0e, 0x01 2873 * 0x0a, 0x80 2874 * 0x09, 0x30 2875 * 0x0c, 0xc9 2876 * 0x0d, 0x70 2877 * 0x08, 0x32 2878 * 0x08, 0x33 2879 */ 2880 break; 2881 default: 2882 break; 2883 } 2884 2885 } 2886 2887 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2888 { 2889 struct drm_device *dev = encoder->dev; 2890 struct radeon_device *rdev = dev->dev_private; 2891 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2892 uint16_t offset; 2893 uint8_t blocks, slave_addr, rev; 2894 uint32_t index, id; 2895 uint32_t reg, val, and_mask, or_mask; 2896 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2897 2898 if (!tmds) 2899 return false; 2900 2901 if (rdev->flags & RADEON_IS_IGP) { 2902 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2903 rev = RBIOS8(offset); 2904 if (offset) { 2905 rev = RBIOS8(offset); 2906 if (rev > 1) { 2907 blocks = RBIOS8(offset + 3); 2908 index = offset + 4; 2909 while (blocks > 0) { 2910 id = RBIOS16(index); 2911 index += 2; 2912 switch (id >> 13) { 2913 case 0: 2914 reg = (id & 0x1fff) * 4; 2915 val = RBIOS32(index); 2916 index += 4; 2917 WREG32(reg, val); 2918 break; 2919 case 2: 2920 reg = (id & 0x1fff) * 4; 2921 and_mask = RBIOS32(index); 2922 index += 4; 2923 or_mask = RBIOS32(index); 2924 index += 4; 2925 val = RREG32(reg); 2926 val = (val & and_mask) | or_mask; 2927 WREG32(reg, val); 2928 break; 2929 case 3: 2930 val = RBIOS16(index); 2931 index += 2; 2932 udelay(val); 2933 break; 2934 case 4: 2935 val = RBIOS16(index); 2936 index += 2; 2937 mdelay(val); 2938 break; 2939 case 6: 2940 slave_addr = id & 0xff; 2941 slave_addr >>= 1; /* 7 bit addressing */ 2942 index++; 2943 reg = RBIOS8(index); 2944 index++; 2945 val = RBIOS8(index); 2946 index++; 2947 radeon_i2c_put_byte(tmds->i2c_bus, 2948 slave_addr, 2949 reg, val); 2950 break; 2951 default: 2952 DRM_ERROR("Unknown id %d\n", id >> 13); 2953 break; 2954 } 2955 blocks--; 2956 } 2957 return true; 2958 } 2959 } 2960 } else { 2961 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2962 if (offset) { 2963 index = offset + 10; 2964 id = RBIOS16(index); 2965 while (id != 0xffff) { 2966 index += 2; 2967 switch (id >> 13) { 2968 case 0: 2969 reg = (id & 0x1fff) * 4; 2970 val = RBIOS32(index); 2971 WREG32(reg, val); 2972 break; 2973 case 2: 2974 reg = (id & 0x1fff) * 4; 2975 and_mask = RBIOS32(index); 2976 index += 4; 2977 or_mask = RBIOS32(index); 2978 index += 4; 2979 val = RREG32(reg); 2980 val = (val & and_mask) | or_mask; 2981 WREG32(reg, val); 2982 break; 2983 case 4: 2984 val = RBIOS16(index); 2985 index += 2; 2986 udelay(val); 2987 break; 2988 case 5: 2989 reg = id & 0x1fff; 2990 and_mask = RBIOS32(index); 2991 index += 4; 2992 or_mask = RBIOS32(index); 2993 index += 4; 2994 val = RREG32_PLL(reg); 2995 val = (val & and_mask) | or_mask; 2996 WREG32_PLL(reg, val); 2997 break; 2998 case 6: 2999 reg = id & 0x1fff; 3000 val = RBIOS8(index); 3001 index += 1; 3002 radeon_i2c_put_byte(tmds->i2c_bus, 3003 tmds->slave_addr, 3004 reg, val); 3005 break; 3006 default: 3007 DRM_ERROR("Unknown id %d\n", id >> 13); 3008 break; 3009 } 3010 id = RBIOS16(index); 3011 } 3012 return true; 3013 } 3014 } 3015 return false; 3016 } 3017 3018 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3019 { 3020 struct radeon_device *rdev = dev->dev_private; 3021 3022 if (offset) { 3023 while (RBIOS16(offset)) { 3024 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3025 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3026 uint32_t val, and_mask, or_mask; 3027 uint32_t tmp; 3028 3029 offset += 2; 3030 switch (cmd) { 3031 case 0: 3032 val = RBIOS32(offset); 3033 offset += 4; 3034 WREG32(addr, val); 3035 break; 3036 case 1: 3037 val = RBIOS32(offset); 3038 offset += 4; 3039 WREG32(addr, val); 3040 break; 3041 case 2: 3042 and_mask = RBIOS32(offset); 3043 offset += 4; 3044 or_mask = RBIOS32(offset); 3045 offset += 4; 3046 tmp = RREG32(addr); 3047 tmp &= and_mask; 3048 tmp |= or_mask; 3049 WREG32(addr, tmp); 3050 break; 3051 case 3: 3052 and_mask = RBIOS32(offset); 3053 offset += 4; 3054 or_mask = RBIOS32(offset); 3055 offset += 4; 3056 tmp = RREG32(addr); 3057 tmp &= and_mask; 3058 tmp |= or_mask; 3059 WREG32(addr, tmp); 3060 break; 3061 case 4: 3062 val = RBIOS16(offset); 3063 offset += 2; 3064 udelay(val); 3065 break; 3066 case 5: 3067 val = RBIOS16(offset); 3068 offset += 2; 3069 switch (addr) { 3070 case 8: 3071 while (val--) { 3072 if (! 3073 (RREG32_PLL 3074 (RADEON_CLK_PWRMGT_CNTL) & 3075 RADEON_MC_BUSY)) 3076 break; 3077 } 3078 break; 3079 case 9: 3080 while (val--) { 3081 if ((RREG32(RADEON_MC_STATUS) & 3082 RADEON_MC_IDLE)) 3083 break; 3084 } 3085 break; 3086 default: 3087 break; 3088 } 3089 break; 3090 default: 3091 break; 3092 } 3093 } 3094 } 3095 } 3096 3097 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3098 { 3099 struct radeon_device *rdev = dev->dev_private; 3100 3101 if (offset) { 3102 while (RBIOS8(offset)) { 3103 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3104 uint8_t addr = (RBIOS8(offset) & 0x3f); 3105 uint32_t val, shift, tmp; 3106 uint32_t and_mask, or_mask; 3107 3108 offset++; 3109 switch (cmd) { 3110 case 0: 3111 val = RBIOS32(offset); 3112 offset += 4; 3113 WREG32_PLL(addr, val); 3114 break; 3115 case 1: 3116 shift = RBIOS8(offset) * 8; 3117 offset++; 3118 and_mask = RBIOS8(offset) << shift; 3119 and_mask |= ~(0xff << shift); 3120 offset++; 3121 or_mask = RBIOS8(offset) << shift; 3122 offset++; 3123 tmp = RREG32_PLL(addr); 3124 tmp &= and_mask; 3125 tmp |= or_mask; 3126 WREG32_PLL(addr, tmp); 3127 break; 3128 case 2: 3129 case 3: 3130 tmp = 1000; 3131 switch (addr) { 3132 case 1: 3133 udelay(150); 3134 break; 3135 case 2: 3136 mdelay(1); 3137 break; 3138 case 3: 3139 while (tmp--) { 3140 if (! 3141 (RREG32_PLL 3142 (RADEON_CLK_PWRMGT_CNTL) & 3143 RADEON_MC_BUSY)) 3144 break; 3145 } 3146 break; 3147 case 4: 3148 while (tmp--) { 3149 if (RREG32_PLL 3150 (RADEON_CLK_PWRMGT_CNTL) & 3151 RADEON_DLL_READY) 3152 break; 3153 } 3154 break; 3155 case 5: 3156 tmp = 3157 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3158 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3159 #if 0 3160 uint32_t mclk_cntl = 3161 RREG32_PLL 3162 (RADEON_MCLK_CNTL); 3163 mclk_cntl &= 0xffff0000; 3164 /*mclk_cntl |= 0x00001111;*//* ??? */ 3165 WREG32_PLL(RADEON_MCLK_CNTL, 3166 mclk_cntl); 3167 mdelay(10); 3168 #endif 3169 WREG32_PLL 3170 (RADEON_CLK_PWRMGT_CNTL, 3171 tmp & 3172 ~RADEON_CG_NO1_DEBUG_0); 3173 mdelay(10); 3174 } 3175 break; 3176 default: 3177 break; 3178 } 3179 break; 3180 default: 3181 break; 3182 } 3183 } 3184 } 3185 } 3186 3187 static void combios_parse_ram_reset_table(struct drm_device *dev, 3188 uint16_t offset) 3189 { 3190 struct radeon_device *rdev = dev->dev_private; 3191 uint32_t tmp; 3192 3193 if (offset) { 3194 uint8_t val = RBIOS8(offset); 3195 while (val != 0xff) { 3196 offset++; 3197 3198 if (val == 0x0f) { 3199 uint32_t channel_complete_mask; 3200 3201 if (ASIC_IS_R300(rdev)) 3202 channel_complete_mask = 3203 R300_MEM_PWRUP_COMPLETE; 3204 else 3205 channel_complete_mask = 3206 RADEON_MEM_PWRUP_COMPLETE; 3207 tmp = 20000; 3208 while (tmp--) { 3209 if ((RREG32(RADEON_MEM_STR_CNTL) & 3210 channel_complete_mask) == 3211 channel_complete_mask) 3212 break; 3213 } 3214 } else { 3215 uint32_t or_mask = RBIOS16(offset); 3216 offset += 2; 3217 3218 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3219 tmp &= RADEON_SDRAM_MODE_MASK; 3220 tmp |= or_mask; 3221 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3222 3223 or_mask = val << 24; 3224 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3225 tmp &= RADEON_B3MEM_RESET_MASK; 3226 tmp |= or_mask; 3227 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3228 } 3229 val = RBIOS8(offset); 3230 } 3231 } 3232 } 3233 3234 static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3235 int mem_addr_mapping) 3236 { 3237 struct radeon_device *rdev = dev->dev_private; 3238 uint32_t mem_cntl; 3239 uint32_t mem_size; 3240 uint32_t addr = 0; 3241 3242 mem_cntl = RREG32(RADEON_MEM_CNTL); 3243 if (mem_cntl & RV100_HALF_MODE) 3244 ram /= 2; 3245 mem_size = ram; 3246 mem_cntl &= ~(0xff << 8); 3247 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3248 WREG32(RADEON_MEM_CNTL, mem_cntl); 3249 RREG32(RADEON_MEM_CNTL); 3250 3251 /* sdram reset ? */ 3252 3253 /* something like this???? */ 3254 while (ram--) { 3255 addr = ram * 1024 * 1024; 3256 /* write to each page */ 3257 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3258 /* read back and verify */ 3259 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3260 return 0; 3261 } 3262 3263 return mem_size; 3264 } 3265 3266 static void combios_write_ram_size(struct drm_device *dev) 3267 { 3268 struct radeon_device *rdev = dev->dev_private; 3269 uint8_t rev; 3270 uint16_t offset; 3271 uint32_t mem_size = 0; 3272 uint32_t mem_cntl = 0; 3273 3274 /* should do something smarter here I guess... */ 3275 if (rdev->flags & RADEON_IS_IGP) 3276 return; 3277 3278 /* first check detected mem table */ 3279 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3280 if (offset) { 3281 rev = RBIOS8(offset); 3282 if (rev < 3) { 3283 mem_cntl = RBIOS32(offset + 1); 3284 mem_size = RBIOS16(offset + 5); 3285 if ((rdev->family < CHIP_R200) && 3286 !ASIC_IS_RN50(rdev)) 3287 WREG32(RADEON_MEM_CNTL, mem_cntl); 3288 } 3289 } 3290 3291 if (!mem_size) { 3292 offset = 3293 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3294 if (offset) { 3295 rev = RBIOS8(offset - 1); 3296 if (rev < 1) { 3297 if ((rdev->family < CHIP_R200) 3298 && !ASIC_IS_RN50(rdev)) { 3299 int ram = 0; 3300 int mem_addr_mapping = 0; 3301 3302 while (RBIOS8(offset)) { 3303 ram = RBIOS8(offset); 3304 mem_addr_mapping = 3305 RBIOS8(offset + 1); 3306 if (mem_addr_mapping != 0x25) 3307 ram *= 2; 3308 mem_size = 3309 combios_detect_ram(dev, ram, 3310 mem_addr_mapping); 3311 if (mem_size) 3312 break; 3313 offset += 2; 3314 } 3315 } else 3316 mem_size = RBIOS8(offset); 3317 } else { 3318 mem_size = RBIOS8(offset); 3319 mem_size *= 2; /* convert to MB */ 3320 } 3321 } 3322 } 3323 3324 mem_size *= (1024 * 1024); /* convert to bytes */ 3325 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3326 } 3327 3328 void radeon_combios_asic_init(struct drm_device *dev) 3329 { 3330 struct radeon_device *rdev = dev->dev_private; 3331 uint16_t table; 3332 3333 /* port hardcoded mac stuff from radeonfb */ 3334 if (rdev->bios == NULL) 3335 return; 3336 3337 /* ASIC INIT 1 */ 3338 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3339 if (table) 3340 combios_parse_mmio_table(dev, table); 3341 3342 /* PLL INIT */ 3343 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3344 if (table) 3345 combios_parse_pll_table(dev, table); 3346 3347 /* ASIC INIT 2 */ 3348 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3349 if (table) 3350 combios_parse_mmio_table(dev, table); 3351 3352 if (!(rdev->flags & RADEON_IS_IGP)) { 3353 /* ASIC INIT 4 */ 3354 table = 3355 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3356 if (table) 3357 combios_parse_mmio_table(dev, table); 3358 3359 /* RAM RESET */ 3360 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3361 if (table) 3362 combios_parse_ram_reset_table(dev, table); 3363 3364 /* ASIC INIT 3 */ 3365 table = 3366 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3367 if (table) 3368 combios_parse_mmio_table(dev, table); 3369 3370 /* write CONFIG_MEMSIZE */ 3371 combios_write_ram_size(dev); 3372 } 3373 3374 /* quirk for rs4xx HP nx6125 laptop to make it resume 3375 * - it hangs on resume inside the dynclk 1 table. 3376 */ 3377 if (rdev->family == CHIP_RS480 && 3378 rdev->pdev->subsystem_vendor == 0x103c && 3379 rdev->pdev->subsystem_device == 0x308b) 3380 return; 3381 3382 /* quirk for rs4xx HP dv5000 laptop to make it resume 3383 * - it hangs on resume inside the dynclk 1 table. 3384 */ 3385 if (rdev->family == CHIP_RS480 && 3386 rdev->pdev->subsystem_vendor == 0x103c && 3387 rdev->pdev->subsystem_device == 0x30a4) 3388 return; 3389 3390 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3391 * - it hangs on resume inside the dynclk 1 table. 3392 */ 3393 if (rdev->family == CHIP_RS480 && 3394 rdev->pdev->subsystem_vendor == 0x103c && 3395 rdev->pdev->subsystem_device == 0x30ae) 3396 return; 3397 3398 /* DYN CLK 1 */ 3399 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3400 if (table) 3401 combios_parse_pll_table(dev, table); 3402 3403 } 3404 3405 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3406 { 3407 struct radeon_device *rdev = dev->dev_private; 3408 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3409 3410 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3411 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3412 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3413 3414 /* let the bios control the backlight */ 3415 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3416 3417 /* tell the bios not to handle mode switching */ 3418 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3419 RADEON_ACC_MODE_CHANGE); 3420 3421 /* tell the bios a driver is loaded */ 3422 bios_7_scratch |= RADEON_DRV_LOADED; 3423 3424 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3425 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3426 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3427 } 3428 3429 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3430 { 3431 struct drm_device *dev = encoder->dev; 3432 struct radeon_device *rdev = dev->dev_private; 3433 uint32_t bios_6_scratch; 3434 3435 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3436 3437 if (lock) 3438 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3439 else 3440 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3441 3442 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3443 } 3444 3445 void 3446 radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3447 struct drm_encoder *encoder, 3448 bool connected) 3449 { 3450 struct drm_device *dev = connector->dev; 3451 struct radeon_device *rdev = dev->dev_private; 3452 struct radeon_connector *radeon_connector = 3453 to_radeon_connector(connector); 3454 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3455 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3456 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3457 3458 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3459 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3460 if (connected) { 3461 DRM_DEBUG_KMS("TV1 connected\n"); 3462 /* fix me */ 3463 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3464 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3465 bios_5_scratch |= RADEON_TV1_ON; 3466 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3467 } else { 3468 DRM_DEBUG_KMS("TV1 disconnected\n"); 3469 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3470 bios_5_scratch &= ~RADEON_TV1_ON; 3471 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3472 } 3473 } 3474 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3475 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3476 if (connected) { 3477 DRM_DEBUG_KMS("LCD1 connected\n"); 3478 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3479 bios_5_scratch |= RADEON_LCD1_ON; 3480 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3481 } else { 3482 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3483 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3484 bios_5_scratch &= ~RADEON_LCD1_ON; 3485 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3486 } 3487 } 3488 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3489 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3490 if (connected) { 3491 DRM_DEBUG_KMS("CRT1 connected\n"); 3492 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3493 bios_5_scratch |= RADEON_CRT1_ON; 3494 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3495 } else { 3496 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3497 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3498 bios_5_scratch &= ~RADEON_CRT1_ON; 3499 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3500 } 3501 } 3502 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3503 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3504 if (connected) { 3505 DRM_DEBUG_KMS("CRT2 connected\n"); 3506 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3507 bios_5_scratch |= RADEON_CRT2_ON; 3508 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3509 } else { 3510 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3511 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3512 bios_5_scratch &= ~RADEON_CRT2_ON; 3513 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3514 } 3515 } 3516 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3517 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3518 if (connected) { 3519 DRM_DEBUG_KMS("DFP1 connected\n"); 3520 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3521 bios_5_scratch |= RADEON_DFP1_ON; 3522 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3523 } else { 3524 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3525 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3526 bios_5_scratch &= ~RADEON_DFP1_ON; 3527 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3528 } 3529 } 3530 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3531 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3532 if (connected) { 3533 DRM_DEBUG_KMS("DFP2 connected\n"); 3534 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3535 bios_5_scratch |= RADEON_DFP2_ON; 3536 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3537 } else { 3538 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3539 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3540 bios_5_scratch &= ~RADEON_DFP2_ON; 3541 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3542 } 3543 } 3544 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3545 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3546 } 3547 3548 void 3549 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3550 { 3551 struct drm_device *dev = encoder->dev; 3552 struct radeon_device *rdev = dev->dev_private; 3553 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3554 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3555 3556 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3557 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3558 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3559 } 3560 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3561 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3562 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3563 } 3564 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3565 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3566 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3567 } 3568 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3569 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3570 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3571 } 3572 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3573 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3574 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3575 } 3576 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3577 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3578 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3579 } 3580 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3581 } 3582 3583 void 3584 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3585 { 3586 struct drm_device *dev = encoder->dev; 3587 struct radeon_device *rdev = dev->dev_private; 3588 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3589 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3590 3591 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3592 if (on) 3593 bios_6_scratch |= RADEON_TV_DPMS_ON; 3594 else 3595 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3596 } 3597 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3598 if (on) 3599 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3600 else 3601 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3602 } 3603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3604 if (on) 3605 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3606 else 3607 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3608 } 3609 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3610 if (on) 3611 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3612 else 3613 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3614 } 3615 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3616 } 3617