1 /* $OpenBSD: radeon_bios.c,v 1.9 2016/02/06 11:59:51 kettenis Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/pcidevs.h> 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "atom.h" 34 35 #if defined(__amd64__) || defined(__i386__) 36 #include <dev/isa/isareg.h> 37 #include <dev/isa/isavar.h> 38 #endif 39 40 /* 41 * BIOS. 42 */ 43 44 bool radeon_read_platform_bios(struct radeon_device *); 45 46 bool 47 radeon_read_platform_bios(struct radeon_device *rdev) 48 { 49 #if defined(__amd64__) || defined(__i386__) 50 uint8_t __iomem *bios; 51 bus_size_t size = 256 * 1024; /* ??? */ 52 uint8_t *found = NULL; 53 int i; 54 55 56 if (!(rdev->flags & RADEON_IS_IGP)) 57 if (!radeon_card_posted(rdev)) 58 return false; 59 60 rdev->bios = NULL; 61 62 bios = (u8 *)ISA_HOLE_VADDR(0xc0000); 63 64 for (i = 0; i + 2 < size; i++) { 65 if (bios[i] == 0x55 && bios[i + 1] == 0xaa) { 66 found = bios + i; 67 break; 68 } 69 70 } 71 if (found == NULL) { 72 DRM_ERROR("bios size zero or checksum mismatch\n"); 73 return false; 74 } 75 76 rdev->bios = kmalloc(size, GFP_KERNEL); 77 if (rdev->bios == NULL) 78 return false; 79 80 memcpy(rdev->bios, found, size); 81 82 return true; 83 #endif 84 return false; 85 } 86 87 /* If you boot an IGP board with a discrete card as the primary, 88 * the IGP rom is not accessible via the rom bar as the IGP rom is 89 * part of the system bios. On boot, the system bios puts a 90 * copy of the igp rom at the start of vram if a discrete card is 91 * present. 92 */ 93 static bool igp_read_bios_from_vram(struct radeon_device *rdev) 94 { 95 uint8_t __iomem *bios; 96 bus_size_t size = 256 * 1024; /* ??? */ 97 bus_space_handle_t bsh; 98 bus_space_tag_t bst = rdev->memt; 99 100 if (!(rdev->flags & RADEON_IS_IGP)) 101 if (!radeon_card_posted(rdev)) 102 return false; 103 104 rdev->bios = NULL; 105 106 if (bus_space_map(bst, rdev->fb_aper_offset, size, BUS_SPACE_MAP_LINEAR, &bsh) != 0) 107 return false; 108 109 bios = bus_space_vaddr(rdev->memt, bsh); 110 if (bios == NULL) { 111 bus_space_unmap(bst, bsh, size); 112 return false; 113 } 114 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 115 bus_space_unmap(bst, bsh, size); 116 return false; 117 } 118 119 rdev->bios = kmalloc(size, GFP_KERNEL); 120 if (rdev->bios == NULL) { 121 bus_space_unmap(bst, bsh, size); 122 return false; 123 } 124 memcpy_fromio(rdev->bios, bios, size); 125 bus_space_unmap(bst, bsh, size); 126 return true; 127 } 128 129 static bool radeon_read_bios(struct radeon_device *rdev) 130 { 131 uint8_t __iomem *bios; 132 bus_size_t size; 133 pcireg_t address, mask; 134 bus_space_handle_t romh; 135 int rc; 136 137 rdev->bios = NULL; 138 /* XXX: some cards may return 0 for rom size? ddx has a workaround */ 139 140 address = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 141 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 142 mask = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_ROM_REG); 143 address |= PCI_ROM_ENABLE; 144 pci_conf_write(rdev->pc, rdev->pa_tag, PCI_ROM_REG, address); 145 146 size = PCI_ROM_SIZE(mask); 147 if (size == 0) 148 return false; 149 rc = bus_space_map(rdev->memt, PCI_ROM_ADDR(address), size, 150 BUS_SPACE_MAP_LINEAR, &romh); 151 if (rc != 0) { 152 printf(": can't map PCI ROM (%d)\n", rc); 153 return false; 154 } 155 bios = (uint8_t *)bus_space_vaddr(rdev->memt, romh); 156 if (!bios) { 157 printf(": bus_space_vaddr failed\n"); 158 return false; 159 } 160 161 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) 162 goto fail; 163 rdev->bios = kmalloc(size, GFP_KERNEL); 164 memcpy(rdev->bios, bios, size); 165 bus_space_unmap(rdev->memt, romh, size); 166 return true; 167 fail: 168 bus_space_unmap(rdev->memt, romh, size); 169 return false; 170 } 171 172 #ifdef CONFIG_ACPI 173 /* ATRM is used to get the BIOS on the discrete cards in 174 * dual-gpu systems. 175 */ 176 /* retrieve the ROM in 4k blocks */ 177 #define ATRM_BIOS_PAGE 4096 178 /** 179 * radeon_atrm_call - fetch a chunk of the vbios 180 * 181 * @atrm_handle: acpi ATRM handle 182 * @bios: vbios image pointer 183 * @offset: offset of vbios image data to fetch 184 * @len: length of vbios image data to fetch 185 * 186 * Executes ATRM to fetch a chunk of the discrete 187 * vbios image on PX systems (all asics). 188 * Returns the length of the buffer fetched. 189 */ 190 static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios, 191 int offset, int len) 192 { 193 acpi_status status; 194 union acpi_object atrm_arg_elements[2], *obj; 195 struct acpi_object_list atrm_arg; 196 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; 197 198 atrm_arg.count = 2; 199 atrm_arg.pointer = &atrm_arg_elements[0]; 200 201 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER; 202 atrm_arg_elements[0].integer.value = offset; 203 204 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER; 205 atrm_arg_elements[1].integer.value = len; 206 207 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer); 208 if (ACPI_FAILURE(status)) { 209 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status)); 210 return -ENODEV; 211 } 212 213 obj = (union acpi_object *)buffer.pointer; 214 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length); 215 len = obj->buffer.length; 216 kfree(buffer.pointer); 217 return len; 218 } 219 220 static bool radeon_atrm_get_bios(struct radeon_device *rdev) 221 { 222 int ret; 223 int size = 256 * 1024; 224 int i; 225 struct pci_dev *pdev = NULL; 226 acpi_handle dhandle, atrm_handle; 227 acpi_status status; 228 bool found = false; 229 230 /* ATRM is for the discrete card only */ 231 if (rdev->flags & RADEON_IS_IGP) 232 return false; 233 234 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 235 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev); 236 if (!dhandle) 237 continue; 238 239 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 240 if (!ACPI_FAILURE(status)) { 241 found = true; 242 break; 243 } 244 } 245 246 if (!found) { 247 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 248 dhandle = ACPI_HANDLE(&pdev->dev); 249 if (!dhandle) 250 continue; 251 252 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle); 253 if (!ACPI_FAILURE(status)) { 254 found = true; 255 break; 256 } 257 } 258 } 259 260 if (!found) 261 return false; 262 263 rdev->bios = kmalloc(size, GFP_KERNEL); 264 if (!rdev->bios) { 265 DRM_ERROR("Unable to allocate bios\n"); 266 return false; 267 } 268 269 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 270 ret = radeon_atrm_call(atrm_handle, 271 rdev->bios, 272 (i * ATRM_BIOS_PAGE), 273 ATRM_BIOS_PAGE); 274 if (ret < ATRM_BIOS_PAGE) 275 break; 276 } 277 278 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 279 kfree(rdev->bios); 280 return false; 281 } 282 return true; 283 } 284 #else 285 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev) 286 { 287 return false; 288 } 289 #endif 290 291 static bool ni_read_disabled_bios(struct radeon_device *rdev) 292 { 293 u32 bus_cntl; 294 u32 d1vga_control; 295 u32 d2vga_control; 296 u32 vga_render_control; 297 u32 rom_cntl; 298 bool r; 299 300 bus_cntl = RREG32(R600_BUS_CNTL); 301 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 302 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 303 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 304 rom_cntl = RREG32(R600_ROM_CNTL); 305 306 /* enable the rom */ 307 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 308 /* Disable VGA mode */ 309 WREG32(AVIVO_D1VGA_CONTROL, 310 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 311 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 312 WREG32(AVIVO_D2VGA_CONTROL, 313 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 314 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 315 WREG32(AVIVO_VGA_RENDER_CONTROL, 316 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 317 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 318 319 r = radeon_read_bios(rdev); 320 321 /* restore regs */ 322 WREG32(R600_BUS_CNTL, bus_cntl); 323 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 324 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 325 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 326 WREG32(R600_ROM_CNTL, rom_cntl); 327 return r; 328 } 329 330 static bool r700_read_disabled_bios(struct radeon_device *rdev) 331 { 332 uint32_t viph_control; 333 uint32_t bus_cntl; 334 uint32_t d1vga_control; 335 uint32_t d2vga_control; 336 uint32_t vga_render_control; 337 uint32_t rom_cntl; 338 uint32_t cg_spll_func_cntl = 0; 339 uint32_t cg_spll_status; 340 bool r; 341 342 viph_control = RREG32(RADEON_VIPH_CONTROL); 343 bus_cntl = RREG32(R600_BUS_CNTL); 344 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 345 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 346 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 347 rom_cntl = RREG32(R600_ROM_CNTL); 348 349 /* disable VIP */ 350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 351 /* enable the rom */ 352 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 353 /* Disable VGA mode */ 354 WREG32(AVIVO_D1VGA_CONTROL, 355 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 356 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 357 WREG32(AVIVO_D2VGA_CONTROL, 358 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 359 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 360 WREG32(AVIVO_VGA_RENDER_CONTROL, 361 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 362 363 if (rdev->family == CHIP_RV730) { 364 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); 365 366 /* enable bypass mode */ 367 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | 368 R600_SPLL_BYPASS_EN)); 369 370 /* wait for SPLL_CHG_STATUS to change to 1 */ 371 cg_spll_status = 0; 372 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 373 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 374 375 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); 376 } else 377 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); 378 379 r = radeon_read_bios(rdev); 380 381 /* restore regs */ 382 if (rdev->family == CHIP_RV730) { 383 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); 384 385 /* wait for SPLL_CHG_STATUS to change to 1 */ 386 cg_spll_status = 0; 387 while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) 388 cg_spll_status = RREG32(R600_CG_SPLL_STATUS); 389 } 390 WREG32(RADEON_VIPH_CONTROL, viph_control); 391 WREG32(R600_BUS_CNTL, bus_cntl); 392 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 393 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 394 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 395 WREG32(R600_ROM_CNTL, rom_cntl); 396 return r; 397 } 398 399 static bool r600_read_disabled_bios(struct radeon_device *rdev) 400 { 401 uint32_t viph_control; 402 uint32_t bus_cntl; 403 uint32_t d1vga_control; 404 uint32_t d2vga_control; 405 uint32_t vga_render_control; 406 uint32_t rom_cntl; 407 uint32_t general_pwrmgt; 408 uint32_t low_vid_lower_gpio_cntl; 409 uint32_t medium_vid_lower_gpio_cntl; 410 uint32_t high_vid_lower_gpio_cntl; 411 uint32_t ctxsw_vid_lower_gpio_cntl; 412 uint32_t lower_gpio_enable; 413 bool r; 414 415 viph_control = RREG32(RADEON_VIPH_CONTROL); 416 bus_cntl = RREG32(R600_BUS_CNTL); 417 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 418 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 419 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 420 rom_cntl = RREG32(R600_ROM_CNTL); 421 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); 422 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); 423 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); 424 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); 425 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); 426 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); 427 428 /* disable VIP */ 429 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 430 /* enable the rom */ 431 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 432 /* Disable VGA mode */ 433 WREG32(AVIVO_D1VGA_CONTROL, 434 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 435 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 436 WREG32(AVIVO_D2VGA_CONTROL, 437 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 438 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 439 WREG32(AVIVO_VGA_RENDER_CONTROL, 440 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 441 442 WREG32(R600_ROM_CNTL, 443 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | 444 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | 445 R600_SCK_OVERWRITE)); 446 447 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); 448 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, 449 (low_vid_lower_gpio_cntl & ~0x400)); 450 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, 451 (medium_vid_lower_gpio_cntl & ~0x400)); 452 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, 453 (high_vid_lower_gpio_cntl & ~0x400)); 454 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, 455 (ctxsw_vid_lower_gpio_cntl & ~0x400)); 456 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); 457 458 r = radeon_read_bios(rdev); 459 460 /* restore regs */ 461 WREG32(RADEON_VIPH_CONTROL, viph_control); 462 WREG32(R600_BUS_CNTL, bus_cntl); 463 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 464 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 465 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 466 WREG32(R600_ROM_CNTL, rom_cntl); 467 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); 468 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); 469 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); 470 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); 471 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); 472 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); 473 return r; 474 } 475 476 static bool avivo_read_disabled_bios(struct radeon_device *rdev) 477 { 478 uint32_t seprom_cntl1; 479 uint32_t viph_control; 480 uint32_t bus_cntl; 481 uint32_t d1vga_control; 482 uint32_t d2vga_control; 483 uint32_t vga_render_control; 484 uint32_t gpiopad_a; 485 uint32_t gpiopad_en; 486 uint32_t gpiopad_mask; 487 bool r; 488 489 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 490 viph_control = RREG32(RADEON_VIPH_CONTROL); 491 bus_cntl = RREG32(RV370_BUS_CNTL); 492 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 493 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 494 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); 495 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 496 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); 497 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); 498 499 WREG32(RADEON_SEPROM_CNTL1, 500 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 501 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 502 WREG32(RADEON_GPIOPAD_A, 0); 503 WREG32(RADEON_GPIOPAD_EN, 0); 504 WREG32(RADEON_GPIOPAD_MASK, 0); 505 506 /* disable VIP */ 507 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 508 509 /* enable the rom */ 510 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 511 512 /* Disable VGA mode */ 513 WREG32(AVIVO_D1VGA_CONTROL, 514 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 515 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 516 WREG32(AVIVO_D2VGA_CONTROL, 517 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 518 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 519 WREG32(AVIVO_VGA_RENDER_CONTROL, 520 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); 521 522 r = radeon_read_bios(rdev); 523 524 /* restore regs */ 525 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 526 WREG32(RADEON_VIPH_CONTROL, viph_control); 527 WREG32(RV370_BUS_CNTL, bus_cntl); 528 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 529 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 530 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); 531 WREG32(RADEON_GPIOPAD_A, gpiopad_a); 532 WREG32(RADEON_GPIOPAD_EN, gpiopad_en); 533 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); 534 return r; 535 } 536 537 static bool legacy_read_disabled_bios(struct radeon_device *rdev) 538 { 539 uint32_t seprom_cntl1; 540 uint32_t viph_control; 541 uint32_t bus_cntl; 542 uint32_t crtc_gen_cntl; 543 uint32_t crtc2_gen_cntl; 544 uint32_t crtc_ext_cntl; 545 uint32_t fp2_gen_cntl; 546 bool r; 547 548 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); 549 viph_control = RREG32(RADEON_VIPH_CONTROL); 550 if (rdev->flags & RADEON_IS_PCIE) 551 bus_cntl = RREG32(RV370_BUS_CNTL); 552 else 553 bus_cntl = RREG32(RADEON_BUS_CNTL); 554 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); 555 crtc2_gen_cntl = 0; 556 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 557 fp2_gen_cntl = 0; 558 559 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 560 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 561 } 562 563 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 564 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 565 } 566 567 WREG32(RADEON_SEPROM_CNTL1, 568 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | 569 (0xc << RADEON_SCK_PRESCALE_SHIFT))); 570 571 /* disable VIP */ 572 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); 573 574 /* enable the rom */ 575 if (rdev->flags & RADEON_IS_PCIE) 576 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); 577 else 578 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); 579 580 /* Turn off mem requests and CRTC for both controllers */ 581 WREG32(RADEON_CRTC_GEN_CNTL, 582 ((crtc_gen_cntl & ~RADEON_CRTC_EN) | 583 (RADEON_CRTC_DISP_REQ_EN_B | 584 RADEON_CRTC_EXT_DISP_EN))); 585 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 586 WREG32(RADEON_CRTC2_GEN_CNTL, 587 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | 588 RADEON_CRTC2_DISP_REQ_EN_B)); 589 } 590 /* Turn off CRTC */ 591 WREG32(RADEON_CRTC_EXT_CNTL, 592 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | 593 (RADEON_CRTC_SYNC_TRISTAT | 594 RADEON_CRTC_DISPLAY_DIS))); 595 596 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 597 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); 598 } 599 600 r = radeon_read_bios(rdev); 601 602 /* restore regs */ 603 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); 604 WREG32(RADEON_VIPH_CONTROL, viph_control); 605 if (rdev->flags & RADEON_IS_PCIE) 606 WREG32(RV370_BUS_CNTL, bus_cntl); 607 else 608 WREG32(RADEON_BUS_CNTL, bus_cntl); 609 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); 610 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 611 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 612 } 613 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 614 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { 615 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 616 } 617 return r; 618 } 619 620 static bool radeon_read_disabled_bios(struct radeon_device *rdev) 621 { 622 if (rdev->flags & RADEON_IS_IGP) 623 return igp_read_bios_from_vram(rdev); 624 else if (rdev->family >= CHIP_BARTS) 625 return ni_read_disabled_bios(rdev); 626 else if (rdev->family >= CHIP_RV770) 627 return r700_read_disabled_bios(rdev); 628 else if (rdev->family >= CHIP_R600) 629 return r600_read_disabled_bios(rdev); 630 else if (rdev->family >= CHIP_RS600) 631 return avivo_read_disabled_bios(rdev); 632 else 633 return legacy_read_disabled_bios(rdev); 634 } 635 636 #if defined(__amd64__) || defined(__i386__) 637 #include "acpi.h" 638 #endif 639 640 #if NACPI > 0 641 #define CONFIG_ACPI 642 #endif 643 644 #ifdef CONFIG_ACPI 645 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 646 { 647 bool ret = false; 648 struct acpi_table_header *hdr; 649 acpi_size tbl_size; 650 UEFI_ACPI_VFCT *vfct; 651 GOP_VBIOS_CONTENT *vbios; 652 VFCT_IMAGE_HEADER *vhdr; 653 654 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size))) 655 return false; 656 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) { 657 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n"); 658 goto out_unmap; 659 } 660 661 vfct = (UEFI_ACPI_VFCT *)hdr; 662 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) { 663 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n"); 664 goto out_unmap; 665 } 666 667 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset); 668 vhdr = &vbios->VbiosHeader; 669 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n", 670 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction, 671 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength); 672 673 if (vhdr->PCIBus != rdev->pdev->bus->number || 674 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) || 675 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) || 676 vhdr->VendorID != rdev->pdev->vendor || 677 vhdr->DeviceID != rdev->pdev->device) { 678 DRM_INFO("ACPI VFCT table is not for this card\n"); 679 goto out_unmap; 680 }; 681 682 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) { 683 DRM_ERROR("ACPI VFCT image truncated\n"); 684 goto out_unmap; 685 } 686 687 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL); 688 ret = !!rdev->bios; 689 690 out_unmap: 691 return ret; 692 } 693 #else 694 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev) 695 { 696 return false; 697 } 698 #endif 699 700 bool radeon_get_bios(struct radeon_device *rdev) 701 { 702 bool r; 703 uint16_t tmp; 704 705 r = radeon_atrm_get_bios(rdev); 706 if (r == false) 707 r = radeon_acpi_vfct_bios(rdev); 708 if (r == false) 709 r = igp_read_bios_from_vram(rdev); 710 if (r == false) 711 r = radeon_read_platform_bios(rdev); 712 if (r == false) 713 r = radeon_read_bios(rdev); 714 if (r == false) { 715 r = radeon_read_disabled_bios(rdev); 716 } 717 if (r == false || rdev->bios == NULL) { 718 DRM_ERROR("Unable to locate a BIOS ROM\n"); 719 rdev->bios = NULL; 720 return false; 721 } 722 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { 723 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]); 724 goto free_bios; 725 } 726 727 tmp = RBIOS16(0x18); 728 if (RBIOS8(tmp + 0x14) != 0x0) { 729 DRM_INFO("Not an x86 BIOS ROM, not using.\n"); 730 goto free_bios; 731 } 732 733 rdev->bios_header_start = RBIOS16(0x48); 734 if (!rdev->bios_header_start) { 735 goto free_bios; 736 } 737 tmp = rdev->bios_header_start + 4; 738 if (!memcmp(rdev->bios + tmp, "ATOM", 4) || 739 !memcmp(rdev->bios + tmp, "MOTA", 4)) { 740 rdev->is_atom_bios = true; 741 } else { 742 rdev->is_atom_bios = false; 743 } 744 745 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); 746 return true; 747 free_bios: 748 kfree(rdev->bios); 749 rdev->bios = NULL; 750 return false; 751 } 752