1 /* $OpenBSD: radeon_asic.h,v 1.1 2013/08/12 04:11:53 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #ifndef __RADEON_ASIC_H__ 30 #define __RADEON_ASIC_H__ 31 32 /* 33 * common functions 34 */ 35 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); 36 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 37 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); 38 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 39 40 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); 41 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 42 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); 43 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 44 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 45 46 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 47 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder); 48 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level); 49 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder); 50 51 52 /* 53 * r100,rv100,rs100,rv200,rs200 54 */ 55 struct r100_mc_save { 56 u32 GENMO_WT; 57 u32 CRTC_EXT_CNTL; 58 u32 CRTC_GEN_CNTL; 59 u32 CRTC2_GEN_CNTL; 60 u32 CUR_OFFSET; 61 u32 CUR2_OFFSET; 62 }; 63 int r100_init(struct radeon_device *rdev); 64 void r100_fini(struct radeon_device *rdev); 65 int r100_suspend(struct radeon_device *rdev); 66 int r100_resume(struct radeon_device *rdev); 67 void r100_vga_set_state(struct radeon_device *rdev, bool state); 68 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 69 int r100_asic_reset(struct radeon_device *rdev); 70 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 71 void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 72 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 73 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 74 int r100_irq_set(struct radeon_device *rdev); 75 int r100_irq_process(struct radeon_device *rdev); 76 void r100_fence_ring_emit(struct radeon_device *rdev, 77 struct radeon_fence *fence); 78 void r100_semaphore_ring_emit(struct radeon_device *rdev, 79 struct radeon_ring *cp, 80 struct radeon_semaphore *semaphore, 81 bool emit_wait); 82 int r100_cs_parse(struct radeon_cs_parser *p); 83 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 84 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 85 int r100_copy_blit(struct radeon_device *rdev, 86 uint64_t src_offset, 87 uint64_t dst_offset, 88 unsigned num_gpu_pages, 89 struct radeon_fence **fence); 90 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 91 uint32_t tiling_flags, uint32_t pitch, 92 uint32_t offset, uint32_t obj_size); 93 void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 94 void r100_bandwidth_update(struct radeon_device *rdev); 95 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 96 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 97 void r100_hpd_init(struct radeon_device *rdev); 98 void r100_hpd_fini(struct radeon_device *rdev); 99 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 100 void r100_hpd_set_polarity(struct radeon_device *rdev, 101 enum radeon_hpd_id hpd); 102 int r100_debugfs_rbbm_init(struct radeon_device *rdev); 103 int r100_debugfs_cp_init(struct radeon_device *rdev); 104 void r100_cp_disable(struct radeon_device *rdev); 105 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); 106 void r100_cp_fini(struct radeon_device *rdev); 107 int r100_pci_gart_init(struct radeon_device *rdev); 108 void r100_pci_gart_fini(struct radeon_device *rdev); 109 int r100_pci_gart_enable(struct radeon_device *rdev); 110 void r100_pci_gart_disable(struct radeon_device *rdev); 111 int r100_debugfs_mc_info_init(struct radeon_device *rdev); 112 int r100_gui_wait_for_idle(struct radeon_device *rdev); 113 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 114 void r100_irq_disable(struct radeon_device *rdev); 115 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); 116 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); 117 void r100_vram_init_sizes(struct radeon_device *rdev); 118 int r100_cp_reset(struct radeon_device *rdev); 119 void r100_vga_render_disable(struct radeon_device *rdev); 120 void r100_restore_sanity(struct radeon_device *rdev); 121 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 122 struct radeon_cs_packet *pkt, 123 struct radeon_bo *robj); 124 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 125 struct radeon_cs_packet *pkt, 126 const unsigned *auth, unsigned n, 127 radeon_packet0_check_t check); 128 int r100_cs_packet_parse(struct radeon_cs_parser *p, 129 struct radeon_cs_packet *pkt, 130 unsigned idx); 131 void r100_enable_bm(struct radeon_device *rdev); 132 void r100_set_common_regs(struct radeon_device *rdev); 133 void r100_bm_disable(struct radeon_device *rdev); 134 extern bool r100_gui_idle(struct radeon_device *rdev); 135 extern void r100_pm_misc(struct radeon_device *rdev); 136 extern void r100_pm_prepare(struct radeon_device *rdev); 137 extern void r100_pm_finish(struct radeon_device *rdev); 138 extern void r100_pm_init_profile(struct radeon_device *rdev); 139 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); 140 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); 141 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 142 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); 143 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc); 144 extern int r100_mc_wait_for_idle(struct radeon_device *rdev); 145 146 /* 147 * r200,rv250,rs300,rv280 148 */ 149 extern int r200_copy_dma(struct radeon_device *rdev, 150 uint64_t src_offset, 151 uint64_t dst_offset, 152 unsigned num_gpu_pages, 153 struct radeon_fence **fence); 154 void r200_set_safe_registers(struct radeon_device *rdev); 155 156 /* 157 * r300,r350,rv350,rv380 158 */ 159 extern int r300_init(struct radeon_device *rdev); 160 extern void r300_fini(struct radeon_device *rdev); 161 extern int r300_suspend(struct radeon_device *rdev); 162 extern int r300_resume(struct radeon_device *rdev); 163 extern int r300_asic_reset(struct radeon_device *rdev); 164 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 165 extern void r300_fence_ring_emit(struct radeon_device *rdev, 166 struct radeon_fence *fence); 167 extern int r300_cs_parse(struct radeon_cs_parser *p); 168 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); 169 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 170 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); 171 extern int rv370_get_pcie_lanes(struct radeon_device *rdev); 172 extern void r300_set_reg_safe(struct radeon_device *rdev); 173 extern void r300_mc_program(struct radeon_device *rdev); 174 extern void r300_mc_init(struct radeon_device *rdev); 175 extern void r300_clock_startup(struct radeon_device *rdev); 176 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 177 extern int rv370_pcie_gart_init(struct radeon_device *rdev); 178 extern void rv370_pcie_gart_fini(struct radeon_device *rdev); 179 extern int rv370_pcie_gart_enable(struct radeon_device *rdev); 180 extern void rv370_pcie_gart_disable(struct radeon_device *rdev); 181 extern int r300_mc_wait_for_idle(struct radeon_device *rdev); 182 183 /* 184 * r420,r423,rv410 185 */ 186 extern int r420_init(struct radeon_device *rdev); 187 extern void r420_fini(struct radeon_device *rdev); 188 extern int r420_suspend(struct radeon_device *rdev); 189 extern int r420_resume(struct radeon_device *rdev); 190 extern void r420_pm_init_profile(struct radeon_device *rdev); 191 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg); 192 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v); 193 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev); 194 extern void r420_pipes_init(struct radeon_device *rdev); 195 196 /* 197 * rs400,rs480 198 */ 199 extern int rs400_init(struct radeon_device *rdev); 200 extern void rs400_fini(struct radeon_device *rdev); 201 extern int rs400_suspend(struct radeon_device *rdev); 202 extern int rs400_resume(struct radeon_device *rdev); 203 void rs400_gart_tlb_flush(struct radeon_device *rdev); 204 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 205 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); 206 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 207 int rs400_gart_init(struct radeon_device *rdev); 208 int rs400_gart_enable(struct radeon_device *rdev); 209 void rs400_gart_adjust_size(struct radeon_device *rdev); 210 void rs400_gart_disable(struct radeon_device *rdev); 211 void rs400_gart_fini(struct radeon_device *rdev); 212 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev); 213 214 /* 215 * rs600. 216 */ 217 extern int rs600_asic_reset(struct radeon_device *rdev); 218 extern int rs600_init(struct radeon_device *rdev); 219 extern void rs600_fini(struct radeon_device *rdev); 220 extern int rs600_suspend(struct radeon_device *rdev); 221 extern int rs600_resume(struct radeon_device *rdev); 222 int rs600_irq_set(struct radeon_device *rdev); 223 int rs600_irq_process(struct radeon_device *rdev); 224 void rs600_irq_disable(struct radeon_device *rdev); 225 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); 226 void rs600_gart_tlb_flush(struct radeon_device *rdev); 227 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 228 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); 229 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 230 void rs600_bandwidth_update(struct radeon_device *rdev); 231 void rs600_hpd_init(struct radeon_device *rdev); 232 void rs600_hpd_fini(struct radeon_device *rdev); 233 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 234 void rs600_hpd_set_polarity(struct radeon_device *rdev, 235 enum radeon_hpd_id hpd); 236 extern void rs600_pm_misc(struct radeon_device *rdev); 237 extern void rs600_pm_prepare(struct radeon_device *rdev); 238 extern void rs600_pm_finish(struct radeon_device *rdev); 239 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); 240 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 241 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); 242 void rs600_set_safe_registers(struct radeon_device *rdev); 243 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc); 244 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev); 245 246 /* 247 * rs690,rs740 248 */ 249 int rs690_init(struct radeon_device *rdev); 250 void rs690_fini(struct radeon_device *rdev); 251 int rs690_resume(struct radeon_device *rdev); 252 int rs690_suspend(struct radeon_device *rdev); 253 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); 254 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 255 void rs690_bandwidth_update(struct radeon_device *rdev); 256 void rs690_line_buffer_adjust(struct radeon_device *rdev, 257 struct drm_display_mode *mode1, 258 struct drm_display_mode *mode2); 259 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev); 260 261 /* 262 * rv515 263 */ 264 struct rv515_mc_save { 265 u32 vga_render_control; 266 u32 vga_hdp_control; 267 bool crtc_enabled[2]; 268 }; 269 270 int rv515_init(struct radeon_device *rdev); 271 void rv515_fini(struct radeon_device *rdev); 272 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); 273 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 274 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); 275 void rv515_bandwidth_update(struct radeon_device *rdev); 276 int rv515_resume(struct radeon_device *rdev); 277 int rv515_suspend(struct radeon_device *rdev); 278 void rv515_bandwidth_avivo_update(struct radeon_device *rdev); 279 void rv515_vga_render_disable(struct radeon_device *rdev); 280 void rv515_set_safe_registers(struct radeon_device *rdev); 281 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); 282 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); 283 void rv515_clock_startup(struct radeon_device *rdev); 284 void rv515_debugfs(struct radeon_device *rdev); 285 int rv515_mc_wait_for_idle(struct radeon_device *rdev); 286 287 /* 288 * r520,rv530,rv560,rv570,r580 289 */ 290 int r520_init(struct radeon_device *rdev); 291 int r520_resume(struct radeon_device *rdev); 292 int r520_mc_wait_for_idle(struct radeon_device *rdev); 293 294 /* 295 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 296 */ 297 int r600_init(struct radeon_device *rdev); 298 void r600_fini(struct radeon_device *rdev); 299 int r600_suspend(struct radeon_device *rdev); 300 int r600_resume(struct radeon_device *rdev); 301 void r600_vga_set_state(struct radeon_device *rdev, bool state); 302 int r600_wb_init(struct radeon_device *rdev); 303 void r600_wb_fini(struct radeon_device *rdev); 304 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 305 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 306 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 307 int r600_cs_parse(struct radeon_cs_parser *p); 308 int r600_dma_cs_parse(struct radeon_cs_parser *p); 309 void r600_fence_ring_emit(struct radeon_device *rdev, 310 struct radeon_fence *fence); 311 void r600_semaphore_ring_emit(struct radeon_device *rdev, 312 struct radeon_ring *cp, 313 struct radeon_semaphore *semaphore, 314 bool emit_wait); 315 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 316 struct radeon_fence *fence); 317 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 318 struct radeon_ring *ring, 319 struct radeon_semaphore *semaphore, 320 bool emit_wait); 321 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 322 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 323 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 324 int r600_asic_reset(struct radeon_device *rdev); 325 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 326 uint32_t tiling_flags, uint32_t pitch, 327 uint32_t offset, uint32_t obj_size); 328 void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 329 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 330 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); 331 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 332 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 333 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 334 int r600_copy_blit(struct radeon_device *rdev, 335 uint64_t src_offset, uint64_t dst_offset, 336 unsigned num_gpu_pages, struct radeon_fence **fence); 337 int r600_copy_dma(struct radeon_device *rdev, 338 uint64_t src_offset, uint64_t dst_offset, 339 unsigned num_gpu_pages, struct radeon_fence **fence); 340 void r600_hpd_init(struct radeon_device *rdev); 341 void r600_hpd_fini(struct radeon_device *rdev); 342 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 343 void r600_hpd_set_polarity(struct radeon_device *rdev, 344 enum radeon_hpd_id hpd); 345 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); 346 extern bool r600_gui_idle(struct radeon_device *rdev); 347 extern void r600_pm_misc(struct radeon_device *rdev); 348 extern void r600_pm_init_profile(struct radeon_device *rdev); 349 extern void rs780_pm_init_profile(struct radeon_device *rdev); 350 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev); 351 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes); 352 extern int r600_get_pcie_lanes(struct radeon_device *rdev); 353 bool r600_card_posted(struct radeon_device *rdev); 354 void r600_cp_stop(struct radeon_device *rdev); 355 int r600_cp_start(struct radeon_device *rdev); 356 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size); 357 int r600_cp_resume(struct radeon_device *rdev); 358 void r600_cp_fini(struct radeon_device *rdev); 359 int r600_count_pipe_bits(uint32_t val); 360 int r600_mc_wait_for_idle(struct radeon_device *rdev); 361 int r600_pcie_gart_init(struct radeon_device *rdev); 362 void r600_scratch_init(struct radeon_device *rdev); 363 int r600_blit_init(struct radeon_device *rdev); 364 void r600_blit_fini(struct radeon_device *rdev); 365 int r600_init_microcode(struct radeon_device *rdev); 366 /* r600 irq */ 367 int r600_irq_process(struct radeon_device *rdev); 368 int r600_irq_init(struct radeon_device *rdev); 369 void r600_irq_fini(struct radeon_device *rdev); 370 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 371 int r600_irq_set(struct radeon_device *rdev); 372 void r600_irq_suspend(struct radeon_device *rdev); 373 void r600_disable_interrupts(struct radeon_device *rdev); 374 void r600_rlc_stop(struct radeon_device *rdev); 375 /* r600 audio */ 376 int r600_audio_init(struct radeon_device *rdev); 377 void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 378 struct r600_audio r600_audio_status(struct radeon_device *rdev); 379 void r600_audio_fini(struct radeon_device *rdev); 380 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 381 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 382 /* r600 blit */ 383 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 384 struct radeon_fence **fence, struct radeon_sa_bo **vb, 385 struct radeon_semaphore **sem); 386 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence, 387 struct radeon_sa_bo *vb, struct radeon_semaphore *sem); 388 void r600_kms_blit_copy(struct radeon_device *rdev, 389 u64 src_gpu_addr, u64 dst_gpu_addr, 390 unsigned num_gpu_pages, 391 struct radeon_sa_bo *vb); 392 int r600_mc_wait_for_idle(struct radeon_device *rdev); 393 uint64_t r600_get_gpu_clock(struct radeon_device *rdev); 394 395 /* 396 * rv770,rv730,rv710,rv740 397 */ 398 int rv770_init(struct radeon_device *rdev); 399 void rv770_fini(struct radeon_device *rdev); 400 int rv770_suspend(struct radeon_device *rdev); 401 int rv770_resume(struct radeon_device *rdev); 402 void rv770_pm_misc(struct radeon_device *rdev); 403 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 404 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 405 void r700_cp_stop(struct radeon_device *rdev); 406 void r700_cp_fini(struct radeon_device *rdev); 407 int rv770_copy_dma(struct radeon_device *rdev, 408 uint64_t src_offset, uint64_t dst_offset, 409 unsigned num_gpu_pages, 410 struct radeon_fence **fence); 411 412 /* 413 * evergreen 414 */ 415 struct evergreen_mc_save { 416 u32 vga_render_control; 417 u32 vga_hdp_control; 418 bool crtc_enabled[RADEON_MAX_CRTCS]; 419 }; 420 421 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev); 422 int evergreen_init(struct radeon_device *rdev); 423 void evergreen_fini(struct radeon_device *rdev); 424 int evergreen_suspend(struct radeon_device *rdev); 425 int evergreen_resume(struct radeon_device *rdev); 426 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 427 int evergreen_asic_reset(struct radeon_device *rdev); 428 void evergreen_bandwidth_update(struct radeon_device *rdev); 429 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 430 void evergreen_hpd_init(struct radeon_device *rdev); 431 void evergreen_hpd_fini(struct radeon_device *rdev); 432 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 433 void evergreen_hpd_set_polarity(struct radeon_device *rdev, 434 enum radeon_hpd_id hpd); 435 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc); 436 int evergreen_irq_set(struct radeon_device *rdev); 437 int evergreen_irq_process(struct radeon_device *rdev); 438 extern int evergreen_cs_parse(struct radeon_cs_parser *p); 439 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p); 440 extern void evergreen_pm_misc(struct radeon_device *rdev); 441 extern void evergreen_pm_prepare(struct radeon_device *rdev); 442 extern void evergreen_pm_finish(struct radeon_device *rdev); 443 extern void sumo_pm_init_profile(struct radeon_device *rdev); 444 extern void btc_pm_init_profile(struct radeon_device *rdev); 445 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); 446 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); 447 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); 448 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc); 449 void evergreen_disable_interrupt_state(struct radeon_device *rdev); 450 int evergreen_blit_init(struct radeon_device *rdev); 451 int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 452 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev, 453 struct radeon_fence *fence); 454 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev, 455 struct radeon_ib *ib); 456 int evergreen_copy_dma(struct radeon_device *rdev, 457 uint64_t src_offset, uint64_t dst_offset, 458 unsigned num_gpu_pages, 459 struct radeon_fence **fence); 460 461 /* 462 * cayman 463 */ 464 void cayman_fence_ring_emit(struct radeon_device *rdev, 465 struct radeon_fence *fence); 466 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev); 467 int cayman_init(struct radeon_device *rdev); 468 void cayman_fini(struct radeon_device *rdev); 469 int cayman_suspend(struct radeon_device *rdev); 470 int cayman_resume(struct radeon_device *rdev); 471 int cayman_asic_reset(struct radeon_device *rdev); 472 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 473 int cayman_vm_init(struct radeon_device *rdev); 474 void cayman_vm_fini(struct radeon_device *rdev); 475 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 476 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 477 void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, 478 uint64_t addr, unsigned count, 479 uint32_t incr, uint32_t flags); 480 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 481 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 482 void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 483 struct radeon_ib *ib); 484 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 485 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 486 487 /* DCE6 - SI */ 488 void dce6_bandwidth_update(struct radeon_device *rdev); 489 490 /* 491 * si 492 */ 493 void si_fence_ring_emit(struct radeon_device *rdev, 494 struct radeon_fence *fence); 495 void si_pcie_gart_tlb_flush(struct radeon_device *rdev); 496 int si_init(struct radeon_device *rdev); 497 void si_fini(struct radeon_device *rdev); 498 int si_suspend(struct radeon_device *rdev); 499 int si_resume(struct radeon_device *rdev); 500 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 501 int si_asic_reset(struct radeon_device *rdev); 502 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 503 int si_irq_set(struct radeon_device *rdev); 504 int si_irq_process(struct radeon_device *rdev); 505 int si_vm_init(struct radeon_device *rdev); 506 void si_vm_fini(struct radeon_device *rdev); 507 void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 508 uint64_t addr, unsigned count, 509 uint32_t incr, uint32_t flags); 510 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 511 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 512 uint64_t si_get_gpu_clock(struct radeon_device *rdev); 513 int si_copy_dma(struct radeon_device *rdev, 514 uint64_t src_offset, uint64_t dst_offset, 515 unsigned num_gpu_pages, 516 struct radeon_fence **fence); 517 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 518 519 #endif 520