1 /* $OpenBSD: radeon.h,v 1.17 2015/09/27 11:09:26 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #ifndef __RADEON_H__ 30 #define __RADEON_H__ 31 32 /* TODO: Here are things that needs to be done : 33 * - surface allocator & initializer : (bit like scratch reg) should 34 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 35 * related to surface 36 * - WB : write back stuff (do it bit like scratch reg things) 37 * - Vblank : look at Jesse's rework and what we should do 38 * - r600/r700: gart & cp 39 * - cs : clean cs ioctl use bitmap & things like that. 40 * - power management stuff 41 * - Barrier in gart code 42 * - Unmappabled vram ? 43 * - TESTING, TESTING, TESTING 44 */ 45 46 /* Initialization path: 47 * We expect that acceleration initialization might fail for various 48 * reasons even thought we work hard to make it works on most 49 * configurations. In order to still have a working userspace in such 50 * situation the init path must succeed up to the memory controller 51 * initialization point. Failure before this point are considered as 52 * fatal error. Here is the init callchain : 53 * radeon_device_init perform common structure, mutex initialization 54 * asic_init setup the GPU memory layout and perform all 55 * one time initialization (failure in this 56 * function are considered fatal) 57 * asic_startup setup the GPU acceleration, in order to 58 * follow guideline the first thing this 59 * function should do is setting the GPU 60 * memory controller (only MC setup failure 61 * are considered as fatal) 62 */ 63 64 #include <dev/pci/drm/ttm/ttm_bo_api.h> 65 #include <dev/pci/drm/ttm/ttm_bo_driver.h> 66 #include <dev/pci/drm/ttm/ttm_placement.h> 67 #include <dev/pci/drm/ttm/ttm_module.h> 68 #include <dev/pci/drm/ttm/ttm_execbuf_util.h> 69 70 #include <dev/wscons/wsconsio.h> 71 #include <dev/wscons/wsdisplayvar.h> 72 #include <dev/rasops/rasops.h> 73 74 #ifdef __sparc64__ 75 #include <machine/fbvar.h> 76 #endif 77 78 #include "radeon_family.h" 79 #include "radeon_mode.h" 80 #include "radeon_reg.h" 81 82 /* 83 * Modules parameters. 84 */ 85 extern int radeon_no_wb; 86 extern int radeon_modeset; 87 extern int radeon_dynclks; 88 extern int radeon_r4xx_atom; 89 extern int radeon_agpmode; 90 extern int radeon_vram_limit; 91 extern int radeon_gart_size; 92 extern int radeon_benchmarking; 93 extern int radeon_testing; 94 extern int radeon_connector_table; 95 extern int radeon_tv; 96 extern int radeon_audio; 97 extern int radeon_disp_priority; 98 extern int radeon_hw_i2c; 99 extern int radeon_pcie_gen2; 100 extern int radeon_msi; 101 extern int radeon_lockup_timeout; 102 103 /* 104 * Copy from radeon_drv.h so we don't have to include both and have conflicting 105 * symbol; 106 */ 107 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 108 #define RADEON_FENCE_JIFFIES_TIMEOUT (hz / 2) 109 /* RADEON_IB_POOL_SIZE must be a power of 2 */ 110 #define RADEON_IB_POOL_SIZE 16 111 #define RADEON_DEBUGFS_MAX_COMPONENTS 32 112 #define RADEONFB_CONN_LIMIT 4 113 #define RADEON_BIOS_NUM_SCRATCH 8 114 115 /* max number of rings */ 116 #define RADEON_NUM_RINGS 5 117 118 /* fence seq are set to this number when signaled */ 119 #define RADEON_FENCE_SIGNALED_SEQ 0LL 120 121 /* internal ring indices */ 122 /* r1xx+ has gfx CP ring */ 123 #define RADEON_RING_TYPE_GFX_INDEX 0 124 125 /* cayman has 2 compute CP rings */ 126 #define CAYMAN_RING_TYPE_CP1_INDEX 1 127 #define CAYMAN_RING_TYPE_CP2_INDEX 2 128 129 /* R600+ has an async dma ring */ 130 #define R600_RING_TYPE_DMA_INDEX 3 131 /* cayman add a second async dma ring */ 132 #define CAYMAN_RING_TYPE_DMA1_INDEX 4 133 134 /* hardcode those limit for now */ 135 #define RADEON_VA_IB_OFFSET (1 << 20) 136 #define RADEON_VA_RESERVED_SIZE (8 << 20) 137 #define RADEON_IB_VM_MAX_SIZE (64 << 10) 138 139 /* reset flags */ 140 #define RADEON_RESET_GFX (1 << 0) 141 #define RADEON_RESET_COMPUTE (1 << 1) 142 #define RADEON_RESET_DMA (1 << 2) 143 144 /* 145 * Errata workarounds. 146 */ 147 enum radeon_pll_errata { 148 CHIP_ERRATA_R300_CG = 0x00000001, 149 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 150 CHIP_ERRATA_PLL_DELAY = 0x00000004 151 }; 152 153 154 struct radeon_device; 155 156 157 /* 158 * BIOS. 159 */ 160 bool radeon_get_bios(struct radeon_device *rdev); 161 162 /* 163 * Dummy page 164 */ 165 struct radeon_dummy_page { 166 struct drm_dmamem *dmah; 167 bus_addr_t addr; 168 }; 169 int radeon_dummy_page_init(struct radeon_device *rdev); 170 void radeon_dummy_page_fini(struct radeon_device *rdev); 171 172 173 /* 174 * Clocks 175 */ 176 struct radeon_clock { 177 struct radeon_pll p1pll; 178 struct radeon_pll p2pll; 179 struct radeon_pll dcpll; 180 struct radeon_pll spll; 181 struct radeon_pll mpll; 182 /* 10 Khz units */ 183 uint32_t default_mclk; 184 uint32_t default_sclk; 185 uint32_t default_dispclk; 186 uint32_t dp_extclk; 187 uint32_t max_pixel_clock; 188 }; 189 190 /* 191 * Power management 192 */ 193 int radeon_pm_init(struct radeon_device *rdev); 194 void radeon_pm_fini(struct radeon_device *rdev); 195 void radeon_pm_compute_clocks(struct radeon_device *rdev); 196 void radeon_pm_suspend(struct radeon_device *rdev); 197 void radeon_pm_resume(struct radeon_device *rdev); 198 void radeon_combios_get_power_modes(struct radeon_device *rdev); 199 void radeon_atombios_get_power_modes(struct radeon_device *rdev); 200 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); 201 void rs690_pm_info(struct radeon_device *rdev); 202 extern int rv6xx_get_temp(struct radeon_device *rdev); 203 extern int rv770_get_temp(struct radeon_device *rdev); 204 extern int evergreen_get_temp(struct radeon_device *rdev); 205 extern int sumo_get_temp(struct radeon_device *rdev); 206 extern int si_get_temp(struct radeon_device *rdev); 207 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 208 unsigned *bankh, unsigned *mtaspect, 209 unsigned *tile_split); 210 211 /* 212 * Fences. 213 */ 214 struct radeon_fence_driver { 215 uint32_t scratch_reg; 216 uint64_t gpu_addr; 217 volatile uint32_t *cpu_addr; 218 /* sync_seq is protected by ring emission lock */ 219 uint64_t sync_seq[RADEON_NUM_RINGS]; 220 atomic64_t last_seq; 221 unsigned long last_activity; 222 bool initialized; 223 }; 224 225 struct radeon_fence { 226 struct radeon_device *rdev; 227 struct kref kref; 228 /* protected by radeon_fence.lock */ 229 uint64_t seq; 230 /* RB, DMA, etc. */ 231 unsigned ring; 232 }; 233 234 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 235 int radeon_fence_driver_init(struct radeon_device *rdev); 236 void radeon_fence_driver_fini(struct radeon_device *rdev); 237 void radeon_fence_driver_force_completion(struct radeon_device *rdev); 238 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 239 void radeon_fence_process(struct radeon_device *rdev, int ring); 240 bool radeon_fence_signaled(struct radeon_fence *fence); 241 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); 242 int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); 243 int radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); 244 int radeon_fence_wait_any(struct radeon_device *rdev, 245 struct radeon_fence **fences, 246 bool intr); 247 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); 248 void radeon_fence_unref(struct radeon_fence **fence); 249 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); 250 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); 251 void radeon_fence_note_sync(struct radeon_fence *fence, int ring); 252 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, 253 struct radeon_fence *b) 254 { 255 if (!a) { 256 return b; 257 } 258 259 if (!b) { 260 return a; 261 } 262 263 BUG_ON(a->ring != b->ring); 264 265 if (a->seq > b->seq) { 266 return a; 267 } else { 268 return b; 269 } 270 } 271 272 static inline bool radeon_fence_is_earlier(struct radeon_fence *a, 273 struct radeon_fence *b) 274 { 275 if (!a) { 276 return false; 277 } 278 279 if (!b) { 280 return true; 281 } 282 283 BUG_ON(a->ring != b->ring); 284 285 return a->seq < b->seq; 286 } 287 288 /* 289 * Tiling registers 290 */ 291 struct radeon_surface_reg { 292 struct radeon_bo *bo; 293 }; 294 295 #define RADEON_GEM_MAX_SURFACES 8 296 297 /* 298 * TTM. 299 */ 300 struct radeon_mman { 301 struct ttm_bo_global_ref bo_global_ref; 302 struct drm_global_reference mem_global_ref; 303 struct ttm_bo_device bdev; 304 bool mem_global_referenced; 305 bool initialized; 306 }; 307 308 /* bo virtual address in a specific vm */ 309 struct radeon_bo_va { 310 /* protected by bo being reserved */ 311 struct list_head bo_list; 312 uint64_t soffset; 313 uint64_t eoffset; 314 uint32_t flags; 315 bool valid; 316 unsigned ref_count; 317 318 /* protected by vm rwlock */ 319 struct list_head vm_list; 320 321 /* constant after initialization */ 322 struct radeon_vm *vm; 323 struct radeon_bo *bo; 324 }; 325 326 struct radeon_bo { 327 struct drm_gem_object gem_base; 328 /* Protected by gem.rwlock */ 329 struct list_head list; 330 /* Protected by tbo.reserved */ 331 u32 placements[3]; 332 struct ttm_placement placement; 333 struct ttm_buffer_object tbo; 334 struct ttm_bo_kmap_obj kmap; 335 unsigned pin_count; 336 void *kptr; 337 u32 tiling_flags; 338 u32 pitch; 339 int surface_reg; 340 /* list of all virtual address to which this bo 341 * is associated to 342 */ 343 struct list_head va; 344 /* Constant after initialization */ 345 struct radeon_device *rdev; 346 347 struct ttm_bo_kmap_obj dma_buf_vmap; 348 int vmapping_count; 349 }; 350 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) 351 352 struct radeon_bo_list { 353 struct ttm_validate_buffer tv; 354 struct radeon_bo *bo; 355 uint64_t gpu_offset; 356 unsigned rdomain; 357 unsigned wdomain; 358 u32 tiling_flags; 359 }; 360 361 /* sub-allocation manager, it has to be protected by another lock. 362 * By conception this is an helper for other part of the driver 363 * like the indirect buffer or semaphore, which both have their 364 * locking. 365 * 366 * Principe is simple, we keep a list of sub allocation in offset 367 * order (first entry has offset == 0, last entry has the highest 368 * offset). 369 * 370 * When allocating new object we first check if there is room at 371 * the end total_size - (last_object_offset + last_object_size) >= 372 * alloc_size. If so we allocate new object there. 373 * 374 * When there is not enough room at the end, we start waiting for 375 * each sub object until we reach object_offset+object_size >= 376 * alloc_size, this object then become the sub object we return. 377 * 378 * Alignment can't be bigger than page size. 379 * 380 * Hole are not considered for allocation to keep things simple. 381 * Assumption is that there won't be hole (all object on same 382 * alignment). 383 */ 384 struct radeon_sa_manager { 385 wait_queue_head_t wq; 386 struct radeon_bo *bo; 387 struct list_head *hole; 388 struct list_head flist[RADEON_NUM_RINGS]; 389 struct list_head olist; 390 unsigned size; 391 uint64_t gpu_addr; 392 void *cpu_ptr; 393 uint32_t domain; 394 uint32_t align; 395 }; 396 397 struct radeon_sa_bo; 398 399 /* sub-allocation buffer */ 400 struct radeon_sa_bo { 401 struct list_head olist; 402 struct list_head flist; 403 struct radeon_sa_manager *manager; 404 unsigned soffset; 405 unsigned eoffset; 406 struct radeon_fence *fence; 407 }; 408 409 /* 410 * GEM objects. 411 */ 412 struct radeon_gem { 413 struct rwlock mutex; 414 struct list_head objects; 415 }; 416 417 int radeon_gem_init(struct radeon_device *rdev); 418 void radeon_gem_fini(struct radeon_device *rdev); 419 int radeon_gem_object_create(struct radeon_device *rdev, int size, 420 int alignment, int initial_domain, 421 bool discardable, bool kernel, 422 struct drm_gem_object **obj); 423 424 int radeon_mode_dumb_create(struct drm_file *file_priv, 425 struct drm_device *dev, 426 struct drm_mode_create_dumb *args); 427 int radeon_mode_dumb_mmap(struct drm_file *filp, 428 struct drm_device *dev, 429 uint32_t handle, uint64_t *offset_p); 430 int radeon_mode_dumb_destroy(struct drm_file *file_priv, 431 struct drm_device *dev, 432 uint32_t handle); 433 434 /* 435 * Semaphores. 436 */ 437 /* everything here is constant */ 438 struct radeon_semaphore { 439 struct radeon_sa_bo *sa_bo; 440 signed waiters; 441 uint64_t gpu_addr; 442 }; 443 444 int radeon_semaphore_create(struct radeon_device *rdev, 445 struct radeon_semaphore **semaphore); 446 void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 447 struct radeon_semaphore *semaphore); 448 void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 449 struct radeon_semaphore *semaphore); 450 int radeon_semaphore_sync_rings(struct radeon_device *rdev, 451 struct radeon_semaphore *semaphore, 452 int signaler, int waiter); 453 void radeon_semaphore_free(struct radeon_device *rdev, 454 struct radeon_semaphore **semaphore, 455 struct radeon_fence *fence); 456 457 /* 458 * GART structures, functions & helpers 459 */ 460 struct radeon_mc; 461 462 #define RADEON_GPU_PAGE_SIZE 4096 463 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) 464 #define RADEON_GPU_PAGE_SHIFT 12 465 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) 466 467 struct radeon_gart { 468 bus_addr_t table_addr; 469 struct drm_dmamem *dmah; 470 struct radeon_bo *robj; 471 void *ptr; 472 unsigned num_gpu_pages; 473 unsigned num_cpu_pages; 474 unsigned table_size; 475 struct vm_page **pages; 476 bus_addr_t *pages_addr; 477 bool ready; 478 }; 479 480 int radeon_gart_table_ram_alloc(struct radeon_device *rdev); 481 void radeon_gart_table_ram_free(struct radeon_device *rdev); 482 int radeon_gart_table_vram_alloc(struct radeon_device *rdev); 483 void radeon_gart_table_vram_free(struct radeon_device *rdev); 484 int radeon_gart_table_vram_pin(struct radeon_device *rdev); 485 void radeon_gart_table_vram_unpin(struct radeon_device *rdev); 486 int radeon_gart_init(struct radeon_device *rdev); 487 void radeon_gart_fini(struct radeon_device *rdev); 488 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, 489 int pages); 490 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, 491 int pages, struct vm_page **pagelist, 492 bus_addr_t *dma_addr); 493 void radeon_gart_restore(struct radeon_device *rdev); 494 495 496 /* 497 * GPU MC structures, functions & helpers 498 */ 499 struct radeon_mc { 500 bus_size_t aper_size; 501 bus_addr_t aper_base; 502 bus_addr_t agp_base; 503 /* for some chips with <= 32MB we need to lie 504 * about vram size near mc fb location */ 505 u64 mc_vram_size; 506 u64 visible_vram_size; 507 u64 gtt_size; 508 u64 gtt_start; 509 u64 gtt_end; 510 u64 vram_start; 511 u64 vram_end; 512 unsigned vram_width; 513 u64 real_vram_size; 514 int vram_mtrr; 515 bool vram_is_ddr; 516 bool igp_sideport_enabled; 517 u64 gtt_base_align; 518 }; 519 520 bool radeon_combios_sideport_present(struct radeon_device *rdev); 521 bool radeon_atombios_sideport_present(struct radeon_device *rdev); 522 523 /* 524 * GPU scratch registers structures, functions & helpers 525 */ 526 struct radeon_scratch { 527 unsigned num_reg; 528 uint32_t reg_base; 529 bool free[32]; 530 uint32_t reg[32]; 531 }; 532 533 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); 534 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); 535 536 537 /* 538 * IRQS. 539 */ 540 541 struct radeon_unpin_work { 542 struct task task; 543 struct radeon_device *rdev; 544 int crtc_id; 545 struct radeon_fence *fence; 546 struct drm_pending_vblank_event *event; 547 struct radeon_bo *old_rbo; 548 u64 new_crtc_base; 549 }; 550 551 struct r500_irq_stat_regs { 552 u32 disp_int; 553 u32 hdmi0_status; 554 }; 555 556 struct r600_irq_stat_regs { 557 u32 disp_int; 558 u32 disp_int_cont; 559 u32 disp_int_cont2; 560 u32 d1grph_int; 561 u32 d2grph_int; 562 u32 hdmi0_status; 563 u32 hdmi1_status; 564 }; 565 566 struct evergreen_irq_stat_regs { 567 u32 disp_int; 568 u32 disp_int_cont; 569 u32 disp_int_cont2; 570 u32 disp_int_cont3; 571 u32 disp_int_cont4; 572 u32 disp_int_cont5; 573 u32 d1grph_int; 574 u32 d2grph_int; 575 u32 d3grph_int; 576 u32 d4grph_int; 577 u32 d5grph_int; 578 u32 d6grph_int; 579 u32 afmt_status1; 580 u32 afmt_status2; 581 u32 afmt_status3; 582 u32 afmt_status4; 583 u32 afmt_status5; 584 u32 afmt_status6; 585 }; 586 587 union radeon_irq_stat_regs { 588 struct r500_irq_stat_regs r500; 589 struct r600_irq_stat_regs r600; 590 struct evergreen_irq_stat_regs evergreen; 591 }; 592 593 #define RADEON_MAX_HPD_PINS 6 594 #define RADEON_MAX_CRTCS 6 595 #define RADEON_MAX_AFMT_BLOCKS 6 596 597 struct radeon_irq { 598 bool installed; 599 spinlock_t lock; 600 atomic_t ring_int[RADEON_NUM_RINGS]; 601 bool crtc_vblank_int[RADEON_MAX_CRTCS]; 602 atomic_t pflip[RADEON_MAX_CRTCS]; 603 wait_queue_head_t vblank_queue; 604 bool hpd[RADEON_MAX_HPD_PINS]; 605 bool afmt[RADEON_MAX_AFMT_BLOCKS]; 606 union radeon_irq_stat_regs stat_regs; 607 }; 608 609 int radeon_irq_kms_init(struct radeon_device *rdev); 610 void radeon_irq_kms_fini(struct radeon_device *rdev); 611 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); 612 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); 613 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); 614 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); 615 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); 616 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); 617 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 618 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); 619 bool radeon_msi_ok(struct radeon_device *rdev); 620 621 /* 622 * CP & rings. 623 */ 624 625 struct radeon_ib { 626 struct radeon_sa_bo *sa_bo; 627 uint32_t length_dw; 628 uint64_t gpu_addr; 629 uint32_t *ptr; 630 int ring; 631 struct radeon_fence *fence; 632 struct radeon_vm *vm; 633 bool is_const_ib; 634 struct radeon_fence *sync_to[RADEON_NUM_RINGS]; 635 struct radeon_semaphore *semaphore; 636 }; 637 638 struct radeon_ring { 639 struct radeon_bo *ring_obj; 640 volatile uint32_t *ring; 641 unsigned rptr; 642 unsigned rptr_offs; 643 unsigned rptr_reg; 644 unsigned rptr_save_reg; 645 u64 next_rptr_gpu_addr; 646 volatile u32 *next_rptr_cpu_addr; 647 unsigned wptr; 648 unsigned wptr_old; 649 unsigned wptr_reg; 650 unsigned ring_size; 651 unsigned ring_free_dw; 652 int count_dw; 653 unsigned long last_activity; 654 unsigned last_rptr; 655 uint64_t gpu_addr; 656 uint32_t align_mask; 657 uint32_t ptr_mask; 658 bool ready; 659 u32 ptr_reg_shift; 660 u32 ptr_reg_mask; 661 u32 nop; 662 u32 idx; 663 u64 last_semaphore_signal_addr; 664 u64 last_semaphore_wait_addr; 665 }; 666 667 /* 668 * VM 669 */ 670 671 /* maximum number of VMIDs */ 672 #define RADEON_NUM_VM 16 673 674 /* defines number of bits in page table versus page directory, 675 * a page is 4KB so we have 12 bits offset, 9 bits in the page 676 * table and the remaining 19 bits are in the page directory */ 677 #define RADEON_VM_BLOCK_SIZE 9 678 679 /* number of entries in page table */ 680 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) 681 682 struct radeon_vm { 683 struct list_head list; 684 struct list_head va; 685 unsigned id; 686 687 /* contains the page directory */ 688 struct radeon_sa_bo *page_directory; 689 uint64_t pd_gpu_addr; 690 691 /* array of page tables, one for each page directory entry */ 692 struct radeon_sa_bo **page_tables; 693 694 struct rwlock mutex; 695 /* last fence for cs using this vm */ 696 struct radeon_fence *fence; 697 /* last flush or NULL if we still need to flush */ 698 struct radeon_fence *last_flush; 699 }; 700 701 struct radeon_vm_manager { 702 struct rwlock lock; 703 struct list_head lru_vm; 704 struct radeon_fence *active[RADEON_NUM_VM]; 705 struct radeon_sa_manager sa_manager; 706 uint32_t max_pfn; 707 /* number of VMIDs */ 708 unsigned nvm; 709 /* vram base address for page table entry */ 710 u64 vram_base_offset; 711 /* is vm enabled? */ 712 bool enabled; 713 }; 714 715 /* 716 * file private structure 717 */ 718 struct radeon_fpriv { 719 struct radeon_vm vm; 720 }; 721 722 /* 723 * R6xx+ IH ring 724 */ 725 struct r600_ih { 726 struct radeon_bo *ring_obj; 727 volatile uint32_t *ring; 728 unsigned rptr; 729 unsigned ring_size; 730 uint64_t gpu_addr; 731 uint32_t ptr_mask; 732 atomic_t lock; 733 bool enabled; 734 }; 735 736 struct r600_blit_cp_primitives { 737 void (*set_render_target)(struct radeon_device *rdev, int format, 738 int w, int h, u64 gpu_addr); 739 void (*cp_set_surface_sync)(struct radeon_device *rdev, 740 u32 sync_type, u32 size, 741 u64 mc_addr); 742 void (*set_shaders)(struct radeon_device *rdev); 743 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); 744 void (*set_tex_resource)(struct radeon_device *rdev, 745 int format, int w, int h, int pitch, 746 u64 gpu_addr, u32 size); 747 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, 748 int x2, int y2); 749 void (*draw_auto)(struct radeon_device *rdev); 750 void (*set_default_state)(struct radeon_device *rdev); 751 }; 752 753 struct r600_blit { 754 struct radeon_bo *shader_obj; 755 struct r600_blit_cp_primitives primitives; 756 int max_dim; 757 int ring_size_common; 758 int ring_size_per_loop; 759 u64 shader_gpu_addr; 760 u32 vs_offset, ps_offset; 761 u32 state_offset; 762 u32 state_len; 763 }; 764 765 /* 766 * SI RLC stuff 767 */ 768 struct si_rlc { 769 /* for power gating */ 770 struct radeon_bo *save_restore_obj; 771 uint64_t save_restore_gpu_addr; 772 /* for clear state */ 773 struct radeon_bo *clear_state_obj; 774 uint64_t clear_state_gpu_addr; 775 }; 776 777 int radeon_ib_get(struct radeon_device *rdev, int ring, 778 struct radeon_ib *ib, struct radeon_vm *vm, 779 unsigned size); 780 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 781 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 782 struct radeon_ib *const_ib); 783 int radeon_ib_pool_init(struct radeon_device *rdev); 784 void radeon_ib_pool_fini(struct radeon_device *rdev); 785 int radeon_ib_ring_tests(struct radeon_device *rdev); 786 /* Ring access between begin & end cannot sleep */ 787 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, 788 struct radeon_ring *ring); 789 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); 790 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 791 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); 792 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); 793 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); 794 void radeon_ring_undo(struct radeon_ring *ring); 795 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); 796 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); 797 void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); 798 void radeon_ring_lockup_update(struct radeon_ring *ring); 799 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 800 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, 801 uint32_t **data); 802 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, 803 unsigned size, uint32_t *data); 804 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, 805 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, 806 u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); 807 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); 808 809 810 /* r600 async dma */ 811 void r600_dma_stop(struct radeon_device *rdev); 812 int r600_dma_resume(struct radeon_device *rdev); 813 void r600_dma_fini(struct radeon_device *rdev); 814 815 void cayman_dma_stop(struct radeon_device *rdev); 816 int cayman_dma_resume(struct radeon_device *rdev); 817 void cayman_dma_fini(struct radeon_device *rdev); 818 819 /* 820 * CS. 821 */ 822 struct radeon_cs_reloc { 823 struct drm_gem_object *gobj; 824 struct radeon_bo *robj; 825 struct radeon_bo_list lobj; 826 uint32_t handle; 827 uint32_t flags; 828 }; 829 830 struct radeon_cs_chunk { 831 uint32_t chunk_id; 832 uint32_t length_dw; 833 int kpage_idx[2]; 834 uint32_t *kpage[2]; 835 uint32_t *kdata; 836 void __user *user_ptr; 837 int last_copied_page; 838 int last_page_index; 839 }; 840 841 struct radeon_cs_parser { 842 struct device *dev; 843 struct radeon_device *rdev; 844 struct drm_file *filp; 845 /* chunks */ 846 unsigned nchunks; 847 struct radeon_cs_chunk *chunks; 848 uint64_t *chunks_array; 849 /* IB */ 850 unsigned idx; 851 /* relocations */ 852 unsigned nrelocs; 853 struct radeon_cs_reloc *relocs; 854 struct radeon_cs_reloc **relocs_ptr; 855 struct list_head validated; 856 unsigned dma_reloc_idx; 857 /* indices of various chunks */ 858 int chunk_ib_idx; 859 int chunk_relocs_idx; 860 int chunk_flags_idx; 861 int chunk_const_ib_idx; 862 struct radeon_ib ib; 863 struct radeon_ib const_ib; 864 void *track; 865 unsigned family; 866 int parser_error; 867 u32 cs_flags; 868 u32 ring; 869 s32 priority; 870 }; 871 872 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 873 extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); 874 875 struct radeon_cs_packet { 876 unsigned idx; 877 unsigned type; 878 unsigned reg; 879 unsigned opcode; 880 int count; 881 unsigned one_reg_wr; 882 }; 883 884 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, 885 struct radeon_cs_packet *pkt, 886 unsigned idx, unsigned reg); 887 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, 888 struct radeon_cs_packet *pkt); 889 890 891 /* 892 * AGP 893 */ 894 int radeon_agp_init(struct radeon_device *rdev); 895 void radeon_agp_resume(struct radeon_device *rdev); 896 void radeon_agp_suspend(struct radeon_device *rdev); 897 void radeon_agp_fini(struct radeon_device *rdev); 898 899 900 /* 901 * Writeback 902 */ 903 struct radeon_wb { 904 struct radeon_bo *wb_obj; 905 volatile uint32_t *wb; 906 uint64_t gpu_addr; 907 bool enabled; 908 bool use_event; 909 }; 910 911 #define RADEON_WB_SCRATCH_OFFSET 0 912 #define RADEON_WB_RING0_NEXT_RPTR 256 913 #define RADEON_WB_CP_RPTR_OFFSET 1024 914 #define RADEON_WB_CP1_RPTR_OFFSET 1280 915 #define RADEON_WB_CP2_RPTR_OFFSET 1536 916 #define R600_WB_DMA_RPTR_OFFSET 1792 917 #define R600_WB_IH_WPTR_OFFSET 2048 918 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304 919 #define R600_WB_EVENT_OFFSET 3072 920 921 /** 922 * struct radeon_pm - power management datas 923 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) 924 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) 925 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) 926 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) 927 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) 928 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) 929 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) 930 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) 931 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) 932 * @sclk: GPU clock Mhz (core bandwidth depends of this clock) 933 * @needed_bandwidth: current bandwidth needs 934 * 935 * It keeps track of various data needed to take powermanagement decision. 936 * Bandwidth need is used to determine minimun clock of the GPU and memory. 937 * Equation between gpu/memory clock and available bandwidth is hw dependent 938 * (type of memory, bus size, efficiency, ...) 939 */ 940 941 enum radeon_pm_method { 942 PM_METHOD_PROFILE, 943 PM_METHOD_DYNPM, 944 }; 945 946 enum radeon_dynpm_state { 947 DYNPM_STATE_DISABLED, 948 DYNPM_STATE_MINIMUM, 949 DYNPM_STATE_PAUSED, 950 DYNPM_STATE_ACTIVE, 951 DYNPM_STATE_SUSPENDED, 952 }; 953 enum radeon_dynpm_action { 954 DYNPM_ACTION_NONE, 955 DYNPM_ACTION_MINIMUM, 956 DYNPM_ACTION_DOWNCLOCK, 957 DYNPM_ACTION_UPCLOCK, 958 DYNPM_ACTION_DEFAULT 959 }; 960 961 enum radeon_voltage_type { 962 VOLTAGE_NONE = 0, 963 VOLTAGE_GPIO, 964 VOLTAGE_VDDC, 965 VOLTAGE_SW 966 }; 967 968 enum radeon_pm_state_type { 969 POWER_STATE_TYPE_DEFAULT, 970 POWER_STATE_TYPE_POWERSAVE, 971 POWER_STATE_TYPE_BATTERY, 972 POWER_STATE_TYPE_BALANCED, 973 POWER_STATE_TYPE_PERFORMANCE, 974 }; 975 976 enum radeon_pm_profile_type { 977 PM_PROFILE_DEFAULT, 978 PM_PROFILE_AUTO, 979 PM_PROFILE_LOW, 980 PM_PROFILE_MID, 981 PM_PROFILE_HIGH, 982 }; 983 984 #define PM_PROFILE_DEFAULT_IDX 0 985 #define PM_PROFILE_LOW_SH_IDX 1 986 #define PM_PROFILE_MID_SH_IDX 2 987 #define PM_PROFILE_HIGH_SH_IDX 3 988 #define PM_PROFILE_LOW_MH_IDX 4 989 #define PM_PROFILE_MID_MH_IDX 5 990 #define PM_PROFILE_HIGH_MH_IDX 6 991 #define PM_PROFILE_MAX 7 992 993 struct radeon_pm_profile { 994 int dpms_off_ps_idx; 995 int dpms_on_ps_idx; 996 int dpms_off_cm_idx; 997 int dpms_on_cm_idx; 998 }; 999 1000 enum radeon_int_thermal_type { 1001 THERMAL_TYPE_NONE, 1002 THERMAL_TYPE_RV6XX, 1003 THERMAL_TYPE_RV770, 1004 THERMAL_TYPE_EVERGREEN, 1005 THERMAL_TYPE_SUMO, 1006 THERMAL_TYPE_NI, 1007 THERMAL_TYPE_SI, 1008 }; 1009 1010 struct radeon_voltage { 1011 enum radeon_voltage_type type; 1012 /* gpio voltage */ 1013 struct radeon_gpio_rec gpio; 1014 u32 delay; /* delay in usec from voltage drop to sclk change */ 1015 bool active_high; /* voltage drop is active when bit is high */ 1016 /* VDDC voltage */ 1017 u8 vddc_id; /* index into vddc voltage table */ 1018 u8 vddci_id; /* index into vddci voltage table */ 1019 bool vddci_enabled; 1020 /* r6xx+ sw */ 1021 u16 voltage; 1022 /* evergreen+ vddci */ 1023 u16 vddci; 1024 }; 1025 1026 /* clock mode flags */ 1027 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) 1028 1029 struct radeon_pm_clock_info { 1030 /* memory clock */ 1031 u32 mclk; 1032 /* engine clock */ 1033 u32 sclk; 1034 /* voltage info */ 1035 struct radeon_voltage voltage; 1036 /* standardized clock flags */ 1037 u32 flags; 1038 }; 1039 1040 /* state flags */ 1041 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) 1042 1043 struct radeon_power_state { 1044 enum radeon_pm_state_type type; 1045 struct radeon_pm_clock_info *clock_info; 1046 /* number of valid clock modes in this power state */ 1047 int num_clock_modes; 1048 struct radeon_pm_clock_info *default_clock_mode; 1049 /* standardized state flags */ 1050 u32 flags; 1051 u32 misc; /* vbios specific flags */ 1052 u32 misc2; /* vbios specific flags */ 1053 int pcie_lanes; /* pcie lanes */ 1054 }; 1055 1056 /* 1057 * Some modes are overclocked by very low value, accept them 1058 */ 1059 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ 1060 1061 struct radeon_pm { 1062 struct rwlock mutex; 1063 /* write locked while reprogramming mclk */ 1064 struct rwlock mclk_lock; 1065 u32 active_crtcs; 1066 int active_crtc_count; 1067 int req_vblank; 1068 bool vblank_sync; 1069 fixed20_12 max_bandwidth; 1070 fixed20_12 igp_sideport_mclk; 1071 fixed20_12 igp_system_mclk; 1072 fixed20_12 igp_ht_link_clk; 1073 fixed20_12 igp_ht_link_width; 1074 fixed20_12 k8_bandwidth; 1075 fixed20_12 sideport_bandwidth; 1076 fixed20_12 ht_bandwidth; 1077 fixed20_12 core_bandwidth; 1078 fixed20_12 sclk; 1079 fixed20_12 mclk; 1080 fixed20_12 needed_bandwidth; 1081 struct radeon_power_state *power_state; 1082 /* number of valid power states */ 1083 int num_power_states; 1084 int current_power_state_index; 1085 int current_clock_mode_index; 1086 int requested_power_state_index; 1087 int requested_clock_mode_index; 1088 int default_power_state_index; 1089 u32 current_sclk; 1090 u32 current_mclk; 1091 u16 current_vddc; 1092 u16 current_vddci; 1093 u32 default_sclk; 1094 u32 default_mclk; 1095 u16 default_vddc; 1096 u16 default_vddci; 1097 struct radeon_i2c_chan *i2c_bus; 1098 /* selected pm method */ 1099 enum radeon_pm_method pm_method; 1100 /* dynpm power management */ 1101 struct delayed_work dynpm_idle_work; 1102 enum radeon_dynpm_state dynpm_state; 1103 enum radeon_dynpm_action dynpm_planned_action; 1104 unsigned long dynpm_action_timeout; 1105 bool dynpm_can_upclock; 1106 bool dynpm_can_downclock; 1107 /* profile-based power management */ 1108 enum radeon_pm_profile_type profile; 1109 int profile_index; 1110 struct radeon_pm_profile profiles[PM_PROFILE_MAX]; 1111 /* internal thermal controller on rv6xx+ */ 1112 enum radeon_int_thermal_type int_thermal_type; 1113 struct device *int_hwmon_dev; 1114 }; 1115 1116 int radeon_pm_get_type_index(struct radeon_device *rdev, 1117 enum radeon_pm_state_type ps_type, 1118 int instance); 1119 1120 struct r600_audio { 1121 int channels; 1122 int rate; 1123 int bits_per_sample; 1124 u8 status_bits; 1125 u8 category_code; 1126 }; 1127 1128 /* 1129 * Benchmarking 1130 */ 1131 void radeon_benchmark(struct radeon_device *rdev, int test_number); 1132 1133 1134 /* 1135 * Testing 1136 */ 1137 void radeon_test_moves(struct radeon_device *rdev); 1138 void radeon_test_ring_sync(struct radeon_device *rdev, 1139 struct radeon_ring *cpA, 1140 struct radeon_ring *cpB); 1141 void radeon_test_syncing(struct radeon_device *rdev); 1142 1143 1144 /* 1145 * Debugfs 1146 */ 1147 struct radeon_debugfs { 1148 struct drm_info_list *files; 1149 unsigned num_files; 1150 }; 1151 1152 int radeon_debugfs_add_files(struct radeon_device *rdev, 1153 struct drm_info_list *files, 1154 unsigned nfiles); 1155 int radeon_debugfs_fence_init(struct radeon_device *rdev); 1156 1157 1158 /* 1159 * ASIC specific functions. 1160 */ 1161 struct radeon_asic { 1162 int (*init)(struct radeon_device *rdev); 1163 void (*fini)(struct radeon_device *rdev); 1164 int (*resume)(struct radeon_device *rdev); 1165 int (*suspend)(struct radeon_device *rdev); 1166 void (*vga_set_state)(struct radeon_device *rdev, bool state); 1167 int (*asic_reset)(struct radeon_device *rdev); 1168 /* ioctl hw specific callback. Some hw might want to perform special 1169 * operation on specific ioctl. For instance on wait idle some hw 1170 * might want to perform and HDP flush through MMIO as it seems that 1171 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed 1172 * through ring. 1173 */ 1174 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); 1175 /* check if 3D engine is idle */ 1176 bool (*gui_idle)(struct radeon_device *rdev); 1177 /* wait for mc_idle */ 1178 int (*mc_wait_for_idle)(struct radeon_device *rdev); 1179 /* gart */ 1180 struct { 1181 void (*tlb_flush)(struct radeon_device *rdev); 1182 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); 1183 } gart; 1184 struct { 1185 int (*init)(struct radeon_device *rdev); 1186 void (*fini)(struct radeon_device *rdev); 1187 1188 u32 pt_ring_index; 1189 void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1190 uint64_t addr, unsigned count, 1191 uint32_t incr, uint32_t flags); 1192 } vm; 1193 /* ring specific callbacks */ 1194 struct { 1195 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 1196 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); 1197 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); 1198 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1199 struct radeon_semaphore *semaphore, bool emit_wait); 1200 int (*cs_parse)(struct radeon_cs_parser *p); 1201 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); 1202 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1203 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1204 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); 1205 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1206 } ring[RADEON_NUM_RINGS]; 1207 /* irqs */ 1208 struct { 1209 int (*set)(struct radeon_device *rdev); 1210 int (*process)(struct radeon_device *rdev); 1211 } irq; 1212 /* displays */ 1213 struct { 1214 /* display watermarks */ 1215 void (*bandwidth_update)(struct radeon_device *rdev); 1216 /* get frame count */ 1217 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 1218 /* wait for vblank */ 1219 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1220 /* set backlight level */ 1221 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1222 /* get backlight level */ 1223 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1224 } display; 1225 /* copy functions for bo handling */ 1226 struct { 1227 int (*blit)(struct radeon_device *rdev, 1228 uint64_t src_offset, 1229 uint64_t dst_offset, 1230 unsigned num_gpu_pages, 1231 struct radeon_fence **fence); 1232 u32 blit_ring_index; 1233 int (*dma)(struct radeon_device *rdev, 1234 uint64_t src_offset, 1235 uint64_t dst_offset, 1236 unsigned num_gpu_pages, 1237 struct radeon_fence **fence); 1238 u32 dma_ring_index; 1239 /* method used for bo copy */ 1240 int (*copy)(struct radeon_device *rdev, 1241 uint64_t src_offset, 1242 uint64_t dst_offset, 1243 unsigned num_gpu_pages, 1244 struct radeon_fence **fence); 1245 /* ring used for bo copies */ 1246 u32 copy_ring_index; 1247 } copy; 1248 /* surfaces */ 1249 struct { 1250 int (*set_reg)(struct radeon_device *rdev, int reg, 1251 uint32_t tiling_flags, uint32_t pitch, 1252 uint32_t offset, uint32_t obj_size); 1253 void (*clear_reg)(struct radeon_device *rdev, int reg); 1254 } surface; 1255 /* hotplug detect */ 1256 struct { 1257 void (*init)(struct radeon_device *rdev); 1258 void (*fini)(struct radeon_device *rdev); 1259 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1260 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 1261 } hpd; 1262 /* power management */ 1263 struct { 1264 void (*misc)(struct radeon_device *rdev); 1265 void (*prepare)(struct radeon_device *rdev); 1266 void (*finish)(struct radeon_device *rdev); 1267 void (*init_profile)(struct radeon_device *rdev); 1268 void (*get_dynpm_state)(struct radeon_device *rdev); 1269 uint32_t (*get_engine_clock)(struct radeon_device *rdev); 1270 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 1271 uint32_t (*get_memory_clock)(struct radeon_device *rdev); 1272 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 1273 int (*get_pcie_lanes)(struct radeon_device *rdev); 1274 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 1275 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 1276 } pm; 1277 /* pageflipping */ 1278 struct { 1279 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1280 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1281 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1282 } pflip; 1283 }; 1284 1285 /* 1286 * Asic structures 1287 */ 1288 struct r100_asic { 1289 const unsigned *reg_safe_bm; 1290 unsigned reg_safe_bm_size; 1291 u32 hdp_cntl; 1292 }; 1293 1294 struct r300_asic { 1295 const unsigned *reg_safe_bm; 1296 unsigned reg_safe_bm_size; 1297 u32 resync_scratch; 1298 u32 hdp_cntl; 1299 }; 1300 1301 struct r600_asic { 1302 unsigned max_pipes; 1303 unsigned max_tile_pipes; 1304 unsigned max_simds; 1305 unsigned max_backends; 1306 unsigned max_gprs; 1307 unsigned max_threads; 1308 unsigned max_stack_entries; 1309 unsigned max_hw_contexts; 1310 unsigned max_gs_threads; 1311 unsigned sx_max_export_size; 1312 unsigned sx_max_export_pos_size; 1313 unsigned sx_max_export_smx_size; 1314 unsigned sq_num_cf_insts; 1315 unsigned tiling_nbanks; 1316 unsigned tiling_npipes; 1317 unsigned tiling_group_size; 1318 unsigned tile_config; 1319 unsigned backend_map; 1320 }; 1321 1322 struct rv770_asic { 1323 unsigned max_pipes; 1324 unsigned max_tile_pipes; 1325 unsigned max_simds; 1326 unsigned max_backends; 1327 unsigned max_gprs; 1328 unsigned max_threads; 1329 unsigned max_stack_entries; 1330 unsigned max_hw_contexts; 1331 unsigned max_gs_threads; 1332 unsigned sx_max_export_size; 1333 unsigned sx_max_export_pos_size; 1334 unsigned sx_max_export_smx_size; 1335 unsigned sq_num_cf_insts; 1336 unsigned sx_num_of_sets; 1337 unsigned sc_prim_fifo_size; 1338 unsigned sc_hiz_tile_fifo_size; 1339 unsigned sc_earlyz_tile_fifo_fize; 1340 unsigned tiling_nbanks; 1341 unsigned tiling_npipes; 1342 unsigned tiling_group_size; 1343 unsigned tile_config; 1344 unsigned backend_map; 1345 }; 1346 1347 struct evergreen_asic { 1348 unsigned num_ses; 1349 unsigned max_pipes; 1350 unsigned max_tile_pipes; 1351 unsigned max_simds; 1352 unsigned max_backends; 1353 unsigned max_gprs; 1354 unsigned max_threads; 1355 unsigned max_stack_entries; 1356 unsigned max_hw_contexts; 1357 unsigned max_gs_threads; 1358 unsigned sx_max_export_size; 1359 unsigned sx_max_export_pos_size; 1360 unsigned sx_max_export_smx_size; 1361 unsigned sq_num_cf_insts; 1362 unsigned sx_num_of_sets; 1363 unsigned sc_prim_fifo_size; 1364 unsigned sc_hiz_tile_fifo_size; 1365 unsigned sc_earlyz_tile_fifo_size; 1366 unsigned tiling_nbanks; 1367 unsigned tiling_npipes; 1368 unsigned tiling_group_size; 1369 unsigned tile_config; 1370 unsigned backend_map; 1371 }; 1372 1373 struct cayman_asic { 1374 unsigned max_shader_engines; 1375 unsigned max_pipes_per_simd; 1376 unsigned max_tile_pipes; 1377 unsigned max_simds_per_se; 1378 unsigned max_backends_per_se; 1379 unsigned max_texture_channel_caches; 1380 unsigned max_gprs; 1381 unsigned max_threads; 1382 unsigned max_gs_threads; 1383 unsigned max_stack_entries; 1384 unsigned sx_num_of_sets; 1385 unsigned sx_max_export_size; 1386 unsigned sx_max_export_pos_size; 1387 unsigned sx_max_export_smx_size; 1388 unsigned max_hw_contexts; 1389 unsigned sq_num_cf_insts; 1390 unsigned sc_prim_fifo_size; 1391 unsigned sc_hiz_tile_fifo_size; 1392 unsigned sc_earlyz_tile_fifo_size; 1393 1394 unsigned num_shader_engines; 1395 unsigned num_shader_pipes_per_simd; 1396 unsigned num_tile_pipes; 1397 unsigned num_simds_per_se; 1398 unsigned num_backends_per_se; 1399 unsigned backend_disable_mask_per_asic; 1400 unsigned backend_map; 1401 unsigned num_texture_channel_caches; 1402 unsigned mem_max_burst_length_bytes; 1403 unsigned mem_row_size_in_kb; 1404 unsigned shader_engine_tile_size; 1405 unsigned num_gpus; 1406 unsigned multi_gpu_tile_size; 1407 1408 unsigned tile_config; 1409 }; 1410 1411 struct si_asic { 1412 unsigned max_shader_engines; 1413 unsigned max_tile_pipes; 1414 unsigned max_cu_per_sh; 1415 unsigned max_sh_per_se; 1416 unsigned max_backends_per_se; 1417 unsigned max_texture_channel_caches; 1418 unsigned max_gprs; 1419 unsigned max_gs_threads; 1420 unsigned max_hw_contexts; 1421 unsigned sc_prim_fifo_size_frontend; 1422 unsigned sc_prim_fifo_size_backend; 1423 unsigned sc_hiz_tile_fifo_size; 1424 unsigned sc_earlyz_tile_fifo_size; 1425 1426 unsigned num_tile_pipes; 1427 unsigned backend_enable_mask; 1428 unsigned backend_disable_mask_per_asic; 1429 unsigned backend_map; 1430 unsigned num_texture_channel_caches; 1431 unsigned mem_max_burst_length_bytes; 1432 unsigned mem_row_size_in_kb; 1433 unsigned shader_engine_tile_size; 1434 unsigned num_gpus; 1435 unsigned multi_gpu_tile_size; 1436 1437 unsigned tile_config; 1438 }; 1439 1440 union radeon_asic_config { 1441 struct r300_asic r300; 1442 struct r100_asic r100; 1443 struct r600_asic r600; 1444 struct rv770_asic rv770; 1445 struct evergreen_asic evergreen; 1446 struct cayman_asic cayman; 1447 struct si_asic si; 1448 }; 1449 1450 /* 1451 * asic initizalization from radeon_asic.c 1452 */ 1453 void radeon_agp_disable(struct radeon_device *rdev); 1454 int radeon_asic_init(struct radeon_device *rdev); 1455 1456 1457 /* 1458 * IOCTL. 1459 */ 1460 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 1461 struct drm_file *filp); 1462 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 1463 struct drm_file *filp); 1464 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, 1465 struct drm_file *file_priv); 1466 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, 1467 struct drm_file *file_priv); 1468 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1469 struct drm_file *file_priv); 1470 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, 1471 struct drm_file *file_priv); 1472 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1473 struct drm_file *filp); 1474 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 1475 struct drm_file *filp); 1476 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 1477 struct drm_file *filp); 1478 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1479 struct drm_file *filp); 1480 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 1481 struct drm_file *filp); 1482 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1483 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 1484 struct drm_file *filp); 1485 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 1486 struct drm_file *filp); 1487 1488 /* VRAM scratch page for HDP bug, default vram page */ 1489 struct r600_vram_scratch { 1490 struct radeon_bo *robj; 1491 volatile uint32_t *ptr; 1492 u64 gpu_addr; 1493 }; 1494 1495 /* 1496 * ACPI 1497 */ 1498 struct radeon_atif_notification_cfg { 1499 bool enabled; 1500 int command_code; 1501 }; 1502 1503 struct radeon_atif_notifications { 1504 bool display_switch; 1505 bool expansion_mode_change; 1506 bool thermal_state; 1507 bool forced_power_state; 1508 bool system_power_state; 1509 bool display_conf_change; 1510 bool px_gfx_switch; 1511 bool brightness_change; 1512 bool dgpu_display_event; 1513 }; 1514 1515 struct radeon_atif_functions { 1516 bool system_params; 1517 bool sbios_requests; 1518 bool select_active_disp; 1519 bool lid_state; 1520 bool get_tv_standard; 1521 bool set_tv_standard; 1522 bool get_panel_expansion_mode; 1523 bool set_panel_expansion_mode; 1524 bool temperature_change; 1525 bool graphics_device_types; 1526 }; 1527 1528 struct radeon_atif { 1529 struct radeon_atif_notifications notifications; 1530 struct radeon_atif_functions functions; 1531 struct radeon_atif_notification_cfg notification_cfg; 1532 struct radeon_encoder *encoder_for_bl; 1533 }; 1534 1535 struct radeon_atcs_functions { 1536 bool get_ext_state; 1537 bool pcie_perf_req; 1538 bool pcie_dev_rdy; 1539 bool pcie_bus_width; 1540 }; 1541 1542 struct radeon_atcs { 1543 struct radeon_atcs_functions functions; 1544 }; 1545 1546 /* 1547 * Core structure, functions and helpers. 1548 */ 1549 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); 1550 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); 1551 1552 struct radeon_device { 1553 struct device dev; 1554 struct drm_device *ddev; 1555 struct pci_dev *pdev; 1556 1557 pci_chipset_tag_t pc; 1558 pcitag_t pa_tag; 1559 pci_intr_handle_t intrh; 1560 bus_space_tag_t iot; 1561 bus_space_tag_t memt; 1562 bus_dma_tag_t dmat; 1563 void *irqh; 1564 1565 void (*switchcb)(void *, int, int); 1566 void *switchcbarg; 1567 void *switchcookie; 1568 struct task switchtask; 1569 struct rasops_info ro; 1570 int console; 1571 1572 struct task burner_task; 1573 int burner_dpms_mode; 1574 1575 #ifdef __sparc64__ 1576 struct sunfb sf; 1577 bus_size_t fb_offset; 1578 bus_space_handle_t memh; 1579 #endif 1580 1581 struct rwlock exclusive_lock; 1582 1583 unsigned long fb_aper_offset; 1584 unsigned long fb_aper_size; 1585 1586 /* ASIC */ 1587 union radeon_asic_config config; 1588 enum radeon_family family; 1589 unsigned long flags; 1590 int usec_timeout; 1591 enum radeon_pll_errata pll_errata; 1592 int num_gb_pipes; 1593 int num_z_pipes; 1594 int disp_priority; 1595 /* BIOS */ 1596 uint8_t *bios; 1597 bool is_atom_bios; 1598 uint16_t bios_header_start; 1599 struct radeon_bo *stollen_vga_memory; 1600 /* Register mmio */ 1601 bus_addr_t rmmio_base; 1602 bus_size_t rmmio_size; 1603 /* protects concurrent MM_INDEX/DATA based register access */ 1604 spinlock_t mmio_idx_lock; 1605 bus_space_handle_t rmmio; 1606 radeon_rreg_t mc_rreg; 1607 radeon_wreg_t mc_wreg; 1608 radeon_rreg_t pll_rreg; 1609 radeon_wreg_t pll_wreg; 1610 uint32_t pcie_reg_mask; 1611 radeon_rreg_t pciep_rreg; 1612 radeon_wreg_t pciep_wreg; 1613 /* io port */ 1614 bus_space_handle_t rio_mem; 1615 bus_size_t rio_mem_size; 1616 struct radeon_clock clock; 1617 struct radeon_mc mc; 1618 struct radeon_gart gart; 1619 struct radeon_mode_info mode_info; 1620 struct radeon_scratch scratch; 1621 struct radeon_mman mman; 1622 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1623 wait_queue_head_t fence_queue; 1624 struct rwlock ring_lock; 1625 struct radeon_ring ring[RADEON_NUM_RINGS]; 1626 bool ib_pool_ready; 1627 struct radeon_sa_manager ring_tmp_bo; 1628 struct radeon_irq irq; 1629 struct radeon_asic *asic; 1630 struct radeon_gem gem; 1631 struct radeon_pm pm; 1632 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; 1633 struct radeon_wb wb; 1634 struct radeon_dummy_page dummy_page; 1635 bool shutdown; 1636 bool suspend; 1637 bool need_dma32; 1638 bool accel_working; 1639 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 1640 u_char *me_fw; /* all family ME firmware */ 1641 size_t me_fw_size; 1642 u_char *pfp_fw; /* r6/700 PFP firmware */ 1643 size_t pfp_fw_size; 1644 u_char *rlc_fw; /* r6/700 RLC firmware */ 1645 size_t rlc_fw_size; 1646 u_char *mc_fw; /* NI MC firmware */ 1647 size_t mc_fw_size; 1648 u_char *ce_fw; /* SI CE firmware */ 1649 size_t ce_fw_size; 1650 struct r600_blit r600_blit; 1651 struct r600_vram_scratch vram_scratch; 1652 int msi_enabled; /* msi enabled */ 1653 struct r600_ih ih; /* r6/700 interrupt ring */ 1654 struct si_rlc rlc; 1655 struct task hotplug_task; 1656 struct task audio_task; 1657 int num_crtc; /* number of crtcs */ 1658 struct rwlock dc_hw_i2c_mutex; /* display controller hw i2c mutex */ 1659 bool audio_enabled; 1660 struct r600_audio audio_status; /* audio stuff */ 1661 #ifdef notyet 1662 struct notifier_block acpi_nb; 1663 #endif 1664 /* only one userspace can use Hyperz features or CMASK at a time */ 1665 struct drm_file *hyperz_filp; 1666 struct drm_file *cmask_filp; 1667 /* i2c buses */ 1668 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; 1669 /* debugfs */ 1670 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; 1671 unsigned debugfs_count; 1672 /* virtual memory */ 1673 struct radeon_vm_manager vm_manager; 1674 struct rwlock gpu_clock_mutex; 1675 /* ACPI interface */ 1676 struct radeon_atif atif; 1677 struct radeon_atcs atcs; 1678 }; 1679 1680 int radeon_device_init(struct radeon_device *rdev, 1681 struct drm_device *ddev); 1682 void radeon_device_fini(struct radeon_device *rdev); 1683 int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1684 1685 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 1686 bool always_indirect); 1687 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 1688 bool always_indirect); 1689 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); 1690 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); 1691 1692 /* 1693 * Cast helper 1694 */ 1695 #define to_radeon_fence(p) ((struct radeon_fence *)(p)) 1696 1697 /* 1698 * Registers read & write functions. 1699 */ 1700 #define RREG8(reg) \ 1701 bus_space_read_1(rdev->memt, rdev->rmmio, (reg)) 1702 #define WREG8(reg, v) \ 1703 bus_space_write_1(rdev->memt, rdev->rmmio, (reg), (v)) 1704 #define RREG16(reg) \ 1705 bus_space_read_2(rdev->memt, rdev->rmmio, (reg)) 1706 #define WREG16(reg, v) \ 1707 bus_space_write_2(rdev->memt, rdev->rmmio, (reg), (v)) 1708 1709 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false) 1710 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true) 1711 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false)) 1712 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false) 1713 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true) 1714 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1715 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1716 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) 1717 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) 1718 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) 1719 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) 1720 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) 1721 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) 1722 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) 1723 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) 1724 #define WREG32_P(reg, val, mask) \ 1725 do { \ 1726 uint32_t tmp_ = RREG32(reg); \ 1727 tmp_ &= (mask); \ 1728 tmp_ |= ((val) & ~(mask)); \ 1729 WREG32(reg, tmp_); \ 1730 } while (0) 1731 #define WREG32_PLL_P(reg, val, mask) \ 1732 do { \ 1733 uint32_t tmp_ = RREG32_PLL(reg); \ 1734 tmp_ &= (mask); \ 1735 tmp_ |= ((val) & ~(mask)); \ 1736 WREG32_PLL(reg, tmp_); \ 1737 } while (0) 1738 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false)) 1739 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) 1740 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) 1741 1742 /* 1743 * Indirect registers accessor 1744 */ 1745 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) 1746 { 1747 uint32_t r; 1748 1749 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1750 r = RREG32(RADEON_PCIE_DATA); 1751 return r; 1752 } 1753 1754 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 1755 { 1756 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); 1757 WREG32(RADEON_PCIE_DATA, (v)); 1758 } 1759 1760 void r100_pll_errata_after_index(struct radeon_device *rdev); 1761 1762 1763 /* 1764 * ASICs helpers. 1765 */ 1766 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ 1767 (rdev->pdev->device == 0x5969)) 1768 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ 1769 (rdev->family == CHIP_RV200) || \ 1770 (rdev->family == CHIP_RS100) || \ 1771 (rdev->family == CHIP_RS200) || \ 1772 (rdev->family == CHIP_RV250) || \ 1773 (rdev->family == CHIP_RV280) || \ 1774 (rdev->family == CHIP_RS300)) 1775 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ 1776 (rdev->family == CHIP_RV350) || \ 1777 (rdev->family == CHIP_R350) || \ 1778 (rdev->family == CHIP_RV380) || \ 1779 (rdev->family == CHIP_R420) || \ 1780 (rdev->family == CHIP_R423) || \ 1781 (rdev->family == CHIP_RV410) || \ 1782 (rdev->family == CHIP_RS400) || \ 1783 (rdev->family == CHIP_RS480)) 1784 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ 1785 (rdev->ddev->pdev->device == 0x9443) || \ 1786 (rdev->ddev->pdev->device == 0x944B) || \ 1787 (rdev->ddev->pdev->device == 0x9506) || \ 1788 (rdev->ddev->pdev->device == 0x9509) || \ 1789 (rdev->ddev->pdev->device == 0x950F) || \ 1790 (rdev->ddev->pdev->device == 0x689C) || \ 1791 (rdev->ddev->pdev->device == 0x689D)) 1792 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) 1793 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ 1794 (rdev->family == CHIP_RS690) || \ 1795 (rdev->family == CHIP_RS740) || \ 1796 (rdev->family >= CHIP_R600)) 1797 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) 1798 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) 1799 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) 1800 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ 1801 (rdev->flags & RADEON_IS_IGP)) 1802 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) 1803 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1804 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1805 (rdev->flags & RADEON_IS_IGP)) 1806 1807 /* 1808 * BIOS helpers. 1809 */ 1810 #define RBIOS8(i) (rdev->bios[i]) 1811 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1812 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1813 1814 int radeon_combios_init(struct radeon_device *rdev); 1815 void radeon_combios_fini(struct radeon_device *rdev); 1816 int radeon_atombios_init(struct radeon_device *rdev); 1817 void radeon_atombios_fini(struct radeon_device *rdev); 1818 1819 1820 /* 1821 * RING helpers. 1822 */ 1823 #if !defined(DRM_DEBUG_CODE) || DRM_DEBUG_CODE == 0 1824 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) 1825 { 1826 ring->ring[ring->wptr++] = v; 1827 ring->wptr &= ring->ptr_mask; 1828 ring->count_dw--; 1829 ring->ring_free_dw--; 1830 } 1831 #else 1832 /* With debugging this is just too big to inline */ 1833 void radeon_ring_write(struct radeon_ring *ring, uint32_t v); 1834 #endif 1835 1836 /* 1837 * ASICs macro. 1838 */ 1839 #define radeon_init(rdev) (rdev)->asic->init((rdev)) 1840 #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) 1841 #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) 1842 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1843 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) 1844 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1845 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1846 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) 1847 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1848 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1849 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1850 #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1851 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1852 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1853 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1854 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) 1855 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) 1856 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) 1857 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) 1858 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) 1859 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) 1860 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1861 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1862 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1863 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1864 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1865 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1866 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) 1867 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) 1868 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index 1869 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index 1870 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index 1871 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) 1872 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) 1873 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) 1874 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) 1875 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) 1876 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) 1877 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) 1878 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) 1879 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) 1880 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) 1881 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) 1882 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) 1883 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) 1884 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) 1885 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) 1886 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) 1887 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) 1888 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) 1889 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) 1890 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) 1891 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) 1892 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) 1893 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) 1894 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) 1895 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) 1896 1897 /* Common functions */ 1898 /* AGP */ 1899 extern int radeon_gpu_reset(struct radeon_device *rdev); 1900 extern void radeon_agp_disable(struct radeon_device *rdev); 1901 extern int radeon_modeset_init(struct radeon_device *rdev); 1902 extern void radeon_modeset_fini(struct radeon_device *rdev); 1903 extern bool radeon_card_posted(struct radeon_device *rdev); 1904 extern void radeon_update_bandwidth_info(struct radeon_device *rdev); 1905 extern void radeon_update_display_priority(struct radeon_device *rdev); 1906 extern bool radeon_boot_test_post_card(struct radeon_device *rdev); 1907 extern void radeon_scratch_init(struct radeon_device *rdev); 1908 extern void radeon_wb_fini(struct radeon_device *rdev); 1909 extern int radeon_wb_init(struct radeon_device *rdev); 1910 extern void radeon_wb_disable(struct radeon_device *rdev); 1911 extern void radeon_surface_init(struct radeon_device *rdev); 1912 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); 1913 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 1914 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 1915 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); 1916 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); 1917 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); 1918 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 1919 extern int radeon_resume_kms(struct drm_device *dev); 1920 extern int radeon_suspend_kms(struct drm_device *dev); 1921 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1922 extern struct uvm_object *radeon_mmap(struct drm_device *, voff_t, vsize_t); 1923 1924 /* 1925 * vm 1926 */ 1927 int radeon_vm_manager_init(struct radeon_device *rdev); 1928 void radeon_vm_manager_fini(struct radeon_device *rdev); 1929 void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 1930 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 1931 int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); 1932 void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); 1933 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 1934 struct radeon_vm *vm, int ring); 1935 void radeon_vm_fence(struct radeon_device *rdev, 1936 struct radeon_vm *vm, 1937 struct radeon_fence *fence); 1938 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); 1939 int radeon_vm_bo_update_pte(struct radeon_device *rdev, 1940 struct radeon_vm *vm, 1941 struct radeon_bo *bo, 1942 struct ttm_mem_reg *mem); 1943 void radeon_vm_bo_invalidate(struct radeon_device *rdev, 1944 struct radeon_bo *bo); 1945 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, 1946 struct radeon_bo *bo); 1947 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, 1948 struct radeon_vm *vm, 1949 struct radeon_bo *bo); 1950 int radeon_vm_bo_set_addr(struct radeon_device *rdev, 1951 struct radeon_bo_va *bo_va, 1952 uint64_t offset, 1953 uint32_t flags); 1954 int radeon_vm_bo_rmv(struct radeon_device *rdev, 1955 struct radeon_bo_va *bo_va); 1956 1957 /* audio */ 1958 void r600_audio_update_hdmi(void *arg1); 1959 1960 /* 1961 * R600 vram scratch functions 1962 */ 1963 int r600_vram_scratch_init(struct radeon_device *rdev); 1964 void r600_vram_scratch_fini(struct radeon_device *rdev); 1965 1966 /* 1967 * r600 cs checking helper 1968 */ 1969 unsigned r600_mip_minify(unsigned size, unsigned level); 1970 bool r600_fmt_is_valid_color(u32 format); 1971 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); 1972 int r600_fmt_get_blocksize(u32 format); 1973 int r600_fmt_get_nblocksx(u32 format, u32 w); 1974 int r600_fmt_get_nblocksy(u32 format, u32 h); 1975 1976 /* 1977 * r600 functions used by radeon_encoder.c 1978 */ 1979 struct radeon_hdmi_acr { 1980 u32 clock; 1981 1982 int n_32khz; 1983 int cts_32khz; 1984 1985 int n_44_1khz; 1986 int cts_44_1khz; 1987 1988 int n_48khz; 1989 int cts_48khz; 1990 1991 }; 1992 1993 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 1994 1995 extern void r600_hdmi_enable(struct drm_encoder *encoder); 1996 extern void r600_hdmi_disable(struct drm_encoder *encoder); 1997 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 1998 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1999 u32 tiling_pipe_num, 2000 u32 max_rb_num, 2001 u32 total_max_rb_num, 2002 u32 enabled_rb_mask); 2003 2004 /* 2005 * evergreen functions used by radeon_encoder.c 2006 */ 2007 2008 extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); 2009 2010 extern int ni_init_microcode(struct radeon_device *rdev); 2011 extern int ni_mc_load_microcode(struct radeon_device *rdev); 2012 2013 /* radeon_acpi.c */ 2014 #if defined(CONFIG_ACPI) 2015 extern int radeon_acpi_init(struct radeon_device *rdev); 2016 extern void radeon_acpi_fini(struct radeon_device *rdev); 2017 #else 2018 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } 2019 static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 2020 #endif 2021 2022 #include "radeon_object.h" 2023 2024 #endif 2025