1 /* $OpenBSD: r600.c,v 1.10 2014/07/12 18:48:52 tedu Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/drm/radeon_drm.h> 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "radeon_mode.h" 34 #include "r600d.h" 35 #include "atom.h" 36 #include "avivod.h" 37 38 #define PFP_UCODE_SIZE 576 39 #define PM4_UCODE_SIZE 1792 40 #define RLC_UCODE_SIZE 768 41 #define R700_PFP_UCODE_SIZE 848 42 #define R700_PM4_UCODE_SIZE 1360 43 #define R700_RLC_UCODE_SIZE 1024 44 #define EVERGREEN_PFP_UCODE_SIZE 1120 45 #define EVERGREEN_PM4_UCODE_SIZE 1376 46 #define EVERGREEN_RLC_UCODE_SIZE 768 47 #define CAYMAN_RLC_UCODE_SIZE 1024 48 #define ARUBA_RLC_UCODE_SIZE 1536 49 50 /* Firmware Names */ 51 MODULE_FIRMWARE("radeon/R600_pfp.bin"); 52 MODULE_FIRMWARE("radeon/R600_me.bin"); 53 MODULE_FIRMWARE("radeon/RV610_pfp.bin"); 54 MODULE_FIRMWARE("radeon/RV610_me.bin"); 55 MODULE_FIRMWARE("radeon/RV630_pfp.bin"); 56 MODULE_FIRMWARE("radeon/RV630_me.bin"); 57 MODULE_FIRMWARE("radeon/RV620_pfp.bin"); 58 MODULE_FIRMWARE("radeon/RV620_me.bin"); 59 MODULE_FIRMWARE("radeon/RV635_pfp.bin"); 60 MODULE_FIRMWARE("radeon/RV635_me.bin"); 61 MODULE_FIRMWARE("radeon/RV670_pfp.bin"); 62 MODULE_FIRMWARE("radeon/RV670_me.bin"); 63 MODULE_FIRMWARE("radeon/RS780_pfp.bin"); 64 MODULE_FIRMWARE("radeon/RS780_me.bin"); 65 MODULE_FIRMWARE("radeon/RV770_pfp.bin"); 66 MODULE_FIRMWARE("radeon/RV770_me.bin"); 67 MODULE_FIRMWARE("radeon/RV730_pfp.bin"); 68 MODULE_FIRMWARE("radeon/RV730_me.bin"); 69 MODULE_FIRMWARE("radeon/RV710_pfp.bin"); 70 MODULE_FIRMWARE("radeon/RV710_me.bin"); 71 MODULE_FIRMWARE("radeon/R600_rlc.bin"); 72 MODULE_FIRMWARE("radeon/R700_rlc.bin"); 73 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin"); 74 MODULE_FIRMWARE("radeon/CEDAR_me.bin"); 75 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin"); 76 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin"); 77 MODULE_FIRMWARE("radeon/REDWOOD_me.bin"); 78 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin"); 79 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin"); 80 MODULE_FIRMWARE("radeon/JUNIPER_me.bin"); 81 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin"); 82 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin"); 83 MODULE_FIRMWARE("radeon/CYPRESS_me.bin"); 84 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin"); 85 MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 86 MODULE_FIRMWARE("radeon/PALM_me.bin"); 87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin"); 89 MODULE_FIRMWARE("radeon/SUMO_me.bin"); 90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 91 MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 92 93 int r600_debugfs_mc_info_init(struct radeon_device *rdev); 94 95 /* r600,rv610,rv630,rv620,rv635,rv670 */ 96 int r600_mc_wait_for_idle(struct radeon_device *rdev); 97 static void r600_gpu_init(struct radeon_device *rdev); 98 void r600_fini(struct radeon_device *rdev); 99 void r600_irq_disable(struct radeon_device *rdev); 100 static void r600_pcie_gen2_enable(struct radeon_device *rdev); 101 int r600_ih_ring_alloc(struct radeon_device *rdev); 102 void r600_ih_ring_fini(struct radeon_device *rdev); 103 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); 104 void r600_rlc_start(struct radeon_device *rdev); 105 106 /* get temperature in millidegrees */ 107 int rv6xx_get_temp(struct radeon_device *rdev) 108 { 109 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >> 110 ASIC_T_SHIFT; 111 int actual_temp = temp & 0xff; 112 113 if (temp & 0x100) 114 actual_temp -= 256; 115 116 return actual_temp * 1000; 117 } 118 119 void r600_pm_get_dynpm_state(struct radeon_device *rdev) 120 { 121 int i; 122 123 rdev->pm.dynpm_can_upclock = true; 124 rdev->pm.dynpm_can_downclock = true; 125 126 /* power state array is low to high, default is first */ 127 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { 128 int min_power_state_index = 0; 129 130 if (rdev->pm.num_power_states > 2) 131 min_power_state_index = 1; 132 133 switch (rdev->pm.dynpm_planned_action) { 134 case DYNPM_ACTION_MINIMUM: 135 rdev->pm.requested_power_state_index = min_power_state_index; 136 rdev->pm.requested_clock_mode_index = 0; 137 rdev->pm.dynpm_can_downclock = false; 138 break; 139 case DYNPM_ACTION_DOWNCLOCK: 140 if (rdev->pm.current_power_state_index == min_power_state_index) { 141 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 142 rdev->pm.dynpm_can_downclock = false; 143 } else { 144 if (rdev->pm.active_crtc_count > 1) { 145 for (i = 0; i < rdev->pm.num_power_states; i++) { 146 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 147 continue; 148 else if (i >= rdev->pm.current_power_state_index) { 149 rdev->pm.requested_power_state_index = 150 rdev->pm.current_power_state_index; 151 break; 152 } else { 153 rdev->pm.requested_power_state_index = i; 154 break; 155 } 156 } 157 } else { 158 if (rdev->pm.current_power_state_index == 0) 159 rdev->pm.requested_power_state_index = 160 rdev->pm.num_power_states - 1; 161 else 162 rdev->pm.requested_power_state_index = 163 rdev->pm.current_power_state_index - 1; 164 } 165 } 166 rdev->pm.requested_clock_mode_index = 0; 167 /* don't use the power state if crtcs are active and no display flag is set */ 168 if ((rdev->pm.active_crtc_count > 0) && 169 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 170 clock_info[rdev->pm.requested_clock_mode_index].flags & 171 RADEON_PM_MODE_NO_DISPLAY)) { 172 rdev->pm.requested_power_state_index++; 173 } 174 break; 175 case DYNPM_ACTION_UPCLOCK: 176 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 177 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 178 rdev->pm.dynpm_can_upclock = false; 179 } else { 180 if (rdev->pm.active_crtc_count > 1) { 181 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 182 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 183 continue; 184 else if (i <= rdev->pm.current_power_state_index) { 185 rdev->pm.requested_power_state_index = 186 rdev->pm.current_power_state_index; 187 break; 188 } else { 189 rdev->pm.requested_power_state_index = i; 190 break; 191 } 192 } 193 } else 194 rdev->pm.requested_power_state_index = 195 rdev->pm.current_power_state_index + 1; 196 } 197 rdev->pm.requested_clock_mode_index = 0; 198 break; 199 case DYNPM_ACTION_DEFAULT: 200 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 201 rdev->pm.requested_clock_mode_index = 0; 202 rdev->pm.dynpm_can_upclock = false; 203 break; 204 case DYNPM_ACTION_NONE: 205 default: 206 DRM_ERROR("Requested mode for not defined action\n"); 207 return; 208 } 209 } else { 210 /* XXX select a power state based on AC/DC, single/dualhead, etc. */ 211 /* for now just select the first power state and switch between clock modes */ 212 /* power state array is low to high, default is first (0) */ 213 if (rdev->pm.active_crtc_count > 1) { 214 rdev->pm.requested_power_state_index = -1; 215 /* start at 1 as we don't want the default mode */ 216 for (i = 1; i < rdev->pm.num_power_states; i++) { 217 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 218 continue; 219 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || 220 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { 221 rdev->pm.requested_power_state_index = i; 222 break; 223 } 224 } 225 /* if nothing selected, grab the default state. */ 226 if (rdev->pm.requested_power_state_index == -1) 227 rdev->pm.requested_power_state_index = 0; 228 } else 229 rdev->pm.requested_power_state_index = 1; 230 231 switch (rdev->pm.dynpm_planned_action) { 232 case DYNPM_ACTION_MINIMUM: 233 rdev->pm.requested_clock_mode_index = 0; 234 rdev->pm.dynpm_can_downclock = false; 235 break; 236 case DYNPM_ACTION_DOWNCLOCK: 237 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 238 if (rdev->pm.current_clock_mode_index == 0) { 239 rdev->pm.requested_clock_mode_index = 0; 240 rdev->pm.dynpm_can_downclock = false; 241 } else 242 rdev->pm.requested_clock_mode_index = 243 rdev->pm.current_clock_mode_index - 1; 244 } else { 245 rdev->pm.requested_clock_mode_index = 0; 246 rdev->pm.dynpm_can_downclock = false; 247 } 248 /* don't use the power state if crtcs are active and no display flag is set */ 249 if ((rdev->pm.active_crtc_count > 0) && 250 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. 251 clock_info[rdev->pm.requested_clock_mode_index].flags & 252 RADEON_PM_MODE_NO_DISPLAY)) { 253 rdev->pm.requested_clock_mode_index++; 254 } 255 break; 256 case DYNPM_ACTION_UPCLOCK: 257 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { 258 if (rdev->pm.current_clock_mode_index == 259 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { 260 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; 261 rdev->pm.dynpm_can_upclock = false; 262 } else 263 rdev->pm.requested_clock_mode_index = 264 rdev->pm.current_clock_mode_index + 1; 265 } else { 266 rdev->pm.requested_clock_mode_index = 267 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; 268 rdev->pm.dynpm_can_upclock = false; 269 } 270 break; 271 case DYNPM_ACTION_DEFAULT: 272 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 273 rdev->pm.requested_clock_mode_index = 0; 274 rdev->pm.dynpm_can_upclock = false; 275 break; 276 case DYNPM_ACTION_NONE: 277 default: 278 DRM_ERROR("Requested mode for not defined action\n"); 279 return; 280 } 281 } 282 283 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 284 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 285 clock_info[rdev->pm.requested_clock_mode_index].sclk, 286 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 287 clock_info[rdev->pm.requested_clock_mode_index].mclk, 288 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 289 pcie_lanes); 290 } 291 292 void rs780_pm_init_profile(struct radeon_device *rdev) 293 { 294 if (rdev->pm.num_power_states == 2) { 295 /* default */ 296 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 297 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 298 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 299 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 300 /* low sh */ 301 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 302 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 303 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 304 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 305 /* mid sh */ 306 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 307 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 308 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 309 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 310 /* high sh */ 311 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 312 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 313 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 314 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 315 /* low mh */ 316 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 317 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 320 /* mid mh */ 321 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 322 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 325 /* high mh */ 326 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 327 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; 328 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 329 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 330 } else if (rdev->pm.num_power_states == 3) { 331 /* default */ 332 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 333 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 334 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 336 /* low sh */ 337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 341 /* mid sh */ 342 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 343 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 344 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 345 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 346 /* high sh */ 347 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 348 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; 349 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 350 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 351 /* low mh */ 352 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; 353 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; 354 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 355 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 356 /* mid mh */ 357 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; 358 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; 359 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 360 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 361 /* high mh */ 362 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; 363 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 366 } else { 367 /* default */ 368 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 369 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 370 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 371 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 372 /* low sh */ 373 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; 374 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; 375 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 376 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 377 /* mid sh */ 378 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; 379 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; 380 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 381 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 382 /* high sh */ 383 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; 384 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; 385 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 386 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 387 /* low mh */ 388 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 389 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; 390 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 391 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 392 /* mid mh */ 393 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 394 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; 395 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 396 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 397 /* high mh */ 398 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 399 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; 400 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 401 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 402 } 403 } 404 405 void r600_pm_init_profile(struct radeon_device *rdev) 406 { 407 int idx; 408 409 if (rdev->family == CHIP_R600) { 410 /* XXX */ 411 /* default */ 412 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 413 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 414 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 415 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 416 /* low sh */ 417 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 418 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 419 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 420 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 421 /* mid sh */ 422 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 423 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 424 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 425 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 426 /* high sh */ 427 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 428 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 429 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 430 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 431 /* low mh */ 432 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 433 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 434 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 435 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 436 /* mid mh */ 437 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 438 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 439 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 440 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 441 /* high mh */ 442 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 443 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 444 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 445 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 446 } else { 447 if (rdev->pm.num_power_states < 4) { 448 /* default */ 449 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 450 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 451 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 452 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 453 /* low sh */ 454 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; 455 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; 456 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 457 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 458 /* mid sh */ 459 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; 460 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 461 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 462 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 463 /* high sh */ 464 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; 465 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; 466 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 467 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 468 /* low mh */ 469 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; 470 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; 471 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 473 /* low mh */ 474 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; 475 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; 476 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 477 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 478 /* high mh */ 479 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; 480 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; 481 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 482 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 483 } else { 484 /* default */ 485 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 486 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 487 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 488 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; 489 /* low sh */ 490 if (rdev->flags & RADEON_IS_MOBILITY) 491 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); 492 else 493 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 494 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; 495 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; 496 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 497 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 498 /* mid sh */ 499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; 500 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; 501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 502 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; 503 /* high sh */ 504 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); 505 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; 506 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; 507 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 508 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; 509 /* low mh */ 510 if (rdev->flags & RADEON_IS_MOBILITY) 511 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1); 512 else 513 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 514 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; 515 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; 516 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 518 /* mid mh */ 519 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; 520 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; 521 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 522 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; 523 /* high mh */ 524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1); 525 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; 526 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; 527 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 528 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; 529 } 530 } 531 } 532 533 void r600_pm_misc(struct radeon_device *rdev) 534 { 535 int req_ps_idx = rdev->pm.requested_power_state_index; 536 int req_cm_idx = rdev->pm.requested_clock_mode_index; 537 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; 538 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; 539 540 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { 541 /* 0xff01 is a flag rather then an actual voltage */ 542 if (voltage->voltage == 0xff01) 543 return; 544 if (voltage->voltage != rdev->pm.current_vddc) { 545 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); 546 rdev->pm.current_vddc = voltage->voltage; 547 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); 548 } 549 } 550 } 551 552 bool r600_gui_idle(struct radeon_device *rdev) 553 { 554 if (RREG32(GRBM_STATUS) & GUI_ACTIVE) 555 return false; 556 else 557 return true; 558 } 559 560 /* hpd for digital panel detect/disconnect */ 561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 562 { 563 bool connected = false; 564 565 if (ASIC_IS_DCE3(rdev)) { 566 switch (hpd) { 567 case RADEON_HPD_1: 568 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) 569 connected = true; 570 break; 571 case RADEON_HPD_2: 572 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) 573 connected = true; 574 break; 575 case RADEON_HPD_3: 576 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) 577 connected = true; 578 break; 579 case RADEON_HPD_4: 580 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) 581 connected = true; 582 break; 583 /* DCE 3.2 */ 584 case RADEON_HPD_5: 585 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) 586 connected = true; 587 break; 588 case RADEON_HPD_6: 589 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) 590 connected = true; 591 break; 592 default: 593 break; 594 } 595 } else { 596 switch (hpd) { 597 case RADEON_HPD_1: 598 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 599 connected = true; 600 break; 601 case RADEON_HPD_2: 602 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 603 connected = true; 604 break; 605 case RADEON_HPD_3: 606 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE) 607 connected = true; 608 break; 609 default: 610 break; 611 } 612 } 613 return connected; 614 } 615 616 void r600_hpd_set_polarity(struct radeon_device *rdev, 617 enum radeon_hpd_id hpd) 618 { 619 u32 tmp; 620 bool connected = r600_hpd_sense(rdev, hpd); 621 622 if (ASIC_IS_DCE3(rdev)) { 623 switch (hpd) { 624 case RADEON_HPD_1: 625 tmp = RREG32(DC_HPD1_INT_CONTROL); 626 if (connected) 627 tmp &= ~DC_HPDx_INT_POLARITY; 628 else 629 tmp |= DC_HPDx_INT_POLARITY; 630 WREG32(DC_HPD1_INT_CONTROL, tmp); 631 break; 632 case RADEON_HPD_2: 633 tmp = RREG32(DC_HPD2_INT_CONTROL); 634 if (connected) 635 tmp &= ~DC_HPDx_INT_POLARITY; 636 else 637 tmp |= DC_HPDx_INT_POLARITY; 638 WREG32(DC_HPD2_INT_CONTROL, tmp); 639 break; 640 case RADEON_HPD_3: 641 tmp = RREG32(DC_HPD3_INT_CONTROL); 642 if (connected) 643 tmp &= ~DC_HPDx_INT_POLARITY; 644 else 645 tmp |= DC_HPDx_INT_POLARITY; 646 WREG32(DC_HPD3_INT_CONTROL, tmp); 647 break; 648 case RADEON_HPD_4: 649 tmp = RREG32(DC_HPD4_INT_CONTROL); 650 if (connected) 651 tmp &= ~DC_HPDx_INT_POLARITY; 652 else 653 tmp |= DC_HPDx_INT_POLARITY; 654 WREG32(DC_HPD4_INT_CONTROL, tmp); 655 break; 656 case RADEON_HPD_5: 657 tmp = RREG32(DC_HPD5_INT_CONTROL); 658 if (connected) 659 tmp &= ~DC_HPDx_INT_POLARITY; 660 else 661 tmp |= DC_HPDx_INT_POLARITY; 662 WREG32(DC_HPD5_INT_CONTROL, tmp); 663 break; 664 /* DCE 3.2 */ 665 case RADEON_HPD_6: 666 tmp = RREG32(DC_HPD6_INT_CONTROL); 667 if (connected) 668 tmp &= ~DC_HPDx_INT_POLARITY; 669 else 670 tmp |= DC_HPDx_INT_POLARITY; 671 WREG32(DC_HPD6_INT_CONTROL, tmp); 672 break; 673 default: 674 break; 675 } 676 } else { 677 switch (hpd) { 678 case RADEON_HPD_1: 679 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 680 if (connected) 681 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 682 else 683 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 684 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 685 break; 686 case RADEON_HPD_2: 687 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 688 if (connected) 689 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 690 else 691 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 692 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 693 break; 694 case RADEON_HPD_3: 695 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 696 if (connected) 697 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; 698 else 699 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; 700 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 701 break; 702 default: 703 break; 704 } 705 } 706 } 707 708 void r600_hpd_init(struct radeon_device *rdev) 709 { 710 struct drm_device *dev = rdev->ddev; 711 struct drm_connector *connector; 712 unsigned enable = 0; 713 714 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 715 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 716 717 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 718 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 719 /* don't try to enable hpd on eDP or LVDS avoid breaking the 720 * aux dp channel on imac and help (but not completely fix) 721 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 722 */ 723 continue; 724 } 725 if (ASIC_IS_DCE3(rdev)) { 726 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); 727 if (ASIC_IS_DCE32(rdev)) 728 tmp |= DC_HPDx_EN; 729 730 switch (radeon_connector->hpd.hpd) { 731 case RADEON_HPD_1: 732 WREG32(DC_HPD1_CONTROL, tmp); 733 break; 734 case RADEON_HPD_2: 735 WREG32(DC_HPD2_CONTROL, tmp); 736 break; 737 case RADEON_HPD_3: 738 WREG32(DC_HPD3_CONTROL, tmp); 739 break; 740 case RADEON_HPD_4: 741 WREG32(DC_HPD4_CONTROL, tmp); 742 break; 743 /* DCE 3.2 */ 744 case RADEON_HPD_5: 745 WREG32(DC_HPD5_CONTROL, tmp); 746 break; 747 case RADEON_HPD_6: 748 WREG32(DC_HPD6_CONTROL, tmp); 749 break; 750 default: 751 break; 752 } 753 } else { 754 switch (radeon_connector->hpd.hpd) { 755 case RADEON_HPD_1: 756 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); 757 break; 758 case RADEON_HPD_2: 759 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); 760 break; 761 case RADEON_HPD_3: 762 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); 763 break; 764 default: 765 break; 766 } 767 } 768 enable |= 1 << radeon_connector->hpd.hpd; 769 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 770 } 771 radeon_irq_kms_enable_hpd(rdev, enable); 772 } 773 774 void r600_hpd_fini(struct radeon_device *rdev) 775 { 776 struct drm_device *dev = rdev->ddev; 777 struct drm_connector *connector; 778 unsigned disable = 0; 779 780 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 781 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 782 if (ASIC_IS_DCE3(rdev)) { 783 switch (radeon_connector->hpd.hpd) { 784 case RADEON_HPD_1: 785 WREG32(DC_HPD1_CONTROL, 0); 786 break; 787 case RADEON_HPD_2: 788 WREG32(DC_HPD2_CONTROL, 0); 789 break; 790 case RADEON_HPD_3: 791 WREG32(DC_HPD3_CONTROL, 0); 792 break; 793 case RADEON_HPD_4: 794 WREG32(DC_HPD4_CONTROL, 0); 795 break; 796 /* DCE 3.2 */ 797 case RADEON_HPD_5: 798 WREG32(DC_HPD5_CONTROL, 0); 799 break; 800 case RADEON_HPD_6: 801 WREG32(DC_HPD6_CONTROL, 0); 802 break; 803 default: 804 break; 805 } 806 } else { 807 switch (radeon_connector->hpd.hpd) { 808 case RADEON_HPD_1: 809 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); 810 break; 811 case RADEON_HPD_2: 812 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); 813 break; 814 case RADEON_HPD_3: 815 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); 816 break; 817 default: 818 break; 819 } 820 } 821 disable |= 1 << radeon_connector->hpd.hpd; 822 } 823 radeon_irq_kms_disable_hpd(rdev, disable); 824 } 825 826 /* 827 * R600 PCIE GART 828 */ 829 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) 830 { 831 unsigned i; 832 u32 tmp; 833 834 /* flush hdp cache so updates hit vram */ 835 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 836 !(rdev->flags & RADEON_IS_AGP)) { 837 volatile uint32_t *ptr = rdev->gart.ptr; 838 u32 tmp; 839 840 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 841 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 842 * This seems to cause problems on some AGP cards. Just use the old 843 * method for them. 844 */ 845 WREG32(HDP_DEBUG1, 0); 846 tmp = *ptr; 847 } else 848 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 849 850 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); 851 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); 852 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 853 for (i = 0; i < rdev->usec_timeout; i++) { 854 /* read MC_STATUS */ 855 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); 856 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; 857 if (tmp == 2) { 858 DRM_ERROR("[drm] r600 flush TLB failed\n"); 859 return; 860 } 861 if (tmp) { 862 return; 863 } 864 udelay(1); 865 } 866 } 867 868 int r600_pcie_gart_init(struct radeon_device *rdev) 869 { 870 int r; 871 872 if (rdev->gart.robj) { 873 WARN(1, "R600 PCIE GART already initialized\n"); 874 return 0; 875 } 876 /* Initialize common gart structure */ 877 r = radeon_gart_init(rdev); 878 if (r) 879 return r; 880 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; 881 return radeon_gart_table_vram_alloc(rdev); 882 } 883 884 static int r600_pcie_gart_enable(struct radeon_device *rdev) 885 { 886 u32 tmp; 887 int r, i; 888 889 if (rdev->gart.robj == NULL) { 890 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 891 return -EINVAL; 892 } 893 r = radeon_gart_table_vram_pin(rdev); 894 if (r) 895 return r; 896 radeon_gart_restore(rdev); 897 898 /* Setup L2 cache */ 899 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 900 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 901 EFFECTIVE_L2_QUEUE_SIZE(7)); 902 WREG32(VM_L2_CNTL2, 0); 903 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 904 /* Setup TLB control */ 905 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 906 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 907 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 908 ENABLE_WAIT_L2_QUERY; 909 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 910 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 911 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 912 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 913 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 914 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 915 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 916 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 917 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 918 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 919 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 920 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 921 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 922 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 923 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); 924 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); 925 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); 926 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 927 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 928 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 929 (u32)(rdev->dummy_page.addr >> 12)); 930 for (i = 1; i < 7; i++) 931 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 932 933 r600_pcie_gart_tlb_flush(rdev); 934 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 935 (unsigned)(rdev->mc.gtt_size >> 20), 936 (unsigned long long)rdev->gart.table_addr); 937 rdev->gart.ready = true; 938 return 0; 939 } 940 941 static void r600_pcie_gart_disable(struct radeon_device *rdev) 942 { 943 u32 tmp; 944 int i; 945 946 /* Disable all tables */ 947 for (i = 0; i < 7; i++) 948 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 949 950 /* Disable L2 cache */ 951 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 952 EFFECTIVE_L2_QUEUE_SIZE(7)); 953 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 954 /* Setup L1 TLB control */ 955 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 956 ENABLE_WAIT_L2_QUERY; 957 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 958 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 959 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 960 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 961 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 962 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 963 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 964 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 965 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); 966 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); 967 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 968 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 969 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); 970 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 971 radeon_gart_table_vram_unpin(rdev); 972 } 973 974 static void r600_pcie_gart_fini(struct radeon_device *rdev) 975 { 976 radeon_gart_fini(rdev); 977 r600_pcie_gart_disable(rdev); 978 radeon_gart_table_vram_free(rdev); 979 } 980 981 static void r600_agp_enable(struct radeon_device *rdev) 982 { 983 u32 tmp; 984 int i; 985 986 /* Setup L2 cache */ 987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 988 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | 989 EFFECTIVE_L2_QUEUE_SIZE(7)); 990 WREG32(VM_L2_CNTL2, 0); 991 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); 992 /* Setup TLB control */ 993 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | 994 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 995 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | 996 ENABLE_WAIT_L2_QUERY; 997 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); 998 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); 999 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); 1000 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); 1001 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); 1002 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); 1003 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); 1004 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); 1005 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); 1006 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); 1007 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); 1008 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); 1009 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1010 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); 1011 for (i = 0; i < 7; i++) 1012 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 1013 } 1014 1015 int r600_mc_wait_for_idle(struct radeon_device *rdev) 1016 { 1017 unsigned i; 1018 u32 tmp; 1019 1020 for (i = 0; i < rdev->usec_timeout; i++) { 1021 /* read MC_STATUS */ 1022 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; 1023 if (!tmp) 1024 return 0; 1025 udelay(1); 1026 } 1027 return -1; 1028 } 1029 1030 static void r600_mc_program(struct radeon_device *rdev) 1031 { 1032 struct rv515_mc_save save; 1033 u32 tmp; 1034 int i, j; 1035 1036 /* Initialize HDP */ 1037 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1038 WREG32((0x2c14 + j), 0x00000000); 1039 WREG32((0x2c18 + j), 0x00000000); 1040 WREG32((0x2c1c + j), 0x00000000); 1041 WREG32((0x2c20 + j), 0x00000000); 1042 WREG32((0x2c24 + j), 0x00000000); 1043 } 1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); 1045 1046 rv515_mc_stop(rdev, &save); 1047 if (r600_mc_wait_for_idle(rdev)) { 1048 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1049 } 1050 /* Lockout access through VGA aperture (doesn't exist before R600) */ 1051 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); 1052 /* Update configuration */ 1053 if (rdev->flags & RADEON_IS_AGP) { 1054 if (rdev->mc.vram_start < rdev->mc.gtt_start) { 1055 /* VRAM before AGP */ 1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1057 rdev->mc.vram_start >> 12); 1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1059 rdev->mc.gtt_end >> 12); 1060 } else { 1061 /* VRAM after AGP */ 1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, 1063 rdev->mc.gtt_start >> 12); 1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, 1065 rdev->mc.vram_end >> 12); 1066 } 1067 } else { 1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); 1069 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); 1070 } 1071 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); 1072 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1073 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1074 WREG32(MC_VM_FB_LOCATION, tmp); 1075 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1076 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1077 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1078 if (rdev->flags & RADEON_IS_AGP) { 1079 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); 1080 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); 1081 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); 1082 } else { 1083 WREG32(MC_VM_AGP_BASE, 0); 1084 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); 1085 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); 1086 } 1087 if (r600_mc_wait_for_idle(rdev)) { 1088 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1089 } 1090 rv515_mc_resume(rdev, &save); 1091 /* we need to own VRAM, so turn off the VGA renderer here 1092 * to stop it overwriting our objects */ 1093 rv515_vga_render_disable(rdev); 1094 } 1095 1096 /** 1097 * r600_vram_gtt_location - try to find VRAM & GTT location 1098 * @rdev: radeon device structure holding all necessary informations 1099 * @mc: memory controller structure holding memory informations 1100 * 1101 * Function will place try to place VRAM at same place as in CPU (PCI) 1102 * address space as some GPU seems to have issue when we reprogram at 1103 * different address space. 1104 * 1105 * If there is not enough space to fit the unvisible VRAM after the 1106 * aperture then we limit the VRAM size to the aperture. 1107 * 1108 * If we are using AGP then place VRAM adjacent to AGP aperture are we need 1109 * them to be in one from GPU point of view so that we can program GPU to 1110 * catch access outside them (weird GPU policy see ??). 1111 * 1112 * This function will never fails, worst case are limiting VRAM or GTT. 1113 * 1114 * Note: GTT start, end, size should be initialized before calling this 1115 * function on AGP platform. 1116 */ 1117 void 1118 r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 1119 { 1120 u64 size_bf, size_af; 1121 1122 if (mc->mc_vram_size > 0xE0000000) { 1123 /* leave room for at least 512M GTT */ 1124 dev_warn(rdev->dev, "limiting VRAM\n"); 1125 mc->real_vram_size = 0xE0000000; 1126 mc->mc_vram_size = 0xE0000000; 1127 } 1128 if (rdev->flags & RADEON_IS_AGP) { 1129 size_bf = mc->gtt_start; 1130 size_af = 0xFFFFFFFF - mc->gtt_end; 1131 if (size_bf > size_af) { 1132 if (mc->mc_vram_size > size_bf) { 1133 dev_warn(rdev->dev, "limiting VRAM\n"); 1134 mc->real_vram_size = size_bf; 1135 mc->mc_vram_size = size_bf; 1136 } 1137 mc->vram_start = mc->gtt_start - mc->mc_vram_size; 1138 } else { 1139 if (mc->mc_vram_size > size_af) { 1140 dev_warn(rdev->dev, "limiting VRAM\n"); 1141 mc->real_vram_size = size_af; 1142 mc->mc_vram_size = size_af; 1143 } 1144 mc->vram_start = mc->gtt_end + 1; 1145 } 1146 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 1147 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", 1148 mc->mc_vram_size >> 20, mc->vram_start, 1149 mc->vram_end, mc->real_vram_size >> 20); 1150 } else { 1151 u64 base = 0; 1152 if (rdev->flags & RADEON_IS_IGP) { 1153 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF; 1154 base <<= 24; 1155 } 1156 radeon_vram_location(rdev, &rdev->mc, base); 1157 rdev->mc.gtt_base_align = 0; 1158 radeon_gtt_location(rdev, mc); 1159 } 1160 } 1161 1162 static int r600_mc_init(struct radeon_device *rdev) 1163 { 1164 u32 tmp; 1165 int chansize, numchan; 1166 1167 /* Get VRAM informations */ 1168 rdev->mc.vram_is_ddr = true; 1169 tmp = RREG32(RAMCFG); 1170 if (tmp & CHANSIZE_OVERRIDE) { 1171 chansize = 16; 1172 } else if (tmp & CHANSIZE_MASK) { 1173 chansize = 64; 1174 } else { 1175 chansize = 32; 1176 } 1177 tmp = RREG32(CHMAP); 1178 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { 1179 case 0: 1180 default: 1181 numchan = 1; 1182 break; 1183 case 1: 1184 numchan = 2; 1185 break; 1186 case 2: 1187 numchan = 4; 1188 break; 1189 case 3: 1190 numchan = 8; 1191 break; 1192 } 1193 rdev->mc.vram_width = numchan * chansize; 1194 /* Could aper size report 0 ? */ 1195 rdev->mc.aper_base = rdev->fb_aper_offset; 1196 rdev->mc.aper_size = rdev->fb_aper_size; 1197 /* Setup GPU memory space */ 1198 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); 1199 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 1200 rdev->mc.visible_vram_size = rdev->mc.aper_size; 1201 r600_vram_gtt_location(rdev, &rdev->mc); 1202 1203 if (rdev->flags & RADEON_IS_IGP) { 1204 rs690_pm_info(rdev); 1205 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); 1206 } 1207 radeon_update_bandwidth_info(rdev); 1208 return 0; 1209 } 1210 1211 int r600_vram_scratch_init(struct radeon_device *rdev) 1212 { 1213 int r; 1214 1215 if (rdev->vram_scratch.robj == NULL) { 1216 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, 1217 PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 1218 NULL, &rdev->vram_scratch.robj); 1219 if (r) { 1220 return r; 1221 } 1222 } 1223 1224 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1225 if (unlikely(r != 0)) 1226 return r; 1227 r = radeon_bo_pin(rdev->vram_scratch.robj, 1228 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); 1229 if (r) { 1230 radeon_bo_unreserve(rdev->vram_scratch.robj); 1231 return r; 1232 } 1233 r = radeon_bo_kmap(rdev->vram_scratch.robj, 1234 (void **)&rdev->vram_scratch.ptr); 1235 if (r) 1236 radeon_bo_unpin(rdev->vram_scratch.robj); 1237 radeon_bo_unreserve(rdev->vram_scratch.robj); 1238 1239 return r; 1240 } 1241 1242 void r600_vram_scratch_fini(struct radeon_device *rdev) 1243 { 1244 int r; 1245 1246 if (rdev->vram_scratch.robj == NULL) { 1247 return; 1248 } 1249 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); 1250 if (likely(r == 0)) { 1251 radeon_bo_kunmap(rdev->vram_scratch.robj); 1252 radeon_bo_unpin(rdev->vram_scratch.robj); 1253 radeon_bo_unreserve(rdev->vram_scratch.robj); 1254 } 1255 radeon_bo_unref(&rdev->vram_scratch.robj); 1256 } 1257 1258 /* We doesn't check that the GPU really needs a reset we simply do the 1259 * reset, it's up to the caller to determine if the GPU needs one. We 1260 * might add an helper function to check that. 1261 */ 1262 static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev) 1263 { 1264 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 1265 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) | 1266 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) | 1267 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) | 1268 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) | 1269 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) | 1270 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) | 1271 S_008010_GUI_ACTIVE(1); 1272 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) | 1273 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) | 1274 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) | 1275 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) | 1276 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) | 1277 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) | 1278 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) | 1279 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1); 1280 u32 tmp; 1281 1282 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1283 return; 1284 1285 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1286 RREG32(R_008010_GRBM_STATUS)); 1287 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1288 RREG32(R_008014_GRBM_STATUS2)); 1289 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1290 RREG32(R_000E50_SRBM_STATUS)); 1291 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1292 RREG32(CP_STALLED_STAT1)); 1293 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1294 RREG32(CP_STALLED_STAT2)); 1295 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1296 RREG32(CP_BUSY_STAT)); 1297 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1298 RREG32(CP_STAT)); 1299 1300 /* Disable CP parsing/prefetching */ 1301 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1302 1303 /* Check if any of the rendering block is busy and reset it */ 1304 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 1305 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 1306 tmp = S_008020_SOFT_RESET_CR(1) | 1307 S_008020_SOFT_RESET_DB(1) | 1308 S_008020_SOFT_RESET_CB(1) | 1309 S_008020_SOFT_RESET_PA(1) | 1310 S_008020_SOFT_RESET_SC(1) | 1311 S_008020_SOFT_RESET_SMX(1) | 1312 S_008020_SOFT_RESET_SPI(1) | 1313 S_008020_SOFT_RESET_SX(1) | 1314 S_008020_SOFT_RESET_SH(1) | 1315 S_008020_SOFT_RESET_TC(1) | 1316 S_008020_SOFT_RESET_TA(1) | 1317 S_008020_SOFT_RESET_VC(1) | 1318 S_008020_SOFT_RESET_VGT(1); 1319 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1320 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1321 RREG32(R_008020_GRBM_SOFT_RESET); 1322 mdelay(15); 1323 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1324 } 1325 /* Reset CP (we always reset CP) */ 1326 tmp = S_008020_SOFT_RESET_CP(1); 1327 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); 1328 WREG32(R_008020_GRBM_SOFT_RESET, tmp); 1329 RREG32(R_008020_GRBM_SOFT_RESET); 1330 mdelay(15); 1331 WREG32(R_008020_GRBM_SOFT_RESET, 0); 1332 1333 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1334 RREG32(R_008010_GRBM_STATUS)); 1335 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1336 RREG32(R_008014_GRBM_STATUS2)); 1337 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1338 RREG32(R_000E50_SRBM_STATUS)); 1339 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1340 RREG32(CP_STALLED_STAT1)); 1341 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1342 RREG32(CP_STALLED_STAT2)); 1343 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1344 RREG32(CP_BUSY_STAT)); 1345 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1346 RREG32(CP_STAT)); 1347 1348 } 1349 1350 static void r600_gpu_soft_reset_dma(struct radeon_device *rdev) 1351 { 1352 u32 tmp; 1353 1354 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1355 return; 1356 1357 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1358 RREG32(DMA_STATUS_REG)); 1359 1360 /* Disable DMA */ 1361 tmp = RREG32(DMA_RB_CNTL); 1362 tmp &= ~DMA_RB_ENABLE; 1363 WREG32(DMA_RB_CNTL, tmp); 1364 1365 /* Reset dma */ 1366 if (rdev->family >= CHIP_RV770) 1367 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 1368 else 1369 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 1370 RREG32(SRBM_SOFT_RESET); 1371 udelay(50); 1372 WREG32(SRBM_SOFT_RESET, 0); 1373 1374 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1375 RREG32(DMA_STATUS_REG)); 1376 } 1377 1378 static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1379 { 1380 struct rv515_mc_save save; 1381 1382 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1383 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE); 1384 1385 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1386 reset_mask &= ~RADEON_RESET_DMA; 1387 1388 if (reset_mask == 0) 1389 return 0; 1390 1391 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1392 1393 rv515_mc_stop(rdev, &save); 1394 if (r600_mc_wait_for_idle(rdev)) { 1395 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1396 } 1397 1398 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 1399 r600_gpu_soft_reset_gfx(rdev); 1400 1401 if (reset_mask & RADEON_RESET_DMA) 1402 r600_gpu_soft_reset_dma(rdev); 1403 1404 /* Wait a little for things to settle down */ 1405 mdelay(1); 1406 1407 rv515_mc_resume(rdev, &save); 1408 return 0; 1409 } 1410 1411 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1412 { 1413 u32 srbm_status; 1414 u32 grbm_status; 1415 u32 grbm_status2; 1416 1417 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1418 grbm_status = RREG32(R_008010_GRBM_STATUS); 1419 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1420 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1421 radeon_ring_lockup_update(ring); 1422 return false; 1423 } 1424 /* force CP activities */ 1425 radeon_ring_force_activity(rdev, ring); 1426 return radeon_ring_test_lockup(rdev, ring); 1427 } 1428 1429 /** 1430 * r600_dma_is_lockup - Check if the DMA engine is locked up 1431 * 1432 * @rdev: radeon_device pointer 1433 * @ring: radeon_ring structure holding ring information 1434 * 1435 * Check if the async DMA engine is locked up (r6xx-evergreen). 1436 * Returns true if the engine appears to be locked up, false if not. 1437 */ 1438 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1439 { 1440 u32 dma_status_reg; 1441 1442 dma_status_reg = RREG32(DMA_STATUS_REG); 1443 if (dma_status_reg & DMA_IDLE) { 1444 radeon_ring_lockup_update(ring); 1445 return false; 1446 } 1447 /* force ring activities */ 1448 radeon_ring_force_activity(rdev, ring); 1449 return radeon_ring_test_lockup(rdev, ring); 1450 } 1451 1452 int r600_asic_reset(struct radeon_device *rdev) 1453 { 1454 return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 1455 RADEON_RESET_COMPUTE | 1456 RADEON_RESET_DMA)); 1457 } 1458 1459 u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1460 u32 tiling_pipe_num, 1461 u32 max_rb_num, 1462 u32 total_max_rb_num, 1463 u32 disabled_rb_mask) 1464 { 1465 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1466 u32 pipe_rb_ratio, pipe_rb_remain, tmp; 1467 u32 data = 0, mask = 1 << (max_rb_num - 1); 1468 unsigned i, j; 1469 1470 /* mask out the RBs that don't exist on that asic */ 1471 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); 1472 /* make sure at least one RB is available */ 1473 if ((tmp & 0xff) != 0xff) 1474 disabled_rb_mask = tmp; 1475 1476 rendering_pipe_num = 1 << tiling_pipe_num; 1477 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1478 BUG_ON(rendering_pipe_num < req_rb_num); 1479 1480 pipe_rb_ratio = rendering_pipe_num / req_rb_num; 1481 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; 1482 1483 if (rdev->family <= CHIP_RV740) { 1484 /* r6xx/r7xx */ 1485 rb_num_width = 2; 1486 } else { 1487 /* eg+ */ 1488 rb_num_width = 4; 1489 } 1490 1491 for (i = 0; i < max_rb_num; i++) { 1492 if (!(mask & disabled_rb_mask)) { 1493 for (j = 0; j < pipe_rb_ratio; j++) { 1494 data <<= rb_num_width; 1495 data |= max_rb_num - i - 1; 1496 } 1497 if (pipe_rb_remain) { 1498 data <<= rb_num_width; 1499 data |= max_rb_num - i - 1; 1500 pipe_rb_remain--; 1501 } 1502 } 1503 mask >>= 1; 1504 } 1505 1506 return data; 1507 } 1508 1509 static inline uint32_t hweight32(uint32_t x) 1510 { 1511 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 1512 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 1513 x = (x + (x >> 4)) & 0x0f0f0f0f; 1514 x = (x + (x >> 8)); 1515 x = (x + (x >> 16)) & 0x000000ff; 1516 return x; 1517 } 1518 1519 int r600_count_pipe_bits(uint32_t val) 1520 { 1521 return hweight32(val); 1522 } 1523 1524 static void r600_gpu_init(struct radeon_device *rdev) 1525 { 1526 u32 tiling_config; 1527 u32 ramcfg; 1528 u32 cc_rb_backend_disable; 1529 u32 cc_gc_shader_pipe_config; 1530 u32 tmp; 1531 int i, j; 1532 u32 sq_config; 1533 u32 sq_gpr_resource_mgmt_1 = 0; 1534 u32 sq_gpr_resource_mgmt_2 = 0; 1535 u32 sq_thread_resource_mgmt = 0; 1536 u32 sq_stack_resource_mgmt_1 = 0; 1537 u32 sq_stack_resource_mgmt_2 = 0; 1538 u32 disabled_rb_mask; 1539 1540 rdev->config.r600.tiling_group_size = 256; 1541 switch (rdev->family) { 1542 case CHIP_R600: 1543 rdev->config.r600.max_pipes = 4; 1544 rdev->config.r600.max_tile_pipes = 8; 1545 rdev->config.r600.max_simds = 4; 1546 rdev->config.r600.max_backends = 4; 1547 rdev->config.r600.max_gprs = 256; 1548 rdev->config.r600.max_threads = 192; 1549 rdev->config.r600.max_stack_entries = 256; 1550 rdev->config.r600.max_hw_contexts = 8; 1551 rdev->config.r600.max_gs_threads = 16; 1552 rdev->config.r600.sx_max_export_size = 128; 1553 rdev->config.r600.sx_max_export_pos_size = 16; 1554 rdev->config.r600.sx_max_export_smx_size = 128; 1555 rdev->config.r600.sq_num_cf_insts = 2; 1556 break; 1557 case CHIP_RV630: 1558 case CHIP_RV635: 1559 rdev->config.r600.max_pipes = 2; 1560 rdev->config.r600.max_tile_pipes = 2; 1561 rdev->config.r600.max_simds = 3; 1562 rdev->config.r600.max_backends = 1; 1563 rdev->config.r600.max_gprs = 128; 1564 rdev->config.r600.max_threads = 192; 1565 rdev->config.r600.max_stack_entries = 128; 1566 rdev->config.r600.max_hw_contexts = 8; 1567 rdev->config.r600.max_gs_threads = 4; 1568 rdev->config.r600.sx_max_export_size = 128; 1569 rdev->config.r600.sx_max_export_pos_size = 16; 1570 rdev->config.r600.sx_max_export_smx_size = 128; 1571 rdev->config.r600.sq_num_cf_insts = 2; 1572 break; 1573 case CHIP_RV610: 1574 case CHIP_RV620: 1575 case CHIP_RS780: 1576 case CHIP_RS880: 1577 rdev->config.r600.max_pipes = 1; 1578 rdev->config.r600.max_tile_pipes = 1; 1579 rdev->config.r600.max_simds = 2; 1580 rdev->config.r600.max_backends = 1; 1581 rdev->config.r600.max_gprs = 128; 1582 rdev->config.r600.max_threads = 192; 1583 rdev->config.r600.max_stack_entries = 128; 1584 rdev->config.r600.max_hw_contexts = 4; 1585 rdev->config.r600.max_gs_threads = 4; 1586 rdev->config.r600.sx_max_export_size = 128; 1587 rdev->config.r600.sx_max_export_pos_size = 16; 1588 rdev->config.r600.sx_max_export_smx_size = 128; 1589 rdev->config.r600.sq_num_cf_insts = 1; 1590 break; 1591 case CHIP_RV670: 1592 rdev->config.r600.max_pipes = 4; 1593 rdev->config.r600.max_tile_pipes = 4; 1594 rdev->config.r600.max_simds = 4; 1595 rdev->config.r600.max_backends = 4; 1596 rdev->config.r600.max_gprs = 192; 1597 rdev->config.r600.max_threads = 192; 1598 rdev->config.r600.max_stack_entries = 256; 1599 rdev->config.r600.max_hw_contexts = 8; 1600 rdev->config.r600.max_gs_threads = 16; 1601 rdev->config.r600.sx_max_export_size = 128; 1602 rdev->config.r600.sx_max_export_pos_size = 16; 1603 rdev->config.r600.sx_max_export_smx_size = 128; 1604 rdev->config.r600.sq_num_cf_insts = 2; 1605 break; 1606 default: 1607 break; 1608 } 1609 1610 /* Initialize HDP */ 1611 for (i = 0, j = 0; i < 32; i++, j += 0x18) { 1612 WREG32((0x2c14 + j), 0x00000000); 1613 WREG32((0x2c18 + j), 0x00000000); 1614 WREG32((0x2c1c + j), 0x00000000); 1615 WREG32((0x2c20 + j), 0x00000000); 1616 WREG32((0x2c24 + j), 0x00000000); 1617 } 1618 1619 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 1620 1621 /* Setup tiling */ 1622 tiling_config = 0; 1623 ramcfg = RREG32(RAMCFG); 1624 switch (rdev->config.r600.max_tile_pipes) { 1625 case 1: 1626 tiling_config |= PIPE_TILING(0); 1627 break; 1628 case 2: 1629 tiling_config |= PIPE_TILING(1); 1630 break; 1631 case 4: 1632 tiling_config |= PIPE_TILING(2); 1633 break; 1634 case 8: 1635 tiling_config |= PIPE_TILING(3); 1636 break; 1637 default: 1638 break; 1639 } 1640 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; 1641 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1642 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); 1643 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT); 1644 1645 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 1646 if (tmp > 3) { 1647 tiling_config |= ROW_TILING(3); 1648 tiling_config |= SAMPLE_SPLIT(3); 1649 } else { 1650 tiling_config |= ROW_TILING(tmp); 1651 tiling_config |= SAMPLE_SPLIT(tmp); 1652 } 1653 tiling_config |= BANK_SWAPS(1); 1654 1655 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1656 tmp = R6XX_MAX_BACKENDS - 1657 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK); 1658 if (tmp < rdev->config.r600.max_backends) { 1659 rdev->config.r600.max_backends = tmp; 1660 } 1661 1662 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00; 1663 tmp = R6XX_MAX_PIPES - 1664 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK); 1665 if (tmp < rdev->config.r600.max_pipes) { 1666 rdev->config.r600.max_pipes = tmp; 1667 } 1668 tmp = R6XX_MAX_SIMDS - 1669 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK); 1670 if (tmp < rdev->config.r600.max_simds) { 1671 rdev->config.r600.max_simds = tmp; 1672 } 1673 1674 disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK; 1675 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; 1676 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, 1677 R6XX_MAX_BACKENDS, disabled_rb_mask); 1678 tiling_config |= tmp << 16; 1679 rdev->config.r600.backend_map = tmp; 1680 1681 rdev->config.r600.tile_config = tiling_config; 1682 WREG32(GB_TILING_CONFIG, tiling_config); 1683 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); 1684 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); 1685 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); 1686 1687 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8); 1688 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); 1689 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); 1690 1691 /* Setup some CP states */ 1692 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); 1693 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); 1694 1695 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | 1696 SYNC_WALKER | SYNC_ALIGNER)); 1697 /* Setup various GPU states */ 1698 if (rdev->family == CHIP_RV670) 1699 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); 1700 1701 tmp = RREG32(SX_DEBUG_1); 1702 tmp |= SMX_EVENT_RELEASE; 1703 if ((rdev->family > CHIP_R600)) 1704 tmp |= ENABLE_NEW_SMX_ADDRESS; 1705 WREG32(SX_DEBUG_1, tmp); 1706 1707 if (((rdev->family) == CHIP_R600) || 1708 ((rdev->family) == CHIP_RV630) || 1709 ((rdev->family) == CHIP_RV610) || 1710 ((rdev->family) == CHIP_RV620) || 1711 ((rdev->family) == CHIP_RS780) || 1712 ((rdev->family) == CHIP_RS880)) { 1713 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 1714 } else { 1715 WREG32(DB_DEBUG, 0); 1716 } 1717 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | 1718 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4))); 1719 1720 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1721 WREG32(VGT_NUM_INSTANCES, 0); 1722 1723 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); 1724 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); 1725 1726 tmp = RREG32(SQ_MS_FIFO_SIZES); 1727 if (((rdev->family) == CHIP_RV610) || 1728 ((rdev->family) == CHIP_RV620) || 1729 ((rdev->family) == CHIP_RS780) || 1730 ((rdev->family) == CHIP_RS880)) { 1731 tmp = (CACHE_FIFO_SIZE(0xa) | 1732 FETCH_FIFO_HIWATER(0xa) | 1733 DONE_FIFO_HIWATER(0xe0) | 1734 ALU_UPDATE_FIFO_HIWATER(0x8)); 1735 } else if (((rdev->family) == CHIP_R600) || 1736 ((rdev->family) == CHIP_RV630)) { 1737 tmp &= ~DONE_FIFO_HIWATER(0xff); 1738 tmp |= DONE_FIFO_HIWATER(0x4); 1739 } 1740 WREG32(SQ_MS_FIFO_SIZES, tmp); 1741 1742 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1743 * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1744 */ 1745 sq_config = RREG32(SQ_CONFIG); 1746 sq_config &= ~(PS_PRIO(3) | 1747 VS_PRIO(3) | 1748 GS_PRIO(3) | 1749 ES_PRIO(3)); 1750 sq_config |= (DX9_CONSTS | 1751 VC_ENABLE | 1752 PS_PRIO(0) | 1753 VS_PRIO(1) | 1754 GS_PRIO(2) | 1755 ES_PRIO(3)); 1756 1757 if ((rdev->family) == CHIP_R600) { 1758 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) | 1759 NUM_VS_GPRS(124) | 1760 NUM_CLAUSE_TEMP_GPRS(4)); 1761 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) | 1762 NUM_ES_GPRS(0)); 1763 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) | 1764 NUM_VS_THREADS(48) | 1765 NUM_GS_THREADS(4) | 1766 NUM_ES_THREADS(4)); 1767 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) | 1768 NUM_VS_STACK_ENTRIES(128)); 1769 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) | 1770 NUM_ES_STACK_ENTRIES(0)); 1771 } else if (((rdev->family) == CHIP_RV610) || 1772 ((rdev->family) == CHIP_RV620) || 1773 ((rdev->family) == CHIP_RS780) || 1774 ((rdev->family) == CHIP_RS880)) { 1775 /* no vertex cache */ 1776 sq_config &= ~VC_ENABLE; 1777 1778 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1779 NUM_VS_GPRS(44) | 1780 NUM_CLAUSE_TEMP_GPRS(2)); 1781 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1782 NUM_ES_GPRS(17)); 1783 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1784 NUM_VS_THREADS(78) | 1785 NUM_GS_THREADS(4) | 1786 NUM_ES_THREADS(31)); 1787 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1788 NUM_VS_STACK_ENTRIES(40)); 1789 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1790 NUM_ES_STACK_ENTRIES(16)); 1791 } else if (((rdev->family) == CHIP_RV630) || 1792 ((rdev->family) == CHIP_RV635)) { 1793 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1794 NUM_VS_GPRS(44) | 1795 NUM_CLAUSE_TEMP_GPRS(2)); 1796 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) | 1797 NUM_ES_GPRS(18)); 1798 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1799 NUM_VS_THREADS(78) | 1800 NUM_GS_THREADS(4) | 1801 NUM_ES_THREADS(31)); 1802 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) | 1803 NUM_VS_STACK_ENTRIES(40)); 1804 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) | 1805 NUM_ES_STACK_ENTRIES(16)); 1806 } else if ((rdev->family) == CHIP_RV670) { 1807 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) | 1808 NUM_VS_GPRS(44) | 1809 NUM_CLAUSE_TEMP_GPRS(2)); 1810 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) | 1811 NUM_ES_GPRS(17)); 1812 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) | 1813 NUM_VS_THREADS(78) | 1814 NUM_GS_THREADS(4) | 1815 NUM_ES_THREADS(31)); 1816 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) | 1817 NUM_VS_STACK_ENTRIES(64)); 1818 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) | 1819 NUM_ES_STACK_ENTRIES(64)); 1820 } 1821 1822 WREG32(SQ_CONFIG, sq_config); 1823 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1824 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1825 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1826 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1827 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1828 1829 if (((rdev->family) == CHIP_RV610) || 1830 ((rdev->family) == CHIP_RV620) || 1831 ((rdev->family) == CHIP_RS780) || 1832 ((rdev->family) == CHIP_RS880)) { 1833 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 1834 } else { 1835 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 1836 } 1837 1838 /* More default values. 2D/3D driver should adjust as needed */ 1839 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | 1840 S1_X(0x4) | S1_Y(0xc))); 1841 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | 1842 S1_X(0x2) | S1_Y(0x2) | 1843 S2_X(0xa) | S2_Y(0x6) | 1844 S3_X(0x6) | S3_Y(0xa))); 1845 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | 1846 S1_X(0x4) | S1_Y(0xc) | 1847 S2_X(0x1) | S2_Y(0x6) | 1848 S3_X(0xa) | S3_Y(0xe))); 1849 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | 1850 S5_X(0x0) | S5_Y(0x0) | 1851 S6_X(0xb) | S6_Y(0x4) | 1852 S7_X(0x7) | S7_Y(0x8))); 1853 1854 WREG32(VGT_STRMOUT_EN, 0); 1855 tmp = rdev->config.r600.max_pipes * 16; 1856 switch (rdev->family) { 1857 case CHIP_RV610: 1858 case CHIP_RV620: 1859 case CHIP_RS780: 1860 case CHIP_RS880: 1861 tmp += 32; 1862 break; 1863 case CHIP_RV670: 1864 tmp += 128; 1865 break; 1866 default: 1867 break; 1868 } 1869 if (tmp > 256) { 1870 tmp = 256; 1871 } 1872 WREG32(VGT_ES_PER_GS, 128); 1873 WREG32(VGT_GS_PER_ES, tmp); 1874 WREG32(VGT_GS_PER_VS, 2); 1875 WREG32(VGT_GS_VERTEX_REUSE, 16); 1876 1877 /* more default values. 2D/3D driver should adjust as needed */ 1878 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1879 WREG32(VGT_STRMOUT_EN, 0); 1880 WREG32(SX_MISC, 0); 1881 WREG32(PA_SC_MODE_CNTL, 0); 1882 WREG32(PA_SC_AA_CONFIG, 0); 1883 WREG32(PA_SC_LINE_STIPPLE, 0); 1884 WREG32(SPI_INPUT_Z, 0); 1885 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); 1886 WREG32(CB_COLOR7_FRAG, 0); 1887 1888 /* Clear render buffer base addresses */ 1889 WREG32(CB_COLOR0_BASE, 0); 1890 WREG32(CB_COLOR1_BASE, 0); 1891 WREG32(CB_COLOR2_BASE, 0); 1892 WREG32(CB_COLOR3_BASE, 0); 1893 WREG32(CB_COLOR4_BASE, 0); 1894 WREG32(CB_COLOR5_BASE, 0); 1895 WREG32(CB_COLOR6_BASE, 0); 1896 WREG32(CB_COLOR7_BASE, 0); 1897 WREG32(CB_COLOR7_FRAG, 0); 1898 1899 switch (rdev->family) { 1900 case CHIP_RV610: 1901 case CHIP_RV620: 1902 case CHIP_RS780: 1903 case CHIP_RS880: 1904 tmp = TC_L2_SIZE(8); 1905 break; 1906 case CHIP_RV630: 1907 case CHIP_RV635: 1908 tmp = TC_L2_SIZE(4); 1909 break; 1910 case CHIP_R600: 1911 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; 1912 break; 1913 default: 1914 tmp = TC_L2_SIZE(0); 1915 break; 1916 } 1917 WREG32(TC_CNTL, tmp); 1918 1919 tmp = RREG32(HDP_HOST_PATH_CNTL); 1920 WREG32(HDP_HOST_PATH_CNTL, tmp); 1921 1922 tmp = RREG32(ARB_POP); 1923 tmp |= ENABLE_TC128; 1924 WREG32(ARB_POP, tmp); 1925 1926 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 1927 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1928 NUM_CLIP_SEQ(3))); 1929 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1930 WREG32(VC_ENHANCE, 0); 1931 } 1932 1933 1934 /* 1935 * Indirect registers accessor 1936 */ 1937 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg) 1938 { 1939 u32 r; 1940 1941 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1942 (void)RREG32(PCIE_PORT_INDEX); 1943 r = RREG32(PCIE_PORT_DATA); 1944 return r; 1945 } 1946 1947 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v) 1948 { 1949 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1950 (void)RREG32(PCIE_PORT_INDEX); 1951 WREG32(PCIE_PORT_DATA, (v)); 1952 (void)RREG32(PCIE_PORT_DATA); 1953 } 1954 1955 /* 1956 * CP & Ring 1957 */ 1958 void r600_cp_stop(struct radeon_device *rdev) 1959 { 1960 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1961 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1962 WREG32(SCRATCH_UMSK, 0); 1963 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1964 } 1965 1966 int r600_init_microcode(struct radeon_device *rdev) 1967 { 1968 const char *chip_name; 1969 const char *rlc_chip_name; 1970 size_t pfp_req_size, me_req_size, rlc_req_size; 1971 char fw_name[30]; 1972 int err; 1973 1974 DRM_DEBUG("\n"); 1975 1976 #if 0 1977 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0); 1978 err = IS_ERR(pdev); 1979 if (err) { 1980 DRM_ERROR( "radeon_cp: Failed to register firmware\n"); 1981 return -EINVAL; 1982 } 1983 #endif 1984 1985 switch (rdev->family) { 1986 case CHIP_R600: 1987 chip_name = "r600"; 1988 rlc_chip_name = "r600"; 1989 break; 1990 case CHIP_RV610: 1991 chip_name = "rv610"; 1992 rlc_chip_name = "r600"; 1993 break; 1994 case CHIP_RV630: 1995 chip_name = "rv630"; 1996 rlc_chip_name = "r600"; 1997 break; 1998 case CHIP_RV620: 1999 chip_name = "rv620"; 2000 rlc_chip_name = "r600"; 2001 break; 2002 case CHIP_RV635: 2003 chip_name = "rv635"; 2004 rlc_chip_name = "r600"; 2005 break; 2006 case CHIP_RV670: 2007 chip_name = "rv670"; 2008 rlc_chip_name = "r600"; 2009 break; 2010 case CHIP_RS780: 2011 case CHIP_RS880: 2012 chip_name = "rs780"; 2013 rlc_chip_name = "r600"; 2014 break; 2015 case CHIP_RV770: 2016 chip_name = "rv770"; 2017 rlc_chip_name = "r700"; 2018 break; 2019 case CHIP_RV730: 2020 case CHIP_RV740: 2021 chip_name = "rv730"; 2022 rlc_chip_name = "r700"; 2023 break; 2024 case CHIP_RV710: 2025 chip_name = "rv710"; 2026 rlc_chip_name = "r700"; 2027 break; 2028 case CHIP_CEDAR: 2029 chip_name = "cedar"; 2030 rlc_chip_name = "cedar"; 2031 break; 2032 case CHIP_REDWOOD: 2033 chip_name = "redwood"; 2034 rlc_chip_name = "redwood"; 2035 break; 2036 case CHIP_JUNIPER: 2037 chip_name = "juniper"; 2038 rlc_chip_name = "juniper"; 2039 break; 2040 case CHIP_CYPRESS: 2041 case CHIP_HEMLOCK: 2042 chip_name = "cypress"; 2043 rlc_chip_name = "cypress"; 2044 break; 2045 case CHIP_PALM: 2046 chip_name = "palm"; 2047 rlc_chip_name = "sumo"; 2048 break; 2049 case CHIP_SUMO: 2050 chip_name = "sumo"; 2051 rlc_chip_name = "sumo"; 2052 break; 2053 case CHIP_SUMO2: 2054 chip_name = "sumo2"; 2055 rlc_chip_name = "sumo"; 2056 break; 2057 default: BUG(); 2058 } 2059 2060 if (rdev->family >= CHIP_CEDAR) { 2061 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; 2062 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; 2063 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; 2064 } else if (rdev->family >= CHIP_RV770) { 2065 pfp_req_size = R700_PFP_UCODE_SIZE * 4; 2066 me_req_size = R700_PM4_UCODE_SIZE * 4; 2067 rlc_req_size = R700_RLC_UCODE_SIZE * 4; 2068 } else { 2069 pfp_req_size = PFP_UCODE_SIZE * 4; 2070 me_req_size = PM4_UCODE_SIZE * 12; 2071 rlc_req_size = RLC_UCODE_SIZE * 4; 2072 } 2073 2074 #ifdef DRMDEBUG 2075 DRM_INFO("Loading %s Microcode\n", chip_name); 2076 #endif 2077 2078 snprintf(fw_name, sizeof(fw_name), "radeon-%s_pfp", chip_name); 2079 err = loadfirmware(fw_name, &rdev->pfp_fw, &rdev->pfp_fw_size); 2080 if (err) 2081 goto out; 2082 if (rdev->pfp_fw_size != pfp_req_size) { 2083 DRM_ERROR( 2084 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2085 rdev->pfp_fw_size, fw_name); 2086 err = -EINVAL; 2087 goto out; 2088 } 2089 2090 snprintf(fw_name, sizeof(fw_name), "radeon-%s_me", chip_name); 2091 err = loadfirmware(fw_name, &rdev->me_fw, &rdev->me_fw_size); 2092 if (err) 2093 goto out; 2094 if (rdev->me_fw_size != me_req_size) { 2095 DRM_ERROR( 2096 "r600_cp: Bogus length %zu in firmware \"%s\"\n", 2097 rdev->me_fw_size, fw_name); 2098 err = -EINVAL; 2099 } 2100 2101 snprintf(fw_name, sizeof(fw_name), "radeon-%s_rlc", rlc_chip_name); 2102 err = loadfirmware(fw_name, &rdev->rlc_fw, &rdev->rlc_fw_size); 2103 if (err) 2104 goto out; 2105 if (rdev->rlc_fw_size != rlc_req_size) { 2106 DRM_ERROR( 2107 "r600_rlc: Bogus length %zu in firmware \"%s\"\n", 2108 rdev->rlc_fw_size, fw_name); 2109 err = -EINVAL; 2110 } 2111 2112 out: 2113 if (err) { 2114 if (err != -EINVAL) 2115 DRM_ERROR( 2116 "r600_cp: Failed to load firmware \"%s\"\n", 2117 fw_name); 2118 if (rdev->pfp_fw) { 2119 free(rdev->pfp_fw, M_DEVBUF, 0); 2120 rdev->pfp_fw = NULL; 2121 } 2122 if (rdev->me_fw) { 2123 free(rdev->me_fw, M_DEVBUF, 0); 2124 rdev->me_fw = NULL; 2125 } 2126 if (rdev->rlc_fw) { 2127 free(rdev->rlc_fw, M_DEVBUF, 0); 2128 rdev->rlc_fw = NULL; 2129 } 2130 } 2131 return err; 2132 } 2133 2134 static int r600_cp_load_microcode(struct radeon_device *rdev) 2135 { 2136 const __be32 *fw_data; 2137 int i; 2138 2139 if (!rdev->me_fw || !rdev->pfp_fw) 2140 return -EINVAL; 2141 2142 r600_cp_stop(rdev); 2143 2144 WREG32(CP_RB_CNTL, 2145 #ifdef __BIG_ENDIAN 2146 BUF_SWAP_32BIT | 2147 #endif 2148 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); 2149 2150 /* Reset cp */ 2151 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2152 RREG32(GRBM_SOFT_RESET); 2153 mdelay(15); 2154 WREG32(GRBM_SOFT_RESET, 0); 2155 2156 WREG32(CP_ME_RAM_WADDR, 0); 2157 2158 fw_data = (const __be32 *)rdev->me_fw; 2159 WREG32(CP_ME_RAM_WADDR, 0); 2160 for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 2161 WREG32(CP_ME_RAM_DATA, 2162 be32_to_cpup(fw_data++)); 2163 2164 fw_data = (const __be32 *)rdev->pfp_fw; 2165 WREG32(CP_PFP_UCODE_ADDR, 0); 2166 for (i = 0; i < PFP_UCODE_SIZE; i++) 2167 WREG32(CP_PFP_UCODE_DATA, 2168 be32_to_cpup(fw_data++)); 2169 2170 WREG32(CP_PFP_UCODE_ADDR, 0); 2171 WREG32(CP_ME_RAM_WADDR, 0); 2172 WREG32(CP_ME_RAM_RADDR, 0); 2173 return 0; 2174 } 2175 2176 int r600_cp_start(struct radeon_device *rdev) 2177 { 2178 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2179 int r; 2180 uint32_t cp_me; 2181 2182 r = radeon_ring_lock(rdev, ring, 7); 2183 if (r) { 2184 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2185 return r; 2186 } 2187 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2188 radeon_ring_write(ring, 0x1); 2189 if (rdev->family >= CHIP_RV770) { 2190 radeon_ring_write(ring, 0x0); 2191 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); 2192 } else { 2193 radeon_ring_write(ring, 0x3); 2194 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); 2195 } 2196 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2197 radeon_ring_write(ring, 0); 2198 radeon_ring_write(ring, 0); 2199 radeon_ring_unlock_commit(rdev, ring); 2200 2201 cp_me = 0xff; 2202 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2203 return 0; 2204 } 2205 2206 int r600_cp_resume(struct radeon_device *rdev) 2207 { 2208 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2209 u32 tmp; 2210 u32 rb_bufsz; 2211 int r; 2212 2213 /* Reset cp */ 2214 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); 2215 RREG32(GRBM_SOFT_RESET); 2216 mdelay(15); 2217 WREG32(GRBM_SOFT_RESET, 0); 2218 2219 /* Set ring buffer size */ 2220 rb_bufsz = drm_order(ring->ring_size / 8); 2221 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2222 #ifdef __BIG_ENDIAN 2223 tmp |= BUF_SWAP_32BIT; 2224 #endif 2225 WREG32(CP_RB_CNTL, tmp); 2226 WREG32(CP_SEM_WAIT_TIMER, 0x0); 2227 2228 /* Set the write pointer delay */ 2229 WREG32(CP_RB_WPTR_DELAY, 0); 2230 2231 /* Initialize the ring buffer's read and write pointers */ 2232 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2233 WREG32(CP_RB_RPTR_WR, 0); 2234 ring->wptr = 0; 2235 WREG32(CP_RB_WPTR, ring->wptr); 2236 2237 /* set the wb address whether it's enabled or not */ 2238 WREG32(CP_RB_RPTR_ADDR, 2239 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); 2240 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 2241 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 2242 2243 if (rdev->wb.enabled) 2244 WREG32(SCRATCH_UMSK, 0xff); 2245 else { 2246 tmp |= RB_NO_UPDATE; 2247 WREG32(SCRATCH_UMSK, 0); 2248 } 2249 2250 mdelay(1); 2251 WREG32(CP_RB_CNTL, tmp); 2252 2253 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); 2254 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2255 2256 ring->rptr = RREG32(CP_RB_RPTR); 2257 2258 r600_cp_start(rdev); 2259 ring->ready = true; 2260 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 2261 if (r) { 2262 ring->ready = false; 2263 return r; 2264 } 2265 return 0; 2266 } 2267 2268 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size) 2269 { 2270 u32 rb_bufsz; 2271 int r; 2272 2273 /* Align ring size */ 2274 rb_bufsz = drm_order(ring_size / 8); 2275 ring_size = (1 << (rb_bufsz + 1)) * 4; 2276 ring->ring_size = ring_size; 2277 ring->align_mask = 16 - 1; 2278 2279 if (radeon_ring_supports_scratch_reg(rdev, ring)) { 2280 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 2281 if (r) { 2282 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 2283 ring->rptr_save_reg = 0; 2284 } 2285 } 2286 } 2287 2288 void r600_cp_fini(struct radeon_device *rdev) 2289 { 2290 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2291 r600_cp_stop(rdev); 2292 radeon_ring_fini(rdev, ring); 2293 radeon_scratch_free(rdev, ring->rptr_save_reg); 2294 } 2295 2296 /* 2297 * DMA 2298 * Starting with R600, the GPU has an asynchronous 2299 * DMA engine. The programming model is very similar 2300 * to the 3D engine (ring buffer, IBs, etc.), but the 2301 * DMA controller has it's own packet format that is 2302 * different form the PM4 format used by the 3D engine. 2303 * It supports copying data, writing embedded data, 2304 * solid fills, and a number of other things. It also 2305 * has support for tiling/detiling of buffers. 2306 */ 2307 /** 2308 * r600_dma_stop - stop the async dma engine 2309 * 2310 * @rdev: radeon_device pointer 2311 * 2312 * Stop the async dma engine (r6xx-evergreen). 2313 */ 2314 void r600_dma_stop(struct radeon_device *rdev) 2315 { 2316 u32 rb_cntl = RREG32(DMA_RB_CNTL); 2317 2318 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 2319 2320 rb_cntl &= ~DMA_RB_ENABLE; 2321 WREG32(DMA_RB_CNTL, rb_cntl); 2322 2323 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; 2324 } 2325 2326 /** 2327 * r600_dma_resume - setup and start the async dma engine 2328 * 2329 * @rdev: radeon_device pointer 2330 * 2331 * Set up the DMA ring buffer and enable it. (r6xx-evergreen). 2332 * Returns 0 for success, error for failure. 2333 */ 2334 int r600_dma_resume(struct radeon_device *rdev) 2335 { 2336 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2337 u32 rb_cntl, dma_cntl, ib_cntl; 2338 u32 rb_bufsz; 2339 int r; 2340 2341 /* Reset dma */ 2342 if (rdev->family >= CHIP_RV770) 2343 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 2344 else 2345 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2346 RREG32(SRBM_SOFT_RESET); 2347 udelay(50); 2348 WREG32(SRBM_SOFT_RESET, 0); 2349 2350 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0); 2351 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0); 2352 2353 /* Set ring buffer size in dwords */ 2354 rb_bufsz = drm_order(ring->ring_size / 4); 2355 rb_cntl = rb_bufsz << 1; 2356 #ifdef __BIG_ENDIAN 2357 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 2358 #endif 2359 WREG32(DMA_RB_CNTL, rb_cntl); 2360 2361 /* Initialize the ring buffer's read and write pointers */ 2362 WREG32(DMA_RB_RPTR, 0); 2363 WREG32(DMA_RB_WPTR, 0); 2364 2365 /* set the wb address whether it's enabled or not */ 2366 WREG32(DMA_RB_RPTR_ADDR_HI, 2367 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 2368 WREG32(DMA_RB_RPTR_ADDR_LO, 2369 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 2370 2371 if (rdev->wb.enabled) 2372 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; 2373 2374 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2375 2376 /* enable DMA IBs */ 2377 ib_cntl = DMA_IB_ENABLE; 2378 #ifdef __BIG_ENDIAN 2379 ib_cntl |= DMA_IB_SWAP_ENABLE; 2380 #endif 2381 WREG32(DMA_IB_CNTL, ib_cntl); 2382 2383 dma_cntl = RREG32(DMA_CNTL); 2384 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2385 WREG32(DMA_CNTL, dma_cntl); 2386 2387 if (rdev->family >= CHIP_RV770) 2388 WREG32(DMA_MODE, 1); 2389 2390 ring->wptr = 0; 2391 WREG32(DMA_RB_WPTR, ring->wptr << 2); 2392 2393 ring->rptr = RREG32(DMA_RB_RPTR) >> 2; 2394 2395 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); 2396 2397 ring->ready = true; 2398 2399 r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring); 2400 if (r) { 2401 ring->ready = false; 2402 return r; 2403 } 2404 2405 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 2406 2407 return 0; 2408 } 2409 2410 /** 2411 * r600_dma_fini - tear down the async dma engine 2412 * 2413 * @rdev: radeon_device pointer 2414 * 2415 * Stop the async dma engine and free the ring (r6xx-evergreen). 2416 */ 2417 void r600_dma_fini(struct radeon_device *rdev) 2418 { 2419 r600_dma_stop(rdev); 2420 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); 2421 } 2422 2423 /* 2424 * GPU scratch registers helpers function. 2425 */ 2426 void r600_scratch_init(struct radeon_device *rdev) 2427 { 2428 int i; 2429 2430 rdev->scratch.num_reg = 7; 2431 rdev->scratch.reg_base = SCRATCH_REG0; 2432 for (i = 0; i < rdev->scratch.num_reg; i++) { 2433 rdev->scratch.free[i] = true; 2434 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 2435 } 2436 } 2437 2438 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 2439 { 2440 uint32_t scratch; 2441 uint32_t tmp = 0; 2442 unsigned i; 2443 int r; 2444 2445 r = radeon_scratch_get(rdev, &scratch); 2446 if (r) { 2447 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 2448 return r; 2449 } 2450 WREG32(scratch, 0xCAFEDEAD); 2451 r = radeon_ring_lock(rdev, ring, 3); 2452 if (r) { 2453 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); 2454 radeon_scratch_free(rdev, scratch); 2455 return r; 2456 } 2457 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2458 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2459 radeon_ring_write(ring, 0xDEADBEEF); 2460 radeon_ring_unlock_commit(rdev, ring); 2461 for (i = 0; i < rdev->usec_timeout; i++) { 2462 tmp = RREG32(scratch); 2463 if (tmp == 0xDEADBEEF) 2464 break; 2465 udelay(1); 2466 } 2467 if (i < rdev->usec_timeout) { 2468 #ifdef DRMDEBUG 2469 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2470 #endif 2471 } else { 2472 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 2473 ring->idx, scratch, tmp); 2474 r = -EINVAL; 2475 } 2476 radeon_scratch_free(rdev, scratch); 2477 return r; 2478 } 2479 2480 /** 2481 * r600_dma_ring_test - simple async dma engine test 2482 * 2483 * @rdev: radeon_device pointer 2484 * @ring: radeon_ring structure holding ring information 2485 * 2486 * Test the DMA engine by writing using it to write an 2487 * value to memory. (r6xx-SI). 2488 * Returns 0 for success, error for failure. 2489 */ 2490 int r600_dma_ring_test(struct radeon_device *rdev, 2491 struct radeon_ring *ring) 2492 { 2493 unsigned i; 2494 int r; 2495 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 2496 u32 tmp; 2497 2498 if (!ptr) { 2499 DRM_ERROR("invalid vram scratch pointer\n"); 2500 return -EINVAL; 2501 } 2502 2503 tmp = 0xCAFEDEAD; 2504 *ptr = tmp; 2505 2506 r = radeon_ring_lock(rdev, ring, 4); 2507 if (r) { 2508 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r); 2509 return r; 2510 } 2511 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 2512 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 2513 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff); 2514 radeon_ring_write(ring, 0xDEADBEEF); 2515 radeon_ring_unlock_commit(rdev, ring); 2516 2517 for (i = 0; i < rdev->usec_timeout; i++) { 2518 tmp = *ptr; 2519 if (tmp == 0xDEADBEEF) 2520 break; 2521 udelay(1); 2522 } 2523 2524 if (i < rdev->usec_timeout) { 2525 #ifdef DRMDEBUG 2526 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 2527 #endif 2528 } else { 2529 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n", 2530 ring->idx, tmp); 2531 r = -EINVAL; 2532 } 2533 return r; 2534 } 2535 2536 /* 2537 * CP fences/semaphores 2538 */ 2539 2540 void r600_fence_ring_emit(struct radeon_device *rdev, 2541 struct radeon_fence *fence) 2542 { 2543 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2544 u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA | 2545 PACKET3_SH_ACTION_ENA; 2546 2547 if (rdev->family >= CHIP_RV770) 2548 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA; 2549 2550 if (rdev->wb.use_event) { 2551 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2552 /* flush read cache over gart */ 2553 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2554 radeon_ring_write(ring, cp_coher_cntl); 2555 radeon_ring_write(ring, 0xFFFFFFFF); 2556 radeon_ring_write(ring, 0); 2557 radeon_ring_write(ring, 10); /* poll interval */ 2558 /* EVENT_WRITE_EOP - flush caches, send int */ 2559 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2560 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2561 radeon_ring_write(ring, addr & 0xffffffff); 2562 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2563 radeon_ring_write(ring, fence->seq); 2564 radeon_ring_write(ring, 0); 2565 } else { 2566 /* flush read cache over gart */ 2567 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2568 radeon_ring_write(ring, cp_coher_cntl); 2569 radeon_ring_write(ring, 0xFFFFFFFF); 2570 radeon_ring_write(ring, 0); 2571 radeon_ring_write(ring, 10); /* poll interval */ 2572 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); 2573 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2574 /* wait for 3D idle clean */ 2575 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2576 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2577 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2578 /* Emit fence sequence & fire IRQ */ 2579 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2580 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2581 radeon_ring_write(ring, fence->seq); 2582 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2583 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0)); 2584 radeon_ring_write(ring, RB_INT_STAT); 2585 } 2586 } 2587 2588 void r600_semaphore_ring_emit(struct radeon_device *rdev, 2589 struct radeon_ring *ring, 2590 struct radeon_semaphore *semaphore, 2591 bool emit_wait) 2592 { 2593 uint64_t addr = semaphore->gpu_addr; 2594 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2595 2596 if (rdev->family < CHIP_CAYMAN) 2597 sel |= PACKET3_SEM_WAIT_ON_SIGNAL; 2598 2599 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2600 radeon_ring_write(ring, addr & 0xffffffff); 2601 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel); 2602 } 2603 2604 /* 2605 * DMA fences/semaphores 2606 */ 2607 2608 /** 2609 * r600_dma_fence_ring_emit - emit a fence on the DMA ring 2610 * 2611 * @rdev: radeon_device pointer 2612 * @fence: radeon fence object 2613 * 2614 * Add a DMA fence packet to the ring to write 2615 * the fence seq number and DMA trap packet to generate 2616 * an interrupt if needed (r6xx-r7xx). 2617 */ 2618 void r600_dma_fence_ring_emit(struct radeon_device *rdev, 2619 struct radeon_fence *fence) 2620 { 2621 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2622 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 2623 2624 /* write the fence */ 2625 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 2626 radeon_ring_write(ring, addr & 0xfffffffc); 2627 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 2628 radeon_ring_write(ring, lower_32_bits(fence->seq)); 2629 /* generate an interrupt */ 2630 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 2631 } 2632 2633 /** 2634 * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring 2635 * 2636 * @rdev: radeon_device pointer 2637 * @ring: radeon_ring structure holding ring information 2638 * @semaphore: radeon semaphore object 2639 * @emit_wait: wait or signal semaphore 2640 * 2641 * Add a DMA semaphore packet to the ring wait on or signal 2642 * other rings (r6xx-SI). 2643 */ 2644 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev, 2645 struct radeon_ring *ring, 2646 struct radeon_semaphore *semaphore, 2647 bool emit_wait) 2648 { 2649 u64 addr = semaphore->gpu_addr; 2650 u32 s = emit_wait ? 0 : 1; 2651 2652 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0)); 2653 radeon_ring_write(ring, addr & 0xfffffffc); 2654 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); 2655 } 2656 2657 int r600_copy_blit(struct radeon_device *rdev, 2658 uint64_t src_offset, 2659 uint64_t dst_offset, 2660 unsigned num_gpu_pages, 2661 struct radeon_fence **fence) 2662 { 2663 struct radeon_semaphore *sem = NULL; 2664 struct radeon_sa_bo *vb = NULL; 2665 int r; 2666 2667 r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem); 2668 if (r) { 2669 return r; 2670 } 2671 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb); 2672 r600_blit_done_copy(rdev, fence, vb, sem); 2673 return 0; 2674 } 2675 2676 /** 2677 * r600_copy_dma - copy pages using the DMA engine 2678 * 2679 * @rdev: radeon_device pointer 2680 * @src_offset: src GPU address 2681 * @dst_offset: dst GPU address 2682 * @num_gpu_pages: number of GPU pages to xfer 2683 * @fence: radeon fence object 2684 * 2685 * Copy GPU paging using the DMA engine (r6xx). 2686 * Used by the radeon ttm implementation to move pages if 2687 * registered as the asic copy callback. 2688 */ 2689 int r600_copy_dma(struct radeon_device *rdev, 2690 uint64_t src_offset, uint64_t dst_offset, 2691 unsigned num_gpu_pages, 2692 struct radeon_fence **fence) 2693 { 2694 struct radeon_semaphore *sem = NULL; 2695 int ring_index = rdev->asic->copy.dma_ring_index; 2696 struct radeon_ring *ring = &rdev->ring[ring_index]; 2697 u32 size_in_dw, cur_size_in_dw; 2698 int i, num_loops; 2699 int r = 0; 2700 2701 r = radeon_semaphore_create(rdev, &sem); 2702 if (r) { 2703 DRM_ERROR("radeon: moving bo (%d).\n", r); 2704 return r; 2705 } 2706 2707 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; 2708 num_loops = howmany(size_in_dw, 0xFFFE); 2709 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8); 2710 if (r) { 2711 DRM_ERROR("radeon: moving bo (%d).\n", r); 2712 radeon_semaphore_free(rdev, &sem, NULL); 2713 return r; 2714 } 2715 2716 if (radeon_fence_need_sync(*fence, ring->idx)) { 2717 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, 2718 ring->idx); 2719 radeon_fence_note_sync(*fence, ring->idx); 2720 } else { 2721 radeon_semaphore_free(rdev, &sem, NULL); 2722 } 2723 2724 for (i = 0; i < num_loops; i++) { 2725 cur_size_in_dw = size_in_dw; 2726 if (cur_size_in_dw > 0xFFFE) 2727 cur_size_in_dw = 0xFFFE; 2728 size_in_dw -= cur_size_in_dw; 2729 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 2730 radeon_ring_write(ring, dst_offset & 0xfffffffc); 2731 radeon_ring_write(ring, src_offset & 0xfffffffc); 2732 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | 2733 (upper_32_bits(src_offset) & 0xff))); 2734 src_offset += cur_size_in_dw * 4; 2735 dst_offset += cur_size_in_dw * 4; 2736 } 2737 2738 r = radeon_fence_emit(rdev, fence, ring->idx); 2739 if (r) { 2740 radeon_ring_unlock_undo(rdev, ring); 2741 return r; 2742 } 2743 2744 radeon_ring_unlock_commit(rdev, ring); 2745 radeon_semaphore_free(rdev, &sem, *fence); 2746 2747 return r; 2748 } 2749 2750 int r600_set_surface_reg(struct radeon_device *rdev, int reg, 2751 uint32_t tiling_flags, uint32_t pitch, 2752 uint32_t offset, uint32_t obj_size) 2753 { 2754 /* FIXME: implement */ 2755 return 0; 2756 } 2757 2758 void r600_clear_surface_reg(struct radeon_device *rdev, int reg) 2759 { 2760 /* FIXME: implement */ 2761 } 2762 2763 static int r600_startup(struct radeon_device *rdev) 2764 { 2765 struct radeon_ring *ring; 2766 int r; 2767 2768 /* enable pcie gen2 link */ 2769 r600_pcie_gen2_enable(rdev); 2770 2771 r600_mc_program(rdev); 2772 2773 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2774 r = r600_init_microcode(rdev); 2775 if (r) { 2776 DRM_ERROR("Failed to load firmware!\n"); 2777 return r; 2778 } 2779 } 2780 2781 r = r600_vram_scratch_init(rdev); 2782 if (r) 2783 return r; 2784 2785 if (rdev->flags & RADEON_IS_AGP) { 2786 r600_agp_enable(rdev); 2787 } else { 2788 r = r600_pcie_gart_enable(rdev); 2789 if (r) 2790 return r; 2791 } 2792 r600_gpu_init(rdev); 2793 r = r600_blit_init(rdev); 2794 if (r) { 2795 r600_blit_fini(rdev); 2796 rdev->asic->copy.copy = NULL; 2797 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2798 } 2799 2800 /* allocate wb buffer */ 2801 r = radeon_wb_init(rdev); 2802 if (r) 2803 return r; 2804 2805 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 2806 if (r) { 2807 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 2808 return r; 2809 } 2810 2811 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); 2812 if (r) { 2813 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); 2814 return r; 2815 } 2816 2817 /* Enable IRQ */ 2818 if (!rdev->irq.installed) { 2819 r = radeon_irq_kms_init(rdev); 2820 if (r) 2821 return r; 2822 } 2823 2824 r = r600_irq_init(rdev); 2825 if (r) { 2826 DRM_ERROR("radeon: IH init failed (%d).\n", r); 2827 radeon_irq_kms_fini(rdev); 2828 return r; 2829 } 2830 r600_irq_set(rdev); 2831 2832 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 2833 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 2834 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 2835 0, 0xfffff, RADEON_CP_PACKET2); 2836 if (r) 2837 return r; 2838 2839 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2840 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 2841 DMA_RB_RPTR, DMA_RB_WPTR, 2842 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 2843 if (r) 2844 return r; 2845 2846 r = r600_cp_load_microcode(rdev); 2847 if (r) 2848 return r; 2849 r = r600_cp_resume(rdev); 2850 if (r) 2851 return r; 2852 2853 r = r600_dma_resume(rdev); 2854 if (r) 2855 return r; 2856 2857 r = radeon_ib_pool_init(rdev); 2858 if (r) { 2859 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2860 return r; 2861 } 2862 2863 r = r600_audio_init(rdev); 2864 if (r) { 2865 DRM_ERROR("radeon: audio init failed\n"); 2866 return r; 2867 } 2868 2869 return 0; 2870 } 2871 2872 void r600_vga_set_state(struct radeon_device *rdev, bool state) 2873 { 2874 uint32_t temp; 2875 2876 temp = RREG32(CONFIG_CNTL); 2877 if (state == false) { 2878 temp &= ~(1<<0); 2879 temp |= (1<<1); 2880 } else { 2881 temp &= ~(1<<1); 2882 } 2883 WREG32(CONFIG_CNTL, temp); 2884 } 2885 2886 int r600_resume(struct radeon_device *rdev) 2887 { 2888 int r; 2889 2890 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw, 2891 * posting will perform necessary task to bring back GPU into good 2892 * shape. 2893 */ 2894 /* post card */ 2895 atom_asic_init(rdev->mode_info.atom_context); 2896 2897 rdev->accel_working = true; 2898 r = r600_startup(rdev); 2899 if (r) { 2900 DRM_ERROR("r600 startup failed on resume\n"); 2901 rdev->accel_working = false; 2902 return r; 2903 } 2904 2905 return r; 2906 } 2907 2908 int r600_suspend(struct radeon_device *rdev) 2909 { 2910 r600_audio_fini(rdev); 2911 r600_cp_stop(rdev); 2912 r600_dma_stop(rdev); 2913 r600_irq_suspend(rdev); 2914 radeon_wb_disable(rdev); 2915 r600_pcie_gart_disable(rdev); 2916 2917 return 0; 2918 } 2919 2920 /* Plan is to move initialization in that function and use 2921 * helper function so that radeon_device_init pretty much 2922 * do nothing more than calling asic specific function. This 2923 * should also allow to remove a bunch of callback function 2924 * like vram_info. 2925 */ 2926 int r600_init(struct radeon_device *rdev) 2927 { 2928 int r; 2929 2930 if (r600_debugfs_mc_info_init(rdev)) { 2931 DRM_ERROR("Failed to register debugfs file for mc !\n"); 2932 } 2933 /* Read BIOS */ 2934 if (!radeon_get_bios(rdev)) { 2935 if (ASIC_IS_AVIVO(rdev)) 2936 return -EINVAL; 2937 } 2938 /* Must be an ATOMBIOS */ 2939 if (!rdev->is_atom_bios) { 2940 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); 2941 return -EINVAL; 2942 } 2943 r = radeon_atombios_init(rdev); 2944 if (r) 2945 return r; 2946 /* Post card if necessary */ 2947 if (!radeon_card_posted(rdev)) { 2948 if (!rdev->bios) { 2949 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 2950 return -EINVAL; 2951 } 2952 DRM_INFO("GPU not posted. posting now...\n"); 2953 atom_asic_init(rdev->mode_info.atom_context); 2954 } 2955 /* Initialize scratch registers */ 2956 r600_scratch_init(rdev); 2957 /* Initialize surface registers */ 2958 radeon_surface_init(rdev); 2959 /* Initialize clocks */ 2960 radeon_get_clock_info(rdev->ddev); 2961 /* Fence driver */ 2962 r = radeon_fence_driver_init(rdev); 2963 if (r) 2964 return r; 2965 if (rdev->flags & RADEON_IS_AGP) { 2966 r = radeon_agp_init(rdev); 2967 if (r) 2968 radeon_agp_disable(rdev); 2969 } 2970 r = r600_mc_init(rdev); 2971 if (r) 2972 return r; 2973 /* Memory manager */ 2974 r = radeon_bo_init(rdev); 2975 if (r) 2976 return r; 2977 2978 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; 2979 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); 2980 2981 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; 2982 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); 2983 2984 rdev->ih.ring_obj = NULL; 2985 r600_ih_ring_init(rdev, 64 * 1024); 2986 2987 r = r600_pcie_gart_init(rdev); 2988 if (r) 2989 return r; 2990 2991 rdev->accel_working = true; 2992 r = r600_startup(rdev); 2993 if (r) { 2994 dev_err(rdev->dev, "disabling GPU acceleration\n"); 2995 r600_cp_fini(rdev); 2996 r600_dma_fini(rdev); 2997 r600_irq_fini(rdev); 2998 radeon_wb_fini(rdev); 2999 radeon_ib_pool_fini(rdev); 3000 radeon_irq_kms_fini(rdev); 3001 r600_pcie_gart_fini(rdev); 3002 rdev->accel_working = false; 3003 } 3004 3005 return 0; 3006 } 3007 3008 void r600_fini(struct radeon_device *rdev) 3009 { 3010 r600_audio_fini(rdev); 3011 r600_blit_fini(rdev); 3012 r600_cp_fini(rdev); 3013 r600_dma_fini(rdev); 3014 r600_irq_fini(rdev); 3015 radeon_wb_fini(rdev); 3016 radeon_ib_pool_fini(rdev); 3017 radeon_irq_kms_fini(rdev); 3018 r600_pcie_gart_fini(rdev); 3019 r600_vram_scratch_fini(rdev); 3020 radeon_agp_fini(rdev); 3021 radeon_gem_fini(rdev); 3022 radeon_fence_driver_fini(rdev); 3023 radeon_bo_fini(rdev); 3024 radeon_atombios_fini(rdev); 3025 kfree(rdev->bios); 3026 rdev->bios = NULL; 3027 } 3028 3029 3030 /* 3031 * CS stuff 3032 */ 3033 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3034 { 3035 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3036 u32 next_rptr; 3037 3038 if (ring->rptr_save_reg) { 3039 next_rptr = ring->wptr + 3 + 4; 3040 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3041 radeon_ring_write(ring, ((ring->rptr_save_reg - 3042 PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 3043 radeon_ring_write(ring, next_rptr); 3044 } else if (rdev->wb.enabled) { 3045 next_rptr = ring->wptr + 5 + 4; 3046 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); 3047 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3048 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); 3049 radeon_ring_write(ring, next_rptr); 3050 radeon_ring_write(ring, 0); 3051 } 3052 3053 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3054 radeon_ring_write(ring, 3055 #ifdef __BIG_ENDIAN 3056 (2 << 0) | 3057 #endif 3058 (ib->gpu_addr & 0xFFFFFFFC)); 3059 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); 3060 radeon_ring_write(ring, ib->length_dw); 3061 } 3062 3063 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3064 { 3065 struct radeon_ib ib; 3066 uint32_t scratch; 3067 uint32_t tmp = 0; 3068 unsigned i; 3069 int r; 3070 3071 r = radeon_scratch_get(rdev, &scratch); 3072 if (r) { 3073 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3074 return r; 3075 } 3076 WREG32(scratch, 0xCAFEDEAD); 3077 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3078 if (r) { 3079 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3080 goto free_scratch; 3081 } 3082 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); 3083 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 3084 ib.ptr[2] = 0xDEADBEEF; 3085 ib.length_dw = 3; 3086 r = radeon_ib_schedule(rdev, &ib, NULL); 3087 if (r) { 3088 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3089 goto free_ib; 3090 } 3091 r = radeon_fence_wait(ib.fence, false); 3092 if (r) { 3093 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3094 goto free_ib; 3095 } 3096 for (i = 0; i < rdev->usec_timeout; i++) { 3097 tmp = RREG32(scratch); 3098 if (tmp == 0xDEADBEEF) 3099 break; 3100 udelay(1); 3101 } 3102 if (i < rdev->usec_timeout) { 3103 #ifdef DRMDEBUG 3104 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3105 #endif 3106 } else { 3107 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3108 scratch, tmp); 3109 r = -EINVAL; 3110 } 3111 free_ib: 3112 radeon_ib_free(rdev, &ib); 3113 free_scratch: 3114 radeon_scratch_free(rdev, scratch); 3115 return r; 3116 } 3117 3118 /** 3119 * r600_dma_ib_test - test an IB on the DMA engine 3120 * 3121 * @rdev: radeon_device pointer 3122 * @ring: radeon_ring structure holding ring information 3123 * 3124 * Test a simple IB in the DMA ring (r6xx-SI). 3125 * Returns 0 on success, error on failure. 3126 */ 3127 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3128 { 3129 struct radeon_ib ib; 3130 unsigned i; 3131 int r; 3132 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 3133 u32 tmp = 0; 3134 3135 if (!ptr) { 3136 DRM_ERROR("invalid vram scratch pointer\n"); 3137 return -EINVAL; 3138 } 3139 3140 tmp = 0xCAFEDEAD; 3141 *ptr = tmp; 3142 3143 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); 3144 if (r) { 3145 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3146 return r; 3147 } 3148 3149 ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1); 3150 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 3151 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff; 3152 ib.ptr[3] = 0xDEADBEEF; 3153 ib.length_dw = 4; 3154 3155 r = radeon_ib_schedule(rdev, &ib, NULL); 3156 if (r) { 3157 radeon_ib_free(rdev, &ib); 3158 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3159 return r; 3160 } 3161 r = radeon_fence_wait(ib.fence, false); 3162 if (r) { 3163 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3164 return r; 3165 } 3166 for (i = 0; i < rdev->usec_timeout; i++) { 3167 tmp = *ptr; 3168 if (tmp == 0xDEADBEEF) 3169 break; 3170 udelay(1); 3171 } 3172 if (i < rdev->usec_timeout) { 3173 #ifdef DRMDEBUG 3174 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); 3175 #endif 3176 } else { 3177 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp); 3178 r = -EINVAL; 3179 } 3180 radeon_ib_free(rdev, &ib); 3181 return r; 3182 } 3183 3184 /** 3185 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine 3186 * 3187 * @rdev: radeon_device pointer 3188 * @ib: IB object to schedule 3189 * 3190 * Schedule an IB in the DMA ring (r6xx-r7xx). 3191 */ 3192 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3193 { 3194 struct radeon_ring *ring = &rdev->ring[ib->ring]; 3195 3196 if (rdev->wb.enabled) { 3197 u32 next_rptr = ring->wptr + 4; 3198 while ((next_rptr & 7) != 5) 3199 next_rptr++; 3200 next_rptr += 3; 3201 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3202 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3203 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3204 radeon_ring_write(ring, next_rptr); 3205 } 3206 3207 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. 3208 * Pad as necessary with NOPs. 3209 */ 3210 while ((ring->wptr & 7) != 5) 3211 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3212 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3213 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3214 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3215 3216 } 3217 3218 /* 3219 * Interrupts 3220 * 3221 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty 3222 * the same as the CP ring buffer, but in reverse. Rather than the CPU 3223 * writing to the ring and the GPU consuming, the GPU writes to the ring 3224 * and host consumes. As the host irq handler processes interrupts, it 3225 * increments the rptr. When the rptr catches up with the wptr, all the 3226 * current interrupts have been processed. 3227 */ 3228 3229 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) 3230 { 3231 u32 rb_bufsz; 3232 3233 /* Align ring size */ 3234 rb_bufsz = drm_order(ring_size / 4); 3235 ring_size = (1 << rb_bufsz) * 4; 3236 rdev->ih.ring_size = ring_size; 3237 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; 3238 rdev->ih.rptr = 0; 3239 } 3240 3241 int r600_ih_ring_alloc(struct radeon_device *rdev) 3242 { 3243 int r; 3244 3245 /* Allocate ring buffer */ 3246 if (rdev->ih.ring_obj == NULL) { 3247 r = radeon_bo_create(rdev, rdev->ih.ring_size, 3248 PAGE_SIZE, true, 3249 RADEON_GEM_DOMAIN_GTT, 3250 NULL, &rdev->ih.ring_obj); 3251 if (r) { 3252 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r); 3253 return r; 3254 } 3255 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3256 if (unlikely(r != 0)) 3257 return r; 3258 r = radeon_bo_pin(rdev->ih.ring_obj, 3259 RADEON_GEM_DOMAIN_GTT, 3260 &rdev->ih.gpu_addr); 3261 if (r) { 3262 radeon_bo_unreserve(rdev->ih.ring_obj); 3263 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r); 3264 return r; 3265 } 3266 r = radeon_bo_kmap(rdev->ih.ring_obj, 3267 (void **)&rdev->ih.ring); 3268 radeon_bo_unreserve(rdev->ih.ring_obj); 3269 if (r) { 3270 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r); 3271 return r; 3272 } 3273 } 3274 return 0; 3275 } 3276 3277 void r600_ih_ring_fini(struct radeon_device *rdev) 3278 { 3279 int r; 3280 if (rdev->ih.ring_obj) { 3281 r = radeon_bo_reserve(rdev->ih.ring_obj, false); 3282 if (likely(r == 0)) { 3283 radeon_bo_kunmap(rdev->ih.ring_obj); 3284 radeon_bo_unpin(rdev->ih.ring_obj); 3285 radeon_bo_unreserve(rdev->ih.ring_obj); 3286 } 3287 radeon_bo_unref(&rdev->ih.ring_obj); 3288 rdev->ih.ring = NULL; 3289 rdev->ih.ring_obj = NULL; 3290 } 3291 } 3292 3293 void r600_rlc_stop(struct radeon_device *rdev) 3294 { 3295 3296 if ((rdev->family >= CHIP_RV770) && 3297 (rdev->family <= CHIP_RV740)) { 3298 /* r7xx asics need to soft reset RLC before halting */ 3299 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); 3300 RREG32(SRBM_SOFT_RESET); 3301 mdelay(15); 3302 WREG32(SRBM_SOFT_RESET, 0); 3303 RREG32(SRBM_SOFT_RESET); 3304 } 3305 3306 WREG32(RLC_CNTL, 0); 3307 } 3308 3309 void 3310 r600_rlc_start(struct radeon_device *rdev) 3311 { 3312 WREG32(RLC_CNTL, RLC_ENABLE); 3313 } 3314 3315 static int r600_rlc_init(struct radeon_device *rdev) 3316 { 3317 u32 i; 3318 const __be32 *fw_data; 3319 3320 if (!rdev->rlc_fw) 3321 return -EINVAL; 3322 3323 r600_rlc_stop(rdev); 3324 3325 WREG32(RLC_HB_CNTL, 0); 3326 3327 if (rdev->family == CHIP_ARUBA) { 3328 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); 3329 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); 3330 } 3331 if (rdev->family <= CHIP_CAYMAN) { 3332 WREG32(RLC_HB_BASE, 0); 3333 WREG32(RLC_HB_RPTR, 0); 3334 WREG32(RLC_HB_WPTR, 0); 3335 } 3336 if (rdev->family <= CHIP_CAICOS) { 3337 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); 3338 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); 3339 } 3340 WREG32(RLC_MC_CNTL, 0); 3341 WREG32(RLC_UCODE_CNTL, 0); 3342 3343 fw_data = (const __be32 *)rdev->rlc_fw; 3344 if (rdev->family >= CHIP_ARUBA) { 3345 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) { 3346 WREG32(RLC_UCODE_ADDR, i); 3347 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3348 } 3349 } else if (rdev->family >= CHIP_CAYMAN) { 3350 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { 3351 WREG32(RLC_UCODE_ADDR, i); 3352 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3353 } 3354 } else if (rdev->family >= CHIP_CEDAR) { 3355 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) { 3356 WREG32(RLC_UCODE_ADDR, i); 3357 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3358 } 3359 } else if (rdev->family >= CHIP_RV770) { 3360 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) { 3361 WREG32(RLC_UCODE_ADDR, i); 3362 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3363 } 3364 } else { 3365 for (i = 0; i < RLC_UCODE_SIZE; i++) { 3366 WREG32(RLC_UCODE_ADDR, i); 3367 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); 3368 } 3369 } 3370 WREG32(RLC_UCODE_ADDR, 0); 3371 3372 r600_rlc_start(rdev); 3373 3374 return 0; 3375 } 3376 3377 static void r600_enable_interrupts(struct radeon_device *rdev) 3378 { 3379 u32 ih_cntl = RREG32(IH_CNTL); 3380 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3381 3382 ih_cntl |= ENABLE_INTR; 3383 ih_rb_cntl |= IH_RB_ENABLE; 3384 WREG32(IH_CNTL, ih_cntl); 3385 WREG32(IH_RB_CNTL, ih_rb_cntl); 3386 rdev->ih.enabled = true; 3387 } 3388 3389 void r600_disable_interrupts(struct radeon_device *rdev) 3390 { 3391 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); 3392 u32 ih_cntl = RREG32(IH_CNTL); 3393 3394 ih_rb_cntl &= ~IH_RB_ENABLE; 3395 ih_cntl &= ~ENABLE_INTR; 3396 WREG32(IH_RB_CNTL, ih_rb_cntl); 3397 WREG32(IH_CNTL, ih_cntl); 3398 /* set rptr, wptr to 0 */ 3399 WREG32(IH_RB_RPTR, 0); 3400 WREG32(IH_RB_WPTR, 0); 3401 rdev->ih.enabled = false; 3402 rdev->ih.rptr = 0; 3403 } 3404 3405 static void r600_disable_interrupt_state(struct radeon_device *rdev) 3406 { 3407 u32 tmp; 3408 3409 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); 3410 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3411 WREG32(DMA_CNTL, tmp); 3412 WREG32(GRBM_INT_CNTL, 0); 3413 WREG32(DxMODE_INT_MASK, 0); 3414 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); 3415 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); 3416 if (ASIC_IS_DCE3(rdev)) { 3417 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); 3418 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); 3419 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3420 WREG32(DC_HPD1_INT_CONTROL, tmp); 3421 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3422 WREG32(DC_HPD2_INT_CONTROL, tmp); 3423 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3424 WREG32(DC_HPD3_INT_CONTROL, tmp); 3425 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3426 WREG32(DC_HPD4_INT_CONTROL, tmp); 3427 if (ASIC_IS_DCE32(rdev)) { 3428 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3429 WREG32(DC_HPD5_INT_CONTROL, tmp); 3430 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; 3431 WREG32(DC_HPD6_INT_CONTROL, tmp); 3432 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3433 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3434 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3435 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3436 } else { 3437 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3438 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3439 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3440 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3441 } 3442 } else { 3443 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 3444 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 3445 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3446 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3447 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3448 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3449 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; 3450 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3451 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3452 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3453 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3454 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3455 } 3456 } 3457 3458 int r600_irq_init(struct radeon_device *rdev) 3459 { 3460 int ret = 0; 3461 int rb_bufsz; 3462 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 3463 3464 /* allocate ring */ 3465 ret = r600_ih_ring_alloc(rdev); 3466 if (ret) 3467 return ret; 3468 3469 /* disable irqs */ 3470 r600_disable_interrupts(rdev); 3471 3472 /* init rlc */ 3473 ret = r600_rlc_init(rdev); 3474 if (ret) { 3475 r600_ih_ring_fini(rdev); 3476 return ret; 3477 } 3478 3479 /* setup interrupt control */ 3480 /* set dummy read address to ring address */ 3481 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); 3482 interrupt_cntl = RREG32(INTERRUPT_CNTL); 3483 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi 3484 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN 3485 */ 3486 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE; 3487 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ 3488 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN; 3489 WREG32(INTERRUPT_CNTL, interrupt_cntl); 3490 3491 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); 3492 rb_bufsz = drm_order(rdev->ih.ring_size / 4); 3493 3494 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE | 3495 IH_WPTR_OVERFLOW_CLEAR | 3496 (rb_bufsz << 1)); 3497 3498 if (rdev->wb.enabled) 3499 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE; 3500 3501 /* set the writeback address whether it's enabled or not */ 3502 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); 3503 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); 3504 3505 WREG32(IH_RB_CNTL, ih_rb_cntl); 3506 3507 /* set rptr, wptr to 0 */ 3508 WREG32(IH_RB_RPTR, 0); 3509 WREG32(IH_RB_WPTR, 0); 3510 3511 /* Default settings for IH_CNTL (disabled at first) */ 3512 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); 3513 /* RPTR_REARM only works if msi's are enabled */ 3514 if (rdev->msi_enabled) 3515 ih_cntl |= RPTR_REARM; 3516 WREG32(IH_CNTL, ih_cntl); 3517 3518 /* force the active interrupt state to all disabled */ 3519 if (rdev->family >= CHIP_CEDAR) 3520 evergreen_disable_interrupt_state(rdev); 3521 else 3522 r600_disable_interrupt_state(rdev); 3523 3524 /* at this point everything should be setup correctly to enable master */ 3525 #ifdef notyet 3526 pci_set_master(rdev->pdev); 3527 #endif 3528 3529 /* enable irqs */ 3530 r600_enable_interrupts(rdev); 3531 3532 return ret; 3533 } 3534 3535 void r600_irq_suspend(struct radeon_device *rdev) 3536 { 3537 r600_irq_disable(rdev); 3538 r600_rlc_stop(rdev); 3539 } 3540 3541 void r600_irq_fini(struct radeon_device *rdev) 3542 { 3543 r600_irq_suspend(rdev); 3544 r600_ih_ring_fini(rdev); 3545 } 3546 3547 int r600_irq_set(struct radeon_device *rdev) 3548 { 3549 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 3550 u32 mode_int = 0; 3551 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 3552 u32 grbm_int_cntl = 0; 3553 u32 hdmi0, hdmi1; 3554 u32 d1grph = 0, d2grph = 0; 3555 u32 dma_cntl; 3556 3557 if (!rdev->irq.installed) { 3558 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 3559 return -EINVAL; 3560 } 3561 /* don't enable anything if the ih is disabled */ 3562 if (!rdev->ih.enabled) { 3563 r600_disable_interrupts(rdev); 3564 /* force the active interrupt state to all disabled */ 3565 r600_disable_interrupt_state(rdev); 3566 return 0; 3567 } 3568 3569 if (ASIC_IS_DCE3(rdev)) { 3570 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3571 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3572 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3573 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; 3574 if (ASIC_IS_DCE32(rdev)) { 3575 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; 3576 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; 3577 hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3578 hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK; 3579 } else { 3580 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3581 hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3582 } 3583 } else { 3584 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN; 3585 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN; 3586 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; 3587 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3588 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; 3589 } 3590 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 3591 3592 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 3593 DRM_DEBUG("r600_irq_set: sw int\n"); 3594 cp_int_cntl |= RB_INT_ENABLE; 3595 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3596 } 3597 3598 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { 3599 DRM_DEBUG("r600_irq_set: sw int dma\n"); 3600 dma_cntl |= TRAP_ENABLE; 3601 } 3602 3603 if (rdev->irq.crtc_vblank_int[0] || 3604 atomic_read(&rdev->irq.pflip[0])) { 3605 DRM_DEBUG("r600_irq_set: vblank 0\n"); 3606 mode_int |= D1MODE_VBLANK_INT_MASK; 3607 } 3608 if (rdev->irq.crtc_vblank_int[1] || 3609 atomic_read(&rdev->irq.pflip[1])) { 3610 DRM_DEBUG("r600_irq_set: vblank 1\n"); 3611 mode_int |= D2MODE_VBLANK_INT_MASK; 3612 } 3613 if (rdev->irq.hpd[0]) { 3614 DRM_DEBUG("r600_irq_set: hpd 1\n"); 3615 hpd1 |= DC_HPDx_INT_EN; 3616 } 3617 if (rdev->irq.hpd[1]) { 3618 DRM_DEBUG("r600_irq_set: hpd 2\n"); 3619 hpd2 |= DC_HPDx_INT_EN; 3620 } 3621 if (rdev->irq.hpd[2]) { 3622 DRM_DEBUG("r600_irq_set: hpd 3\n"); 3623 hpd3 |= DC_HPDx_INT_EN; 3624 } 3625 if (rdev->irq.hpd[3]) { 3626 DRM_DEBUG("r600_irq_set: hpd 4\n"); 3627 hpd4 |= DC_HPDx_INT_EN; 3628 } 3629 if (rdev->irq.hpd[4]) { 3630 DRM_DEBUG("r600_irq_set: hpd 5\n"); 3631 hpd5 |= DC_HPDx_INT_EN; 3632 } 3633 if (rdev->irq.hpd[5]) { 3634 DRM_DEBUG("r600_irq_set: hpd 6\n"); 3635 hpd6 |= DC_HPDx_INT_EN; 3636 } 3637 if (rdev->irq.afmt[0]) { 3638 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3639 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3640 } 3641 if (rdev->irq.afmt[1]) { 3642 DRM_DEBUG("r600_irq_set: hdmi 0\n"); 3643 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK; 3644 } 3645 3646 WREG32(CP_INT_CNTL, cp_int_cntl); 3647 WREG32(DMA_CNTL, dma_cntl); 3648 WREG32(DxMODE_INT_MASK, mode_int); 3649 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); 3650 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); 3651 WREG32(GRBM_INT_CNTL, grbm_int_cntl); 3652 if (ASIC_IS_DCE3(rdev)) { 3653 WREG32(DC_HPD1_INT_CONTROL, hpd1); 3654 WREG32(DC_HPD2_INT_CONTROL, hpd2); 3655 WREG32(DC_HPD3_INT_CONTROL, hpd3); 3656 WREG32(DC_HPD4_INT_CONTROL, hpd4); 3657 if (ASIC_IS_DCE32(rdev)) { 3658 WREG32(DC_HPD5_INT_CONTROL, hpd5); 3659 WREG32(DC_HPD6_INT_CONTROL, hpd6); 3660 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); 3661 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); 3662 } else { 3663 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3664 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3665 } 3666 } else { 3667 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); 3668 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); 3669 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); 3670 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); 3671 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); 3672 } 3673 3674 return 0; 3675 } 3676 3677 static void r600_irq_ack(struct radeon_device *rdev) 3678 { 3679 u32 tmp; 3680 3681 if (ASIC_IS_DCE3(rdev)) { 3682 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); 3683 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); 3684 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); 3685 if (ASIC_IS_DCE32(rdev)) { 3686 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); 3687 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); 3688 } else { 3689 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3690 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); 3691 } 3692 } else { 3693 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); 3694 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 3695 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; 3696 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); 3697 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); 3698 } 3699 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); 3700 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); 3701 3702 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3703 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3704 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) 3705 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); 3706 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) 3707 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3708 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) 3709 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3710 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) 3711 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); 3712 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) 3713 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); 3714 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3715 if (ASIC_IS_DCE3(rdev)) { 3716 tmp = RREG32(DC_HPD1_INT_CONTROL); 3717 tmp |= DC_HPDx_INT_ACK; 3718 WREG32(DC_HPD1_INT_CONTROL, tmp); 3719 } else { 3720 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); 3721 tmp |= DC_HPDx_INT_ACK; 3722 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); 3723 } 3724 } 3725 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3726 if (ASIC_IS_DCE3(rdev)) { 3727 tmp = RREG32(DC_HPD2_INT_CONTROL); 3728 tmp |= DC_HPDx_INT_ACK; 3729 WREG32(DC_HPD2_INT_CONTROL, tmp); 3730 } else { 3731 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); 3732 tmp |= DC_HPDx_INT_ACK; 3733 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); 3734 } 3735 } 3736 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3737 if (ASIC_IS_DCE3(rdev)) { 3738 tmp = RREG32(DC_HPD3_INT_CONTROL); 3739 tmp |= DC_HPDx_INT_ACK; 3740 WREG32(DC_HPD3_INT_CONTROL, tmp); 3741 } else { 3742 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); 3743 tmp |= DC_HPDx_INT_ACK; 3744 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); 3745 } 3746 } 3747 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3748 tmp = RREG32(DC_HPD4_INT_CONTROL); 3749 tmp |= DC_HPDx_INT_ACK; 3750 WREG32(DC_HPD4_INT_CONTROL, tmp); 3751 } 3752 if (ASIC_IS_DCE32(rdev)) { 3753 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3754 tmp = RREG32(DC_HPD5_INT_CONTROL); 3755 tmp |= DC_HPDx_INT_ACK; 3756 WREG32(DC_HPD5_INT_CONTROL, tmp); 3757 } 3758 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3759 tmp = RREG32(DC_HPD5_INT_CONTROL); 3760 tmp |= DC_HPDx_INT_ACK; 3761 WREG32(DC_HPD6_INT_CONTROL, tmp); 3762 } 3763 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { 3764 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); 3765 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3766 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); 3767 } 3768 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { 3769 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); 3770 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; 3771 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); 3772 } 3773 } else { 3774 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 3775 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); 3776 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3777 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); 3778 } 3779 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 3780 if (ASIC_IS_DCE3(rdev)) { 3781 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); 3782 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3783 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); 3784 } else { 3785 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); 3786 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; 3787 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); 3788 } 3789 } 3790 } 3791 } 3792 3793 void r600_irq_disable(struct radeon_device *rdev) 3794 { 3795 r600_disable_interrupts(rdev); 3796 /* Wait and acknowledge irq */ 3797 mdelay(1); 3798 r600_irq_ack(rdev); 3799 r600_disable_interrupt_state(rdev); 3800 } 3801 3802 static u32 r600_get_ih_wptr(struct radeon_device *rdev) 3803 { 3804 u32 wptr, tmp; 3805 3806 if (rdev->wb.enabled) 3807 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); 3808 else 3809 wptr = RREG32(IH_RB_WPTR); 3810 3811 if (wptr & RB_OVERFLOW) { 3812 /* When a ring buffer overflow happen start parsing interrupt 3813 * from the last not overwritten vector (wptr + 16). Hopefully 3814 * this should allow us to catchup. 3815 */ 3816 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", 3817 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); 3818 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; 3819 tmp = RREG32(IH_RB_CNTL); 3820 tmp |= IH_WPTR_OVERFLOW_CLEAR; 3821 WREG32(IH_RB_CNTL, tmp); 3822 } 3823 return (wptr & rdev->ih.ptr_mask); 3824 } 3825 3826 /* r600 IV Ring 3827 * Each IV ring entry is 128 bits: 3828 * [7:0] - interrupt source id 3829 * [31:8] - reserved 3830 * [59:32] - interrupt source data 3831 * [127:60] - reserved 3832 * 3833 * The basic interrupt vector entries 3834 * are decoded as follows: 3835 * src_id src_data description 3836 * 1 0 D1 Vblank 3837 * 1 1 D1 Vline 3838 * 5 0 D2 Vblank 3839 * 5 1 D2 Vline 3840 * 19 0 FP Hot plug detection A 3841 * 19 1 FP Hot plug detection B 3842 * 19 2 DAC A auto-detection 3843 * 19 3 DAC B auto-detection 3844 * 21 4 HDMI block A 3845 * 21 5 HDMI block B 3846 * 176 - CP_INT RB 3847 * 177 - CP_INT IB1 3848 * 178 - CP_INT IB2 3849 * 181 - EOP Interrupt 3850 * 233 - GUI Idle 3851 * 3852 * Note, these are based on r600 and may need to be 3853 * adjusted or added to on newer asics 3854 */ 3855 3856 int r600_irq_process(struct radeon_device *rdev) 3857 { 3858 u32 wptr; 3859 u32 rptr; 3860 u32 src_id, src_data; 3861 u32 ring_index; 3862 bool queue_hotplug = false; 3863 bool queue_hdmi = false; 3864 3865 if (!rdev->ih.enabled || rdev->shutdown) 3866 return (0); 3867 3868 /* No MSIs, need a dummy read to flush PCI DMAs */ 3869 if (!rdev->msi_enabled) 3870 RREG32(IH_RB_WPTR); 3871 3872 wptr = r600_get_ih_wptr(rdev); 3873 3874 if (wptr == rdev->ih.rptr) 3875 return (0); 3876 restart_ih: 3877 /* is somebody else already processing irqs? */ 3878 if (atomic_xchg(&rdev->ih.lock, 1)) 3879 return (0); 3880 3881 rptr = rdev->ih.rptr; 3882 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 3883 3884 /* Order reading of wptr vs. reading of IH ring data */ 3885 DRM_READMEMORYBARRIER(); 3886 3887 /* display interrupts */ 3888 r600_irq_ack(rdev); 3889 3890 while (rptr != wptr) { 3891 /* wptr/rptr are in bytes! */ 3892 ring_index = rptr / 4; 3893 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; 3894 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; 3895 3896 switch (src_id) { 3897 case 1: /* D1 vblank/vline */ 3898 switch (src_data) { 3899 case 0: /* D1 vblank */ 3900 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) { 3901 if (rdev->irq.crtc_vblank_int[0]) { 3902 drm_handle_vblank(rdev->ddev, 0); 3903 rdev->pm.vblank_sync = true; 3904 wakeup(&rdev->irq.vblank_queue); 3905 } 3906 if (atomic_read(&rdev->irq.pflip[0])) 3907 radeon_crtc_handle_flip(rdev, 0); 3908 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; 3909 DRM_DEBUG("IH: D1 vblank\n"); 3910 } 3911 break; 3912 case 1: /* D1 vline */ 3913 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) { 3914 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; 3915 DRM_DEBUG("IH: D1 vline\n"); 3916 } 3917 break; 3918 default: 3919 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3920 break; 3921 } 3922 break; 3923 case 5: /* D2 vblank/vline */ 3924 switch (src_data) { 3925 case 0: /* D2 vblank */ 3926 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) { 3927 if (rdev->irq.crtc_vblank_int[1]) { 3928 drm_handle_vblank(rdev->ddev, 1); 3929 rdev->pm.vblank_sync = true; 3930 wakeup(&rdev->irq.vblank_queue); 3931 } 3932 if (atomic_read(&rdev->irq.pflip[1])) 3933 radeon_crtc_handle_flip(rdev, 1); 3934 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; 3935 DRM_DEBUG("IH: D2 vblank\n"); 3936 } 3937 break; 3938 case 1: /* D1 vline */ 3939 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) { 3940 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; 3941 DRM_DEBUG("IH: D2 vline\n"); 3942 } 3943 break; 3944 default: 3945 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3946 break; 3947 } 3948 break; 3949 case 19: /* HPD/DAC hotplug */ 3950 switch (src_data) { 3951 case 0: 3952 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { 3953 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; 3954 queue_hotplug = true; 3955 DRM_DEBUG("IH: HPD1\n"); 3956 } 3957 break; 3958 case 1: 3959 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { 3960 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; 3961 queue_hotplug = true; 3962 DRM_DEBUG("IH: HPD2\n"); 3963 } 3964 break; 3965 case 4: 3966 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { 3967 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; 3968 queue_hotplug = true; 3969 DRM_DEBUG("IH: HPD3\n"); 3970 } 3971 break; 3972 case 5: 3973 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { 3974 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; 3975 queue_hotplug = true; 3976 DRM_DEBUG("IH: HPD4\n"); 3977 } 3978 break; 3979 case 10: 3980 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { 3981 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; 3982 queue_hotplug = true; 3983 DRM_DEBUG("IH: HPD5\n"); 3984 } 3985 break; 3986 case 12: 3987 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { 3988 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; 3989 queue_hotplug = true; 3990 DRM_DEBUG("IH: HPD6\n"); 3991 } 3992 break; 3993 default: 3994 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 3995 break; 3996 } 3997 break; 3998 case 21: /* hdmi */ 3999 switch (src_data) { 4000 case 4: 4001 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { 4002 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4003 queue_hdmi = true; 4004 DRM_DEBUG("IH: HDMI0\n"); 4005 } 4006 break; 4007 case 5: 4008 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { 4009 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; 4010 queue_hdmi = true; 4011 DRM_DEBUG("IH: HDMI1\n"); 4012 } 4013 break; 4014 default: 4015 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 4016 break; 4017 } 4018 break; 4019 case 176: /* CP_INT in ring buffer */ 4020 case 177: /* CP_INT in IB1 */ 4021 case 178: /* CP_INT in IB2 */ 4022 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); 4023 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4024 break; 4025 case 181: /* CP EOP event */ 4026 DRM_DEBUG("IH: CP EOP\n"); 4027 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 4028 break; 4029 case 224: /* DMA trap event */ 4030 DRM_DEBUG("IH: DMA trap\n"); 4031 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); 4032 break; 4033 case 233: /* GUI IDLE */ 4034 DRM_DEBUG("IH: GUI idle\n"); 4035 break; 4036 default: 4037 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 4038 break; 4039 } 4040 4041 /* wptr/rptr are in bytes! */ 4042 rptr += 16; 4043 rptr &= rdev->ih.ptr_mask; 4044 } 4045 if (queue_hotplug) 4046 task_add(systq, &rdev->hotplug_task); 4047 if (queue_hdmi) 4048 task_add(systq, &rdev->audio_task); 4049 rdev->ih.rptr = rptr; 4050 WREG32(IH_RB_RPTR, rdev->ih.rptr); 4051 atomic_set(&rdev->ih.lock, 0); 4052 4053 /* make sure wptr hasn't changed while processing */ 4054 wptr = r600_get_ih_wptr(rdev); 4055 if (wptr != rptr) 4056 goto restart_ih; 4057 4058 return (1); 4059 } 4060 4061 /* 4062 * Debugfs info 4063 */ 4064 #if defined(CONFIG_DEBUG_FS) 4065 4066 static int r600_debugfs_mc_info(struct seq_file *m, void *data) 4067 { 4068 struct drm_info_node *node = (struct drm_info_node *) m->private; 4069 struct drm_device *dev = node->minor->dev; 4070 struct radeon_device *rdev = dev->dev_private; 4071 4072 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS); 4073 DREG32_SYS(m, rdev, VM_L2_STATUS); 4074 return 0; 4075 } 4076 4077 static struct drm_info_list r600_mc_info_list[] = { 4078 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, 4079 }; 4080 #endif 4081 4082 int r600_debugfs_mc_info_init(struct radeon_device *rdev) 4083 { 4084 #if defined(CONFIG_DEBUG_FS) 4085 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list)); 4086 #else 4087 return 0; 4088 #endif 4089 } 4090 4091 /** 4092 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl 4093 * rdev: radeon device structure 4094 * bo: buffer object struct which userspace is waiting for idle 4095 * 4096 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed 4097 * through ring buffer, this leads to corruption in rendering, see 4098 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we 4099 * directly perform HDP flush by writing register through MMIO. 4100 */ 4101 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 4102 { 4103 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 4104 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL. 4105 * This seems to cause problems on some AGP cards. Just use the old 4106 * method for them. 4107 */ 4108 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 4109 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { 4110 volatile uint32_t *ptr = rdev->vram_scratch.ptr; 4111 u32 tmp; 4112 4113 WREG32(HDP_DEBUG1, 0); 4114 tmp = *ptr; 4115 } else 4116 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); 4117 } 4118 4119 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) 4120 { 4121 u32 link_width_cntl, mask, target_reg; 4122 4123 if (rdev->flags & RADEON_IS_IGP) 4124 return; 4125 4126 if (!(rdev->flags & RADEON_IS_PCIE)) 4127 return; 4128 4129 /* x2 cards have a special sequence */ 4130 if (ASIC_IS_X2(rdev)) 4131 return; 4132 4133 /* FIXME wait for idle */ 4134 4135 switch (lanes) { 4136 case 0: 4137 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 4138 break; 4139 case 1: 4140 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 4141 break; 4142 case 2: 4143 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 4144 break; 4145 case 4: 4146 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 4147 break; 4148 case 8: 4149 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 4150 break; 4151 case 12: 4152 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 4153 break; 4154 case 16: 4155 default: 4156 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 4157 break; 4158 } 4159 4160 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4161 4162 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 4163 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 4164 return; 4165 4166 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS) 4167 return; 4168 4169 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 4170 RADEON_PCIE_LC_RECONFIG_NOW | 4171 R600_PCIE_LC_RENEGOTIATE_EN | 4172 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE); 4173 link_width_cntl |= mask; 4174 4175 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4176 4177 /* some northbridges can renegotiate the link rather than requiring 4178 * a complete re-config. 4179 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.) 4180 */ 4181 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT) 4182 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT; 4183 else 4184 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE; 4185 4186 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 4187 RADEON_PCIE_LC_RECONFIG_NOW)); 4188 4189 if (rdev->family >= CHIP_RV770) 4190 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX; 4191 else 4192 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX; 4193 4194 /* wait for lane set to complete */ 4195 link_width_cntl = RREG32(target_reg); 4196 while (link_width_cntl == 0xffffffff) 4197 link_width_cntl = RREG32(target_reg); 4198 4199 } 4200 4201 int r600_get_pcie_lanes(struct radeon_device *rdev) 4202 { 4203 u32 link_width_cntl; 4204 4205 if (rdev->flags & RADEON_IS_IGP) 4206 return 0; 4207 4208 if (!(rdev->flags & RADEON_IS_PCIE)) 4209 return 0; 4210 4211 /* x2 cards have a special sequence */ 4212 if (ASIC_IS_X2(rdev)) 4213 return 0; 4214 4215 /* FIXME wait for idle */ 4216 4217 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 4218 4219 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 4220 case RADEON_PCIE_LC_LINK_WIDTH_X0: 4221 return 0; 4222 case RADEON_PCIE_LC_LINK_WIDTH_X1: 4223 return 1; 4224 case RADEON_PCIE_LC_LINK_WIDTH_X2: 4225 return 2; 4226 case RADEON_PCIE_LC_LINK_WIDTH_X4: 4227 return 4; 4228 case RADEON_PCIE_LC_LINK_WIDTH_X8: 4229 return 8; 4230 case RADEON_PCIE_LC_LINK_WIDTH_X16: 4231 default: 4232 return 16; 4233 } 4234 } 4235 4236 static void r600_pcie_gen2_enable(struct radeon_device *rdev) 4237 { 4238 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; 4239 u16 link_cntl2; 4240 u32 mask; 4241 int ret; 4242 4243 if (radeon_pcie_gen2 == 0) 4244 return; 4245 4246 if (rdev->flags & RADEON_IS_IGP) 4247 return; 4248 4249 if (!(rdev->flags & RADEON_IS_PCIE)) 4250 return; 4251 4252 /* x2 cards have a special sequence */ 4253 if (ASIC_IS_X2(rdev)) 4254 return; 4255 4256 /* only RV6xx+ chips are supported */ 4257 if (rdev->family <= CHIP_R600) 4258 return; 4259 4260 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); 4261 if (ret != 0) 4262 return; 4263 4264 if (!(mask & DRM_PCIE_SPEED_50)) 4265 return; 4266 4267 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4268 if (speed_cntl & LC_CURRENT_DATA_RATE) { 4269 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 4270 return; 4271 } 4272 4273 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 4274 4275 /* 55 nm r6xx asics */ 4276 if ((rdev->family == CHIP_RV670) || 4277 (rdev->family == CHIP_RV620) || 4278 (rdev->family == CHIP_RV635)) { 4279 /* advertise upconfig capability */ 4280 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4281 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4282 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4283 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4284 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { 4285 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; 4286 link_width_cntl &= ~(LC_LINK_WIDTH_MASK | 4287 LC_RECONFIG_ARC_MISSING_ESCAPE); 4288 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; 4289 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4290 } else { 4291 link_width_cntl |= LC_UPCONFIGURE_DIS; 4292 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4293 } 4294 } 4295 4296 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4297 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && 4298 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { 4299 4300 /* 55 nm r6xx asics */ 4301 if ((rdev->family == CHIP_RV670) || 4302 (rdev->family == CHIP_RV620) || 4303 (rdev->family == CHIP_RV635)) { 4304 WREG32(MM_CFGREGS_CNTL, 0x8); 4305 link_cntl2 = RREG32(0x4088); 4306 WREG32(MM_CFGREGS_CNTL, 0); 4307 /* not supported yet */ 4308 if (link_cntl2 & SELECTABLE_DEEMPHASIS) 4309 return; 4310 } 4311 4312 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; 4313 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); 4314 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; 4315 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; 4316 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; 4317 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4318 4319 tmp = RREG32(0x541c); 4320 WREG32(0x541c, tmp | 0x8); 4321 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); 4322 link_cntl2 = RREG16(0x4088); 4323 link_cntl2 &= ~TARGET_LINK_SPEED_MASK; 4324 link_cntl2 |= 0x2; 4325 WREG16(0x4088, link_cntl2); 4326 WREG32(MM_CFGREGS_CNTL, 0); 4327 4328 if ((rdev->family == CHIP_RV670) || 4329 (rdev->family == CHIP_RV620) || 4330 (rdev->family == CHIP_RV635)) { 4331 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL); 4332 training_cntl &= ~LC_POINT_7_PLUS_EN; 4333 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl); 4334 } else { 4335 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4336 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; 4337 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4338 } 4339 4340 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); 4341 speed_cntl |= LC_GEN2_EN_STRAP; 4342 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); 4343 4344 } else { 4345 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); 4346 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ 4347 if (1) 4348 link_width_cntl |= LC_UPCONFIGURE_DIS; 4349 else 4350 link_width_cntl &= ~LC_UPCONFIGURE_DIS; 4351 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 4352 } 4353 } 4354 4355 /** 4356 * r600_get_gpu_clock - return GPU clock counter snapshot 4357 * 4358 * @rdev: radeon_device pointer 4359 * 4360 * Fetches a GPU clock counter snapshot (R6xx-cayman). 4361 * Returns the 64 bit clock counter snapshot. 4362 */ 4363 uint64_t r600_get_gpu_clock(struct radeon_device *rdev) 4364 { 4365 uint64_t clock; 4366 4367 rw_enter_write(&rdev->gpu_clock_rwlock); 4368 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); 4369 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | 4370 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 4371 rw_exit_write(&rdev->gpu_clock_rwlock); 4372 return clock; 4373 } 4374