1 /* $OpenBSD: r520.c,v 1.4 2015/04/06 03:49:47 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "atom.h" 33 #include "r520d.h" 34 35 /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ 36 37 int r520_mc_wait_for_idle(struct radeon_device *rdev) 38 { 39 unsigned i; 40 uint32_t tmp; 41 42 for (i = 0; i < rdev->usec_timeout; i++) { 43 /* read MC_STATUS */ 44 tmp = RREG32_MC(R520_MC_STATUS); 45 if (tmp & R520_MC_STATUS_IDLE) { 46 return 0; 47 } 48 DRM_UDELAY(1); 49 } 50 return -1; 51 } 52 53 static void r520_gpu_init(struct radeon_device *rdev) 54 { 55 unsigned pipe_select_current, gb_pipe_select, tmp; 56 57 rv515_vga_render_disable(rdev); 58 /* 59 * DST_PIPE_CONFIG 0x170C 60 * GB_TILE_CONFIG 0x4018 61 * GB_FIFO_SIZE 0x4024 62 * GB_PIPE_SELECT 0x402C 63 * GB_PIPE_SELECT2 0x4124 64 * Z_PIPE_SHIFT 0 65 * Z_PIPE_MASK 0x000000003 66 * GB_FIFO_SIZE2 0x4128 67 * SC_SFIFO_SIZE_SHIFT 0 68 * SC_SFIFO_SIZE_MASK 0x000000003 69 * SC_MFIFO_SIZE_SHIFT 2 70 * SC_MFIFO_SIZE_MASK 0x00000000C 71 * FG_SFIFO_SIZE_SHIFT 4 72 * FG_SFIFO_SIZE_MASK 0x000000030 73 * ZB_MFIFO_SIZE_SHIFT 6 74 * ZB_MFIFO_SIZE_MASK 0x0000000C0 75 * GA_ENHANCE 0x4274 76 * SU_REG_DEST 0x42C8 77 */ 78 /* workaround for RV530 */ 79 if (rdev->family == CHIP_RV530) { 80 WREG32(0x4128, 0xFF); 81 } 82 r420_pipes_init(rdev); 83 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 84 tmp = RREG32(R300_DST_PIPE_CONFIG); 85 pipe_select_current = (tmp >> 2) & 3; 86 tmp = (1 << pipe_select_current) | 87 (((gb_pipe_select >> 8) & 0xF) << 4); 88 WREG32_PLL(0x000D, tmp); 89 if (r520_mc_wait_for_idle(rdev)) { 90 printk(KERN_WARNING "Failed to wait MC idle while " 91 "programming pipes. Bad things might happen.\n"); 92 } 93 } 94 95 static void r520_vram_get_type(struct radeon_device *rdev) 96 { 97 uint32_t tmp; 98 99 rdev->mc.vram_width = 128; 100 rdev->mc.vram_is_ddr = true; 101 tmp = RREG32_MC(R520_MC_CNTL0); 102 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 103 case 0: 104 rdev->mc.vram_width = 32; 105 break; 106 case 1: 107 rdev->mc.vram_width = 64; 108 break; 109 case 2: 110 rdev->mc.vram_width = 128; 111 break; 112 case 3: 113 rdev->mc.vram_width = 256; 114 break; 115 default: 116 rdev->mc.vram_width = 128; 117 break; 118 } 119 if (tmp & R520_MC_CHANNEL_SIZE) 120 rdev->mc.vram_width *= 2; 121 } 122 123 static void r520_mc_init(struct radeon_device *rdev) 124 { 125 126 r520_vram_get_type(rdev); 127 r100_vram_init_sizes(rdev); 128 radeon_vram_location(rdev, &rdev->mc, 0); 129 rdev->mc.gtt_base_align = 0; 130 if (!(rdev->flags & RADEON_IS_AGP)) 131 radeon_gtt_location(rdev, &rdev->mc); 132 radeon_update_bandwidth_info(rdev); 133 } 134 135 static void r520_mc_program(struct radeon_device *rdev) 136 { 137 struct rv515_mc_save save; 138 139 /* Stops all mc clients */ 140 rv515_mc_stop(rdev, &save); 141 142 /* Wait for mc idle */ 143 if (r520_mc_wait_for_idle(rdev)) 144 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 145 /* Write VRAM size in case we are limiting it */ 146 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 147 /* Program MC, should be a 32bits limited address space */ 148 WREG32_MC(R_000004_MC_FB_LOCATION, 149 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | 150 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); 151 WREG32(R_000134_HDP_FB_LOCATION, 152 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); 153 if (rdev->flags & RADEON_IS_AGP) { 154 WREG32_MC(R_000005_MC_AGP_LOCATION, 155 S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | 156 S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 157 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 158 WREG32_MC(R_000007_AGP_BASE_2, 159 S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); 160 } else { 161 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); 162 WREG32_MC(R_000006_AGP_BASE, 0); 163 WREG32_MC(R_000007_AGP_BASE_2, 0); 164 } 165 166 rv515_mc_resume(rdev, &save); 167 } 168 169 static int r520_startup(struct radeon_device *rdev) 170 { 171 int r; 172 173 r520_mc_program(rdev); 174 /* Resume clock */ 175 rv515_clock_startup(rdev); 176 /* Initialize GPU configuration (# pipes, ...) */ 177 r520_gpu_init(rdev); 178 /* Initialize GART (initialize after TTM so we can allocate 179 * memory through TTM but finalize after TTM) */ 180 if (rdev->flags & RADEON_IS_PCIE) { 181 r = rv370_pcie_gart_enable(rdev); 182 if (r) 183 return r; 184 } 185 186 /* allocate wb buffer */ 187 r = radeon_wb_init(rdev); 188 if (r) 189 return r; 190 191 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 192 if (r) { 193 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 194 return r; 195 } 196 197 /* Enable IRQ */ 198 if (!rdev->irq.installed) { 199 r = radeon_irq_kms_init(rdev); 200 if (r) 201 return r; 202 } 203 204 rs600_irq_set(rdev); 205 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 206 /* 1M ring buffer */ 207 r = r100_cp_init(rdev, 1024 * 1024); 208 if (r) { 209 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 210 return r; 211 } 212 213 r = radeon_ib_pool_init(rdev); 214 if (r) { 215 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 216 return r; 217 } 218 219 return 0; 220 } 221 222 int r520_resume(struct radeon_device *rdev) 223 { 224 int r; 225 226 /* Make sur GART are not working */ 227 if (rdev->flags & RADEON_IS_PCIE) 228 rv370_pcie_gart_disable(rdev); 229 /* Resume clock before doing reset */ 230 rv515_clock_startup(rdev); 231 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 232 if (radeon_asic_reset(rdev)) { 233 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 234 RREG32(R_000E40_RBBM_STATUS), 235 RREG32(R_0007C0_CP_STAT)); 236 } 237 /* post */ 238 atom_asic_init(rdev->mode_info.atom_context); 239 /* Resume clock after posting */ 240 rv515_clock_startup(rdev); 241 /* Initialize surface registers */ 242 radeon_surface_init(rdev); 243 244 rdev->accel_working = true; 245 r = r520_startup(rdev); 246 if (r) { 247 rdev->accel_working = false; 248 } 249 return r; 250 } 251 252 int r520_init(struct radeon_device *rdev) 253 { 254 int r; 255 256 /* Initialize scratch registers */ 257 radeon_scratch_init(rdev); 258 /* Initialize surface registers */ 259 radeon_surface_init(rdev); 260 /* restore some register to sane defaults */ 261 r100_restore_sanity(rdev); 262 /* TODO: disable VGA need to use VGA request */ 263 /* BIOS*/ 264 if (!radeon_get_bios(rdev)) { 265 if (ASIC_IS_AVIVO(rdev)) 266 return -EINVAL; 267 } 268 if (rdev->is_atom_bios) { 269 r = radeon_atombios_init(rdev); 270 if (r) 271 return r; 272 } else { 273 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); 274 return -EINVAL; 275 } 276 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 277 if (radeon_asic_reset(rdev)) { 278 dev_warn(rdev->dev, 279 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 280 RREG32(R_000E40_RBBM_STATUS), 281 RREG32(R_0007C0_CP_STAT)); 282 } 283 /* check if cards are posted or not */ 284 if (radeon_boot_test_post_card(rdev) == false) 285 return -EINVAL; 286 287 if (!radeon_card_posted(rdev) && rdev->bios) { 288 DRM_INFO("GPU not posted. posting now...\n"); 289 atom_asic_init(rdev->mode_info.atom_context); 290 } 291 /* Initialize clocks */ 292 radeon_get_clock_info(rdev->ddev); 293 /* initialize AGP */ 294 if (rdev->flags & RADEON_IS_AGP) { 295 r = radeon_agp_init(rdev); 296 if (r) { 297 radeon_agp_disable(rdev); 298 } 299 } 300 /* initialize memory controller */ 301 r520_mc_init(rdev); 302 rv515_debugfs(rdev); 303 /* Fence driver */ 304 r = radeon_fence_driver_init(rdev); 305 if (r) 306 return r; 307 /* Memory manager */ 308 r = radeon_bo_init(rdev); 309 if (r) 310 return r; 311 r = rv370_pcie_gart_init(rdev); 312 if (r) 313 return r; 314 rv515_set_safe_registers(rdev); 315 316 rdev->accel_working = true; 317 r = r520_startup(rdev); 318 if (r) { 319 /* Somethings want wront with the accel init stop accel */ 320 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 321 r100_cp_fini(rdev); 322 radeon_wb_fini(rdev); 323 radeon_ib_pool_fini(rdev); 324 radeon_irq_kms_fini(rdev); 325 rv370_pcie_gart_fini(rdev); 326 radeon_agp_fini(rdev); 327 rdev->accel_working = false; 328 } 329 return 0; 330 } 331