1 /* $OpenBSD: r420.c,v 1.5 2015/02/11 07:01:37 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include "radeon_reg.h" 31 #include "radeon.h" 32 #include "radeon_asic.h" 33 #include "atom.h" 34 #include "r100d.h" 35 #include "r420d.h" 36 #include "r420_reg_safe.h" 37 38 void r420_pm_init_profile(struct radeon_device *rdev) 39 { 40 /* default */ 41 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 45 /* low sh */ 46 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 50 /* mid sh */ 51 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; 53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 55 /* high sh */ 56 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 60 /* low mh */ 61 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 65 /* mid mh */ 66 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 70 /* high mh */ 71 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 75 } 76 77 static void r420_set_reg_safe(struct radeon_device *rdev) 78 { 79 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; 80 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); 81 } 82 83 void r420_pipes_init(struct radeon_device *rdev) 84 { 85 unsigned tmp; 86 unsigned gb_pipe_select; 87 unsigned num_pipes; 88 89 /* GA_ENHANCE workaround TCL deadlock issue */ 90 WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL | 91 (1 << 2) | (1 << 3)); 92 /* add idle wait as per freedesktop.org bug 24041 */ 93 if (r100_gui_wait_for_idle(rdev)) { 94 printk(KERN_WARNING "Failed to wait GUI idle while " 95 "programming pipes. Bad things might happen.\n"); 96 } 97 /* get max number of pipes */ 98 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT); 99 num_pipes = ((gb_pipe_select >> 12) & 3) + 1; 100 101 /* SE chips have 1 pipe */ 102 if ((rdev->pdev->device == 0x5e4c) || 103 (rdev->pdev->device == 0x5e4f)) 104 num_pipes = 1; 105 106 rdev->num_gb_pipes = num_pipes; 107 tmp = 0; 108 switch (num_pipes) { 109 default: 110 /* force to 1 pipe */ 111 num_pipes = 1; 112 case 1: 113 tmp = (0 << 1); 114 break; 115 case 2: 116 tmp = (3 << 1); 117 break; 118 case 3: 119 tmp = (6 << 1); 120 break; 121 case 4: 122 tmp = (7 << 1); 123 break; 124 } 125 WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1); 126 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 127 tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING; 128 WREG32(R300_GB_TILE_CONFIG, tmp); 129 if (r100_gui_wait_for_idle(rdev)) { 130 printk(KERN_WARNING "Failed to wait GUI idle while " 131 "programming pipes. Bad things might happen.\n"); 132 } 133 134 tmp = RREG32(R300_DST_PIPE_CONFIG); 135 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 136 137 WREG32(R300_RB2D_DSTCACHE_MODE, 138 RREG32(R300_RB2D_DSTCACHE_MODE) | 139 R300_DC_AUTOFLUSH_ENABLE | 140 R300_DC_DC_DISABLE_IGNORE_PE); 141 142 if (r100_gui_wait_for_idle(rdev)) { 143 printk(KERN_WARNING "Failed to wait GUI idle while " 144 "programming pipes. Bad things might happen.\n"); 145 } 146 147 if (rdev->family == CHIP_RV530) { 148 tmp = RREG32(RV530_GB_PIPE_SELECT2); 149 if ((tmp & 3) == 3) 150 rdev->num_z_pipes = 2; 151 else 152 rdev->num_z_pipes = 1; 153 } else 154 rdev->num_z_pipes = 1; 155 156 DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n", 157 rdev->num_gb_pipes, rdev->num_z_pipes); 158 } 159 160 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) 161 { 162 u32 r; 163 164 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg)); 165 r = RREG32(R_0001FC_MC_IND_DATA); 166 return r; 167 } 168 169 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) 170 { 171 WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) | 172 S_0001F8_MC_IND_WR_EN(1)); 173 WREG32(R_0001FC_MC_IND_DATA, v); 174 } 175 176 static void r420_debugfs(struct radeon_device *rdev) 177 { 178 if (r100_debugfs_rbbm_init(rdev)) { 179 DRM_ERROR("Failed to register debugfs file for RBBM !\n"); 180 } 181 if (r420_debugfs_pipes_info_init(rdev)) { 182 DRM_ERROR("Failed to register debugfs file for pipes !\n"); 183 } 184 } 185 186 static void r420_clock_resume(struct radeon_device *rdev) 187 { 188 u32 sclk_cntl; 189 190 if (radeon_dynclks != -1 && radeon_dynclks) 191 radeon_atom_set_clock_gating(rdev, 1); 192 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL); 193 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 194 if (rdev->family == CHIP_R420) 195 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1); 196 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 197 } 198 199 static void r420_cp_errata_init(struct radeon_device *rdev) 200 { 201 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 202 203 /* RV410 and R420 can lock up if CP DMA to host memory happens 204 * while the 2D engine is busy. 205 * 206 * The proper workaround is to queue a RESYNC at the beginning 207 * of the CP init, apparently. 208 */ 209 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 210 radeon_ring_lock(rdev, ring, 8); 211 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)); 212 radeon_ring_write(ring, rdev->config.r300.resync_scratch); 213 radeon_ring_write(ring, 0xDEADBEEF); 214 radeon_ring_unlock_commit(rdev, ring); 215 } 216 217 static void r420_cp_errata_fini(struct radeon_device *rdev) 218 { 219 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 220 221 /* Catch the RESYNC we dispatched all the way back, 222 * at the very beginning of the CP init. 223 */ 224 radeon_ring_lock(rdev, ring, 8); 225 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 226 radeon_ring_write(ring, R300_RB3D_DC_FINISH); 227 radeon_ring_unlock_commit(rdev, ring); 228 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 229 } 230 231 static int r420_startup(struct radeon_device *rdev) 232 { 233 int r; 234 235 /* set common regs */ 236 r100_set_common_regs(rdev); 237 /* program mc */ 238 r300_mc_program(rdev); 239 /* Resume clock */ 240 r420_clock_resume(rdev); 241 /* Initialize GART (initialize after TTM so we can allocate 242 * memory through TTM but finalize after TTM) */ 243 if (rdev->flags & RADEON_IS_PCIE) { 244 r = rv370_pcie_gart_enable(rdev); 245 if (r) 246 return r; 247 } 248 if (rdev->flags & RADEON_IS_PCI) { 249 r = r100_pci_gart_enable(rdev); 250 if (r) 251 return r; 252 } 253 r420_pipes_init(rdev); 254 255 /* allocate wb buffer */ 256 r = radeon_wb_init(rdev); 257 if (r) 258 return r; 259 260 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 261 if (r) { 262 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 263 return r; 264 } 265 266 /* Enable IRQ */ 267 if (!rdev->irq.installed) { 268 r = radeon_irq_kms_init(rdev); 269 if (r) 270 return r; 271 } 272 273 r100_irq_set(rdev); 274 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 275 /* 1M ring buffer */ 276 r = r100_cp_init(rdev, 1024 * 1024); 277 if (r) { 278 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 279 return r; 280 } 281 r420_cp_errata_init(rdev); 282 283 r = radeon_ib_pool_init(rdev); 284 if (r) { 285 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 286 return r; 287 } 288 289 return 0; 290 } 291 292 int r420_resume(struct radeon_device *rdev) 293 { 294 int r; 295 296 /* Make sur GART are not working */ 297 if (rdev->flags & RADEON_IS_PCIE) 298 rv370_pcie_gart_disable(rdev); 299 if (rdev->flags & RADEON_IS_PCI) 300 r100_pci_gart_disable(rdev); 301 /* Resume clock before doing reset */ 302 r420_clock_resume(rdev); 303 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 304 if (radeon_asic_reset(rdev)) { 305 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 306 RREG32(R_000E40_RBBM_STATUS), 307 RREG32(R_0007C0_CP_STAT)); 308 } 309 /* check if cards are posted or not */ 310 if (rdev->is_atom_bios) { 311 atom_asic_init(rdev->mode_info.atom_context); 312 } else { 313 radeon_combios_asic_init(rdev->ddev); 314 } 315 /* Resume clock after posting */ 316 r420_clock_resume(rdev); 317 /* Initialize surface registers */ 318 radeon_surface_init(rdev); 319 320 rdev->accel_working = true; 321 r = r420_startup(rdev); 322 if (r) { 323 rdev->accel_working = false; 324 } 325 return r; 326 } 327 328 int r420_suspend(struct radeon_device *rdev) 329 { 330 r420_cp_errata_fini(rdev); 331 r100_cp_disable(rdev); 332 radeon_wb_disable(rdev); 333 r100_irq_disable(rdev); 334 if (rdev->flags & RADEON_IS_PCIE) 335 rv370_pcie_gart_disable(rdev); 336 if (rdev->flags & RADEON_IS_PCI) 337 r100_pci_gart_disable(rdev); 338 return 0; 339 } 340 341 void r420_fini(struct radeon_device *rdev) 342 { 343 r100_cp_fini(rdev); 344 radeon_wb_fini(rdev); 345 radeon_ib_pool_fini(rdev); 346 radeon_gem_fini(rdev); 347 if (rdev->flags & RADEON_IS_PCIE) 348 rv370_pcie_gart_fini(rdev); 349 if (rdev->flags & RADEON_IS_PCI) 350 r100_pci_gart_fini(rdev); 351 radeon_agp_fini(rdev); 352 radeon_irq_kms_fini(rdev); 353 radeon_fence_driver_fini(rdev); 354 radeon_bo_fini(rdev); 355 if (rdev->is_atom_bios) { 356 radeon_atombios_fini(rdev); 357 } else { 358 radeon_combios_fini(rdev); 359 } 360 kfree(rdev->bios); 361 rdev->bios = NULL; 362 } 363 364 int r420_init(struct radeon_device *rdev) 365 { 366 int r; 367 368 /* Initialize scratch registers */ 369 radeon_scratch_init(rdev); 370 /* Initialize surface registers */ 371 radeon_surface_init(rdev); 372 /* TODO: disable VGA need to use VGA request */ 373 /* restore some register to sane defaults */ 374 r100_restore_sanity(rdev); 375 /* BIOS*/ 376 if (!radeon_get_bios(rdev)) { 377 if (ASIC_IS_AVIVO(rdev)) 378 return -EINVAL; 379 } 380 if (rdev->is_atom_bios) { 381 r = radeon_atombios_init(rdev); 382 if (r) { 383 return r; 384 } 385 } else { 386 r = radeon_combios_init(rdev); 387 if (r) { 388 return r; 389 } 390 } 391 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 392 if (radeon_asic_reset(rdev)) { 393 dev_warn(rdev->dev, 394 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 395 RREG32(R_000E40_RBBM_STATUS), 396 RREG32(R_0007C0_CP_STAT)); 397 } 398 /* check if cards are posted or not */ 399 if (radeon_boot_test_post_card(rdev) == false) 400 return -EINVAL; 401 402 /* Initialize clocks */ 403 radeon_get_clock_info(rdev->ddev); 404 /* initialize AGP */ 405 if (rdev->flags & RADEON_IS_AGP) { 406 r = radeon_agp_init(rdev); 407 if (r) { 408 radeon_agp_disable(rdev); 409 } 410 } 411 /* initialize memory controller */ 412 r300_mc_init(rdev); 413 r420_debugfs(rdev); 414 /* Fence driver */ 415 r = radeon_fence_driver_init(rdev); 416 if (r) { 417 return r; 418 } 419 /* Memory manager */ 420 r = radeon_bo_init(rdev); 421 if (r) { 422 return r; 423 } 424 if (rdev->family == CHIP_R420) 425 r100_enable_bm(rdev); 426 427 if (rdev->flags & RADEON_IS_PCIE) { 428 r = rv370_pcie_gart_init(rdev); 429 if (r) 430 return r; 431 } 432 if (rdev->flags & RADEON_IS_PCI) { 433 r = r100_pci_gart_init(rdev); 434 if (r) 435 return r; 436 } 437 r420_set_reg_safe(rdev); 438 439 rdev->accel_working = true; 440 r = r420_startup(rdev); 441 if (r) { 442 /* Somethings want wront with the accel init stop accel */ 443 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 444 r100_cp_fini(rdev); 445 radeon_wb_fini(rdev); 446 radeon_ib_pool_fini(rdev); 447 radeon_irq_kms_fini(rdev); 448 if (rdev->flags & RADEON_IS_PCIE) 449 rv370_pcie_gart_fini(rdev); 450 if (rdev->flags & RADEON_IS_PCI) 451 r100_pci_gart_fini(rdev); 452 radeon_agp_fini(rdev); 453 rdev->accel_working = false; 454 } 455 return 0; 456 } 457 458 /* 459 * Debugfs info 460 */ 461 #if defined(CONFIG_DEBUG_FS) 462 static int r420_debugfs_pipes_info(struct seq_file *m, void *data) 463 { 464 struct drm_info_node *node = (struct drm_info_node *) m->private; 465 struct drm_device *dev = node->minor->dev; 466 struct radeon_device *rdev = dev->dev_private; 467 uint32_t tmp; 468 469 tmp = RREG32(R400_GB_PIPE_SELECT); 470 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); 471 tmp = RREG32(R300_GB_TILE_CONFIG); 472 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); 473 tmp = RREG32(R300_DST_PIPE_CONFIG); 474 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); 475 return 0; 476 } 477 478 static struct drm_info_list r420_pipes_info_list[] = { 479 {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL}, 480 }; 481 #endif 482 483 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) 484 { 485 #if defined(CONFIG_DEBUG_FS) 486 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); 487 #else 488 return 0; 489 #endif 490 } 491