1 /* $OpenBSD: r300.c,v 1.4 2014/04/07 06:43:11 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/drm/drm.h> 31 #include <dev/pci/drm/drm_crtc_helper.h> 32 #include "radeon_reg.h" 33 #include "radeon.h" 34 #include "radeon_asic.h" 35 #include <dev/pci/drm/radeon_drm.h> 36 #include "r100_track.h" 37 #include "r300d.h" 38 #include "rv350d.h" 39 #include "r300_reg_safe.h" 40 41 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 42 * 43 * GPU Errata: 44 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL 45 * using MMIO to flush host path read cache, this lead to HARDLOCKUP. 46 * However, scheduling such write to the ring seems harmless, i suspect 47 * the CP read collide with the flush somehow, or maybe the MC, hard to 48 * tell. (Jerome Glisse) 49 */ 50 51 /* 52 * rv370,rv380 PCIE GART 53 */ 54 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); 55 56 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev) 57 { 58 uint32_t tmp; 59 int i; 60 61 /* Workaround HW bug do flush 2 times */ 62 for (i = 0; i < 2; i++) { 63 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 64 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB); 65 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 66 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 67 } 68 DRM_MEMORYBARRIER(); 69 } 70 71 #define R300_PTE_WRITEABLE (1 << 2) 72 #define R300_PTE_READABLE (1 << 3) 73 74 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 75 { 76 volatile uint32_t *ptr = rdev->gart.ptr; 77 78 if (i < 0 || i > rdev->gart.num_gpu_pages) { 79 return -EINVAL; 80 } 81 addr = (lower_32_bits(addr) >> 8) | 82 ((upper_32_bits(addr) & 0xff) << 24) | 83 R300_PTE_WRITEABLE | R300_PTE_READABLE; 84 /* on x86 we want this to be CPU endian, on powerpc 85 * on powerpc without HW swappers, it'll get swapped on way 86 * into VRAM - so no need for cpu_to_le32 on VRAM tables */ 87 ptr += i; 88 *ptr = (uint32_t)addr; 89 return 0; 90 } 91 92 int rv370_pcie_gart_init(struct radeon_device *rdev) 93 { 94 int r; 95 96 if (rdev->gart.robj) { 97 WARN(1, "RV370 PCIE GART already initialized\n"); 98 return 0; 99 } 100 /* Initialize common gart structure */ 101 r = radeon_gart_init(rdev); 102 if (r) 103 return r; 104 r = rv370_debugfs_pcie_gart_info_init(rdev); 105 if (r) 106 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); 107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 108 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 109 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 110 return radeon_gart_table_vram_alloc(rdev); 111 } 112 113 int rv370_pcie_gart_enable(struct radeon_device *rdev) 114 { 115 uint32_t table_addr; 116 uint32_t tmp; 117 int r; 118 119 if (rdev->gart.robj == NULL) { 120 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 121 return -EINVAL; 122 } 123 r = radeon_gart_table_vram_pin(rdev); 124 if (r) 125 return r; 126 radeon_gart_restore(rdev); 127 /* discard memory request outside of configured range */ 128 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 129 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 130 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); 131 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; 132 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 133 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 134 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 135 table_addr = rdev->gart.table_addr; 136 WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr); 137 /* FIXME: setup default page */ 138 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); 139 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0); 140 /* Clear error */ 141 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); 142 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 143 tmp |= RADEON_PCIE_TX_GART_EN; 144 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 145 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 146 rv370_pcie_gart_tlb_flush(rdev); 147 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 148 (unsigned)(rdev->mc.gtt_size >> 20), 149 (unsigned long long)table_addr); 150 rdev->gart.ready = true; 151 return 0; 152 } 153 154 void rv370_pcie_gart_disable(struct radeon_device *rdev) 155 { 156 u32 tmp; 157 158 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); 159 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); 160 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 161 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 162 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 163 tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 164 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN); 165 radeon_gart_table_vram_unpin(rdev); 166 } 167 168 void rv370_pcie_gart_fini(struct radeon_device *rdev) 169 { 170 radeon_gart_fini(rdev); 171 rv370_pcie_gart_disable(rdev); 172 radeon_gart_table_vram_free(rdev); 173 } 174 175 void r300_fence_ring_emit(struct radeon_device *rdev, 176 struct radeon_fence *fence) 177 { 178 struct radeon_ring *ring = &rdev->ring[fence->ring]; 179 180 /* Who ever call radeon_fence_emit should call ring_lock and ask 181 * for enough space (today caller are ib schedule and buffer move) */ 182 /* Write SC register so SC & US assert idle */ 183 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0)); 184 radeon_ring_write(ring, 0); 185 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0)); 186 radeon_ring_write(ring, 0); 187 /* Flush 3D cache */ 188 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 189 radeon_ring_write(ring, R300_RB3D_DC_FLUSH); 190 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 191 radeon_ring_write(ring, R300_ZC_FLUSH); 192 /* Wait until IDLE & CLEAN */ 193 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 194 radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN | 195 RADEON_WAIT_2D_IDLECLEAN | 196 RADEON_WAIT_DMA_GUI_IDLE)); 197 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 198 radeon_ring_write(ring, rdev->config.r300.hdp_cntl | 199 RADEON_HDP_READ_BUFFER_INVALIDATE); 200 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 201 radeon_ring_write(ring, rdev->config.r300.hdp_cntl); 202 /* Emit fence sequence & fire IRQ */ 203 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 204 radeon_ring_write(ring, fence->seq); 205 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 206 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 207 } 208 209 void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 210 { 211 unsigned gb_tile_config; 212 int r; 213 214 /* Sub pixel 1/12 so we can have 4K rendering according to doc */ 215 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 216 switch(rdev->num_gb_pipes) { 217 case 2: 218 gb_tile_config |= R300_PIPE_COUNT_R300; 219 break; 220 case 3: 221 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 222 break; 223 case 4: 224 gb_tile_config |= R300_PIPE_COUNT_R420; 225 break; 226 case 1: 227 default: 228 gb_tile_config |= R300_PIPE_COUNT_RV350; 229 break; 230 } 231 232 r = radeon_ring_lock(rdev, ring, 64); 233 if (r) { 234 return; 235 } 236 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 237 radeon_ring_write(ring, 238 RADEON_ISYNC_ANY2D_IDLE3D | 239 RADEON_ISYNC_ANY3D_IDLE2D | 240 RADEON_ISYNC_WAIT_IDLEGUI | 241 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 242 radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0)); 243 radeon_ring_write(ring, gb_tile_config); 244 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 245 radeon_ring_write(ring, 246 RADEON_WAIT_2D_IDLECLEAN | 247 RADEON_WAIT_3D_IDLECLEAN); 248 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)); 249 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG); 250 radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0)); 251 radeon_ring_write(ring, 0); 252 radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0)); 253 radeon_ring_write(ring, 0); 254 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 255 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 256 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 257 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 258 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 259 radeon_ring_write(ring, 260 RADEON_WAIT_2D_IDLECLEAN | 261 RADEON_WAIT_3D_IDLECLEAN); 262 radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0)); 263 radeon_ring_write(ring, 0); 264 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 265 radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 266 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 267 radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE); 268 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0)); 269 radeon_ring_write(ring, 270 ((6 << R300_MS_X0_SHIFT) | 271 (6 << R300_MS_Y0_SHIFT) | 272 (6 << R300_MS_X1_SHIFT) | 273 (6 << R300_MS_Y1_SHIFT) | 274 (6 << R300_MS_X2_SHIFT) | 275 (6 << R300_MS_Y2_SHIFT) | 276 (6 << R300_MSBD0_Y_SHIFT) | 277 (6 << R300_MSBD0_X_SHIFT))); 278 radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0)); 279 radeon_ring_write(ring, 280 ((6 << R300_MS_X3_SHIFT) | 281 (6 << R300_MS_Y3_SHIFT) | 282 (6 << R300_MS_X4_SHIFT) | 283 (6 << R300_MS_Y4_SHIFT) | 284 (6 << R300_MS_X5_SHIFT) | 285 (6 << R300_MS_Y5_SHIFT) | 286 (6 << R300_MSBD1_SHIFT))); 287 radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0)); 288 radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 289 radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0)); 290 radeon_ring_write(ring, 291 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 292 radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0)); 293 radeon_ring_write(ring, 294 R300_GEOMETRY_ROUND_NEAREST | 295 R300_COLOR_ROUND_NEAREST); 296 radeon_ring_unlock_commit(rdev, ring); 297 } 298 299 static void r300_errata(struct radeon_device *rdev) 300 { 301 rdev->pll_errata = 0; 302 303 if (rdev->family == CHIP_R300 && 304 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { 305 rdev->pll_errata |= CHIP_ERRATA_R300_CG; 306 } 307 } 308 309 int r300_mc_wait_for_idle(struct radeon_device *rdev) 310 { 311 unsigned i; 312 uint32_t tmp; 313 314 for (i = 0; i < rdev->usec_timeout; i++) { 315 /* read MC_STATUS */ 316 tmp = RREG32(RADEON_MC_STATUS); 317 if (tmp & R300_MC_IDLE) { 318 return 0; 319 } 320 udelay(1); 321 } 322 return -1; 323 } 324 325 static void r300_gpu_init(struct radeon_device *rdev) 326 { 327 uint32_t gb_tile_config, tmp; 328 329 if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) || 330 (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) { 331 /* r300,r350 */ 332 rdev->num_gb_pipes = 2; 333 } else { 334 /* rv350,rv370,rv380,r300 AD, r350 AH */ 335 rdev->num_gb_pipes = 1; 336 } 337 rdev->num_z_pipes = 1; 338 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 339 switch (rdev->num_gb_pipes) { 340 case 2: 341 gb_tile_config |= R300_PIPE_COUNT_R300; 342 break; 343 case 3: 344 gb_tile_config |= R300_PIPE_COUNT_R420_3P; 345 break; 346 case 4: 347 gb_tile_config |= R300_PIPE_COUNT_R420; 348 break; 349 default: 350 case 1: 351 gb_tile_config |= R300_PIPE_COUNT_RV350; 352 break; 353 } 354 WREG32(R300_GB_TILE_CONFIG, gb_tile_config); 355 356 if (r100_gui_wait_for_idle(rdev)) { 357 DRM_ERROR("Failed to wait GUI idle while " 358 "programming pipes. Bad things might happen.\n"); 359 } 360 361 tmp = RREG32(R300_DST_PIPE_CONFIG); 362 WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG); 363 364 WREG32(R300_RB2D_DSTCACHE_MODE, 365 R300_DC_AUTOFLUSH_ENABLE | 366 R300_DC_DC_DISABLE_IGNORE_PE); 367 368 if (r100_gui_wait_for_idle(rdev)) { 369 DRM_ERROR("Failed to wait GUI idle while " 370 "programming pipes. Bad things might happen.\n"); 371 } 372 if (r300_mc_wait_for_idle(rdev)) { 373 DRM_ERROR("Failed to wait MC idle while " 374 "programming pipes. Bad things might happen.\n"); 375 } 376 #ifdef DRMDEBUG 377 DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n", 378 rdev->num_gb_pipes, rdev->num_z_pipes); 379 #endif 380 } 381 382 int r300_asic_reset(struct radeon_device *rdev) 383 { 384 struct r100_mc_save save; 385 u32 status, tmp; 386 int ret = 0; 387 388 status = RREG32(R_000E40_RBBM_STATUS); 389 if (!G_000E40_GUI_ACTIVE(status)) { 390 return 0; 391 } 392 r100_mc_stop(rdev, &save); 393 status = RREG32(R_000E40_RBBM_STATUS); 394 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 395 /* stop CP */ 396 WREG32(RADEON_CP_CSQ_CNTL, 0); 397 tmp = RREG32(RADEON_CP_RB_CNTL); 398 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 399 WREG32(RADEON_CP_RB_RPTR_WR, 0); 400 WREG32(RADEON_CP_RB_WPTR, 0); 401 WREG32(RADEON_CP_RB_CNTL, tmp); 402 /* save PCI state */ 403 #ifdef notyet 404 pci_save_state(rdev->pdev); 405 #endif 406 /* disable bus mastering */ 407 r100_bm_disable(rdev); 408 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 409 S_0000F0_SOFT_RESET_GA(1)); 410 RREG32(R_0000F0_RBBM_SOFT_RESET); 411 mdelay(500); 412 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 413 mdelay(1); 414 status = RREG32(R_000E40_RBBM_STATUS); 415 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 416 /* resetting the CP seems to be problematic sometimes it end up 417 * hard locking the computer, but it's necessary for successful 418 * reset more test & playing is needed on R3XX/R4XX to find a 419 * reliable (if any solution) 420 */ 421 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 422 RREG32(R_0000F0_RBBM_SOFT_RESET); 423 mdelay(500); 424 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 425 mdelay(1); 426 status = RREG32(R_000E40_RBBM_STATUS); 427 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 428 /* restore PCI & busmastering */ 429 #ifdef notyet 430 pci_restore_state(rdev->pdev); 431 #endif 432 r100_enable_bm(rdev); 433 /* Check if GPU is idle */ 434 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 435 dev_err(rdev->dev, "failed to reset GPU\n"); 436 ret = -1; 437 } else 438 dev_info(rdev->dev, "GPU reset succeed\n"); 439 r100_mc_resume(rdev, &save); 440 return ret; 441 } 442 443 /* 444 * r300,r350,rv350,rv380 VRAM info 445 */ 446 void r300_mc_init(struct radeon_device *rdev) 447 { 448 u64 base; 449 u32 tmp; 450 451 /* DDR for all card after R300 & IGP */ 452 rdev->mc.vram_is_ddr = true; 453 tmp = RREG32(RADEON_MEM_CNTL); 454 tmp &= R300_MEM_NUM_CHANNELS_MASK; 455 switch (tmp) { 456 case 0: rdev->mc.vram_width = 64; break; 457 case 1: rdev->mc.vram_width = 128; break; 458 case 2: rdev->mc.vram_width = 256; break; 459 default: rdev->mc.vram_width = 128; break; 460 } 461 r100_vram_init_sizes(rdev); 462 base = rdev->mc.aper_base; 463 if (rdev->flags & RADEON_IS_IGP) 464 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 465 radeon_vram_location(rdev, &rdev->mc, base); 466 rdev->mc.gtt_base_align = 0; 467 if (!(rdev->flags & RADEON_IS_AGP)) 468 radeon_gtt_location(rdev, &rdev->mc); 469 radeon_update_bandwidth_info(rdev); 470 } 471 472 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) 473 { 474 uint32_t link_width_cntl, mask; 475 476 if (rdev->flags & RADEON_IS_IGP) 477 return; 478 479 if (!(rdev->flags & RADEON_IS_PCIE)) 480 return; 481 482 /* FIXME wait for idle */ 483 484 switch (lanes) { 485 case 0: 486 mask = RADEON_PCIE_LC_LINK_WIDTH_X0; 487 break; 488 case 1: 489 mask = RADEON_PCIE_LC_LINK_WIDTH_X1; 490 break; 491 case 2: 492 mask = RADEON_PCIE_LC_LINK_WIDTH_X2; 493 break; 494 case 4: 495 mask = RADEON_PCIE_LC_LINK_WIDTH_X4; 496 break; 497 case 8: 498 mask = RADEON_PCIE_LC_LINK_WIDTH_X8; 499 break; 500 case 12: 501 mask = RADEON_PCIE_LC_LINK_WIDTH_X12; 502 break; 503 case 16: 504 default: 505 mask = RADEON_PCIE_LC_LINK_WIDTH_X16; 506 break; 507 } 508 509 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 510 511 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) == 512 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT)) 513 return; 514 515 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK | 516 RADEON_PCIE_LC_RECONFIG_NOW | 517 RADEON_PCIE_LC_RECONFIG_LATER | 518 RADEON_PCIE_LC_SHORT_RECONFIG_EN); 519 link_width_cntl |= mask; 520 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 521 WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl | 522 RADEON_PCIE_LC_RECONFIG_NOW)); 523 524 /* wait for lane set to complete */ 525 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 526 while (link_width_cntl == 0xffffffff) 527 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 528 529 } 530 531 int rv370_get_pcie_lanes(struct radeon_device *rdev) 532 { 533 u32 link_width_cntl; 534 535 if (rdev->flags & RADEON_IS_IGP) 536 return 0; 537 538 if (!(rdev->flags & RADEON_IS_PCIE)) 539 return 0; 540 541 /* FIXME wait for idle */ 542 543 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL); 544 545 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) { 546 case RADEON_PCIE_LC_LINK_WIDTH_X0: 547 return 0; 548 case RADEON_PCIE_LC_LINK_WIDTH_X1: 549 return 1; 550 case RADEON_PCIE_LC_LINK_WIDTH_X2: 551 return 2; 552 case RADEON_PCIE_LC_LINK_WIDTH_X4: 553 return 4; 554 case RADEON_PCIE_LC_LINK_WIDTH_X8: 555 return 8; 556 case RADEON_PCIE_LC_LINK_WIDTH_X16: 557 default: 558 return 16; 559 } 560 } 561 562 #if defined(CONFIG_DEBUG_FS) 563 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data) 564 { 565 struct drm_info_node *node = (struct drm_info_node *) m->private; 566 struct drm_device *dev = node->minor->dev; 567 struct radeon_device *rdev = dev->dev_private; 568 uint32_t tmp; 569 570 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); 571 seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp); 572 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); 573 seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp); 574 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); 575 seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp); 576 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); 577 seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp); 578 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); 579 seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp); 580 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); 581 seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp); 582 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR); 583 seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp); 584 return 0; 585 } 586 587 static struct drm_info_list rv370_pcie_gart_info_list[] = { 588 {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL}, 589 }; 590 #endif 591 592 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev) 593 { 594 #if defined(CONFIG_DEBUG_FS) 595 return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1); 596 #else 597 return 0; 598 #endif 599 } 600 601 static int r300_packet0_check(struct radeon_cs_parser *p, 602 struct radeon_cs_packet *pkt, 603 unsigned idx, unsigned reg) 604 { 605 struct radeon_cs_reloc *reloc; 606 struct r100_cs_track *track; 607 volatile uint32_t *ib; 608 uint32_t tmp, tile_flags = 0; 609 unsigned i; 610 int r; 611 u32 idx_value; 612 613 ib = p->ib.ptr; 614 track = (struct r100_cs_track *)p->track; 615 idx_value = radeon_get_ib_value(p, idx); 616 617 switch(reg) { 618 case AVIVO_D1MODE_VLINE_START_END: 619 case RADEON_CRTC_GUI_TRIG_VLINE: 620 r = r100_cs_packet_parse_vline(p); 621 if (r) { 622 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 623 idx, reg); 624 r100_cs_dump_packet(p, pkt); 625 return r; 626 } 627 break; 628 case RADEON_DST_PITCH_OFFSET: 629 case RADEON_SRC_PITCH_OFFSET: 630 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 631 if (r) 632 return r; 633 break; 634 case R300_RB3D_COLOROFFSET0: 635 case R300_RB3D_COLOROFFSET1: 636 case R300_RB3D_COLOROFFSET2: 637 case R300_RB3D_COLOROFFSET3: 638 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 639 r = r100_cs_packet_next_reloc(p, &reloc); 640 if (r) { 641 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 642 idx, reg); 643 r100_cs_dump_packet(p, pkt); 644 return r; 645 } 646 track->cb[i].robj = reloc->robj; 647 track->cb[i].offset = idx_value; 648 track->cb_dirty = true; 649 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 650 break; 651 case R300_ZB_DEPTHOFFSET: 652 r = r100_cs_packet_next_reloc(p, &reloc); 653 if (r) { 654 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 655 idx, reg); 656 r100_cs_dump_packet(p, pkt); 657 return r; 658 } 659 track->zb.robj = reloc->robj; 660 track->zb.offset = idx_value; 661 track->zb_dirty = true; 662 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 663 break; 664 case R300_TX_OFFSET_0: 665 case R300_TX_OFFSET_0+4: 666 case R300_TX_OFFSET_0+8: 667 case R300_TX_OFFSET_0+12: 668 case R300_TX_OFFSET_0+16: 669 case R300_TX_OFFSET_0+20: 670 case R300_TX_OFFSET_0+24: 671 case R300_TX_OFFSET_0+28: 672 case R300_TX_OFFSET_0+32: 673 case R300_TX_OFFSET_0+36: 674 case R300_TX_OFFSET_0+40: 675 case R300_TX_OFFSET_0+44: 676 case R300_TX_OFFSET_0+48: 677 case R300_TX_OFFSET_0+52: 678 case R300_TX_OFFSET_0+56: 679 case R300_TX_OFFSET_0+60: 680 i = (reg - R300_TX_OFFSET_0) >> 2; 681 r = r100_cs_packet_next_reloc(p, &reloc); 682 if (r) { 683 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 684 idx, reg); 685 r100_cs_dump_packet(p, pkt); 686 return r; 687 } 688 689 if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) { 690 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ 691 ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); 692 } else { 693 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 694 tile_flags |= R300_TXO_MACRO_TILE; 695 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 696 tile_flags |= R300_TXO_MICRO_TILE; 697 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 698 tile_flags |= R300_TXO_MICRO_TILE_SQUARE; 699 700 tmp = idx_value + ((u32)reloc->lobj.gpu_offset); 701 tmp |= tile_flags; 702 ib[idx] = tmp; 703 } 704 track->textures[i].robj = reloc->robj; 705 track->tex_dirty = true; 706 break; 707 /* Tracked registers */ 708 case 0x2084: 709 /* VAP_VF_CNTL */ 710 track->vap_vf_cntl = idx_value; 711 break; 712 case 0x20B4: 713 /* VAP_VTX_SIZE */ 714 track->vtx_size = idx_value & 0x7F; 715 break; 716 case 0x2134: 717 /* VAP_VF_MAX_VTX_INDX */ 718 track->max_indx = idx_value & 0x00FFFFFFUL; 719 break; 720 case 0x2088: 721 /* VAP_ALT_NUM_VERTICES - only valid on r500 */ 722 if (p->rdev->family < CHIP_RV515) 723 goto fail; 724 track->vap_alt_nverts = idx_value & 0xFFFFFF; 725 break; 726 case 0x43E4: 727 /* SC_SCISSOR1 */ 728 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1; 729 if (p->rdev->family < CHIP_RV515) { 730 track->maxy -= 1440; 731 } 732 track->cb_dirty = true; 733 track->zb_dirty = true; 734 break; 735 case 0x4E00: 736 /* RB3D_CCTL */ 737 if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */ 738 p->rdev->cmask_filp != p->filp) { 739 DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n"); 740 return -EINVAL; 741 } 742 track->num_cb = ((idx_value >> 5) & 0x3) + 1; 743 track->cb_dirty = true; 744 break; 745 case 0x4E38: 746 case 0x4E3C: 747 case 0x4E40: 748 case 0x4E44: 749 /* RB3D_COLORPITCH0 */ 750 /* RB3D_COLORPITCH1 */ 751 /* RB3D_COLORPITCH2 */ 752 /* RB3D_COLORPITCH3 */ 753 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 754 r = r100_cs_packet_next_reloc(p, &reloc); 755 if (r) { 756 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 757 idx, reg); 758 r100_cs_dump_packet(p, pkt); 759 return r; 760 } 761 762 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 763 tile_flags |= R300_COLOR_TILE_ENABLE; 764 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 765 tile_flags |= R300_COLOR_MICROTILE_ENABLE; 766 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 767 tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE; 768 769 tmp = idx_value & ~(0x7 << 16); 770 tmp |= tile_flags; 771 ib[idx] = tmp; 772 } 773 i = (reg - 0x4E38) >> 2; 774 track->cb[i].pitch = idx_value & 0x3FFE; 775 switch (((idx_value >> 21) & 0xF)) { 776 case 9: 777 case 11: 778 case 12: 779 track->cb[i].cpp = 1; 780 break; 781 case 3: 782 case 4: 783 case 13: 784 case 15: 785 track->cb[i].cpp = 2; 786 break; 787 case 5: 788 if (p->rdev->family < CHIP_RV515) { 789 DRM_ERROR("Invalid color buffer format (%d)!\n", 790 ((idx_value >> 21) & 0xF)); 791 return -EINVAL; 792 } 793 /* Pass through. */ 794 case 6: 795 track->cb[i].cpp = 4; 796 break; 797 case 10: 798 track->cb[i].cpp = 8; 799 break; 800 case 7: 801 track->cb[i].cpp = 16; 802 break; 803 default: 804 DRM_ERROR("Invalid color buffer format (%d) !\n", 805 ((idx_value >> 21) & 0xF)); 806 return -EINVAL; 807 } 808 track->cb_dirty = true; 809 break; 810 case 0x4F00: 811 /* ZB_CNTL */ 812 if (idx_value & 2) { 813 track->z_enabled = true; 814 } else { 815 track->z_enabled = false; 816 } 817 track->zb_dirty = true; 818 break; 819 case 0x4F10: 820 /* ZB_FORMAT */ 821 switch ((idx_value & 0xF)) { 822 case 0: 823 case 1: 824 track->zb.cpp = 2; 825 break; 826 case 2: 827 track->zb.cpp = 4; 828 break; 829 default: 830 DRM_ERROR("Invalid z buffer format (%d) !\n", 831 (idx_value & 0xF)); 832 return -EINVAL; 833 } 834 track->zb_dirty = true; 835 break; 836 case 0x4F24: 837 /* ZB_DEPTHPITCH */ 838 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 839 r = r100_cs_packet_next_reloc(p, &reloc); 840 if (r) { 841 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 842 idx, reg); 843 r100_cs_dump_packet(p, pkt); 844 return r; 845 } 846 847 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 848 tile_flags |= R300_DEPTHMACROTILE_ENABLE; 849 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 850 tile_flags |= R300_DEPTHMICROTILE_TILED; 851 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) 852 tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE; 853 854 tmp = idx_value & ~(0x7 << 16); 855 tmp |= tile_flags; 856 ib[idx] = tmp; 857 } 858 track->zb.pitch = idx_value & 0x3FFC; 859 track->zb_dirty = true; 860 break; 861 case 0x4104: 862 /* TX_ENABLE */ 863 for (i = 0; i < 16; i++) { 864 bool enabled; 865 866 enabled = !!(idx_value & (1 << i)); 867 track->textures[i].enabled = enabled; 868 } 869 track->tex_dirty = true; 870 break; 871 case 0x44C0: 872 case 0x44C4: 873 case 0x44C8: 874 case 0x44CC: 875 case 0x44D0: 876 case 0x44D4: 877 case 0x44D8: 878 case 0x44DC: 879 case 0x44E0: 880 case 0x44E4: 881 case 0x44E8: 882 case 0x44EC: 883 case 0x44F0: 884 case 0x44F4: 885 case 0x44F8: 886 case 0x44FC: 887 /* TX_FORMAT1_[0-15] */ 888 i = (reg - 0x44C0) >> 2; 889 tmp = (idx_value >> 25) & 0x3; 890 track->textures[i].tex_coord_type = tmp; 891 switch ((idx_value & 0x1F)) { 892 case R300_TX_FORMAT_X8: 893 case R300_TX_FORMAT_Y4X4: 894 case R300_TX_FORMAT_Z3Y3X2: 895 track->textures[i].cpp = 1; 896 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 897 break; 898 case R300_TX_FORMAT_X16: 899 case R300_TX_FORMAT_FL_I16: 900 case R300_TX_FORMAT_Y8X8: 901 case R300_TX_FORMAT_Z5Y6X5: 902 case R300_TX_FORMAT_Z6Y5X5: 903 case R300_TX_FORMAT_W4Z4Y4X4: 904 case R300_TX_FORMAT_W1Z5Y5X5: 905 case R300_TX_FORMAT_D3DMFT_CxV8U8: 906 case R300_TX_FORMAT_B8G8_B8G8: 907 case R300_TX_FORMAT_G8R8_G8B8: 908 track->textures[i].cpp = 2; 909 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 910 break; 911 case R300_TX_FORMAT_Y16X16: 912 case R300_TX_FORMAT_FL_I16A16: 913 case R300_TX_FORMAT_Z11Y11X10: 914 case R300_TX_FORMAT_Z10Y11X11: 915 case R300_TX_FORMAT_W8Z8Y8X8: 916 case R300_TX_FORMAT_W2Z10Y10X10: 917 case 0x17: 918 case R300_TX_FORMAT_FL_I32: 919 case 0x1e: 920 track->textures[i].cpp = 4; 921 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 922 break; 923 case R300_TX_FORMAT_W16Z16Y16X16: 924 case R300_TX_FORMAT_FL_R16G16B16A16: 925 case R300_TX_FORMAT_FL_I32A32: 926 track->textures[i].cpp = 8; 927 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 928 break; 929 case R300_TX_FORMAT_FL_R32G32B32A32: 930 track->textures[i].cpp = 16; 931 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 932 break; 933 case R300_TX_FORMAT_DXT1: 934 track->textures[i].cpp = 1; 935 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 936 break; 937 case R300_TX_FORMAT_ATI2N: 938 if (p->rdev->family < CHIP_R420) { 939 DRM_ERROR("Invalid texture format %u\n", 940 (idx_value & 0x1F)); 941 return -EINVAL; 942 } 943 /* The same rules apply as for DXT3/5. */ 944 /* Pass through. */ 945 case R300_TX_FORMAT_DXT3: 946 case R300_TX_FORMAT_DXT5: 947 track->textures[i].cpp = 1; 948 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 949 break; 950 default: 951 DRM_ERROR("Invalid texture format %u\n", 952 (idx_value & 0x1F)); 953 return -EINVAL; 954 } 955 track->tex_dirty = true; 956 break; 957 case 0x4400: 958 case 0x4404: 959 case 0x4408: 960 case 0x440C: 961 case 0x4410: 962 case 0x4414: 963 case 0x4418: 964 case 0x441C: 965 case 0x4420: 966 case 0x4424: 967 case 0x4428: 968 case 0x442C: 969 case 0x4430: 970 case 0x4434: 971 case 0x4438: 972 case 0x443C: 973 /* TX_FILTER0_[0-15] */ 974 i = (reg - 0x4400) >> 2; 975 tmp = idx_value & 0x7; 976 if (tmp == 2 || tmp == 4 || tmp == 6) { 977 track->textures[i].roundup_w = false; 978 } 979 tmp = (idx_value >> 3) & 0x7; 980 if (tmp == 2 || tmp == 4 || tmp == 6) { 981 track->textures[i].roundup_h = false; 982 } 983 track->tex_dirty = true; 984 break; 985 case 0x4500: 986 case 0x4504: 987 case 0x4508: 988 case 0x450C: 989 case 0x4510: 990 case 0x4514: 991 case 0x4518: 992 case 0x451C: 993 case 0x4520: 994 case 0x4524: 995 case 0x4528: 996 case 0x452C: 997 case 0x4530: 998 case 0x4534: 999 case 0x4538: 1000 case 0x453C: 1001 /* TX_FORMAT2_[0-15] */ 1002 i = (reg - 0x4500) >> 2; 1003 tmp = idx_value & 0x3FFF; 1004 track->textures[i].pitch = tmp + 1; 1005 if (p->rdev->family >= CHIP_RV515) { 1006 tmp = ((idx_value >> 15) & 1) << 11; 1007 track->textures[i].width_11 = tmp; 1008 tmp = ((idx_value >> 16) & 1) << 11; 1009 track->textures[i].height_11 = tmp; 1010 1011 /* ATI1N */ 1012 if (idx_value & (1 << 14)) { 1013 /* The same rules apply as for DXT1. */ 1014 track->textures[i].compress_format = 1015 R100_TRACK_COMP_DXT1; 1016 } 1017 } else if (idx_value & (1 << 14)) { 1018 DRM_ERROR("Forbidden bit TXFORMAT_MSB\n"); 1019 return -EINVAL; 1020 } 1021 track->tex_dirty = true; 1022 break; 1023 case 0x4480: 1024 case 0x4484: 1025 case 0x4488: 1026 case 0x448C: 1027 case 0x4490: 1028 case 0x4494: 1029 case 0x4498: 1030 case 0x449C: 1031 case 0x44A0: 1032 case 0x44A4: 1033 case 0x44A8: 1034 case 0x44AC: 1035 case 0x44B0: 1036 case 0x44B4: 1037 case 0x44B8: 1038 case 0x44BC: 1039 /* TX_FORMAT0_[0-15] */ 1040 i = (reg - 0x4480) >> 2; 1041 tmp = idx_value & 0x7FF; 1042 track->textures[i].width = tmp + 1; 1043 tmp = (idx_value >> 11) & 0x7FF; 1044 track->textures[i].height = tmp + 1; 1045 tmp = (idx_value >> 26) & 0xF; 1046 track->textures[i].num_levels = tmp; 1047 tmp = idx_value & (1 << 31); 1048 track->textures[i].use_pitch = !!tmp; 1049 tmp = (idx_value >> 22) & 0xF; 1050 track->textures[i].txdepth = tmp; 1051 track->tex_dirty = true; 1052 break; 1053 case R300_ZB_ZPASS_ADDR: 1054 r = r100_cs_packet_next_reloc(p, &reloc); 1055 if (r) { 1056 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1057 idx, reg); 1058 r100_cs_dump_packet(p, pkt); 1059 return r; 1060 } 1061 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1062 break; 1063 case 0x4e0c: 1064 /* RB3D_COLOR_CHANNEL_MASK */ 1065 track->color_channel_mask = idx_value; 1066 track->cb_dirty = true; 1067 break; 1068 case 0x43a4: 1069 /* SC_HYPERZ_EN */ 1070 /* r300c emits this register - we need to disable hyperz for it 1071 * without complaining */ 1072 if (p->rdev->hyperz_filp != p->filp) { 1073 if (idx_value & 0x1) 1074 ib[idx] = idx_value & ~1; 1075 } 1076 break; 1077 case 0x4f1c: 1078 /* ZB_BW_CNTL */ 1079 track->zb_cb_clear = !!(idx_value & (1 << 5)); 1080 track->cb_dirty = true; 1081 track->zb_dirty = true; 1082 if (p->rdev->hyperz_filp != p->filp) { 1083 if (idx_value & (R300_HIZ_ENABLE | 1084 R300_RD_COMP_ENABLE | 1085 R300_WR_COMP_ENABLE | 1086 R300_FAST_FILL_ENABLE)) 1087 goto fail; 1088 } 1089 break; 1090 case 0x4e04: 1091 /* RB3D_BLENDCNTL */ 1092 track->blend_read_enable = !!(idx_value & (1 << 2)); 1093 track->cb_dirty = true; 1094 break; 1095 case R300_RB3D_AARESOLVE_OFFSET: 1096 r = r100_cs_packet_next_reloc(p, &reloc); 1097 if (r) { 1098 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1099 idx, reg); 1100 r100_cs_dump_packet(p, pkt); 1101 return r; 1102 } 1103 track->aa.robj = reloc->robj; 1104 track->aa.offset = idx_value; 1105 track->aa_dirty = true; 1106 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1107 break; 1108 case R300_RB3D_AARESOLVE_PITCH: 1109 track->aa.pitch = idx_value & 0x3FFE; 1110 track->aa_dirty = true; 1111 break; 1112 case R300_RB3D_AARESOLVE_CTL: 1113 track->aaresolve = idx_value & 0x1; 1114 track->aa_dirty = true; 1115 break; 1116 case 0x4f30: /* ZB_MASK_OFFSET */ 1117 case 0x4f34: /* ZB_ZMASK_PITCH */ 1118 case 0x4f44: /* ZB_HIZ_OFFSET */ 1119 case 0x4f54: /* ZB_HIZ_PITCH */ 1120 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1121 goto fail; 1122 break; 1123 case 0x4028: 1124 if (idx_value && (p->rdev->hyperz_filp != p->filp)) 1125 goto fail; 1126 /* GB_Z_PEQ_CONFIG */ 1127 if (p->rdev->family >= CHIP_RV350) 1128 break; 1129 goto fail; 1130 break; 1131 case 0x4be8: 1132 /* valid register only on RV530 */ 1133 if (p->rdev->family == CHIP_RV530) 1134 break; 1135 /* fallthrough do not move */ 1136 default: 1137 goto fail; 1138 } 1139 return 0; 1140 fail: 1141 DRM_ERROR( "Forbidden register 0x%04X in cs at %d (val=%08x)\n", 1142 reg, idx, idx_value); 1143 return -EINVAL; 1144 } 1145 1146 static int r300_packet3_check(struct radeon_cs_parser *p, 1147 struct radeon_cs_packet *pkt) 1148 { 1149 struct radeon_cs_reloc *reloc; 1150 struct r100_cs_track *track; 1151 volatile uint32_t *ib; 1152 unsigned idx; 1153 int r; 1154 1155 ib = p->ib.ptr; 1156 idx = pkt->idx + 1; 1157 track = (struct r100_cs_track *)p->track; 1158 switch(pkt->opcode) { 1159 case PACKET3_3D_LOAD_VBPNTR: 1160 r = r100_packet3_load_vbpntr(p, pkt, idx); 1161 if (r) 1162 return r; 1163 break; 1164 case PACKET3_INDX_BUFFER: 1165 r = r100_cs_packet_next_reloc(p, &reloc); 1166 if (r) { 1167 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1168 r100_cs_dump_packet(p, pkt); 1169 return r; 1170 } 1171 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1172 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1173 if (r) { 1174 return r; 1175 } 1176 break; 1177 /* Draw packet */ 1178 case PACKET3_3D_DRAW_IMMD: 1179 /* Number of dwords is vtx_size * (num_vertices - 1) 1180 * PRIM_WALK must be equal to 3 vertex data in embedded 1181 * in cmd stream */ 1182 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 1183 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1184 return -EINVAL; 1185 } 1186 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1187 track->immd_dwords = pkt->count - 1; 1188 r = r100_cs_track_check(p->rdev, track); 1189 if (r) { 1190 return r; 1191 } 1192 break; 1193 case PACKET3_3D_DRAW_IMMD_2: 1194 /* Number of dwords is vtx_size * (num_vertices - 1) 1195 * PRIM_WALK must be equal to 3 vertex data in embedded 1196 * in cmd stream */ 1197 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 1198 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1199 return -EINVAL; 1200 } 1201 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1202 track->immd_dwords = pkt->count; 1203 r = r100_cs_track_check(p->rdev, track); 1204 if (r) { 1205 return r; 1206 } 1207 break; 1208 case PACKET3_3D_DRAW_VBUF: 1209 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1210 r = r100_cs_track_check(p->rdev, track); 1211 if (r) { 1212 return r; 1213 } 1214 break; 1215 case PACKET3_3D_DRAW_VBUF_2: 1216 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1217 r = r100_cs_track_check(p->rdev, track); 1218 if (r) { 1219 return r; 1220 } 1221 break; 1222 case PACKET3_3D_DRAW_INDX: 1223 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1224 r = r100_cs_track_check(p->rdev, track); 1225 if (r) { 1226 return r; 1227 } 1228 break; 1229 case PACKET3_3D_DRAW_INDX_2: 1230 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 1231 r = r100_cs_track_check(p->rdev, track); 1232 if (r) { 1233 return r; 1234 } 1235 break; 1236 case PACKET3_3D_CLEAR_HIZ: 1237 case PACKET3_3D_CLEAR_ZMASK: 1238 if (p->rdev->hyperz_filp != p->filp) 1239 return -EINVAL; 1240 break; 1241 case PACKET3_3D_CLEAR_CMASK: 1242 if (p->rdev->cmask_filp != p->filp) 1243 return -EINVAL; 1244 break; 1245 case PACKET3_NOP: 1246 break; 1247 default: 1248 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 1249 return -EINVAL; 1250 } 1251 return 0; 1252 } 1253 1254 int r300_cs_parse(struct radeon_cs_parser *p) 1255 { 1256 struct radeon_cs_packet pkt; 1257 struct r100_cs_track *track; 1258 int r; 1259 1260 track = kzalloc(sizeof(*track), GFP_KERNEL); 1261 if (track == NULL) 1262 return -ENOMEM; 1263 r100_cs_track_clear(p->rdev, track); 1264 p->track = track; 1265 do { 1266 r = r100_cs_packet_parse(p, &pkt, p->idx); 1267 if (r) { 1268 return r; 1269 } 1270 p->idx += pkt.count + 2; 1271 switch (pkt.type) { 1272 case PACKET_TYPE0: 1273 r = r100_cs_parse_packet0(p, &pkt, 1274 p->rdev->config.r300.reg_safe_bm, 1275 p->rdev->config.r300.reg_safe_bm_size, 1276 &r300_packet0_check); 1277 break; 1278 case PACKET_TYPE2: 1279 break; 1280 case PACKET_TYPE3: 1281 r = r300_packet3_check(p, &pkt); 1282 break; 1283 default: 1284 DRM_ERROR("Unknown packet type %d !\n", pkt.type); 1285 return -EINVAL; 1286 } 1287 if (r) { 1288 return r; 1289 } 1290 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 1291 return 0; 1292 } 1293 1294 void r300_set_reg_safe(struct radeon_device *rdev) 1295 { 1296 rdev->config.r300.reg_safe_bm = r300_reg_safe_bm; 1297 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm); 1298 } 1299 1300 void r300_mc_program(struct radeon_device *rdev) 1301 { 1302 struct r100_mc_save save; 1303 int r; 1304 1305 r = r100_debugfs_mc_info_init(rdev); 1306 if (r) { 1307 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 1308 } 1309 1310 /* Stops all mc clients */ 1311 r100_mc_stop(rdev, &save); 1312 if (rdev->flags & RADEON_IS_AGP) { 1313 WREG32(R_00014C_MC_AGP_LOCATION, 1314 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 1315 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 1316 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); 1317 WREG32(R_00015C_AGP_BASE_2, 1318 upper_32_bits(rdev->mc.agp_base) & 0xff); 1319 } else { 1320 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 1321 WREG32(R_000170_AGP_BASE, 0); 1322 WREG32(R_00015C_AGP_BASE_2, 0); 1323 } 1324 /* Wait for mc idle */ 1325 if (r300_mc_wait_for_idle(rdev)) 1326 DRM_INFO("Failed to wait MC idle before programming MC.\n"); 1327 /* Program MC, should be a 32bits limited address space */ 1328 WREG32(R_000148_MC_FB_LOCATION, 1329 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 1330 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 1331 r100_mc_resume(rdev, &save); 1332 } 1333 1334 void r300_clock_startup(struct radeon_device *rdev) 1335 { 1336 u32 tmp; 1337 1338 if (radeon_dynclks != -1 && radeon_dynclks) 1339 radeon_legacy_set_clock_gating(rdev, 1); 1340 /* We need to force on some of the block */ 1341 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 1342 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 1343 if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) 1344 tmp |= S_00000D_FORCE_VAP(1); 1345 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 1346 } 1347 1348 static int r300_startup(struct radeon_device *rdev) 1349 { 1350 int r; 1351 1352 /* set common regs */ 1353 r100_set_common_regs(rdev); 1354 /* program mc */ 1355 r300_mc_program(rdev); 1356 /* Resume clock */ 1357 r300_clock_startup(rdev); 1358 /* Initialize GPU configuration (# pipes, ...) */ 1359 r300_gpu_init(rdev); 1360 /* Initialize GART (initialize after TTM so we can allocate 1361 * memory through TTM but finalize after TTM) */ 1362 if (rdev->flags & RADEON_IS_PCIE) { 1363 r = rv370_pcie_gart_enable(rdev); 1364 if (r) 1365 return r; 1366 } 1367 1368 if (rdev->family == CHIP_R300 || 1369 rdev->family == CHIP_R350 || 1370 rdev->family == CHIP_RV350) 1371 r100_enable_bm(rdev); 1372 1373 if (rdev->flags & RADEON_IS_PCI) { 1374 r = r100_pci_gart_enable(rdev); 1375 if (r) 1376 return r; 1377 } 1378 1379 /* allocate wb buffer */ 1380 r = radeon_wb_init(rdev); 1381 if (r) 1382 return r; 1383 1384 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 1385 if (r) { 1386 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 1387 return r; 1388 } 1389 1390 /* Enable IRQ */ 1391 if (!rdev->irq.installed) { 1392 r = radeon_irq_kms_init(rdev); 1393 if (r) 1394 return r; 1395 } 1396 1397 r100_irq_set(rdev); 1398 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1399 /* 1M ring buffer */ 1400 r = r100_cp_init(rdev, 1024 * 1024); 1401 if (r) { 1402 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 1403 return r; 1404 } 1405 1406 r = radeon_ib_pool_init(rdev); 1407 if (r) { 1408 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1409 return r; 1410 } 1411 1412 return 0; 1413 } 1414 1415 int r300_resume(struct radeon_device *rdev) 1416 { 1417 int r; 1418 1419 /* Make sur GART are not working */ 1420 if (rdev->flags & RADEON_IS_PCIE) 1421 rv370_pcie_gart_disable(rdev); 1422 if (rdev->flags & RADEON_IS_PCI) 1423 r100_pci_gart_disable(rdev); 1424 /* Resume clock before doing reset */ 1425 r300_clock_startup(rdev); 1426 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1427 if (radeon_asic_reset(rdev)) { 1428 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1429 RREG32(R_000E40_RBBM_STATUS), 1430 RREG32(R_0007C0_CP_STAT)); 1431 } 1432 /* post */ 1433 radeon_combios_asic_init(rdev->ddev); 1434 /* Resume clock after posting */ 1435 r300_clock_startup(rdev); 1436 /* Initialize surface registers */ 1437 radeon_surface_init(rdev); 1438 1439 rdev->accel_working = true; 1440 r = r300_startup(rdev); 1441 if (r) { 1442 rdev->accel_working = false; 1443 } 1444 return r; 1445 } 1446 1447 int r300_suspend(struct radeon_device *rdev) 1448 { 1449 r100_cp_disable(rdev); 1450 radeon_wb_disable(rdev); 1451 r100_irq_disable(rdev); 1452 if (rdev->flags & RADEON_IS_PCIE) 1453 rv370_pcie_gart_disable(rdev); 1454 if (rdev->flags & RADEON_IS_PCI) 1455 r100_pci_gart_disable(rdev); 1456 return 0; 1457 } 1458 1459 void r300_fini(struct radeon_device *rdev) 1460 { 1461 r100_cp_fini(rdev); 1462 radeon_wb_fini(rdev); 1463 radeon_ib_pool_fini(rdev); 1464 radeon_gem_fini(rdev); 1465 if (rdev->flags & RADEON_IS_PCIE) 1466 rv370_pcie_gart_fini(rdev); 1467 if (rdev->flags & RADEON_IS_PCI) 1468 r100_pci_gart_fini(rdev); 1469 radeon_agp_fini(rdev); 1470 radeon_irq_kms_fini(rdev); 1471 radeon_fence_driver_fini(rdev); 1472 radeon_bo_fini(rdev); 1473 radeon_atombios_fini(rdev); 1474 kfree(rdev->bios); 1475 rdev->bios = NULL; 1476 } 1477 1478 int r300_init(struct radeon_device *rdev) 1479 { 1480 int r; 1481 1482 /* Disable VGA */ 1483 r100_vga_render_disable(rdev); 1484 /* Initialize scratch registers */ 1485 radeon_scratch_init(rdev); 1486 /* Initialize surface registers */ 1487 radeon_surface_init(rdev); 1488 /* TODO: disable VGA need to use VGA request */ 1489 /* restore some register to sane defaults */ 1490 r100_restore_sanity(rdev); 1491 /* BIOS*/ 1492 if (!radeon_get_bios(rdev)) { 1493 if (ASIC_IS_AVIVO(rdev)) 1494 return -EINVAL; 1495 } 1496 if (rdev->is_atom_bios) { 1497 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 1498 return -EINVAL; 1499 } else { 1500 r = radeon_combios_init(rdev); 1501 if (r) 1502 return r; 1503 } 1504 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 1505 if (radeon_asic_reset(rdev)) { 1506 dev_warn(rdev->dev, 1507 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 1508 RREG32(R_000E40_RBBM_STATUS), 1509 RREG32(R_0007C0_CP_STAT)); 1510 } 1511 /* check if cards are posted or not */ 1512 if (radeon_boot_test_post_card(rdev) == false) 1513 return -EINVAL; 1514 /* Set asic errata */ 1515 r300_errata(rdev); 1516 /* Initialize clocks */ 1517 radeon_get_clock_info(rdev->ddev); 1518 /* initialize AGP */ 1519 if (rdev->flags & RADEON_IS_AGP) { 1520 r = radeon_agp_init(rdev); 1521 if (r) { 1522 radeon_agp_disable(rdev); 1523 } 1524 } 1525 /* initialize memory controller */ 1526 r300_mc_init(rdev); 1527 /* Fence driver */ 1528 r = radeon_fence_driver_init(rdev); 1529 if (r) 1530 return r; 1531 /* Memory manager */ 1532 r = radeon_bo_init(rdev); 1533 if (r) 1534 return r; 1535 if (rdev->flags & RADEON_IS_PCIE) { 1536 r = rv370_pcie_gart_init(rdev); 1537 if (r) 1538 return r; 1539 } 1540 if (rdev->flags & RADEON_IS_PCI) { 1541 r = r100_pci_gart_init(rdev); 1542 if (r) 1543 return r; 1544 } 1545 r300_set_reg_safe(rdev); 1546 1547 rdev->accel_working = true; 1548 r = r300_startup(rdev); 1549 if (r) { 1550 /* Somethings want wront with the accel init stop accel */ 1551 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1552 r100_cp_fini(rdev); 1553 radeon_wb_fini(rdev); 1554 radeon_ib_pool_fini(rdev); 1555 radeon_irq_kms_fini(rdev); 1556 if (rdev->flags & RADEON_IS_PCIE) 1557 rv370_pcie_gart_fini(rdev); 1558 if (rdev->flags & RADEON_IS_PCI) 1559 r100_pci_gart_fini(rdev); 1560 radeon_agp_fini(rdev); 1561 rdev->accel_working = false; 1562 } 1563 return 0; 1564 } 1565