1 /* $OpenBSD: r100.c,v 1.15 2015/04/06 14:10:59 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Jerome Glisse. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 * Jerome Glisse 28 */ 29 #include <dev/pci/drm/drmP.h> 30 #include <dev/pci/drm/radeon_drm.h> 31 #include "radeon_reg.h" 32 #include "radeon.h" 33 #include "radeon_asic.h" 34 #include "r100d.h" 35 #include "rs100d.h" 36 #include "rv200d.h" 37 #include "rv250d.h" 38 #include "atom.h" 39 40 #include "r100_reg_safe.h" 41 #include "rn50_reg_safe.h" 42 43 /* Firmware Names */ 44 #define FIRMWARE_R100 "radeon-r100_cp" 45 #define FIRMWARE_R200 "radeon-r200_cp" 46 #define FIRMWARE_R300 "radeon-r300_cp" 47 #define FIRMWARE_R420 "radeon-r420_cp" 48 #define FIRMWARE_RS690 "radeon-rs690_cp" 49 #define FIRMWARE_RS600 "radeon-rs600_cp" 50 #define FIRMWARE_R520 "radeon-r520_cp" 51 52 MODULE_FIRMWARE(FIRMWARE_R100); 53 MODULE_FIRMWARE(FIRMWARE_R200); 54 MODULE_FIRMWARE(FIRMWARE_R300); 55 MODULE_FIRMWARE(FIRMWARE_R420); 56 MODULE_FIRMWARE(FIRMWARE_RS690); 57 MODULE_FIRMWARE(FIRMWARE_RS600); 58 MODULE_FIRMWARE(FIRMWARE_R520); 59 60 #include "r100_track.h" 61 62 /* This files gather functions specifics to: 63 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 64 * and others in some cases. 65 */ 66 67 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc) 68 { 69 if (crtc == 0) { 70 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR) 71 return true; 72 else 73 return false; 74 } else { 75 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 76 return true; 77 else 78 return false; 79 } 80 } 81 82 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc) 83 { 84 u32 vline1, vline2; 85 86 if (crtc == 0) { 87 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 88 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 89 } else { 90 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 91 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; 92 } 93 if (vline1 != vline2) 94 return true; 95 else 96 return false; 97 } 98 99 /** 100 * r100_wait_for_vblank - vblank wait asic callback. 101 * 102 * @rdev: radeon_device pointer 103 * @crtc: crtc to wait for vblank on 104 * 105 * Wait for vblank on the requested crtc (r1xx-r4xx). 106 */ 107 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 108 { 109 unsigned i = 0; 110 111 if (crtc >= rdev->num_crtc) 112 return; 113 114 if (crtc == 0) { 115 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN)) 116 return; 117 } else { 118 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN)) 119 return; 120 } 121 122 /* depending on when we hit vblank, we may be close to active; if so, 123 * wait for another frame. 124 */ 125 while (r100_is_in_vblank(rdev, crtc)) { 126 if (i++ % 100 == 0) { 127 if (!r100_is_counter_moving(rdev, crtc)) 128 break; 129 } 130 } 131 132 while (!r100_is_in_vblank(rdev, crtc)) { 133 if (i++ % 100 == 0) { 134 if (!r100_is_counter_moving(rdev, crtc)) 135 break; 136 } 137 } 138 } 139 140 /** 141 * r100_pre_page_flip - pre-pageflip callback. 142 * 143 * @rdev: radeon_device pointer 144 * @crtc: crtc to prepare for pageflip on 145 * 146 * Pre-pageflip callback (r1xx-r4xx). 147 * Enables the pageflip irq (vblank irq). 148 */ 149 void r100_pre_page_flip(struct radeon_device *rdev, int crtc) 150 { 151 /* enable the pflip int */ 152 radeon_irq_kms_pflip_irq_get(rdev, crtc); 153 } 154 155 /** 156 * r100_post_page_flip - pos-pageflip callback. 157 * 158 * @rdev: radeon_device pointer 159 * @crtc: crtc to cleanup pageflip on 160 * 161 * Post-pageflip callback (r1xx-r4xx). 162 * Disables the pageflip irq (vblank irq). 163 */ 164 void r100_post_page_flip(struct radeon_device *rdev, int crtc) 165 { 166 /* disable the pflip int */ 167 radeon_irq_kms_pflip_irq_put(rdev, crtc); 168 } 169 170 /** 171 * r100_page_flip - pageflip callback. 172 * 173 * @rdev: radeon_device pointer 174 * @crtc_id: crtc to cleanup pageflip on 175 * @crtc_base: new address of the crtc (GPU MC address) 176 * 177 * Does the actual pageflip (r1xx-r4xx). 178 * During vblank we take the crtc lock and wait for the update_pending 179 * bit to go high, when it does, we release the lock, and allow the 180 * double buffered update to take place. 181 * Returns the current update pending status. 182 */ 183 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 184 { 185 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; 186 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; 187 int i; 188 189 /* Lock the graphics update lock */ 190 /* update the scanout addresses */ 191 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 192 193 /* Wait for update_pending to go high. */ 194 for (i = 0; i < rdev->usec_timeout; i++) { 195 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) 196 break; 197 udelay(1); 198 } 199 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 200 201 /* Unlock the lock, so double-buffering can take place inside vblank */ 202 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK; 203 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp); 204 205 /* Return current update_pending status: */ 206 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET; 207 } 208 209 /** 210 * r100_pm_get_dynpm_state - look up dynpm power state callback. 211 * 212 * @rdev: radeon_device pointer 213 * 214 * Look up the optimal power state based on the 215 * current state of the GPU (r1xx-r5xx). 216 * Used for dynpm only. 217 */ 218 void r100_pm_get_dynpm_state(struct radeon_device *rdev) 219 { 220 int i; 221 rdev->pm.dynpm_can_upclock = true; 222 rdev->pm.dynpm_can_downclock = true; 223 224 switch (rdev->pm.dynpm_planned_action) { 225 case DYNPM_ACTION_MINIMUM: 226 rdev->pm.requested_power_state_index = 0; 227 rdev->pm.dynpm_can_downclock = false; 228 break; 229 case DYNPM_ACTION_DOWNCLOCK: 230 if (rdev->pm.current_power_state_index == 0) { 231 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 232 rdev->pm.dynpm_can_downclock = false; 233 } else { 234 if (rdev->pm.active_crtc_count > 1) { 235 for (i = 0; i < rdev->pm.num_power_states; i++) { 236 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 237 continue; 238 else if (i >= rdev->pm.current_power_state_index) { 239 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 240 break; 241 } else { 242 rdev->pm.requested_power_state_index = i; 243 break; 244 } 245 } 246 } else 247 rdev->pm.requested_power_state_index = 248 rdev->pm.current_power_state_index - 1; 249 } 250 /* don't use the power state if crtcs are active and no display flag is set */ 251 if ((rdev->pm.active_crtc_count > 0) && 252 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags & 253 RADEON_PM_MODE_NO_DISPLAY)) { 254 rdev->pm.requested_power_state_index++; 255 } 256 break; 257 case DYNPM_ACTION_UPCLOCK: 258 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { 259 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 260 rdev->pm.dynpm_can_upclock = false; 261 } else { 262 if (rdev->pm.active_crtc_count > 1) { 263 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { 264 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 265 continue; 266 else if (i <= rdev->pm.current_power_state_index) { 267 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; 268 break; 269 } else { 270 rdev->pm.requested_power_state_index = i; 271 break; 272 } 273 } 274 } else 275 rdev->pm.requested_power_state_index = 276 rdev->pm.current_power_state_index + 1; 277 } 278 break; 279 case DYNPM_ACTION_DEFAULT: 280 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; 281 rdev->pm.dynpm_can_upclock = false; 282 break; 283 case DYNPM_ACTION_NONE: 284 default: 285 DRM_ERROR("Requested mode for not defined action\n"); 286 return; 287 } 288 /* only one clock mode per power state */ 289 rdev->pm.requested_clock_mode_index = 0; 290 291 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n", 292 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 293 clock_info[rdev->pm.requested_clock_mode_index].sclk, 294 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 295 clock_info[rdev->pm.requested_clock_mode_index].mclk, 296 rdev->pm.power_state[rdev->pm.requested_power_state_index]. 297 pcie_lanes); 298 } 299 300 /** 301 * r100_pm_init_profile - Initialize power profiles callback. 302 * 303 * @rdev: radeon_device pointer 304 * 305 * Initialize the power states used in profile mode 306 * (r1xx-r3xx). 307 * Used for profile mode only. 308 */ 309 void r100_pm_init_profile(struct radeon_device *rdev) 310 { 311 /* default */ 312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; 313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; 315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; 316 /* low sh */ 317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; 318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; 319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; 320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; 321 /* mid sh */ 322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; 323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; 324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; 325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; 326 /* high sh */ 327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; 328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; 330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; 331 /* low mh */ 332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; 333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; 335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; 336 /* mid mh */ 337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; 338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; 340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; 341 /* high mh */ 342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; 343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; 344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; 345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; 346 } 347 348 /** 349 * r100_pm_misc - set additional pm hw parameters callback. 350 * 351 * @rdev: radeon_device pointer 352 * 353 * Set non-clock parameters associated with a power state 354 * (voltage, pcie lanes, etc.) (r1xx-r4xx). 355 */ 356 void r100_pm_misc(struct radeon_device *rdev) 357 { 358 int requested_index = rdev->pm.requested_power_state_index; 359 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; 360 struct radeon_voltage *voltage = &ps->clock_info[0].voltage; 361 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl; 362 363 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) { 364 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) { 365 tmp = RREG32(voltage->gpio.reg); 366 if (voltage->active_high) 367 tmp |= voltage->gpio.mask; 368 else 369 tmp &= ~(voltage->gpio.mask); 370 WREG32(voltage->gpio.reg, tmp); 371 if (voltage->delay) 372 udelay(voltage->delay); 373 } else { 374 tmp = RREG32(voltage->gpio.reg); 375 if (voltage->active_high) 376 tmp &= ~voltage->gpio.mask; 377 else 378 tmp |= voltage->gpio.mask; 379 WREG32(voltage->gpio.reg, tmp); 380 if (voltage->delay) 381 udelay(voltage->delay); 382 } 383 } 384 385 sclk_cntl = RREG32_PLL(SCLK_CNTL); 386 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2); 387 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3); 388 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL); 389 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3); 390 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) { 391 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN; 392 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE) 393 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE; 394 else 395 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE; 396 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) 397 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0); 398 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) 399 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2); 400 } else 401 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN; 402 403 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) { 404 sclk_more_cntl |= IO_CG_VOLTAGE_DROP; 405 if (voltage->delay) { 406 sclk_more_cntl |= VOLTAGE_DROP_SYNC; 407 switch (voltage->delay) { 408 case 33: 409 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0); 410 break; 411 case 66: 412 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1); 413 break; 414 case 99: 415 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2); 416 break; 417 case 132: 418 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3); 419 break; 420 } 421 } else 422 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC; 423 } else 424 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP; 425 426 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN) 427 sclk_cntl &= ~FORCE_HDP; 428 else 429 sclk_cntl |= FORCE_HDP; 430 431 WREG32_PLL(SCLK_CNTL, sclk_cntl); 432 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); 433 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); 434 435 /* set pcie lanes */ 436 if ((rdev->flags & RADEON_IS_PCIE) && 437 !(rdev->flags & RADEON_IS_IGP) && 438 rdev->asic->pm.set_pcie_lanes && 439 (ps->pcie_lanes != 440 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { 441 radeon_set_pcie_lanes(rdev, 442 ps->pcie_lanes); 443 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes); 444 } 445 } 446 447 /** 448 * r100_pm_prepare - pre-power state change callback. 449 * 450 * @rdev: radeon_device pointer 451 * 452 * Prepare for a power state change (r1xx-r4xx). 453 */ 454 void r100_pm_prepare(struct radeon_device *rdev) 455 { 456 struct drm_device *ddev = rdev->ddev; 457 struct drm_crtc *crtc; 458 struct radeon_crtc *radeon_crtc; 459 u32 tmp; 460 461 /* disable any active CRTCs */ 462 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 463 radeon_crtc = to_radeon_crtc(crtc); 464 if (radeon_crtc->enabled) { 465 if (radeon_crtc->crtc_id) { 466 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 467 tmp |= RADEON_CRTC2_DISP_REQ_EN_B; 468 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 469 } else { 470 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 471 tmp |= RADEON_CRTC_DISP_REQ_EN_B; 472 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 473 } 474 } 475 } 476 } 477 478 /** 479 * r100_pm_finish - post-power state change callback. 480 * 481 * @rdev: radeon_device pointer 482 * 483 * Clean up after a power state change (r1xx-r4xx). 484 */ 485 void r100_pm_finish(struct radeon_device *rdev) 486 { 487 struct drm_device *ddev = rdev->ddev; 488 struct drm_crtc *crtc; 489 struct radeon_crtc *radeon_crtc; 490 u32 tmp; 491 492 /* enable any active CRTCs */ 493 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { 494 radeon_crtc = to_radeon_crtc(crtc); 495 if (radeon_crtc->enabled) { 496 if (radeon_crtc->crtc_id) { 497 tmp = RREG32(RADEON_CRTC2_GEN_CNTL); 498 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B; 499 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 500 } else { 501 tmp = RREG32(RADEON_CRTC_GEN_CNTL); 502 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B; 503 WREG32(RADEON_CRTC_GEN_CNTL, tmp); 504 } 505 } 506 } 507 } 508 509 /** 510 * r100_gui_idle - gui idle callback. 511 * 512 * @rdev: radeon_device pointer 513 * 514 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx). 515 * Returns true if idle, false if not. 516 */ 517 bool r100_gui_idle(struct radeon_device *rdev) 518 { 519 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE) 520 return false; 521 else 522 return true; 523 } 524 525 /* hpd for digital panel detect/disconnect */ 526 /** 527 * r100_hpd_sense - hpd sense callback. 528 * 529 * @rdev: radeon_device pointer 530 * @hpd: hpd (hotplug detect) pin 531 * 532 * Checks if a digital monitor is connected (r1xx-r4xx). 533 * Returns true if connected, false if not connected. 534 */ 535 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 536 { 537 bool connected = false; 538 539 switch (hpd) { 540 case RADEON_HPD_1: 541 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE) 542 connected = true; 543 break; 544 case RADEON_HPD_2: 545 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE) 546 connected = true; 547 break; 548 default: 549 break; 550 } 551 return connected; 552 } 553 554 /** 555 * r100_hpd_set_polarity - hpd set polarity callback. 556 * 557 * @rdev: radeon_device pointer 558 * @hpd: hpd (hotplug detect) pin 559 * 560 * Set the polarity of the hpd pin (r1xx-r4xx). 561 */ 562 void r100_hpd_set_polarity(struct radeon_device *rdev, 563 enum radeon_hpd_id hpd) 564 { 565 u32 tmp; 566 bool connected = r100_hpd_sense(rdev, hpd); 567 568 switch (hpd) { 569 case RADEON_HPD_1: 570 tmp = RREG32(RADEON_FP_GEN_CNTL); 571 if (connected) 572 tmp &= ~RADEON_FP_DETECT_INT_POL; 573 else 574 tmp |= RADEON_FP_DETECT_INT_POL; 575 WREG32(RADEON_FP_GEN_CNTL, tmp); 576 break; 577 case RADEON_HPD_2: 578 tmp = RREG32(RADEON_FP2_GEN_CNTL); 579 if (connected) 580 tmp &= ~RADEON_FP2_DETECT_INT_POL; 581 else 582 tmp |= RADEON_FP2_DETECT_INT_POL; 583 WREG32(RADEON_FP2_GEN_CNTL, tmp); 584 break; 585 default: 586 break; 587 } 588 } 589 590 /** 591 * r100_hpd_init - hpd setup callback. 592 * 593 * @rdev: radeon_device pointer 594 * 595 * Setup the hpd pins used by the card (r1xx-r4xx). 596 * Set the polarity, and enable the hpd interrupts. 597 */ 598 void r100_hpd_init(struct radeon_device *rdev) 599 { 600 struct drm_device *dev = rdev->ddev; 601 struct drm_connector *connector; 602 unsigned enable = 0; 603 604 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 605 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 606 enable |= 1 << radeon_connector->hpd.hpd; 607 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 608 } 609 radeon_irq_kms_enable_hpd(rdev, enable); 610 } 611 612 /** 613 * r100_hpd_fini - hpd tear down callback. 614 * 615 * @rdev: radeon_device pointer 616 * 617 * Tear down the hpd pins used by the card (r1xx-r4xx). 618 * Disable the hpd interrupts. 619 */ 620 void r100_hpd_fini(struct radeon_device *rdev) 621 { 622 struct drm_device *dev = rdev->ddev; 623 struct drm_connector *connector; 624 unsigned disable = 0; 625 626 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 627 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 628 disable |= 1 << radeon_connector->hpd.hpd; 629 } 630 radeon_irq_kms_disable_hpd(rdev, disable); 631 } 632 633 /* 634 * PCI GART 635 */ 636 void r100_pci_gart_tlb_flush(struct radeon_device *rdev) 637 { 638 /* TODO: can we do somethings here ? */ 639 /* It seems hw only cache one entry so we should discard this 640 * entry otherwise if first GPU GART read hit this entry it 641 * could end up in wrong address. */ 642 } 643 644 int r100_pci_gart_init(struct radeon_device *rdev) 645 { 646 int r; 647 648 if (rdev->gart.ptr) { 649 WARN(1, "R100 PCI GART already initialized\n"); 650 return 0; 651 } 652 /* Initialize common gart structure */ 653 r = radeon_gart_init(rdev); 654 if (r) 655 return r; 656 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; 657 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 658 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 659 return radeon_gart_table_ram_alloc(rdev); 660 } 661 662 int r100_pci_gart_enable(struct radeon_device *rdev) 663 { 664 uint32_t tmp; 665 666 radeon_gart_restore(rdev); 667 /* discard memory request outside of configured range */ 668 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 669 WREG32(RADEON_AIC_CNTL, tmp); 670 /* set address range for PCI address translate */ 671 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start); 672 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end); 673 /* set PCI GART page-table base address */ 674 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); 675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; 676 WREG32(RADEON_AIC_CNTL, tmp); 677 r100_pci_gart_tlb_flush(rdev); 678 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n", 679 (unsigned)(rdev->mc.gtt_size >> 20), 680 (unsigned long long)rdev->gart.table_addr); 681 rdev->gart.ready = true; 682 return 0; 683 } 684 685 void r100_pci_gart_disable(struct radeon_device *rdev) 686 { 687 uint32_t tmp; 688 689 /* discard memory request outside of configured range */ 690 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; 691 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); 692 WREG32(RADEON_AIC_LO_ADDR, 0); 693 WREG32(RADEON_AIC_HI_ADDR, 0); 694 } 695 696 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) 697 { 698 u32 *gtt = rdev->gart.ptr; 699 700 if (i < 0 || i > rdev->gart.num_gpu_pages) { 701 return -EINVAL; 702 } 703 gtt[i] = cpu_to_le32((u32)addr); 704 return 0; 705 } 706 707 void r100_pci_gart_fini(struct radeon_device *rdev) 708 { 709 radeon_gart_fini(rdev); 710 r100_pci_gart_disable(rdev); 711 radeon_gart_table_ram_free(rdev); 712 } 713 714 int r100_irq_set(struct radeon_device *rdev) 715 { 716 uint32_t tmp = 0; 717 718 if (!rdev->irq.installed) { 719 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 720 WREG32(R_000040_GEN_INT_CNTL, 0); 721 return -EINVAL; 722 } 723 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { 724 tmp |= RADEON_SW_INT_ENABLE; 725 } 726 if (rdev->irq.crtc_vblank_int[0] || 727 atomic_read(&rdev->irq.pflip[0])) { 728 tmp |= RADEON_CRTC_VBLANK_MASK; 729 } 730 if (rdev->irq.crtc_vblank_int[1] || 731 atomic_read(&rdev->irq.pflip[1])) { 732 tmp |= RADEON_CRTC2_VBLANK_MASK; 733 } 734 if (rdev->irq.hpd[0]) { 735 tmp |= RADEON_FP_DETECT_MASK; 736 } 737 if (rdev->irq.hpd[1]) { 738 tmp |= RADEON_FP2_DETECT_MASK; 739 } 740 WREG32(RADEON_GEN_INT_CNTL, tmp); 741 return 0; 742 } 743 744 void r100_irq_disable(struct radeon_device *rdev) 745 { 746 u32 tmp; 747 748 WREG32(R_000040_GEN_INT_CNTL, 0); 749 /* Wait and acknowledge irq */ 750 mdelay(1); 751 tmp = RREG32(R_000044_GEN_INT_STATUS); 752 WREG32(R_000044_GEN_INT_STATUS, tmp); 753 } 754 755 static uint32_t r100_irq_ack(struct radeon_device *rdev) 756 { 757 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); 758 uint32_t irq_mask = RADEON_SW_INT_TEST | 759 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT | 760 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT; 761 762 if (irqs) { 763 WREG32(RADEON_GEN_INT_STATUS, irqs); 764 } 765 return irqs & irq_mask; 766 } 767 768 int r100_irq_process(struct radeon_device *rdev) 769 { 770 uint32_t status, msi_rearm; 771 bool queue_hotplug = false; 772 773 status = r100_irq_ack(rdev); 774 if (!status) { 775 return IRQ_NONE; 776 } 777 if (rdev->shutdown) { 778 return IRQ_NONE; 779 } 780 while (status) { 781 /* SW interrupt */ 782 if (status & RADEON_SW_INT_TEST) { 783 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); 784 } 785 /* Vertical blank interrupts */ 786 if (status & RADEON_CRTC_VBLANK_STAT) { 787 if (rdev->irq.crtc_vblank_int[0]) { 788 drm_handle_vblank(rdev->ddev, 0); 789 rdev->pm.vblank_sync = true; 790 wake_up(&rdev->irq.vblank_queue); 791 } 792 if (atomic_read(&rdev->irq.pflip[0])) 793 radeon_crtc_handle_flip(rdev, 0); 794 } 795 if (status & RADEON_CRTC2_VBLANK_STAT) { 796 if (rdev->irq.crtc_vblank_int[1]) { 797 drm_handle_vblank(rdev->ddev, 1); 798 rdev->pm.vblank_sync = true; 799 wake_up(&rdev->irq.vblank_queue); 800 } 801 if (atomic_read(&rdev->irq.pflip[1])) 802 radeon_crtc_handle_flip(rdev, 1); 803 } 804 if (status & RADEON_FP_DETECT_STAT) { 805 queue_hotplug = true; 806 DRM_DEBUG("HPD1\n"); 807 } 808 if (status & RADEON_FP2_DETECT_STAT) { 809 queue_hotplug = true; 810 DRM_DEBUG("HPD2\n"); 811 } 812 status = r100_irq_ack(rdev); 813 } 814 if (queue_hotplug) 815 task_add(systq, &rdev->hotplug_task); 816 if (rdev->msi_enabled) { 817 switch (rdev->family) { 818 case CHIP_RS400: 819 case CHIP_RS480: 820 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; 821 WREG32(RADEON_AIC_CNTL, msi_rearm); 822 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); 823 break; 824 default: 825 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN); 826 break; 827 } 828 } 829 return IRQ_HANDLED; 830 } 831 832 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 833 { 834 if (crtc == 0) 835 return RREG32(RADEON_CRTC_CRNT_FRAME); 836 else 837 return RREG32(RADEON_CRTC2_CRNT_FRAME); 838 } 839 840 /* Who ever call radeon_fence_emit should call ring_lock and ask 841 * for enough space (today caller are ib schedule and buffer move) */ 842 void r100_fence_ring_emit(struct radeon_device *rdev, 843 struct radeon_fence *fence) 844 { 845 struct radeon_ring *ring = &rdev->ring[fence->ring]; 846 847 /* We have to make sure that caches are flushed before 848 * CPU might read something from VRAM. */ 849 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 850 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL); 851 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 852 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL); 853 /* Wait until IDLE & CLEAN */ 854 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 855 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 856 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 857 radeon_ring_write(ring, rdev->config.r100.hdp_cntl | 858 RADEON_HDP_READ_BUFFER_INVALIDATE); 859 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 860 radeon_ring_write(ring, rdev->config.r100.hdp_cntl); 861 /* Emit fence sequence & fire IRQ */ 862 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 863 radeon_ring_write(ring, fence->seq); 864 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)); 865 radeon_ring_write(ring, RADEON_SW_INT_FIRE); 866 } 867 868 void r100_semaphore_ring_emit(struct radeon_device *rdev, 869 struct radeon_ring *ring, 870 struct radeon_semaphore *semaphore, 871 bool emit_wait) 872 { 873 /* Unused on older asics, since we don't have semaphores or multiple rings */ 874 BUG(); 875 } 876 877 int r100_copy_blit(struct radeon_device *rdev, 878 uint64_t src_offset, 879 uint64_t dst_offset, 880 unsigned num_gpu_pages, 881 struct radeon_fence **fence) 882 { 883 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 884 uint32_t cur_pages; 885 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 886 uint32_t pitch; 887 uint32_t stride_pixels; 888 unsigned ndw; 889 int num_loops; 890 int r = 0; 891 892 /* radeon limited to 16k stride */ 893 stride_bytes &= 0x3fff; 894 /* radeon pitch is /64 */ 895 pitch = stride_bytes / 64; 896 stride_pixels = stride_bytes / 4; 897 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191); 898 899 /* Ask for enough room for blit + flush + fence */ 900 ndw = 64 + (10 * num_loops); 901 r = radeon_ring_lock(rdev, ring, ndw); 902 if (r) { 903 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 904 return -EINVAL; 905 } 906 while (num_gpu_pages > 0) { 907 cur_pages = num_gpu_pages; 908 if (cur_pages > 8191) { 909 cur_pages = 8191; 910 } 911 num_gpu_pages -= cur_pages; 912 913 /* pages are in Y direction - height 914 page width in X direction - width */ 915 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); 916 radeon_ring_write(ring, 917 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 918 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 919 RADEON_GMC_SRC_CLIPPING | 920 RADEON_GMC_DST_CLIPPING | 921 RADEON_GMC_BRUSH_NONE | 922 (RADEON_COLOR_FORMAT_ARGB8888 << 8) | 923 RADEON_GMC_SRC_DATATYPE_COLOR | 924 RADEON_ROP3_S | 925 RADEON_DP_SRC_SOURCE_MEMORY | 926 RADEON_GMC_CLR_CMP_CNTL_DIS | 927 RADEON_GMC_WR_MSK_DIS); 928 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10)); 929 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10)); 930 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 931 radeon_ring_write(ring, 0); 932 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16)); 933 radeon_ring_write(ring, num_gpu_pages); 934 radeon_ring_write(ring, num_gpu_pages); 935 radeon_ring_write(ring, cur_pages | (stride_pixels << 16)); 936 } 937 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 938 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL); 939 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)); 940 radeon_ring_write(ring, 941 RADEON_WAIT_2D_IDLECLEAN | 942 RADEON_WAIT_HOST_IDLECLEAN | 943 RADEON_WAIT_DMA_GUI_IDLE); 944 if (fence) { 945 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX); 946 } 947 radeon_ring_unlock_commit(rdev, ring); 948 return r; 949 } 950 951 static int r100_cp_wait_for_idle(struct radeon_device *rdev) 952 { 953 unsigned i; 954 u32 tmp; 955 956 for (i = 0; i < rdev->usec_timeout; i++) { 957 tmp = RREG32(R_000E40_RBBM_STATUS); 958 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) { 959 return 0; 960 } 961 udelay(1); 962 } 963 return -1; 964 } 965 966 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) 967 { 968 int r; 969 970 r = radeon_ring_lock(rdev, ring, 2); 971 if (r) { 972 return; 973 } 974 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)); 975 radeon_ring_write(ring, 976 RADEON_ISYNC_ANY2D_IDLE3D | 977 RADEON_ISYNC_ANY3D_IDLE2D | 978 RADEON_ISYNC_WAIT_IDLEGUI | 979 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 980 radeon_ring_unlock_commit(rdev, ring); 981 } 982 983 984 /* Load the microcode for the CP */ 985 static int r100_cp_init_microcode(struct radeon_device *rdev) 986 { 987 const char *fw_name = NULL; 988 int err = 0; 989 990 DRM_DEBUG_KMS("\n"); 991 992 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || 993 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || 994 (rdev->family == CHIP_RS200)) { 995 DRM_INFO("Loading R100 Microcode\n"); 996 fw_name = FIRMWARE_R100; 997 } else if ((rdev->family == CHIP_R200) || 998 (rdev->family == CHIP_RV250) || 999 (rdev->family == CHIP_RV280) || 1000 (rdev->family == CHIP_RS300)) { 1001 DRM_INFO("Loading R200 Microcode\n"); 1002 fw_name = FIRMWARE_R200; 1003 } else if ((rdev->family == CHIP_R300) || 1004 (rdev->family == CHIP_R350) || 1005 (rdev->family == CHIP_RV350) || 1006 (rdev->family == CHIP_RV380) || 1007 (rdev->family == CHIP_RS400) || 1008 (rdev->family == CHIP_RS480)) { 1009 DRM_INFO("Loading R300 Microcode\n"); 1010 fw_name = FIRMWARE_R300; 1011 } else if ((rdev->family == CHIP_R420) || 1012 (rdev->family == CHIP_R423) || 1013 (rdev->family == CHIP_RV410)) { 1014 DRM_INFO("Loading R400 Microcode\n"); 1015 fw_name = FIRMWARE_R420; 1016 } else if ((rdev->family == CHIP_RS690) || 1017 (rdev->family == CHIP_RS740)) { 1018 DRM_INFO("Loading RS690/RS740 Microcode\n"); 1019 fw_name = FIRMWARE_RS690; 1020 } else if (rdev->family == CHIP_RS600) { 1021 DRM_INFO("Loading RS600 Microcode\n"); 1022 fw_name = FIRMWARE_RS600; 1023 } else if ((rdev->family == CHIP_RV515) || 1024 (rdev->family == CHIP_R520) || 1025 (rdev->family == CHIP_RV530) || 1026 (rdev->family == CHIP_R580) || 1027 (rdev->family == CHIP_RV560) || 1028 (rdev->family == CHIP_RV570)) { 1029 DRM_INFO("Loading R500 Microcode\n"); 1030 fw_name = FIRMWARE_R520; 1031 } 1032 1033 err = loadfirmware(fw_name, &rdev->me_fw, &rdev->me_fw_size); 1034 if (err) { 1035 DRM_ERROR("radeon_cp: Failed to load firmware \"%s\"\n", 1036 fw_name); 1037 err = -err; 1038 rdev->me_fw = NULL; 1039 } else if (rdev->me_fw_size % 8) { 1040 DRM_ERROR( 1041 "radeon_cp: Bogus length %zu in firmware \"%s\"\n", 1042 rdev->me_fw_size, fw_name); 1043 err = -EINVAL; 1044 free(rdev->me_fw, M_DEVBUF, 0); 1045 rdev->me_fw = NULL; 1046 } 1047 1048 return err; 1049 } 1050 1051 static void r100_cp_load_microcode(struct radeon_device *rdev) 1052 { 1053 const __be32 *fw_data; 1054 int i, size; 1055 1056 if (r100_gui_wait_for_idle(rdev)) { 1057 printk(KERN_WARNING "Failed to wait GUI idle while " 1058 "programming pipes. Bad things might happen.\n"); 1059 } 1060 1061 if (rdev->me_fw) { 1062 size = rdev->me_fw_size / 4; 1063 fw_data = (const __be32 *)&rdev->me_fw[0]; 1064 WREG32(RADEON_CP_ME_RAM_ADDR, 0); 1065 for (i = 0; i < size; i += 2) { 1066 WREG32(RADEON_CP_ME_RAM_DATAH, 1067 be32_to_cpup(&fw_data[i])); 1068 WREG32(RADEON_CP_ME_RAM_DATAL, 1069 be32_to_cpup(&fw_data[i + 1])); 1070 } 1071 } 1072 } 1073 1074 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1075 { 1076 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 1077 unsigned rb_bufsz; 1078 unsigned rb_blksz; 1079 unsigned max_fetch; 1080 unsigned pre_write_timer; 1081 unsigned pre_write_limit; 1082 unsigned indirect2_start; 1083 unsigned indirect1_start; 1084 uint32_t tmp; 1085 int r; 1086 1087 if (r100_debugfs_cp_init(rdev)) { 1088 DRM_ERROR("Failed to register debugfs file for CP !\n"); 1089 } 1090 if (!rdev->me_fw) { 1091 r = r100_cp_init_microcode(rdev); 1092 if (r) { 1093 DRM_ERROR("Failed to load firmware!\n"); 1094 return r; 1095 } 1096 } 1097 1098 /* Align ring size */ 1099 rb_bufsz = drm_order(ring_size / 8); 1100 ring_size = (1 << (rb_bufsz + 1)) * 4; 1101 r100_cp_load_microcode(rdev); 1102 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET, 1103 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR, 1104 0, 0x7fffff, RADEON_CP_PACKET2); 1105 if (r) { 1106 return r; 1107 } 1108 /* Each time the cp read 1024 bytes (16 dword/quadword) update 1109 * the rptr copy in system ram */ 1110 rb_blksz = 9; 1111 /* cp will read 128bytes at a time (4 dwords) */ 1112 max_fetch = 1; 1113 ring->align_mask = 16 - 1; 1114 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1115 pre_write_timer = 64; 1116 /* Force CP_RB_WPTR write if written more than one time before the 1117 * delay expire 1118 */ 1119 pre_write_limit = 0; 1120 /* Setup the cp cache like this (cache size is 96 dwords) : 1121 * RING 0 to 15 1122 * INDIRECT1 16 to 79 1123 * INDIRECT2 80 to 95 1124 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1125 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) 1126 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) 1127 * Idea being that most of the gpu cmd will be through indirect1 buffer 1128 * so it gets the bigger cache. 1129 */ 1130 indirect2_start = 80; 1131 indirect1_start = 16; 1132 /* cp setup */ 1133 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 1134 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | 1135 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 1136 REG_SET(RADEON_MAX_FETCH, max_fetch)); 1137 #ifdef __BIG_ENDIAN 1138 tmp |= RADEON_BUF_SWAP_32BIT; 1139 #endif 1140 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1141 1142 /* Set ring address */ 1143 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr); 1144 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr); 1145 /* Force read & write ptr to 0 */ 1146 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1147 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1148 ring->wptr = 0; 1149 WREG32(RADEON_CP_RB_WPTR, ring->wptr); 1150 1151 /* set the wb address whether it's enabled or not */ 1152 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1153 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2)); 1154 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET); 1155 1156 if (rdev->wb.enabled) 1157 WREG32(R_000770_SCRATCH_UMSK, 0xff); 1158 else { 1159 tmp |= RADEON_RB_NO_UPDATE; 1160 WREG32(R_000770_SCRATCH_UMSK, 0); 1161 } 1162 1163 WREG32(RADEON_CP_RB_CNTL, tmp); 1164 udelay(10); 1165 ring->rptr = RREG32(RADEON_CP_RB_RPTR); 1166 /* Set cp mode to bus mastering & enable cp*/ 1167 WREG32(RADEON_CP_CSQ_MODE, 1168 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1169 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); 1170 WREG32(RADEON_CP_RB_WPTR_DELAY, 0); 1171 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1172 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1173 1174 /* at this point everything should be setup correctly to enable master */ 1175 #ifdef notyet 1176 pci_set_master(rdev->pdev); 1177 #endif 1178 1179 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1180 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); 1181 if (r) { 1182 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1183 return r; 1184 } 1185 ring->ready = true; 1186 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1187 1188 if (!ring->rptr_save_reg /* not resuming from suspend */ 1189 && radeon_ring_supports_scratch_reg(rdev, ring)) { 1190 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); 1191 if (r) { 1192 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r); 1193 ring->rptr_save_reg = 0; 1194 } 1195 } 1196 return 0; 1197 } 1198 1199 void r100_cp_fini(struct radeon_device *rdev) 1200 { 1201 if (r100_cp_wait_for_idle(rdev)) { 1202 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n"); 1203 } 1204 /* Disable ring */ 1205 r100_cp_disable(rdev); 1206 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg); 1207 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); 1208 DRM_INFO("radeon: cp finalized\n"); 1209 } 1210 1211 void r100_cp_disable(struct radeon_device *rdev) 1212 { 1213 /* Disable ring */ 1214 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 1215 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 1216 WREG32(RADEON_CP_CSQ_MODE, 0); 1217 WREG32(RADEON_CP_CSQ_CNTL, 0); 1218 WREG32(R_000770_SCRATCH_UMSK, 0); 1219 if (r100_gui_wait_for_idle(rdev)) { 1220 printk(KERN_WARNING "Failed to wait GUI idle while " 1221 "programming pipes. Bad things might happen.\n"); 1222 } 1223 } 1224 1225 /* 1226 * CS functions 1227 */ 1228 int r100_reloc_pitch_offset(struct radeon_cs_parser *p, 1229 struct radeon_cs_packet *pkt, 1230 unsigned idx, 1231 unsigned reg) 1232 { 1233 int r; 1234 u32 tile_flags = 0; 1235 u32 tmp; 1236 struct radeon_cs_reloc *reloc; 1237 u32 value; 1238 1239 r = r100_cs_packet_next_reloc(p, &reloc); 1240 if (r) { 1241 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1242 idx, reg); 1243 r100_cs_dump_packet(p, pkt); 1244 return r; 1245 } 1246 1247 value = radeon_get_ib_value(p, idx); 1248 tmp = value & 0x003fffff; 1249 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1250 1251 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1252 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1253 tile_flags |= RADEON_DST_TILE_MACRO; 1254 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1255 if (reg == RADEON_SRC_PITCH_OFFSET) { 1256 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1257 r100_cs_dump_packet(p, pkt); 1258 return -EINVAL; 1259 } 1260 tile_flags |= RADEON_DST_TILE_MICRO; 1261 } 1262 1263 tmp |= tile_flags; 1264 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp; 1265 } else 1266 p->ib.ptr[idx] = (value & 0xffc00000) | tmp; 1267 return 0; 1268 } 1269 1270 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 1271 struct radeon_cs_packet *pkt, 1272 int idx) 1273 { 1274 unsigned c, i; 1275 struct radeon_cs_reloc *reloc; 1276 struct r100_cs_track *track; 1277 int r = 0; 1278 volatile uint32_t *ib; 1279 u32 idx_value; 1280 1281 ib = p->ib.ptr; 1282 track = (struct r100_cs_track *)p->track; 1283 c = radeon_get_ib_value(p, idx++) & 0x1F; 1284 if (c > 16) { 1285 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1286 pkt->opcode); 1287 r100_cs_dump_packet(p, pkt); 1288 return -EINVAL; 1289 } 1290 track->num_arrays = c; 1291 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1292 r = r100_cs_packet_next_reloc(p, &reloc); 1293 if (r) { 1294 DRM_ERROR("No reloc for packet3 %d\n", 1295 pkt->opcode); 1296 r100_cs_dump_packet(p, pkt); 1297 return r; 1298 } 1299 idx_value = radeon_get_ib_value(p, idx); 1300 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1301 1302 track->arrays[i + 0].esize = idx_value >> 8; 1303 track->arrays[i + 0].robj = reloc->robj; 1304 track->arrays[i + 0].esize &= 0x7F; 1305 r = r100_cs_packet_next_reloc(p, &reloc); 1306 if (r) { 1307 DRM_ERROR("No reloc for packet3 %d\n", 1308 pkt->opcode); 1309 r100_cs_dump_packet(p, pkt); 1310 return r; 1311 } 1312 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 1313 track->arrays[i + 1].robj = reloc->robj; 1314 track->arrays[i + 1].esize = idx_value >> 24; 1315 track->arrays[i + 1].esize &= 0x7F; 1316 } 1317 if (c & 1) { 1318 r = r100_cs_packet_next_reloc(p, &reloc); 1319 if (r) { 1320 DRM_ERROR("No reloc for packet3 %d\n", 1321 pkt->opcode); 1322 r100_cs_dump_packet(p, pkt); 1323 return r; 1324 } 1325 idx_value = radeon_get_ib_value(p, idx); 1326 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1327 track->arrays[i + 0].robj = reloc->robj; 1328 track->arrays[i + 0].esize = idx_value >> 8; 1329 track->arrays[i + 0].esize &= 0x7F; 1330 } 1331 return r; 1332 } 1333 1334 int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1335 struct radeon_cs_packet *pkt, 1336 const unsigned *auth, unsigned n, 1337 radeon_packet0_check_t check) 1338 { 1339 unsigned reg; 1340 unsigned i, j, m; 1341 unsigned idx; 1342 int r; 1343 1344 idx = pkt->idx + 1; 1345 reg = pkt->reg; 1346 /* Check that register fall into register range 1347 * determined by the number of entry (n) in the 1348 * safe register bitmap. 1349 */ 1350 if (pkt->one_reg_wr) { 1351 if ((reg >> 7) > n) { 1352 return -EINVAL; 1353 } 1354 } else { 1355 if (((reg + (pkt->count << 2)) >> 7) > n) { 1356 return -EINVAL; 1357 } 1358 } 1359 for (i = 0; i <= pkt->count; i++, idx++) { 1360 j = (reg >> 7); 1361 m = 1 << ((reg >> 2) & 31); 1362 if (auth[j] & m) { 1363 r = check(p, pkt, idx, reg); 1364 if (r) { 1365 return r; 1366 } 1367 } 1368 if (pkt->one_reg_wr) { 1369 if (!(auth[j] & m)) { 1370 break; 1371 } 1372 } else { 1373 reg += 4; 1374 } 1375 } 1376 return 0; 1377 } 1378 1379 void r100_cs_dump_packet(struct radeon_cs_parser *p, 1380 struct radeon_cs_packet *pkt) 1381 { 1382 volatile uint32_t *ib; 1383 unsigned i; 1384 unsigned idx; 1385 1386 ib = p->ib.ptr; 1387 idx = pkt->idx; 1388 for (i = 0; i <= (pkt->count + 1); i++, idx++) { 1389 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); 1390 } 1391 } 1392 1393 /** 1394 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet 1395 * @parser: parser structure holding parsing context. 1396 * @pkt: where to store packet informations 1397 * 1398 * Assume that chunk_ib_index is properly set. Will return -EINVAL 1399 * if packet is bigger than remaining ib size. or if packets is unknown. 1400 **/ 1401 int r100_cs_packet_parse(struct radeon_cs_parser *p, 1402 struct radeon_cs_packet *pkt, 1403 unsigned idx) 1404 { 1405 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 1406 uint32_t header; 1407 1408 if (idx >= ib_chunk->length_dw) { 1409 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 1410 idx, ib_chunk->length_dw); 1411 return -EINVAL; 1412 } 1413 header = radeon_get_ib_value(p, idx); 1414 pkt->idx = idx; 1415 pkt->type = CP_PACKET_GET_TYPE(header); 1416 pkt->count = CP_PACKET_GET_COUNT(header); 1417 switch (pkt->type) { 1418 case PACKET_TYPE0: 1419 pkt->reg = CP_PACKET0_GET_REG(header); 1420 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); 1421 break; 1422 case PACKET_TYPE3: 1423 pkt->opcode = CP_PACKET3_GET_OPCODE(header); 1424 break; 1425 case PACKET_TYPE2: 1426 pkt->count = -1; 1427 break; 1428 default: 1429 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 1430 return -EINVAL; 1431 } 1432 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 1433 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 1434 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 1435 return -EINVAL; 1436 } 1437 return 0; 1438 } 1439 1440 /** 1441 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1442 * @parser: parser structure holding parsing context. 1443 * 1444 * Userspace sends a special sequence for VLINE waits. 1445 * PACKET0 - VLINE_START_END + value 1446 * PACKET0 - WAIT_UNTIL +_value 1447 * RELOC (P3) - crtc_id in reloc. 1448 * 1449 * This function parses this and relocates the VLINE START END 1450 * and WAIT UNTIL packets to the correct crtc. 1451 * It also detects a switched off crtc and nulls out the 1452 * wait in that case. 1453 */ 1454 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p) 1455 { 1456 struct drm_mode_object *obj; 1457 struct drm_crtc *crtc; 1458 struct radeon_crtc *radeon_crtc; 1459 struct radeon_cs_packet p3reloc, waitreloc; 1460 int crtc_id; 1461 int r; 1462 uint32_t header, h_idx, reg; 1463 volatile uint32_t *ib; 1464 1465 ib = p->ib.ptr; 1466 1467 /* parse the wait until */ 1468 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 1469 if (r) 1470 return r; 1471 1472 /* check its a wait until and only 1 count */ 1473 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1474 waitreloc.count != 0) { 1475 DRM_ERROR("vline wait had illegal wait until segment\n"); 1476 return -EINVAL; 1477 } 1478 1479 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1480 DRM_ERROR("vline wait had illegal wait until\n"); 1481 return -EINVAL; 1482 } 1483 1484 /* jump over the NOP */ 1485 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1486 if (r) 1487 return r; 1488 1489 h_idx = p->idx - 2; 1490 p->idx += waitreloc.count + 2; 1491 p->idx += p3reloc.count + 2; 1492 1493 header = radeon_get_ib_value(p, h_idx); 1494 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1495 reg = CP_PACKET0_GET_REG(header); 1496 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1497 if (!obj) { 1498 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1499 return -EINVAL; 1500 } 1501 crtc = obj_to_crtc(obj); 1502 radeon_crtc = to_radeon_crtc(crtc); 1503 crtc_id = radeon_crtc->crtc_id; 1504 1505 if (!crtc->enabled) { 1506 /* if the CRTC isn't enabled - we need to nop out the wait until */ 1507 ib[h_idx + 2] = PACKET2(0); 1508 ib[h_idx + 3] = PACKET2(0); 1509 } else if (crtc_id == 1) { 1510 switch (reg) { 1511 case AVIVO_D1MODE_VLINE_START_END: 1512 header &= ~R300_CP_PACKET0_REG_MASK; 1513 header |= AVIVO_D2MODE_VLINE_START_END >> 2; 1514 break; 1515 case RADEON_CRTC_GUI_TRIG_VLINE: 1516 header &= ~R300_CP_PACKET0_REG_MASK; 1517 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2; 1518 break; 1519 default: 1520 DRM_ERROR("unknown crtc reloc\n"); 1521 return -EINVAL; 1522 } 1523 ib[h_idx] = header; 1524 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1525 } 1526 1527 return 0; 1528 } 1529 1530 /** 1531 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1532 * @parser: parser structure holding parsing context. 1533 * @data: pointer to relocation data 1534 * @offset_start: starting offset 1535 * @offset_mask: offset mask (to align start offset on) 1536 * @reloc: reloc informations 1537 * 1538 * Check next packet is relocation packet3, do bo validation and compute 1539 * GPU offset using the provided start. 1540 **/ 1541 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1542 struct radeon_cs_reloc **cs_reloc) 1543 { 1544 struct radeon_cs_chunk *relocs_chunk; 1545 struct radeon_cs_packet p3reloc; 1546 unsigned idx; 1547 int r; 1548 1549 if (p->chunk_relocs_idx == -1) { 1550 DRM_ERROR("No relocation chunk !\n"); 1551 return -EINVAL; 1552 } 1553 *cs_reloc = NULL; 1554 relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1555 r = r100_cs_packet_parse(p, &p3reloc, p->idx); 1556 if (r) { 1557 return r; 1558 } 1559 p->idx += p3reloc.count + 2; 1560 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1561 DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1562 p3reloc.idx); 1563 r100_cs_dump_packet(p, &p3reloc); 1564 return -EINVAL; 1565 } 1566 idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1567 if (idx >= relocs_chunk->length_dw) { 1568 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1569 idx, relocs_chunk->length_dw); 1570 r100_cs_dump_packet(p, &p3reloc); 1571 return -EINVAL; 1572 } 1573 /* FIXME: we assume reloc size is 4 dwords */ 1574 *cs_reloc = p->relocs_ptr[(idx / 4)]; 1575 return 0; 1576 } 1577 1578 static int r100_get_vtx_size(uint32_t vtx_fmt) 1579 { 1580 int vtx_size; 1581 vtx_size = 2; 1582 /* ordered according to bits in spec */ 1583 if (vtx_fmt & RADEON_SE_VTX_FMT_W0) 1584 vtx_size++; 1585 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR) 1586 vtx_size += 3; 1587 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA) 1588 vtx_size++; 1589 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR) 1590 vtx_size++; 1591 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC) 1592 vtx_size += 3; 1593 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG) 1594 vtx_size++; 1595 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC) 1596 vtx_size++; 1597 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0) 1598 vtx_size += 2; 1599 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1) 1600 vtx_size += 2; 1601 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1) 1602 vtx_size++; 1603 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2) 1604 vtx_size += 2; 1605 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2) 1606 vtx_size++; 1607 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3) 1608 vtx_size += 2; 1609 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3) 1610 vtx_size++; 1611 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0) 1612 vtx_size++; 1613 /* blend weight */ 1614 if (vtx_fmt & (0x7 << 15)) 1615 vtx_size += (vtx_fmt >> 15) & 0x7; 1616 if (vtx_fmt & RADEON_SE_VTX_FMT_N0) 1617 vtx_size += 3; 1618 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1) 1619 vtx_size += 2; 1620 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1) 1621 vtx_size++; 1622 if (vtx_fmt & RADEON_SE_VTX_FMT_W1) 1623 vtx_size++; 1624 if (vtx_fmt & RADEON_SE_VTX_FMT_N1) 1625 vtx_size++; 1626 if (vtx_fmt & RADEON_SE_VTX_FMT_Z) 1627 vtx_size++; 1628 return vtx_size; 1629 } 1630 1631 static int r100_packet0_check(struct radeon_cs_parser *p, 1632 struct radeon_cs_packet *pkt, 1633 unsigned idx, unsigned reg) 1634 { 1635 struct radeon_cs_reloc *reloc; 1636 struct r100_cs_track *track; 1637 volatile uint32_t *ib; 1638 uint32_t tmp; 1639 int r; 1640 int i, face; 1641 u32 tile_flags = 0; 1642 u32 idx_value; 1643 1644 ib = p->ib.ptr; 1645 track = (struct r100_cs_track *)p->track; 1646 1647 idx_value = radeon_get_ib_value(p, idx); 1648 1649 switch (reg) { 1650 case RADEON_CRTC_GUI_TRIG_VLINE: 1651 r = r100_cs_packet_parse_vline(p); 1652 if (r) { 1653 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1654 idx, reg); 1655 r100_cs_dump_packet(p, pkt); 1656 return r; 1657 } 1658 break; 1659 /* FIXME: only allow PACKET3 blit? easier to check for out of 1660 * range access */ 1661 case RADEON_DST_PITCH_OFFSET: 1662 case RADEON_SRC_PITCH_OFFSET: 1663 r = r100_reloc_pitch_offset(p, pkt, idx, reg); 1664 if (r) 1665 return r; 1666 break; 1667 case RADEON_RB3D_DEPTHOFFSET: 1668 r = r100_cs_packet_next_reloc(p, &reloc); 1669 if (r) { 1670 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1671 idx, reg); 1672 r100_cs_dump_packet(p, pkt); 1673 return r; 1674 } 1675 track->zb.robj = reloc->robj; 1676 track->zb.offset = idx_value; 1677 track->zb_dirty = true; 1678 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1679 break; 1680 case RADEON_RB3D_COLOROFFSET: 1681 r = r100_cs_packet_next_reloc(p, &reloc); 1682 if (r) { 1683 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1684 idx, reg); 1685 r100_cs_dump_packet(p, pkt); 1686 return r; 1687 } 1688 track->cb[0].robj = reloc->robj; 1689 track->cb[0].offset = idx_value; 1690 track->cb_dirty = true; 1691 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1692 break; 1693 case RADEON_PP_TXOFFSET_0: 1694 case RADEON_PP_TXOFFSET_1: 1695 case RADEON_PP_TXOFFSET_2: 1696 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1697 r = r100_cs_packet_next_reloc(p, &reloc); 1698 if (r) { 1699 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1700 idx, reg); 1701 r100_cs_dump_packet(p, pkt); 1702 return r; 1703 } 1704 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1705 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1706 tile_flags |= RADEON_TXO_MACRO_TILE; 1707 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1708 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1709 1710 tmp = idx_value & ~(0x7 << 2); 1711 tmp |= tile_flags; 1712 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); 1713 } else 1714 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1715 track->textures[i].robj = reloc->robj; 1716 track->tex_dirty = true; 1717 break; 1718 case RADEON_PP_CUBIC_OFFSET_T0_0: 1719 case RADEON_PP_CUBIC_OFFSET_T0_1: 1720 case RADEON_PP_CUBIC_OFFSET_T0_2: 1721 case RADEON_PP_CUBIC_OFFSET_T0_3: 1722 case RADEON_PP_CUBIC_OFFSET_T0_4: 1723 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1724 r = r100_cs_packet_next_reloc(p, &reloc); 1725 if (r) { 1726 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1727 idx, reg); 1728 r100_cs_dump_packet(p, pkt); 1729 return r; 1730 } 1731 track->textures[0].cube_info[i].offset = idx_value; 1732 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1733 track->textures[0].cube_info[i].robj = reloc->robj; 1734 track->tex_dirty = true; 1735 break; 1736 case RADEON_PP_CUBIC_OFFSET_T1_0: 1737 case RADEON_PP_CUBIC_OFFSET_T1_1: 1738 case RADEON_PP_CUBIC_OFFSET_T1_2: 1739 case RADEON_PP_CUBIC_OFFSET_T1_3: 1740 case RADEON_PP_CUBIC_OFFSET_T1_4: 1741 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1742 r = r100_cs_packet_next_reloc(p, &reloc); 1743 if (r) { 1744 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1745 idx, reg); 1746 r100_cs_dump_packet(p, pkt); 1747 return r; 1748 } 1749 track->textures[1].cube_info[i].offset = idx_value; 1750 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1751 track->textures[1].cube_info[i].robj = reloc->robj; 1752 track->tex_dirty = true; 1753 break; 1754 case RADEON_PP_CUBIC_OFFSET_T2_0: 1755 case RADEON_PP_CUBIC_OFFSET_T2_1: 1756 case RADEON_PP_CUBIC_OFFSET_T2_2: 1757 case RADEON_PP_CUBIC_OFFSET_T2_3: 1758 case RADEON_PP_CUBIC_OFFSET_T2_4: 1759 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1760 r = r100_cs_packet_next_reloc(p, &reloc); 1761 if (r) { 1762 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1763 idx, reg); 1764 r100_cs_dump_packet(p, pkt); 1765 return r; 1766 } 1767 track->textures[2].cube_info[i].offset = idx_value; 1768 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1769 track->textures[2].cube_info[i].robj = reloc->robj; 1770 track->tex_dirty = true; 1771 break; 1772 case RADEON_RE_WIDTH_HEIGHT: 1773 track->maxy = ((idx_value >> 16) & 0x7FF); 1774 track->cb_dirty = true; 1775 track->zb_dirty = true; 1776 break; 1777 case RADEON_RB3D_COLORPITCH: 1778 r = r100_cs_packet_next_reloc(p, &reloc); 1779 if (r) { 1780 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1781 idx, reg); 1782 r100_cs_dump_packet(p, pkt); 1783 return r; 1784 } 1785 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1786 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1787 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1788 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1789 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1790 1791 tmp = idx_value & ~(0x7 << 16); 1792 tmp |= tile_flags; 1793 ib[idx] = tmp; 1794 } else 1795 ib[idx] = idx_value; 1796 1797 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; 1798 track->cb_dirty = true; 1799 break; 1800 case RADEON_RB3D_DEPTHPITCH: 1801 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; 1802 track->zb_dirty = true; 1803 break; 1804 case RADEON_RB3D_CNTL: 1805 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { 1806 case 7: 1807 case 8: 1808 case 9: 1809 case 11: 1810 case 12: 1811 track->cb[0].cpp = 1; 1812 break; 1813 case 3: 1814 case 4: 1815 case 15: 1816 track->cb[0].cpp = 2; 1817 break; 1818 case 6: 1819 track->cb[0].cpp = 4; 1820 break; 1821 default: 1822 DRM_ERROR("Invalid color buffer format (%d) !\n", 1823 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); 1824 return -EINVAL; 1825 } 1826 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); 1827 track->cb_dirty = true; 1828 track->zb_dirty = true; 1829 break; 1830 case RADEON_RB3D_ZSTENCILCNTL: 1831 switch (idx_value & 0xf) { 1832 case 0: 1833 track->zb.cpp = 2; 1834 break; 1835 case 2: 1836 case 3: 1837 case 4: 1838 case 5: 1839 case 9: 1840 case 11: 1841 track->zb.cpp = 4; 1842 break; 1843 default: 1844 break; 1845 } 1846 track->zb_dirty = true; 1847 break; 1848 case RADEON_RB3D_ZPASS_ADDR: 1849 r = r100_cs_packet_next_reloc(p, &reloc); 1850 if (r) { 1851 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1852 idx, reg); 1853 r100_cs_dump_packet(p, pkt); 1854 return r; 1855 } 1856 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1857 break; 1858 case RADEON_PP_CNTL: 1859 { 1860 uint32_t temp = idx_value >> 4; 1861 for (i = 0; i < track->num_texture; i++) 1862 track->textures[i].enabled = !!(temp & (1 << i)); 1863 track->tex_dirty = true; 1864 } 1865 break; 1866 case RADEON_SE_VF_CNTL: 1867 track->vap_vf_cntl = idx_value; 1868 break; 1869 case RADEON_SE_VTX_FMT: 1870 track->vtx_size = r100_get_vtx_size(idx_value); 1871 break; 1872 case RADEON_PP_TEX_SIZE_0: 1873 case RADEON_PP_TEX_SIZE_1: 1874 case RADEON_PP_TEX_SIZE_2: 1875 i = (reg - RADEON_PP_TEX_SIZE_0) / 8; 1876 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; 1877 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; 1878 track->tex_dirty = true; 1879 break; 1880 case RADEON_PP_TEX_PITCH_0: 1881 case RADEON_PP_TEX_PITCH_1: 1882 case RADEON_PP_TEX_PITCH_2: 1883 i = (reg - RADEON_PP_TEX_PITCH_0) / 8; 1884 track->textures[i].pitch = idx_value + 32; 1885 track->tex_dirty = true; 1886 break; 1887 case RADEON_PP_TXFILTER_0: 1888 case RADEON_PP_TXFILTER_1: 1889 case RADEON_PP_TXFILTER_2: 1890 i = (reg - RADEON_PP_TXFILTER_0) / 24; 1891 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) 1892 >> RADEON_MAX_MIP_LEVEL_SHIFT); 1893 tmp = (idx_value >> 23) & 0x7; 1894 if (tmp == 2 || tmp == 6) 1895 track->textures[i].roundup_w = false; 1896 tmp = (idx_value >> 27) & 0x7; 1897 if (tmp == 2 || tmp == 6) 1898 track->textures[i].roundup_h = false; 1899 track->tex_dirty = true; 1900 break; 1901 case RADEON_PP_TXFORMAT_0: 1902 case RADEON_PP_TXFORMAT_1: 1903 case RADEON_PP_TXFORMAT_2: 1904 i = (reg - RADEON_PP_TXFORMAT_0) / 24; 1905 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { 1906 track->textures[i].use_pitch = 1; 1907 } else { 1908 track->textures[i].use_pitch = 0; 1909 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK); 1910 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK); 1911 } 1912 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) 1913 track->textures[i].tex_coord_type = 2; 1914 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { 1915 case RADEON_TXFORMAT_I8: 1916 case RADEON_TXFORMAT_RGB332: 1917 case RADEON_TXFORMAT_Y8: 1918 track->textures[i].cpp = 1; 1919 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1920 break; 1921 case RADEON_TXFORMAT_AI88: 1922 case RADEON_TXFORMAT_ARGB1555: 1923 case RADEON_TXFORMAT_RGB565: 1924 case RADEON_TXFORMAT_ARGB4444: 1925 case RADEON_TXFORMAT_VYUY422: 1926 case RADEON_TXFORMAT_YVYU422: 1927 case RADEON_TXFORMAT_SHADOW16: 1928 case RADEON_TXFORMAT_LDUDV655: 1929 case RADEON_TXFORMAT_DUDV88: 1930 track->textures[i].cpp = 2; 1931 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1932 break; 1933 case RADEON_TXFORMAT_ARGB8888: 1934 case RADEON_TXFORMAT_RGBA8888: 1935 case RADEON_TXFORMAT_SHADOW32: 1936 case RADEON_TXFORMAT_LDUDUV8888: 1937 track->textures[i].cpp = 4; 1938 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 1939 break; 1940 case RADEON_TXFORMAT_DXT1: 1941 track->textures[i].cpp = 1; 1942 track->textures[i].compress_format = R100_TRACK_COMP_DXT1; 1943 break; 1944 case RADEON_TXFORMAT_DXT23: 1945 case RADEON_TXFORMAT_DXT45: 1946 track->textures[i].cpp = 1; 1947 track->textures[i].compress_format = R100_TRACK_COMP_DXT35; 1948 break; 1949 } 1950 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); 1951 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); 1952 track->tex_dirty = true; 1953 break; 1954 case RADEON_PP_CUBIC_FACES_0: 1955 case RADEON_PP_CUBIC_FACES_1: 1956 case RADEON_PP_CUBIC_FACES_2: 1957 tmp = idx_value; 1958 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4; 1959 for (face = 0; face < 4; face++) { 1960 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf); 1961 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf); 1962 } 1963 track->tex_dirty = true; 1964 break; 1965 default: 1966 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n", 1967 reg, idx); 1968 return -EINVAL; 1969 } 1970 return 0; 1971 } 1972 1973 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1974 struct radeon_cs_packet *pkt, 1975 struct radeon_bo *robj) 1976 { 1977 unsigned idx; 1978 u32 value; 1979 idx = pkt->idx + 1; 1980 value = radeon_get_ib_value(p, idx + 2); 1981 if ((value + 1) > radeon_bo_size(robj)) { 1982 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " 1983 "(need %u have %lu) !\n", 1984 value + 1, 1985 radeon_bo_size(robj)); 1986 return -EINVAL; 1987 } 1988 return 0; 1989 } 1990 1991 static int r100_packet3_check(struct radeon_cs_parser *p, 1992 struct radeon_cs_packet *pkt) 1993 { 1994 struct radeon_cs_reloc *reloc; 1995 struct r100_cs_track *track; 1996 unsigned idx; 1997 volatile uint32_t *ib; 1998 int r; 1999 2000 ib = p->ib.ptr; 2001 idx = pkt->idx + 1; 2002 track = (struct r100_cs_track *)p->track; 2003 switch (pkt->opcode) { 2004 case PACKET3_3D_LOAD_VBPNTR: 2005 r = r100_packet3_load_vbpntr(p, pkt, idx); 2006 if (r) 2007 return r; 2008 break; 2009 case PACKET3_INDX_BUFFER: 2010 r = r100_cs_packet_next_reloc(p, &reloc); 2011 if (r) { 2012 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 2013 r100_cs_dump_packet(p, pkt); 2014 return r; 2015 } 2016 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 2017 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 2018 if (r) { 2019 return r; 2020 } 2021 break; 2022 case 0x23: 2023 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 2024 r = r100_cs_packet_next_reloc(p, &reloc); 2025 if (r) { 2026 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 2027 r100_cs_dump_packet(p, pkt); 2028 return r; 2029 } 2030 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 2031 track->num_arrays = 1; 2032 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 2033 2034 track->arrays[0].robj = reloc->robj; 2035 track->arrays[0].esize = track->vtx_size; 2036 2037 track->max_indx = radeon_get_ib_value(p, idx+1); 2038 2039 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3); 2040 track->immd_dwords = pkt->count - 1; 2041 r = r100_cs_track_check(p->rdev, track); 2042 if (r) 2043 return r; 2044 break; 2045 case PACKET3_3D_DRAW_IMMD: 2046 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) { 2047 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 2048 return -EINVAL; 2049 } 2050 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0)); 2051 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2052 track->immd_dwords = pkt->count - 1; 2053 r = r100_cs_track_check(p->rdev, track); 2054 if (r) 2055 return r; 2056 break; 2057 /* triggers drawing using in-packet vertex data */ 2058 case PACKET3_3D_DRAW_IMMD_2: 2059 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) { 2060 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 2061 return -EINVAL; 2062 } 2063 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2064 track->immd_dwords = pkt->count; 2065 r = r100_cs_track_check(p->rdev, track); 2066 if (r) 2067 return r; 2068 break; 2069 /* triggers drawing using in-packet vertex data */ 2070 case PACKET3_3D_DRAW_VBUF_2: 2071 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2072 r = r100_cs_track_check(p->rdev, track); 2073 if (r) 2074 return r; 2075 break; 2076 /* triggers drawing of vertex buffers setup elsewhere */ 2077 case PACKET3_3D_DRAW_INDX_2: 2078 track->vap_vf_cntl = radeon_get_ib_value(p, idx); 2079 r = r100_cs_track_check(p->rdev, track); 2080 if (r) 2081 return r; 2082 break; 2083 /* triggers drawing using indices to vertex buffer */ 2084 case PACKET3_3D_DRAW_VBUF: 2085 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2086 r = r100_cs_track_check(p->rdev, track); 2087 if (r) 2088 return r; 2089 break; 2090 /* triggers drawing of vertex buffers setup elsewhere */ 2091 case PACKET3_3D_DRAW_INDX: 2092 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 2093 r = r100_cs_track_check(p->rdev, track); 2094 if (r) 2095 return r; 2096 break; 2097 /* triggers drawing using indices to vertex buffer */ 2098 case PACKET3_3D_CLEAR_HIZ: 2099 case PACKET3_3D_CLEAR_ZMASK: 2100 if (p->rdev->hyperz_filp != p->filp) 2101 return -EINVAL; 2102 break; 2103 case PACKET3_NOP: 2104 break; 2105 default: 2106 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); 2107 return -EINVAL; 2108 } 2109 return 0; 2110 } 2111 2112 int r100_cs_parse(struct radeon_cs_parser *p) 2113 { 2114 struct radeon_cs_packet pkt; 2115 struct r100_cs_track *track; 2116 int r; 2117 2118 track = kzalloc(sizeof(*track), GFP_KERNEL); 2119 if (!track) 2120 return -ENOMEM; 2121 r100_cs_track_clear(p->rdev, track); 2122 p->track = track; 2123 do { 2124 r = r100_cs_packet_parse(p, &pkt, p->idx); 2125 if (r) { 2126 return r; 2127 } 2128 p->idx += pkt.count + 2; 2129 switch (pkt.type) { 2130 case PACKET_TYPE0: 2131 if (p->rdev->family >= CHIP_R200) 2132 r = r100_cs_parse_packet0(p, &pkt, 2133 p->rdev->config.r100.reg_safe_bm, 2134 p->rdev->config.r100.reg_safe_bm_size, 2135 &r200_packet0_check); 2136 else 2137 r = r100_cs_parse_packet0(p, &pkt, 2138 p->rdev->config.r100.reg_safe_bm, 2139 p->rdev->config.r100.reg_safe_bm_size, 2140 &r100_packet0_check); 2141 break; 2142 case PACKET_TYPE2: 2143 break; 2144 case PACKET_TYPE3: 2145 r = r100_packet3_check(p, &pkt); 2146 break; 2147 default: 2148 DRM_ERROR("Unknown packet type %d !\n", 2149 pkt.type); 2150 return -EINVAL; 2151 } 2152 if (r) { 2153 return r; 2154 } 2155 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2156 return 0; 2157 } 2158 2159 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2160 { 2161 DRM_ERROR("pitch %d\n", t->pitch); 2162 DRM_ERROR("use_pitch %d\n", t->use_pitch); 2163 DRM_ERROR("width %d\n", t->width); 2164 DRM_ERROR("width_11 %d\n", t->width_11); 2165 DRM_ERROR("height %d\n", t->height); 2166 DRM_ERROR("height_11 %d\n", t->height_11); 2167 DRM_ERROR("num levels %d\n", t->num_levels); 2168 DRM_ERROR("depth %d\n", t->txdepth); 2169 DRM_ERROR("bpp %d\n", t->cpp); 2170 DRM_ERROR("coordinate type %d\n", t->tex_coord_type); 2171 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w); 2172 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h); 2173 DRM_ERROR("compress format %d\n", t->compress_format); 2174 } 2175 2176 static int r100_track_compress_size(int compress_format, int w, int h) 2177 { 2178 int block_width, block_height, block_bytes; 2179 int wblocks, hblocks; 2180 int min_wblocks; 2181 int sz; 2182 2183 block_width = 4; 2184 block_height = 4; 2185 2186 switch (compress_format) { 2187 case R100_TRACK_COMP_DXT1: 2188 block_bytes = 8; 2189 min_wblocks = 4; 2190 break; 2191 default: 2192 case R100_TRACK_COMP_DXT35: 2193 block_bytes = 16; 2194 min_wblocks = 2; 2195 break; 2196 } 2197 2198 hblocks = (h + block_height - 1) / block_height; 2199 wblocks = (w + block_width - 1) / block_width; 2200 if (wblocks < min_wblocks) 2201 wblocks = min_wblocks; 2202 sz = wblocks * hblocks * block_bytes; 2203 return sz; 2204 } 2205 2206 static int r100_cs_track_cube(struct radeon_device *rdev, 2207 struct r100_cs_track *track, unsigned idx) 2208 { 2209 unsigned face, w, h; 2210 struct radeon_bo *cube_robj; 2211 unsigned long size; 2212 unsigned compress_format = track->textures[idx].compress_format; 2213 2214 for (face = 0; face < 5; face++) { 2215 cube_robj = track->textures[idx].cube_info[face].robj; 2216 w = track->textures[idx].cube_info[face].width; 2217 h = track->textures[idx].cube_info[face].height; 2218 2219 if (compress_format) { 2220 size = r100_track_compress_size(compress_format, w, h); 2221 } else 2222 size = w * h; 2223 size *= track->textures[idx].cpp; 2224 2225 size += track->textures[idx].cube_info[face].offset; 2226 2227 if (size > radeon_bo_size(cube_robj)) { 2228 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n", 2229 size, radeon_bo_size(cube_robj)); 2230 r100_cs_track_texture_print(&track->textures[idx]); 2231 return -1; 2232 } 2233 } 2234 return 0; 2235 } 2236 2237 static int r100_cs_track_texture_check(struct radeon_device *rdev, 2238 struct r100_cs_track *track) 2239 { 2240 struct radeon_bo *robj; 2241 unsigned long size; 2242 unsigned u, i, w, h, d; 2243 int ret; 2244 2245 for (u = 0; u < track->num_texture; u++) { 2246 if (!track->textures[u].enabled) 2247 continue; 2248 if (track->textures[u].lookup_disable) 2249 continue; 2250 robj = track->textures[u].robj; 2251 if (robj == NULL) { 2252 DRM_ERROR("No texture bound to unit %u\n", u); 2253 return -EINVAL; 2254 } 2255 size = 0; 2256 for (i = 0; i <= track->textures[u].num_levels; i++) { 2257 if (track->textures[u].use_pitch) { 2258 if (rdev->family < CHIP_R300) 2259 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i); 2260 else 2261 w = track->textures[u].pitch / (1 << i); 2262 } else { 2263 w = track->textures[u].width; 2264 if (rdev->family >= CHIP_RV515) 2265 w |= track->textures[u].width_11; 2266 w = w / (1 << i); 2267 if (track->textures[u].roundup_w) 2268 w = roundup_pow_of_two(w); 2269 } 2270 h = track->textures[u].height; 2271 if (rdev->family >= CHIP_RV515) 2272 h |= track->textures[u].height_11; 2273 h = h / (1 << i); 2274 if (track->textures[u].roundup_h) 2275 h = roundup_pow_of_two(h); 2276 if (track->textures[u].tex_coord_type == 1) { 2277 d = (1 << track->textures[u].txdepth) / (1 << i); 2278 if (!d) 2279 d = 1; 2280 } else { 2281 d = 1; 2282 } 2283 if (track->textures[u].compress_format) { 2284 2285 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d; 2286 /* compressed textures are block based */ 2287 } else 2288 size += w * h * d; 2289 } 2290 size *= track->textures[u].cpp; 2291 2292 switch (track->textures[u].tex_coord_type) { 2293 case 0: 2294 case 1: 2295 break; 2296 case 2: 2297 if (track->separate_cube) { 2298 ret = r100_cs_track_cube(rdev, track, u); 2299 if (ret) 2300 return ret; 2301 } else 2302 size *= 6; 2303 break; 2304 default: 2305 DRM_ERROR("Invalid texture coordinate type %u for unit " 2306 "%u\n", track->textures[u].tex_coord_type, u); 2307 return -EINVAL; 2308 } 2309 if (size > radeon_bo_size(robj)) { 2310 DRM_ERROR("Texture of unit %u needs %lu bytes but is " 2311 "%lu\n", u, size, radeon_bo_size(robj)); 2312 r100_cs_track_texture_print(&track->textures[u]); 2313 return -EINVAL; 2314 } 2315 } 2316 return 0; 2317 } 2318 2319 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track) 2320 { 2321 unsigned i; 2322 unsigned long size; 2323 unsigned prim_walk; 2324 unsigned nverts; 2325 unsigned num_cb = track->cb_dirty ? track->num_cb : 0; 2326 2327 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask && 2328 !track->blend_read_enable) 2329 num_cb = 0; 2330 2331 for (i = 0; i < num_cb; i++) { 2332 if (track->cb[i].robj == NULL) { 2333 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i); 2334 return -EINVAL; 2335 } 2336 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy; 2337 size += track->cb[i].offset; 2338 if (size > radeon_bo_size(track->cb[i].robj)) { 2339 DRM_ERROR("[drm] Buffer too small for color buffer %d " 2340 "(need %lu have %lu) !\n", i, size, 2341 radeon_bo_size(track->cb[i].robj)); 2342 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n", 2343 i, track->cb[i].pitch, track->cb[i].cpp, 2344 track->cb[i].offset, track->maxy); 2345 return -EINVAL; 2346 } 2347 } 2348 track->cb_dirty = false; 2349 2350 if (track->zb_dirty && track->z_enabled) { 2351 if (track->zb.robj == NULL) { 2352 DRM_ERROR("[drm] No buffer for z buffer !\n"); 2353 return -EINVAL; 2354 } 2355 size = track->zb.pitch * track->zb.cpp * track->maxy; 2356 size += track->zb.offset; 2357 if (size > radeon_bo_size(track->zb.robj)) { 2358 DRM_ERROR("[drm] Buffer too small for z buffer " 2359 "(need %lu have %lu) !\n", size, 2360 radeon_bo_size(track->zb.robj)); 2361 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n", 2362 track->zb.pitch, track->zb.cpp, 2363 track->zb.offset, track->maxy); 2364 return -EINVAL; 2365 } 2366 } 2367 track->zb_dirty = false; 2368 2369 if (track->aa_dirty && track->aaresolve) { 2370 if (track->aa.robj == NULL) { 2371 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i); 2372 return -EINVAL; 2373 } 2374 /* I believe the format comes from colorbuffer0. */ 2375 size = track->aa.pitch * track->cb[0].cpp * track->maxy; 2376 size += track->aa.offset; 2377 if (size > radeon_bo_size(track->aa.robj)) { 2378 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d " 2379 "(need %lu have %lu) !\n", i, size, 2380 radeon_bo_size(track->aa.robj)); 2381 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n", 2382 i, track->aa.pitch, track->cb[0].cpp, 2383 track->aa.offset, track->maxy); 2384 return -EINVAL; 2385 } 2386 } 2387 track->aa_dirty = false; 2388 2389 prim_walk = (track->vap_vf_cntl >> 4) & 0x3; 2390 if (track->vap_vf_cntl & (1 << 14)) { 2391 nverts = track->vap_alt_nverts; 2392 } else { 2393 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF; 2394 } 2395 switch (prim_walk) { 2396 case 1: 2397 for (i = 0; i < track->num_arrays; i++) { 2398 size = track->arrays[i].esize * track->max_indx * 4; 2399 if (track->arrays[i].robj == NULL) { 2400 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2401 "bound\n", prim_walk, i); 2402 return -EINVAL; 2403 } 2404 if (size > radeon_bo_size(track->arrays[i].robj)) { 2405 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2406 "need %lu dwords have %lu dwords\n", 2407 prim_walk, i, size >> 2, 2408 radeon_bo_size(track->arrays[i].robj) 2409 >> 2); 2410 DRM_ERROR("Max indices %u\n", track->max_indx); 2411 return -EINVAL; 2412 } 2413 } 2414 break; 2415 case 2: 2416 for (i = 0; i < track->num_arrays; i++) { 2417 size = track->arrays[i].esize * (nverts - 1) * 4; 2418 if (track->arrays[i].robj == NULL) { 2419 DRM_ERROR("(PW %u) Vertex array %u no buffer " 2420 "bound\n", prim_walk, i); 2421 return -EINVAL; 2422 } 2423 if (size > radeon_bo_size(track->arrays[i].robj)) { 2424 dev_err(rdev->dev, "(PW %u) Vertex array %u " 2425 "need %lu dwords have %lu dwords\n", 2426 prim_walk, i, size >> 2, 2427 radeon_bo_size(track->arrays[i].robj) 2428 >> 2); 2429 return -EINVAL; 2430 } 2431 } 2432 break; 2433 case 3: 2434 size = track->vtx_size * nverts; 2435 if (size != track->immd_dwords) { 2436 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n", 2437 track->immd_dwords, size); 2438 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", 2439 nverts, track->vtx_size); 2440 return -EINVAL; 2441 } 2442 break; 2443 default: 2444 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n", 2445 prim_walk); 2446 return -EINVAL; 2447 } 2448 2449 if (track->tex_dirty) { 2450 track->tex_dirty = false; 2451 return r100_cs_track_texture_check(rdev, track); 2452 } 2453 return 0; 2454 } 2455 2456 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track) 2457 { 2458 unsigned i, face; 2459 2460 track->cb_dirty = true; 2461 track->zb_dirty = true; 2462 track->tex_dirty = true; 2463 track->aa_dirty = true; 2464 2465 if (rdev->family < CHIP_R300) { 2466 track->num_cb = 1; 2467 if (rdev->family <= CHIP_RS200) 2468 track->num_texture = 3; 2469 else 2470 track->num_texture = 6; 2471 track->maxy = 2048; 2472 track->separate_cube = 1; 2473 } else { 2474 track->num_cb = 4; 2475 track->num_texture = 16; 2476 track->maxy = 4096; 2477 track->separate_cube = 0; 2478 track->aaresolve = false; 2479 track->aa.robj = NULL; 2480 } 2481 2482 for (i = 0; i < track->num_cb; i++) { 2483 track->cb[i].robj = NULL; 2484 track->cb[i].pitch = 8192; 2485 track->cb[i].cpp = 16; 2486 track->cb[i].offset = 0; 2487 } 2488 track->z_enabled = true; 2489 track->zb.robj = NULL; 2490 track->zb.pitch = 8192; 2491 track->zb.cpp = 4; 2492 track->zb.offset = 0; 2493 track->vtx_size = 0x7F; 2494 track->immd_dwords = 0xFFFFFFFFUL; 2495 track->num_arrays = 11; 2496 track->max_indx = 0x00FFFFFFUL; 2497 for (i = 0; i < track->num_arrays; i++) { 2498 track->arrays[i].robj = NULL; 2499 track->arrays[i].esize = 0x7F; 2500 } 2501 for (i = 0; i < track->num_texture; i++) { 2502 track->textures[i].compress_format = R100_TRACK_COMP_NONE; 2503 track->textures[i].pitch = 16536; 2504 track->textures[i].width = 16536; 2505 track->textures[i].height = 16536; 2506 track->textures[i].width_11 = 1 << 11; 2507 track->textures[i].height_11 = 1 << 11; 2508 track->textures[i].num_levels = 12; 2509 if (rdev->family <= CHIP_RS200) { 2510 track->textures[i].tex_coord_type = 0; 2511 track->textures[i].txdepth = 0; 2512 } else { 2513 track->textures[i].txdepth = 16; 2514 track->textures[i].tex_coord_type = 1; 2515 } 2516 track->textures[i].cpp = 64; 2517 track->textures[i].robj = NULL; 2518 /* CS IB emission code makes sure texture unit are disabled */ 2519 track->textures[i].enabled = false; 2520 track->textures[i].lookup_disable = false; 2521 track->textures[i].roundup_w = true; 2522 track->textures[i].roundup_h = true; 2523 if (track->separate_cube) 2524 for (face = 0; face < 5; face++) { 2525 track->textures[i].cube_info[face].robj = NULL; 2526 track->textures[i].cube_info[face].width = 16536; 2527 track->textures[i].cube_info[face].height = 16536; 2528 track->textures[i].cube_info[face].offset = 0; 2529 } 2530 } 2531 } 2532 2533 /* 2534 * Global GPU functions 2535 */ 2536 static void r100_errata(struct radeon_device *rdev) 2537 { 2538 rdev->pll_errata = 0; 2539 2540 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { 2541 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; 2542 } 2543 2544 if (rdev->family == CHIP_RV100 || 2545 rdev->family == CHIP_RS100 || 2546 rdev->family == CHIP_RS200) { 2547 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; 2548 } 2549 } 2550 2551 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) 2552 { 2553 unsigned i; 2554 uint32_t tmp; 2555 2556 for (i = 0; i < rdev->usec_timeout; i++) { 2557 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; 2558 if (tmp >= n) { 2559 return 0; 2560 } 2561 DRM_UDELAY(1); 2562 } 2563 return -1; 2564 } 2565 2566 int r100_gui_wait_for_idle(struct radeon_device *rdev) 2567 { 2568 unsigned i; 2569 uint32_t tmp; 2570 2571 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { 2572 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" 2573 " Bad things might happen.\n"); 2574 } 2575 for (i = 0; i < rdev->usec_timeout; i++) { 2576 tmp = RREG32(RADEON_RBBM_STATUS); 2577 if (!(tmp & RADEON_RBBM_ACTIVE)) { 2578 return 0; 2579 } 2580 DRM_UDELAY(1); 2581 } 2582 return -1; 2583 } 2584 2585 int r100_mc_wait_for_idle(struct radeon_device *rdev) 2586 { 2587 unsigned i; 2588 uint32_t tmp; 2589 2590 for (i = 0; i < rdev->usec_timeout; i++) { 2591 /* read MC_STATUS */ 2592 tmp = RREG32(RADEON_MC_STATUS); 2593 if (tmp & RADEON_MC_IDLE) { 2594 return 0; 2595 } 2596 DRM_UDELAY(1); 2597 } 2598 return -1; 2599 } 2600 2601 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2602 { 2603 u32 rbbm_status; 2604 2605 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2606 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2607 radeon_ring_lockup_update(ring); 2608 return false; 2609 } 2610 /* force CP activities */ 2611 radeon_ring_force_activity(rdev, ring); 2612 return radeon_ring_test_lockup(rdev, ring); 2613 } 2614 2615 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 2616 void r100_enable_bm(struct radeon_device *rdev) 2617 { 2618 uint32_t tmp; 2619 /* Enable bus mastering */ 2620 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 2621 WREG32(RADEON_BUS_CNTL, tmp); 2622 } 2623 2624 void r100_bm_disable(struct radeon_device *rdev) 2625 { 2626 u32 tmp; 2627 2628 /* disable bus mastering */ 2629 tmp = RREG32(R_000030_BUS_CNTL); 2630 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044); 2631 mdelay(1); 2632 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042); 2633 mdelay(1); 2634 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); 2635 tmp = RREG32(RADEON_BUS_CNTL); 2636 mdelay(1); 2637 #ifdef notyet 2638 pci_clear_master(rdev->pdev); 2639 #endif 2640 mdelay(1); 2641 } 2642 2643 int r100_asic_reset(struct radeon_device *rdev) 2644 { 2645 struct r100_mc_save save; 2646 u32 status, tmp; 2647 int ret = 0; 2648 2649 status = RREG32(R_000E40_RBBM_STATUS); 2650 if (!G_000E40_GUI_ACTIVE(status)) { 2651 return 0; 2652 } 2653 r100_mc_stop(rdev, &save); 2654 status = RREG32(R_000E40_RBBM_STATUS); 2655 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2656 /* stop CP */ 2657 WREG32(RADEON_CP_CSQ_CNTL, 0); 2658 tmp = RREG32(RADEON_CP_RB_CNTL); 2659 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 2660 WREG32(RADEON_CP_RB_RPTR_WR, 0); 2661 WREG32(RADEON_CP_RB_WPTR, 0); 2662 WREG32(RADEON_CP_RB_CNTL, tmp); 2663 /* save PCI state */ 2664 #ifdef notyet 2665 pci_save_state(rdev->pdev); 2666 #endif 2667 /* disable bus mastering */ 2668 r100_bm_disable(rdev); 2669 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) | 2670 S_0000F0_SOFT_RESET_RE(1) | 2671 S_0000F0_SOFT_RESET_PP(1) | 2672 S_0000F0_SOFT_RESET_RB(1)); 2673 RREG32(R_0000F0_RBBM_SOFT_RESET); 2674 mdelay(500); 2675 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2676 mdelay(1); 2677 status = RREG32(R_000E40_RBBM_STATUS); 2678 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2679 /* reset CP */ 2680 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 2681 RREG32(R_0000F0_RBBM_SOFT_RESET); 2682 mdelay(500); 2683 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 2684 mdelay(1); 2685 status = RREG32(R_000E40_RBBM_STATUS); 2686 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 2687 /* restore PCI & busmastering */ 2688 #ifdef notyet 2689 pci_restore_state(rdev->pdev); 2690 #endif 2691 r100_enable_bm(rdev); 2692 /* Check if GPU is idle */ 2693 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) || 2694 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) { 2695 dev_err(rdev->dev, "failed to reset GPU\n"); 2696 ret = -1; 2697 } else 2698 dev_info(rdev->dev, "GPU reset succeed\n"); 2699 r100_mc_resume(rdev, &save); 2700 return ret; 2701 } 2702 2703 void r100_set_common_regs(struct radeon_device *rdev) 2704 { 2705 struct drm_device *dev = rdev->ddev; 2706 bool force_dac2 = false; 2707 u32 tmp; 2708 2709 /* set these so they don't interfere with anything */ 2710 WREG32(RADEON_OV0_SCALE_CNTL, 0); 2711 WREG32(RADEON_SUBPIC_CNTL, 0); 2712 WREG32(RADEON_VIPH_CONTROL, 0); 2713 WREG32(RADEON_I2C_CNTL_1, 0); 2714 WREG32(RADEON_DVI_I2C_CNTL_1, 0); 2715 WREG32(RADEON_CAP0_TRIG_CNTL, 0); 2716 WREG32(RADEON_CAP1_TRIG_CNTL, 0); 2717 2718 /* always set up dac2 on rn50 and some rv100 as lots 2719 * of servers seem to wire it up to a VGA port but 2720 * don't report it in the bios connector 2721 * table. 2722 */ 2723 switch (dev->pdev->device) { 2724 /* RN50 */ 2725 case 0x515e: 2726 case 0x5969: 2727 force_dac2 = true; 2728 break; 2729 /* RV100*/ 2730 case 0x5159: 2731 case 0x515a: 2732 /* DELL triple head servers */ 2733 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) && 2734 ((dev->pdev->subsystem_device == 0x016c) || 2735 (dev->pdev->subsystem_device == 0x016d) || 2736 (dev->pdev->subsystem_device == 0x016e) || 2737 (dev->pdev->subsystem_device == 0x016f) || 2738 (dev->pdev->subsystem_device == 0x0170) || 2739 (dev->pdev->subsystem_device == 0x017d) || 2740 (dev->pdev->subsystem_device == 0x017e) || 2741 (dev->pdev->subsystem_device == 0x0183) || 2742 (dev->pdev->subsystem_device == 0x018a) || 2743 (dev->pdev->subsystem_device == 0x019a))) 2744 force_dac2 = true; 2745 break; 2746 } 2747 2748 if (force_dac2) { 2749 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 2750 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 2751 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2); 2752 2753 /* For CRT on DAC2, don't turn it on if BIOS didn't 2754 enable it, even it's detected. 2755 */ 2756 2757 /* force it to crtc0 */ 2758 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 2759 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 2760 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 2761 2762 /* set up the TV DAC */ 2763 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL | 2764 RADEON_TV_DAC_STD_MASK | 2765 RADEON_TV_DAC_RDACPD | 2766 RADEON_TV_DAC_GDACPD | 2767 RADEON_TV_DAC_BDACPD | 2768 RADEON_TV_DAC_BGADJ_MASK | 2769 RADEON_TV_DAC_DACADJ_MASK); 2770 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK | 2771 RADEON_TV_DAC_NHOLD | 2772 RADEON_TV_DAC_STD_PS2 | 2773 (0x58 << 16)); 2774 2775 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 2776 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 2777 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 2778 } 2779 2780 /* switch PM block to ACPI mode */ 2781 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); 2782 tmp &= ~RADEON_PM_MODE_SEL; 2783 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); 2784 2785 } 2786 2787 /* 2788 * VRAM info 2789 */ 2790 static void r100_vram_get_type(struct radeon_device *rdev) 2791 { 2792 uint32_t tmp; 2793 2794 rdev->mc.vram_is_ddr = false; 2795 if (rdev->flags & RADEON_IS_IGP) 2796 rdev->mc.vram_is_ddr = true; 2797 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 2798 rdev->mc.vram_is_ddr = true; 2799 if ((rdev->family == CHIP_RV100) || 2800 (rdev->family == CHIP_RS100) || 2801 (rdev->family == CHIP_RS200)) { 2802 tmp = RREG32(RADEON_MEM_CNTL); 2803 if (tmp & RV100_HALF_MODE) { 2804 rdev->mc.vram_width = 32; 2805 } else { 2806 rdev->mc.vram_width = 64; 2807 } 2808 if (rdev->flags & RADEON_SINGLE_CRTC) { 2809 rdev->mc.vram_width /= 4; 2810 rdev->mc.vram_is_ddr = true; 2811 } 2812 } else if (rdev->family <= CHIP_RV280) { 2813 tmp = RREG32(RADEON_MEM_CNTL); 2814 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { 2815 rdev->mc.vram_width = 128; 2816 } else { 2817 rdev->mc.vram_width = 64; 2818 } 2819 } else { 2820 /* newer IGPs */ 2821 rdev->mc.vram_width = 128; 2822 } 2823 } 2824 2825 static u32 r100_get_accessible_vram(struct radeon_device *rdev) 2826 { 2827 u32 aper_size; 2828 pcireg_t reg; 2829 2830 aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2831 2832 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 2833 * that is has the 2nd generation multifunction PCI interface 2834 */ 2835 if (rdev->family == CHIP_RV280 || 2836 rdev->family >= CHIP_RV350) { 2837 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 2838 ~RADEON_HDP_APER_CNTL); 2839 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n"); 2840 return aper_size * 2; 2841 } 2842 2843 /* Older cards have all sorts of funny issues to deal with. First 2844 * check if it's a multifunction card by reading the PCI config 2845 * header type... Limit those to one aperture size 2846 */ 2847 reg = pci_conf_read(rdev->pc, rdev->pa_tag, PCI_BHLC_REG); 2848 if (PCI_HDRTYPE_MULTIFN(reg)) { 2849 DRM_INFO("Generation 1 PCI interface in multifunction mode\n"); 2850 DRM_INFO("Limiting VRAM to one aperture\n"); 2851 return aper_size; 2852 } 2853 2854 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 2855 * have set it up. We don't write this as it's broken on some ASICs but 2856 * we expect the BIOS to have done the right thing (might be too optimistic...) 2857 */ 2858 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 2859 return aper_size * 2; 2860 return aper_size; 2861 } 2862 2863 void r100_vram_init_sizes(struct radeon_device *rdev) 2864 { 2865 u64 config_aper_size; 2866 2867 /* work out accessible VRAM */ 2868 rdev->mc.aper_base = rdev->fb_aper_offset; 2869 rdev->mc.aper_size = rdev->fb_aper_size; 2870 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev); 2871 /* FIXME we don't use the second aperture yet when we could use it */ 2872 if (rdev->mc.visible_vram_size > rdev->mc.aper_size) 2873 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2874 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE); 2875 if (rdev->flags & RADEON_IS_IGP) { 2876 uint32_t tom; 2877 /* read NB_TOM to get the amount of ram stolen for the GPU */ 2878 tom = RREG32(RADEON_NB_TOM); 2879 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); 2880 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2881 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2882 } else { 2883 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); 2884 /* Some production boards of m6 will report 0 2885 * if it's 8 MB 2886 */ 2887 if (rdev->mc.real_vram_size == 0) { 2888 rdev->mc.real_vram_size = 8192 * 1024; 2889 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size); 2890 } 2891 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 2892 * Novell bug 204882 + along with lots of ubuntu ones 2893 */ 2894 if (rdev->mc.aper_size > config_aper_size) 2895 config_aper_size = rdev->mc.aper_size; 2896 2897 if (config_aper_size > rdev->mc.real_vram_size) 2898 rdev->mc.mc_vram_size = config_aper_size; 2899 else 2900 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; 2901 } 2902 } 2903 2904 void r100_vga_set_state(struct radeon_device *rdev, bool state) 2905 { 2906 uint32_t temp; 2907 2908 temp = RREG32(RADEON_CONFIG_CNTL); 2909 if (state == false) { 2910 temp &= ~RADEON_CFG_VGA_RAM_EN; 2911 temp |= RADEON_CFG_VGA_IO_DIS; 2912 } else { 2913 temp &= ~RADEON_CFG_VGA_IO_DIS; 2914 } 2915 WREG32(RADEON_CONFIG_CNTL, temp); 2916 } 2917 2918 static void r100_mc_init(struct radeon_device *rdev) 2919 { 2920 u64 base; 2921 2922 r100_vram_get_type(rdev); 2923 r100_vram_init_sizes(rdev); 2924 base = rdev->mc.aper_base; 2925 if (rdev->flags & RADEON_IS_IGP) 2926 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; 2927 radeon_vram_location(rdev, &rdev->mc, base); 2928 rdev->mc.gtt_base_align = 0; 2929 if (!(rdev->flags & RADEON_IS_AGP)) 2930 radeon_gtt_location(rdev, &rdev->mc); 2931 radeon_update_bandwidth_info(rdev); 2932 } 2933 2934 2935 /* 2936 * Indirect registers accessor 2937 */ 2938 void r100_pll_errata_after_index(struct radeon_device *rdev) 2939 { 2940 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) { 2941 (void)RREG32(RADEON_CLOCK_CNTL_DATA); 2942 (void)RREG32(RADEON_CRTC_GEN_CNTL); 2943 } 2944 } 2945 2946 static void r100_pll_errata_after_data(struct radeon_device *rdev) 2947 { 2948 /* This workarounds is necessary on RV100, RS100 and RS200 chips 2949 * or the chip could hang on a subsequent access 2950 */ 2951 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { 2952 mdelay(5); 2953 } 2954 2955 /* This function is required to workaround a hardware bug in some (all?) 2956 * revisions of the R300. This workaround should be called after every 2957 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 2958 * may not be correct. 2959 */ 2960 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { 2961 uint32_t save, tmp; 2962 2963 save = RREG32(RADEON_CLOCK_CNTL_INDEX); 2964 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2965 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); 2966 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); 2967 WREG32(RADEON_CLOCK_CNTL_INDEX, save); 2968 } 2969 } 2970 2971 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) 2972 { 2973 uint32_t data; 2974 2975 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); 2976 r100_pll_errata_after_index(rdev); 2977 data = RREG32(RADEON_CLOCK_CNTL_DATA); 2978 r100_pll_errata_after_data(rdev); 2979 return data; 2980 } 2981 2982 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 2983 { 2984 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); 2985 r100_pll_errata_after_index(rdev); 2986 WREG32(RADEON_CLOCK_CNTL_DATA, v); 2987 r100_pll_errata_after_data(rdev); 2988 } 2989 2990 static void r100_set_safe_registers(struct radeon_device *rdev) 2991 { 2992 if (ASIC_IS_RN50(rdev)) { 2993 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm; 2994 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm); 2995 } else if (rdev->family < CHIP_R200) { 2996 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm; 2997 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm); 2998 } else { 2999 r200_set_safe_registers(rdev); 3000 } 3001 } 3002 3003 /* 3004 * Debugfs info 3005 */ 3006 #if defined(CONFIG_DEBUG_FS) 3007 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data) 3008 { 3009 struct drm_info_node *node = (struct drm_info_node *) m->private; 3010 struct drm_device *dev = node->minor->dev; 3011 struct radeon_device *rdev = dev->dev_private; 3012 uint32_t reg, value; 3013 unsigned i; 3014 3015 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)); 3016 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)); 3017 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 3018 for (i = 0; i < 64; i++) { 3019 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100); 3020 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2; 3021 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i); 3022 value = RREG32(RADEON_RBBM_CMDFIFO_DATA); 3023 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value); 3024 } 3025 return 0; 3026 } 3027 3028 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) 3029 { 3030 struct drm_info_node *node = (struct drm_info_node *) m->private; 3031 struct drm_device *dev = node->minor->dev; 3032 struct radeon_device *rdev = dev->dev_private; 3033 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3034 uint32_t rdp, wdp; 3035 unsigned count, i, j; 3036 3037 radeon_ring_free_size(rdev, ring); 3038 rdp = RREG32(RADEON_CP_RB_RPTR); 3039 wdp = RREG32(RADEON_CP_RB_WPTR); 3040 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask; 3041 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 3042 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 3043 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 3044 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw); 3045 seq_printf(m, "%u dwords in ring\n", count); 3046 if (ring->ready) { 3047 for (j = 0; j <= count; j++) { 3048 i = (rdp + j) & ring->ptr_mask; 3049 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]); 3050 } 3051 } 3052 return 0; 3053 } 3054 3055 3056 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data) 3057 { 3058 struct drm_info_node *node = (struct drm_info_node *) m->private; 3059 struct drm_device *dev = node->minor->dev; 3060 struct radeon_device *rdev = dev->dev_private; 3061 uint32_t csq_stat, csq2_stat, tmp; 3062 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr; 3063 unsigned i; 3064 3065 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 3066 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)); 3067 csq_stat = RREG32(RADEON_CP_CSQ_STAT); 3068 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT); 3069 r_rptr = (csq_stat >> 0) & 0x3ff; 3070 r_wptr = (csq_stat >> 10) & 0x3ff; 3071 ib1_rptr = (csq_stat >> 20) & 0x3ff; 3072 ib1_wptr = (csq2_stat >> 0) & 0x3ff; 3073 ib2_rptr = (csq2_stat >> 10) & 0x3ff; 3074 ib2_wptr = (csq2_stat >> 20) & 0x3ff; 3075 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat); 3076 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat); 3077 seq_printf(m, "Ring rptr %u\n", r_rptr); 3078 seq_printf(m, "Ring wptr %u\n", r_wptr); 3079 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr); 3080 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr); 3081 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr); 3082 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr); 3083 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms 3084 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */ 3085 seq_printf(m, "Ring fifo:\n"); 3086 for (i = 0; i < 256; i++) { 3087 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3088 tmp = RREG32(RADEON_CP_CSQ_DATA); 3089 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp); 3090 } 3091 seq_printf(m, "Indirect1 fifo:\n"); 3092 for (i = 256; i <= 512; i++) { 3093 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3094 tmp = RREG32(RADEON_CP_CSQ_DATA); 3095 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp); 3096 } 3097 seq_printf(m, "Indirect2 fifo:\n"); 3098 for (i = 640; i < ib1_wptr; i++) { 3099 WREG32(RADEON_CP_CSQ_ADDR, i << 2); 3100 tmp = RREG32(RADEON_CP_CSQ_DATA); 3101 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp); 3102 } 3103 return 0; 3104 } 3105 3106 static int r100_debugfs_mc_info(struct seq_file *m, void *data) 3107 { 3108 struct drm_info_node *node = (struct drm_info_node *) m->private; 3109 struct drm_device *dev = node->minor->dev; 3110 struct radeon_device *rdev = dev->dev_private; 3111 uint32_t tmp; 3112 3113 tmp = RREG32(RADEON_CONFIG_MEMSIZE); 3114 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp); 3115 tmp = RREG32(RADEON_MC_FB_LOCATION); 3116 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp); 3117 tmp = RREG32(RADEON_BUS_CNTL); 3118 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); 3119 tmp = RREG32(RADEON_MC_AGP_LOCATION); 3120 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); 3121 tmp = RREG32(RADEON_AGP_BASE); 3122 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); 3123 tmp = RREG32(RADEON_HOST_PATH_CNTL); 3124 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); 3125 tmp = RREG32(0x01D0); 3126 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp); 3127 tmp = RREG32(RADEON_AIC_LO_ADDR); 3128 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp); 3129 tmp = RREG32(RADEON_AIC_HI_ADDR); 3130 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp); 3131 tmp = RREG32(0x01E4); 3132 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp); 3133 return 0; 3134 } 3135 3136 static struct drm_info_list r100_debugfs_rbbm_list[] = { 3137 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL}, 3138 }; 3139 3140 static struct drm_info_list r100_debugfs_cp_list[] = { 3141 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL}, 3142 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL}, 3143 }; 3144 3145 static struct drm_info_list r100_debugfs_mc_info_list[] = { 3146 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL}, 3147 }; 3148 #endif 3149 3150 int r100_debugfs_rbbm_init(struct radeon_device *rdev) 3151 { 3152 #if defined(CONFIG_DEBUG_FS) 3153 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1); 3154 #else 3155 return 0; 3156 #endif 3157 } 3158 3159 int r100_debugfs_cp_init(struct radeon_device *rdev) 3160 { 3161 #if defined(CONFIG_DEBUG_FS) 3162 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2); 3163 #else 3164 return 0; 3165 #endif 3166 } 3167 3168 int r100_debugfs_mc_info_init(struct radeon_device *rdev) 3169 { 3170 #if defined(CONFIG_DEBUG_FS) 3171 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1); 3172 #else 3173 return 0; 3174 #endif 3175 } 3176 3177 int r100_set_surface_reg(struct radeon_device *rdev, int reg, 3178 uint32_t tiling_flags, uint32_t pitch, 3179 uint32_t offset, uint32_t obj_size) 3180 { 3181 int surf_index = reg * 16; 3182 int flags = 0; 3183 3184 if (rdev->family <= CHIP_RS200) { 3185 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3186 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3187 flags |= RADEON_SURF_TILE_COLOR_BOTH; 3188 if (tiling_flags & RADEON_TILING_MACRO) 3189 flags |= RADEON_SURF_TILE_COLOR_MACRO; 3190 /* setting pitch to 0 disables tiling */ 3191 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) 3192 == 0) 3193 pitch = 0; 3194 } else if (rdev->family <= CHIP_RV280) { 3195 if (tiling_flags & (RADEON_TILING_MACRO)) 3196 flags |= R200_SURF_TILE_COLOR_MACRO; 3197 if (tiling_flags & RADEON_TILING_MICRO) 3198 flags |= R200_SURF_TILE_COLOR_MICRO; 3199 } else { 3200 if (tiling_flags & RADEON_TILING_MACRO) 3201 flags |= R300_SURF_TILE_MACRO; 3202 if (tiling_flags & RADEON_TILING_MICRO) 3203 flags |= R300_SURF_TILE_MICRO; 3204 } 3205 3206 if (tiling_flags & RADEON_TILING_SWAP_16BIT) 3207 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 3208 if (tiling_flags & RADEON_TILING_SWAP_32BIT) 3209 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 3210 3211 /* r100/r200 divide by 16 */ 3212 if (rdev->family < CHIP_R300) 3213 flags |= pitch / 16; 3214 else 3215 flags |= pitch / 8; 3216 3217 3218 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1); 3219 WREG32(RADEON_SURFACE0_INFO + surf_index, flags); 3220 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset); 3221 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1); 3222 return 0; 3223 } 3224 3225 void r100_clear_surface_reg(struct radeon_device *rdev, int reg) 3226 { 3227 int surf_index = reg * 16; 3228 WREG32(RADEON_SURFACE0_INFO + surf_index, 0); 3229 } 3230 3231 void r100_bandwidth_update(struct radeon_device *rdev) 3232 { 3233 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff; 3234 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff; 3235 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff; 3236 uint32_t temp, data, mem_trcd, mem_trp, mem_tras; 3237 fixed20_12 memtcas_ff[8] = { 3238 dfixed_init(1), 3239 dfixed_init(2), 3240 dfixed_init(3), 3241 dfixed_init(0), 3242 dfixed_init_half(1), 3243 dfixed_init_half(2), 3244 dfixed_init(0), 3245 }; 3246 fixed20_12 memtcas_rs480_ff[8] = { 3247 dfixed_init(0), 3248 dfixed_init(1), 3249 dfixed_init(2), 3250 dfixed_init(3), 3251 dfixed_init(0), 3252 dfixed_init_half(1), 3253 dfixed_init_half(2), 3254 dfixed_init_half(3), 3255 }; 3256 fixed20_12 memtcas2_ff[8] = { 3257 dfixed_init(0), 3258 dfixed_init(1), 3259 dfixed_init(2), 3260 dfixed_init(3), 3261 dfixed_init(4), 3262 dfixed_init(5), 3263 dfixed_init(6), 3264 dfixed_init(7), 3265 }; 3266 fixed20_12 memtrbs[8] = { 3267 dfixed_init(1), 3268 dfixed_init_half(1), 3269 dfixed_init(2), 3270 dfixed_init_half(2), 3271 dfixed_init(3), 3272 dfixed_init_half(3), 3273 dfixed_init(4), 3274 dfixed_init_half(4) 3275 }; 3276 fixed20_12 memtrbs_r4xx[8] = { 3277 dfixed_init(4), 3278 dfixed_init(5), 3279 dfixed_init(6), 3280 dfixed_init(7), 3281 dfixed_init(8), 3282 dfixed_init(9), 3283 dfixed_init(10), 3284 dfixed_init(11) 3285 }; 3286 fixed20_12 min_mem_eff; 3287 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1; 3288 fixed20_12 cur_latency_mclk, cur_latency_sclk; 3289 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate, 3290 disp_drain_rate2, read_return_rate; 3291 fixed20_12 time_disp1_drop_priority; 3292 int c; 3293 int cur_size = 16; /* in octawords */ 3294 int critical_point = 0, critical_point2; 3295 /* uint32_t read_return_rate, time_disp1_drop_priority; */ 3296 int stop_req, max_stop_req; 3297 struct drm_display_mode *mode1 = NULL; 3298 struct drm_display_mode *mode2 = NULL; 3299 uint32_t pixel_bytes1 = 0; 3300 uint32_t pixel_bytes2 = 0; 3301 3302 radeon_update_display_priority(rdev); 3303 3304 if (rdev->mode_info.crtcs[0]->base.enabled) { 3305 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 3306 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 3307 } 3308 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3309 if (rdev->mode_info.crtcs[1]->base.enabled) { 3310 mode2 = &rdev->mode_info.crtcs[1]->base.mode; 3311 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8; 3312 } 3313 } 3314 3315 min_mem_eff.full = dfixed_const_8(0); 3316 /* get modes */ 3317 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) { 3318 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER); 3319 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 3320 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 3321 /* check crtc enables */ 3322 if (mode2) 3323 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); 3324 if (mode1) 3325 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); 3326 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 3327 } 3328 3329 /* 3330 * determine is there is enough bw for current mode 3331 */ 3332 sclk_ff = rdev->pm.sclk; 3333 mclk_ff = rdev->pm.mclk; 3334 3335 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 3336 temp_ff.full = dfixed_const(temp); 3337 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); 3338 3339 pix_clk.full = 0; 3340 pix_clk2.full = 0; 3341 peak_disp_bw.full = 0; 3342 if (mode1) { 3343 temp_ff.full = dfixed_const(1000); 3344 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ 3345 pix_clk.full = dfixed_div(pix_clk, temp_ff); 3346 temp_ff.full = dfixed_const(pixel_bytes1); 3347 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); 3348 } 3349 if (mode2) { 3350 temp_ff.full = dfixed_const(1000); 3351 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */ 3352 pix_clk2.full = dfixed_div(pix_clk2, temp_ff); 3353 temp_ff.full = dfixed_const(pixel_bytes2); 3354 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); 3355 } 3356 3357 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); 3358 if (peak_disp_bw.full >= mem_bw.full) { 3359 DRM_ERROR("You may not have enough display bandwidth for current mode\n" 3360 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 3361 } 3362 3363 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 3364 temp = RREG32(RADEON_MEM_TIMING_CNTL); 3365 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */ 3366 mem_trcd = ((temp >> 2) & 0x3) + 1; 3367 mem_trp = ((temp & 0x3)) + 1; 3368 mem_tras = ((temp & 0x70) >> 4) + 1; 3369 } else if (rdev->family == CHIP_R300 || 3370 rdev->family == CHIP_R350) { /* r300, r350 */ 3371 mem_trcd = (temp & 0x7) + 1; 3372 mem_trp = ((temp >> 8) & 0x7) + 1; 3373 mem_tras = ((temp >> 11) & 0xf) + 4; 3374 } else if (rdev->family == CHIP_RV350 || 3375 rdev->family <= CHIP_RV380) { 3376 /* rv3x0 */ 3377 mem_trcd = (temp & 0x7) + 3; 3378 mem_trp = ((temp >> 8) & 0x7) + 3; 3379 mem_tras = ((temp >> 11) & 0xf) + 6; 3380 } else if (rdev->family == CHIP_R420 || 3381 rdev->family == CHIP_R423 || 3382 rdev->family == CHIP_RV410) { 3383 /* r4xx */ 3384 mem_trcd = (temp & 0xf) + 3; 3385 if (mem_trcd > 15) 3386 mem_trcd = 15; 3387 mem_trp = ((temp >> 8) & 0xf) + 3; 3388 if (mem_trp > 15) 3389 mem_trp = 15; 3390 mem_tras = ((temp >> 12) & 0x1f) + 6; 3391 if (mem_tras > 31) 3392 mem_tras = 31; 3393 } else { /* RV200, R200 */ 3394 mem_trcd = (temp & 0x7) + 1; 3395 mem_trp = ((temp >> 8) & 0x7) + 1; 3396 mem_tras = ((temp >> 12) & 0xf) + 4; 3397 } 3398 /* convert to FF */ 3399 trcd_ff.full = dfixed_const(mem_trcd); 3400 trp_ff.full = dfixed_const(mem_trp); 3401 tras_ff.full = dfixed_const(mem_tras); 3402 3403 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 3404 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3405 data = (temp & (7 << 20)) >> 20; 3406 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) { 3407 if (rdev->family == CHIP_RS480) /* don't think rs400 */ 3408 tcas_ff = memtcas_rs480_ff[data]; 3409 else 3410 tcas_ff = memtcas_ff[data]; 3411 } else 3412 tcas_ff = memtcas2_ff[data]; 3413 3414 if (rdev->family == CHIP_RS400 || 3415 rdev->family == CHIP_RS480) { 3416 /* extra cas latency stored in bits 23-25 0-4 clocks */ 3417 data = (temp >> 23) & 0x7; 3418 if (data < 5) 3419 tcas_ff.full += dfixed_const(data); 3420 } 3421 3422 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) { 3423 /* on the R300, Tcas is included in Trbs. 3424 */ 3425 temp = RREG32(RADEON_MEM_CNTL); 3426 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 3427 if (data == 1) { 3428 if (R300_MEM_USE_CD_CH_ONLY & temp) { 3429 temp = RREG32(R300_MC_IND_INDEX); 3430 temp &= ~R300_MC_IND_ADDR_MASK; 3431 temp |= R300_MC_READ_CNTL_CD_mcind; 3432 WREG32(R300_MC_IND_INDEX, temp); 3433 temp = RREG32(R300_MC_IND_DATA); 3434 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 3435 } else { 3436 temp = RREG32(R300_MC_READ_CNTL_AB); 3437 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3438 } 3439 } else { 3440 temp = RREG32(R300_MC_READ_CNTL_AB); 3441 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 3442 } 3443 if (rdev->family == CHIP_RV410 || 3444 rdev->family == CHIP_R420 || 3445 rdev->family == CHIP_R423) 3446 trbs_ff = memtrbs_r4xx[data]; 3447 else 3448 trbs_ff = memtrbs[data]; 3449 tcas_ff.full += trbs_ff.full; 3450 } 3451 3452 sclk_eff_ff.full = sclk_ff.full; 3453 3454 if (rdev->flags & RADEON_IS_AGP) { 3455 fixed20_12 agpmode_ff; 3456 agpmode_ff.full = dfixed_const(radeon_agpmode); 3457 temp_ff.full = dfixed_const_666(16); 3458 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); 3459 } 3460 /* TODO PCIE lanes may affect this - agpmode == 16?? */ 3461 3462 if (ASIC_IS_R300(rdev)) { 3463 sclk_delay_ff.full = dfixed_const(250); 3464 } else { 3465 if ((rdev->family == CHIP_RV100) || 3466 rdev->flags & RADEON_IS_IGP) { 3467 if (rdev->mc.vram_is_ddr) 3468 sclk_delay_ff.full = dfixed_const(41); 3469 else 3470 sclk_delay_ff.full = dfixed_const(33); 3471 } else { 3472 if (rdev->mc.vram_width == 128) 3473 sclk_delay_ff.full = dfixed_const(57); 3474 else 3475 sclk_delay_ff.full = dfixed_const(41); 3476 } 3477 } 3478 3479 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff); 3480 3481 if (rdev->mc.vram_is_ddr) { 3482 if (rdev->mc.vram_width == 32) { 3483 k1.full = dfixed_const(40); 3484 c = 3; 3485 } else { 3486 k1.full = dfixed_const(20); 3487 c = 1; 3488 } 3489 } else { 3490 k1.full = dfixed_const(40); 3491 c = 3; 3492 } 3493 3494 temp_ff.full = dfixed_const(2); 3495 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); 3496 temp_ff.full = dfixed_const(c); 3497 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); 3498 temp_ff.full = dfixed_const(4); 3499 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); 3500 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); 3501 mc_latency_mclk.full += k1.full; 3502 3503 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff); 3504 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff); 3505 3506 /* 3507 HW cursor time assuming worst case of full size colour cursor. 3508 */ 3509 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))); 3510 temp_ff.full += trcd_ff.full; 3511 if (temp_ff.full < tras_ff.full) 3512 temp_ff.full = tras_ff.full; 3513 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff); 3514 3515 temp_ff.full = dfixed_const(cur_size); 3516 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff); 3517 /* 3518 Find the total latency for the display data. 3519 */ 3520 disp_latency_overhead.full = dfixed_const(8); 3521 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff); 3522 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 3523 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 3524 3525 if (mc_latency_mclk.full > mc_latency_sclk.full) 3526 disp_latency.full = mc_latency_mclk.full; 3527 else 3528 disp_latency.full = mc_latency_sclk.full; 3529 3530 /* setup Max GRPH_STOP_REQ default value */ 3531 if (ASIC_IS_RV100(rdev)) 3532 max_stop_req = 0x5c; 3533 else 3534 max_stop_req = 0x7c; 3535 3536 if (mode1) { 3537 /* CRTC1 3538 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 3539 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 3540 */ 3541 stop_req = mode1->hdisplay * pixel_bytes1 / 16; 3542 3543 if (stop_req > max_stop_req) 3544 stop_req = max_stop_req; 3545 3546 /* 3547 Find the drain rate of the display buffer. 3548 */ 3549 temp_ff.full = dfixed_const((16/pixel_bytes1)); 3550 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); 3551 3552 /* 3553 Find the critical point of the display buffer. 3554 */ 3555 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); 3556 crit_point_ff.full += dfixed_const_half(0); 3557 3558 critical_point = dfixed_trunc(crit_point_ff); 3559 3560 if (rdev->disp_priority == 2) { 3561 critical_point = 0; 3562 } 3563 3564 /* 3565 The critical point should never be above max_stop_req-4. Setting 3566 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 3567 */ 3568 if (max_stop_req - critical_point < 4) 3569 critical_point = 0; 3570 3571 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) { 3572 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 3573 critical_point = 0x10; 3574 } 3575 3576 temp = RREG32(RADEON_GRPH_BUFFER_CNTL); 3577 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 3578 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3579 temp &= ~(RADEON_GRPH_START_REQ_MASK); 3580 if ((rdev->family == CHIP_R350) && 3581 (stop_req > 0x15)) { 3582 stop_req -= 0x10; 3583 } 3584 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3585 temp |= RADEON_GRPH_BUFFER_SIZE; 3586 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 3587 RADEON_GRPH_CRITICAL_AT_SOF | 3588 RADEON_GRPH_STOP_CNTL); 3589 /* 3590 Write the result into the register. 3591 */ 3592 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3593 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3594 3595 #if 0 3596 if ((rdev->family == CHIP_RS400) || 3597 (rdev->family == CHIP_RS480)) { 3598 /* attempt to program RS400 disp regs correctly ??? */ 3599 temp = RREG32(RS400_DISP1_REG_CNTL); 3600 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 3601 RS400_DISP1_STOP_REQ_LEVEL_MASK); 3602 WREG32(RS400_DISP1_REQ_CNTL1, (temp | 3603 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3604 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3605 temp = RREG32(RS400_DMIF_MEM_CNTL1); 3606 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 3607 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 3608 WREG32(RS400_DMIF_MEM_CNTL1, (temp | 3609 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 3610 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 3611 } 3612 #endif 3613 3614 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n", 3615 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */ 3616 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL)); 3617 } 3618 3619 if (mode2) { 3620 u32 grph2_cntl; 3621 stop_req = mode2->hdisplay * pixel_bytes2 / 16; 3622 3623 if (stop_req > max_stop_req) 3624 stop_req = max_stop_req; 3625 3626 /* 3627 Find the drain rate of the display buffer. 3628 */ 3629 temp_ff.full = dfixed_const((16/pixel_bytes2)); 3630 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff); 3631 3632 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL); 3633 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK); 3634 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 3635 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK); 3636 if ((rdev->family == CHIP_R350) && 3637 (stop_req > 0x15)) { 3638 stop_req -= 0x10; 3639 } 3640 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 3641 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE; 3642 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL | 3643 RADEON_GRPH_CRITICAL_AT_SOF | 3644 RADEON_GRPH_STOP_CNTL); 3645 3646 if ((rdev->family == CHIP_RS100) || 3647 (rdev->family == CHIP_RS200)) 3648 critical_point2 = 0; 3649 else { 3650 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; 3651 temp_ff.full = dfixed_const(temp); 3652 temp_ff.full = dfixed_mul(mclk_ff, temp_ff); 3653 if (sclk_ff.full < temp_ff.full) 3654 temp_ff.full = sclk_ff.full; 3655 3656 read_return_rate.full = temp_ff.full; 3657 3658 if (mode1) { 3659 temp_ff.full = read_return_rate.full - disp_drain_rate.full; 3660 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff); 3661 } else { 3662 time_disp1_drop_priority.full = 0; 3663 } 3664 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full; 3665 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2); 3666 crit_point_ff.full += dfixed_const_half(0); 3667 3668 critical_point2 = dfixed_trunc(crit_point_ff); 3669 3670 if (rdev->disp_priority == 2) { 3671 critical_point2 = 0; 3672 } 3673 3674 if (max_stop_req - critical_point2 < 4) 3675 critical_point2 = 0; 3676 3677 } 3678 3679 if (critical_point2 == 0 && rdev->family == CHIP_R300) { 3680 /* some R300 cards have problem with this set to 0 */ 3681 critical_point2 = 0x10; 3682 } 3683 3684 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 3685 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 3686 3687 if ((rdev->family == CHIP_RS400) || 3688 (rdev->family == CHIP_RS480)) { 3689 #if 0 3690 /* attempt to program RS400 disp2 regs correctly ??? */ 3691 temp = RREG32(RS400_DISP2_REQ_CNTL1); 3692 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 3693 RS400_DISP2_STOP_REQ_LEVEL_MASK); 3694 WREG32(RS400_DISP2_REQ_CNTL1, (temp | 3695 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 3696 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 3697 temp = RREG32(RS400_DISP2_REQ_CNTL2); 3698 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 3699 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 3700 WREG32(RS400_DISP2_REQ_CNTL2, (temp | 3701 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 3702 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 3703 #endif 3704 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 3705 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000); 3706 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 3707 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 3708 } 3709 3710 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n", 3711 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL)); 3712 } 3713 } 3714 3715 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) 3716 { 3717 uint32_t scratch; 3718 uint32_t tmp = 0; 3719 unsigned i; 3720 int r; 3721 3722 r = radeon_scratch_get(rdev, &scratch); 3723 if (r) { 3724 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); 3725 return r; 3726 } 3727 WREG32(scratch, 0xCAFEDEAD); 3728 r = radeon_ring_lock(rdev, ring, 2); 3729 if (r) { 3730 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3731 radeon_scratch_free(rdev, scratch); 3732 return r; 3733 } 3734 radeon_ring_write(ring, PACKET0(scratch, 0)); 3735 radeon_ring_write(ring, 0xDEADBEEF); 3736 radeon_ring_unlock_commit(rdev, ring); 3737 for (i = 0; i < rdev->usec_timeout; i++) { 3738 tmp = RREG32(scratch); 3739 if (tmp == 0xDEADBEEF) { 3740 break; 3741 } 3742 DRM_UDELAY(1); 3743 } 3744 if (i < rdev->usec_timeout) { 3745 DRM_INFO("ring test succeeded in %d usecs\n", i); 3746 } else { 3747 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 3748 scratch, tmp); 3749 r = -EINVAL; 3750 } 3751 radeon_scratch_free(rdev, scratch); 3752 return r; 3753 } 3754 3755 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3756 { 3757 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3758 3759 if (ring->rptr_save_reg) { 3760 u32 next_rptr = ring->wptr + 2 + 3; 3761 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)); 3762 radeon_ring_write(ring, next_rptr); 3763 } 3764 3765 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)); 3766 radeon_ring_write(ring, ib->gpu_addr); 3767 radeon_ring_write(ring, ib->length_dw); 3768 } 3769 3770 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3771 { 3772 struct radeon_ib ib; 3773 uint32_t scratch; 3774 uint32_t tmp = 0; 3775 unsigned i; 3776 int r; 3777 3778 r = radeon_scratch_get(rdev, &scratch); 3779 if (r) { 3780 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); 3781 return r; 3782 } 3783 WREG32(scratch, 0xCAFEDEAD); 3784 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256); 3785 if (r) { 3786 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 3787 goto free_scratch; 3788 } 3789 ib.ptr[0] = PACKET0(scratch, 0); 3790 ib.ptr[1] = 0xDEADBEEF; 3791 ib.ptr[2] = PACKET2(0); 3792 ib.ptr[3] = PACKET2(0); 3793 ib.ptr[4] = PACKET2(0); 3794 ib.ptr[5] = PACKET2(0); 3795 ib.ptr[6] = PACKET2(0); 3796 ib.ptr[7] = PACKET2(0); 3797 ib.length_dw = 8; 3798 r = radeon_ib_schedule(rdev, &ib, NULL); 3799 if (r) { 3800 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r); 3801 goto free_ib; 3802 } 3803 r = radeon_fence_wait(ib.fence, false); 3804 if (r) { 3805 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3806 goto free_ib; 3807 } 3808 for (i = 0; i < rdev->usec_timeout; i++) { 3809 tmp = RREG32(scratch); 3810 if (tmp == 0xDEADBEEF) { 3811 break; 3812 } 3813 DRM_UDELAY(1); 3814 } 3815 if (i < rdev->usec_timeout) { 3816 DRM_INFO("ib test succeeded in %u usecs\n", i); 3817 } else { 3818 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 3819 scratch, tmp); 3820 r = -EINVAL; 3821 } 3822 free_ib: 3823 radeon_ib_free(rdev, &ib); 3824 free_scratch: 3825 radeon_scratch_free(rdev, scratch); 3826 return r; 3827 } 3828 3829 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) 3830 { 3831 /* Shutdown CP we shouldn't need to do that but better be safe than 3832 * sorry 3833 */ 3834 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; 3835 WREG32(R_000740_CP_CSQ_CNTL, 0); 3836 3837 /* Save few CRTC registers */ 3838 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT); 3839 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3840 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3841 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3842 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3843 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL); 3844 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET); 3845 } 3846 3847 /* Disable VGA aperture access */ 3848 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT); 3849 /* Disable cursor, overlay, crtc */ 3850 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3851 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3852 S_000054_CRTC_DISPLAY_DIS(1)); 3853 WREG32(R_000050_CRTC_GEN_CNTL, 3854 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) | 3855 S_000050_CRTC_DISP_REQ_EN_B(1)); 3856 WREG32(R_000420_OV0_SCALE_CNTL, 3857 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL)); 3858 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET); 3859 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3860 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET | 3861 S_000360_CUR2_LOCK(1)); 3862 WREG32(R_0003F8_CRTC2_GEN_CNTL, 3863 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) | 3864 S_0003F8_CRTC2_DISPLAY_DIS(1) | 3865 S_0003F8_CRTC2_DISP_REQ_EN_B(1)); 3866 WREG32(R_000360_CUR2_OFFSET, 3867 C_000360_CUR2_LOCK & save->CUR2_OFFSET); 3868 } 3869 } 3870 3871 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save) 3872 { 3873 /* Update base address for crtc */ 3874 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3875 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3876 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start); 3877 } 3878 /* Restore CRTC registers */ 3879 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT); 3880 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3881 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3882 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3883 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3884 } 3885 } 3886 3887 void r100_vga_render_disable(struct radeon_device *rdev) 3888 { 3889 u32 tmp; 3890 3891 tmp = RREG8(R_0003C2_GENMO_WT); 3892 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp); 3893 } 3894 3895 static void r100_debugfs(struct radeon_device *rdev) 3896 { 3897 int r; 3898 3899 r = r100_debugfs_mc_info_init(rdev); 3900 if (r) 3901 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n"); 3902 } 3903 3904 static void r100_mc_program(struct radeon_device *rdev) 3905 { 3906 struct r100_mc_save save; 3907 3908 /* Stops all mc clients */ 3909 r100_mc_stop(rdev, &save); 3910 if (rdev->flags & RADEON_IS_AGP) { 3911 WREG32(R_00014C_MC_AGP_LOCATION, 3912 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | 3913 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); 3914 WREG32(R_000170_AGP_BASE, (u32)(rdev->mc.agp_base)); 3915 if (rdev->family > CHIP_RV200) 3916 WREG32(R_00015C_AGP_BASE_2, 3917 upper_32_bits(rdev->mc.agp_base) & 0xff); 3918 } else { 3919 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF); 3920 WREG32(R_000170_AGP_BASE, 0); 3921 if (rdev->family > CHIP_RV200) 3922 WREG32(R_00015C_AGP_BASE_2, 0); 3923 } 3924 /* Wait for mc idle */ 3925 if (r100_mc_wait_for_idle(rdev)) 3926 dev_warn(rdev->dev, "Wait for MC idle timeout.\n"); 3927 /* Program MC, should be a 32bits limited address space */ 3928 WREG32(R_000148_MC_FB_LOCATION, 3929 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 3930 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 3931 r100_mc_resume(rdev, &save); 3932 } 3933 3934 static void r100_clock_startup(struct radeon_device *rdev) 3935 { 3936 u32 tmp; 3937 3938 if (radeon_dynclks != -1 && radeon_dynclks) 3939 radeon_legacy_set_clock_gating(rdev, 1); 3940 /* We need to force on some of the block */ 3941 tmp = RREG32_PLL(R_00000D_SCLK_CNTL); 3942 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); 3943 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280)) 3944 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1); 3945 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); 3946 } 3947 3948 static int r100_startup(struct radeon_device *rdev) 3949 { 3950 int r; 3951 3952 /* set common regs */ 3953 r100_set_common_regs(rdev); 3954 /* program mc */ 3955 r100_mc_program(rdev); 3956 /* Resume clock */ 3957 r100_clock_startup(rdev); 3958 /* Initialize GART (initialize after TTM so we can allocate 3959 * memory through TTM but finalize after TTM) */ 3960 r100_enable_bm(rdev); 3961 if (rdev->flags & RADEON_IS_PCI) { 3962 r = r100_pci_gart_enable(rdev); 3963 if (r) 3964 return r; 3965 } 3966 3967 /* allocate wb buffer */ 3968 r = radeon_wb_init(rdev); 3969 if (r) 3970 return r; 3971 3972 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); 3973 if (r) { 3974 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); 3975 return r; 3976 } 3977 3978 /* Enable IRQ */ 3979 if (!rdev->irq.installed) { 3980 r = radeon_irq_kms_init(rdev); 3981 if (r) 3982 return r; 3983 } 3984 3985 r100_irq_set(rdev); 3986 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3987 /* 1M ring buffer */ 3988 r = r100_cp_init(rdev, 1024 * 1024); 3989 if (r) { 3990 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); 3991 return r; 3992 } 3993 3994 r = radeon_ib_pool_init(rdev); 3995 if (r) { 3996 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 3997 return r; 3998 } 3999 4000 return 0; 4001 } 4002 4003 int r100_resume(struct radeon_device *rdev) 4004 { 4005 int r; 4006 4007 /* Make sur GART are not working */ 4008 if (rdev->flags & RADEON_IS_PCI) 4009 r100_pci_gart_disable(rdev); 4010 /* Resume clock before doing reset */ 4011 r100_clock_startup(rdev); 4012 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4013 if (radeon_asic_reset(rdev)) { 4014 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4015 RREG32(R_000E40_RBBM_STATUS), 4016 RREG32(R_0007C0_CP_STAT)); 4017 } 4018 /* post */ 4019 radeon_combios_asic_init(rdev->ddev); 4020 /* Resume clock after posting */ 4021 r100_clock_startup(rdev); 4022 /* Initialize surface registers */ 4023 radeon_surface_init(rdev); 4024 4025 rdev->accel_working = true; 4026 r = r100_startup(rdev); 4027 if (r) { 4028 rdev->accel_working = false; 4029 } 4030 return r; 4031 } 4032 4033 int r100_suspend(struct radeon_device *rdev) 4034 { 4035 r100_cp_disable(rdev); 4036 radeon_wb_disable(rdev); 4037 r100_irq_disable(rdev); 4038 if (rdev->flags & RADEON_IS_PCI) 4039 r100_pci_gart_disable(rdev); 4040 return 0; 4041 } 4042 4043 void r100_fini(struct radeon_device *rdev) 4044 { 4045 r100_cp_fini(rdev); 4046 radeon_wb_fini(rdev); 4047 radeon_ib_pool_fini(rdev); 4048 radeon_gem_fini(rdev); 4049 if (rdev->flags & RADEON_IS_PCI) 4050 r100_pci_gart_fini(rdev); 4051 radeon_agp_fini(rdev); 4052 radeon_irq_kms_fini(rdev); 4053 radeon_fence_driver_fini(rdev); 4054 radeon_bo_fini(rdev); 4055 radeon_atombios_fini(rdev); 4056 kfree(rdev->bios); 4057 rdev->bios = NULL; 4058 } 4059 4060 /* 4061 * Due to how kexec works, it can leave the hw fully initialised when it 4062 * boots the new kernel. However doing our init sequence with the CP and 4063 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup 4064 * do some quick sanity checks and restore sane values to avoid this 4065 * problem. 4066 */ 4067 void r100_restore_sanity(struct radeon_device *rdev) 4068 { 4069 u32 tmp; 4070 4071 tmp = RREG32(RADEON_CP_CSQ_CNTL); 4072 if (tmp) { 4073 WREG32(RADEON_CP_CSQ_CNTL, 0); 4074 } 4075 tmp = RREG32(RADEON_CP_RB_CNTL); 4076 if (tmp) { 4077 WREG32(RADEON_CP_RB_CNTL, 0); 4078 } 4079 tmp = RREG32(RADEON_SCRATCH_UMSK); 4080 if (tmp) { 4081 WREG32(RADEON_SCRATCH_UMSK, 0); 4082 } 4083 } 4084 4085 int r100_init(struct radeon_device *rdev) 4086 { 4087 int r; 4088 4089 /* Register debugfs file specific to this group of asics */ 4090 r100_debugfs(rdev); 4091 /* Disable VGA */ 4092 r100_vga_render_disable(rdev); 4093 /* Initialize scratch registers */ 4094 radeon_scratch_init(rdev); 4095 /* Initialize surface registers */ 4096 radeon_surface_init(rdev); 4097 /* sanity check some register to avoid hangs like after kexec */ 4098 r100_restore_sanity(rdev); 4099 /* TODO: disable VGA need to use VGA request */ 4100 /* BIOS*/ 4101 if (!radeon_get_bios(rdev)) { 4102 if (ASIC_IS_AVIVO(rdev)) 4103 return -EINVAL; 4104 } 4105 if (rdev->is_atom_bios) { 4106 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); 4107 return -EINVAL; 4108 } else { 4109 r = radeon_combios_init(rdev); 4110 if (r) 4111 return r; 4112 } 4113 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 4114 if (radeon_asic_reset(rdev)) { 4115 dev_warn(rdev->dev, 4116 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 4117 RREG32(R_000E40_RBBM_STATUS), 4118 RREG32(R_0007C0_CP_STAT)); 4119 } 4120 /* check if cards are posted or not */ 4121 if (radeon_boot_test_post_card(rdev) == false) 4122 return -EINVAL; 4123 /* Set asic errata */ 4124 r100_errata(rdev); 4125 /* Initialize clocks */ 4126 radeon_get_clock_info(rdev->ddev); 4127 /* initialize AGP */ 4128 if (rdev->flags & RADEON_IS_AGP) { 4129 r = radeon_agp_init(rdev); 4130 if (r) { 4131 radeon_agp_disable(rdev); 4132 } 4133 } 4134 /* initialize VRAM */ 4135 r100_mc_init(rdev); 4136 /* Fence driver */ 4137 r = radeon_fence_driver_init(rdev); 4138 if (r) 4139 return r; 4140 /* Memory manager */ 4141 r = radeon_bo_init(rdev); 4142 if (r) 4143 return r; 4144 if (rdev->flags & RADEON_IS_PCI) { 4145 r = r100_pci_gart_init(rdev); 4146 if (r) 4147 return r; 4148 } 4149 r100_set_safe_registers(rdev); 4150 4151 rdev->accel_working = true; 4152 r = r100_startup(rdev); 4153 if (r) { 4154 /* Somethings want wront with the accel init stop accel */ 4155 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 4156 r100_cp_fini(rdev); 4157 radeon_wb_fini(rdev); 4158 radeon_ib_pool_fini(rdev); 4159 radeon_irq_kms_fini(rdev); 4160 if (rdev->flags & RADEON_IS_PCI) 4161 r100_pci_gart_fini(rdev); 4162 rdev->accel_working = false; 4163 } 4164 return 0; 4165 } 4166 4167 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg, 4168 bool always_indirect) 4169 { 4170 if (reg < rdev->rmmio_size && !always_indirect) 4171 return bus_space_read_4(rdev->memt, rdev->rmmio, reg); 4172 4173 else { 4174 unsigned long flags; 4175 uint32_t ret; 4176 4177 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4178 bus_space_write_4(rdev->memt, rdev->rmmio, 4179 RADEON_MM_INDEX, reg); 4180 ret = bus_space_read_4(rdev->memt, rdev->rmmio, 4181 RADEON_MM_DATA); 4182 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4183 4184 return ret; 4185 } 4186 } 4187 4188 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v, 4189 bool always_indirect) 4190 { 4191 if (reg < rdev->rmmio_size && !always_indirect) 4192 bus_space_write_4(rdev->memt, rdev->rmmio, reg, v); 4193 else { 4194 unsigned long flags; 4195 4196 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 4197 bus_space_write_4(rdev->memt, rdev->rmmio, 4198 RADEON_MM_INDEX, reg); 4199 bus_space_write_4(rdev->memt, rdev->rmmio, 4200 RADEON_MM_DATA, v); 4201 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 4202 } 4203 } 4204 4205 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) 4206 { 4207 if (reg < rdev->rio_mem_size) 4208 return bus_space_read_4(rdev->iot, rdev->rio_mem, reg); 4209 else { 4210 bus_space_write_4(rdev->iot, rdev->rio_mem, 4211 RADEON_MM_INDEX, reg); 4212 return bus_space_read_4(rdev->iot, rdev->rio_mem, 4213 RADEON_MM_DATA); 4214 } 4215 } 4216 4217 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) 4218 { 4219 if (reg < rdev->rio_mem_size) 4220 bus_space_write_4(rdev->iot, rdev->rio_mem, reg, v); 4221 else { 4222 bus_space_write_4(rdev->iot, rdev->rio_mem, 4223 RADEON_MM_INDEX, reg); 4224 bus_space_write_4(rdev->iot, rdev->rio_mem, 4225 RADEON_MM_DATA, v); 4226 } 4227 } 4228