1 /* $OpenBSD: evergreen_hdmi.c,v 1.2 2014/02/09 13:43:02 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * Copyright 2009 Christian König. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Christian König 26 * Rafał Miłecki 27 */ 28 #include <dev/pci/drm/drmP.h> 29 #include <dev/pci/drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "radeon_asic.h" 32 #include "evergreend.h" 33 #include "atom.h" 34 35 /* 36 * update the N and CTS parameters for a given pixel clock rate 37 */ 38 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) 39 { 40 struct drm_device *dev = encoder->dev; 41 struct radeon_device *rdev = dev->dev_private; 42 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock); 43 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 44 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 45 uint32_t offset = dig->afmt->offset; 46 47 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz)); 48 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz); 49 50 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz)); 51 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz); 52 53 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz)); 54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 55 } 56 57 /* 58 * calculate the crc for a given info frame 59 */ 60 static void evergreen_hdmi_infoframe_checksum(uint8_t packetType, 61 uint8_t versionNumber, 62 uint8_t length, 63 uint8_t *frame) 64 { 65 int i; 66 frame[0] = packetType + versionNumber + length; 67 for (i = 1; i <= length; i++) 68 frame[0] += frame[i]; 69 frame[0] = 0x100 - frame[0]; 70 } 71 72 /* 73 * build a HDMI Video Info Frame 74 */ 75 static void evergreen_hdmi_videoinfoframe( 76 struct drm_encoder *encoder, 77 uint8_t color_format, 78 int active_information_present, 79 uint8_t active_format_aspect_ratio, 80 uint8_t scan_information, 81 uint8_t colorimetry, 82 uint8_t ex_colorimetry, 83 uint8_t quantization, 84 int ITC, 85 uint8_t picture_aspect_ratio, 86 uint8_t video_format_identification, 87 uint8_t pixel_repetition, 88 uint8_t non_uniform_picture_scaling, 89 uint8_t bar_info_data_valid, 90 uint16_t top_bar, 91 uint16_t bottom_bar, 92 uint16_t left_bar, 93 uint16_t right_bar 94 ) 95 { 96 struct drm_device *dev = encoder->dev; 97 struct radeon_device *rdev = dev->dev_private; 98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 99 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 100 uint32_t offset = dig->afmt->offset; 101 102 uint8_t frame[14]; 103 104 frame[0x0] = 0; 105 frame[0x1] = 106 (scan_information & 0x3) | 107 ((bar_info_data_valid & 0x3) << 2) | 108 ((active_information_present & 0x1) << 4) | 109 ((color_format & 0x3) << 5); 110 frame[0x2] = 111 (active_format_aspect_ratio & 0xF) | 112 ((picture_aspect_ratio & 0x3) << 4) | 113 ((colorimetry & 0x3) << 6); 114 frame[0x3] = 115 (non_uniform_picture_scaling & 0x3) | 116 ((quantization & 0x3) << 2) | 117 ((ex_colorimetry & 0x7) << 4) | 118 ((ITC & 0x1) << 7); 119 frame[0x4] = (video_format_identification & 0x7F); 120 frame[0x5] = (pixel_repetition & 0xF); 121 frame[0x6] = (top_bar & 0xFF); 122 frame[0x7] = (top_bar >> 8); 123 frame[0x8] = (bottom_bar & 0xFF); 124 frame[0x9] = (bottom_bar >> 8); 125 frame[0xA] = (left_bar & 0xFF); 126 frame[0xB] = (left_bar >> 8); 127 frame[0xC] = (right_bar & 0xFF); 128 frame[0xD] = (right_bar >> 8); 129 130 evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); 131 /* Our header values (type, version, length) should be alright, Intel 132 * is using the same. Checksum function also seems to be OK, it works 133 * fine for audio infoframe. However calculated value is always lower 134 * by 2 in comparison to fglrx. It breaks displaying anything in case 135 * of TVs that strictly check the checksum. Hack it manually here to 136 * workaround this issue. */ 137 frame[0x0] += 2; 138 139 WREG32(AFMT_AVI_INFO0 + offset, 140 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 141 WREG32(AFMT_AVI_INFO1 + offset, 142 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 143 WREG32(AFMT_AVI_INFO2 + offset, 144 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 145 WREG32(AFMT_AVI_INFO3 + offset, 146 frame[0xC] | (frame[0xD] << 8)); 147 } 148 149 /* 150 * update the info frames with the data from the current display mode 151 */ 152 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) 153 { 154 struct drm_device *dev = encoder->dev; 155 struct radeon_device *rdev = dev->dev_private; 156 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 157 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 158 uint32_t offset; 159 160 if (!dig || !dig->afmt) 161 return; 162 163 /* Silent, r600_hdmi_enable will raise WARN for us */ 164 if (!dig->afmt->enabled) 165 return; 166 offset = dig->afmt->offset; 167 168 r600_audio_set_clock(encoder, mode->clock); 169 170 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 171 HDMI_NULL_SEND); /* send null packets when required */ 172 173 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 174 175 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, 176 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ 177 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ 178 179 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, 180 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ 181 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 182 183 WREG32(HDMI_ACR_PACKET_CONTROL + offset, 184 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ 185 HDMI_ACR_SOURCE); /* select SW CTS value */ 186 187 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 188 HDMI_NULL_SEND | /* send null packets when required */ 189 HDMI_GC_SEND | /* send general control packets */ 190 HDMI_GC_CONT); /* send general control packets every frame */ 191 192 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 193 HDMI_AVI_INFO_SEND | /* enable AVI info frames */ 194 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */ 195 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 196 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 197 198 WREG32(AFMT_INFOFRAME_CONTROL0 + offset, 199 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 200 201 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 202 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */ 203 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 204 205 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 206 207 evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 208 0, 0, 0, 0, 0, 0); 209 210 evergreen_hdmi_update_ACR(encoder, mode->clock); 211 212 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 213 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 214 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 215 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 216 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 217 } 218