1 /* $OpenBSD: atombios_encoders.c,v 1.9 2015/04/18 14:47:34 jsg Exp $ */ 2 /* 3 * Copyright 2007-11 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 #include <dev/pci/drm/drmP.h> 28 #include <dev/pci/drm/drm_crtc_helper.h> 29 #include <dev/pci/drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "atom.h" 32 33 extern int atom_debug; 34 35 static u8 36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 37 { 38 u8 backlight_level; 39 u32 bios_2_scratch; 40 41 if (rdev->family >= CHIP_R600) 42 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 43 else 44 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 45 46 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 47 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 48 49 return backlight_level; 50 } 51 52 static void 53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 54 u8 backlight_level) 55 { 56 u32 bios_2_scratch; 57 58 if (rdev->family >= CHIP_R600) 59 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 60 else 61 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 62 63 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 64 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 65 ATOM_S2_CURRENT_BL_LEVEL_MASK); 66 67 if (rdev->family >= CHIP_R600) 68 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 69 else 70 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 71 } 72 73 u8 74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 75 { 76 struct drm_device *dev = radeon_encoder->base.dev; 77 struct radeon_device *rdev = dev->dev_private; 78 79 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 80 return 0; 81 82 return radeon_atom_get_backlight_level_from_reg(rdev); 83 } 84 85 void 86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 87 { 88 struct drm_encoder *encoder = &radeon_encoder->base; 89 struct drm_device *dev = radeon_encoder->base.dev; 90 struct radeon_device *rdev = dev->dev_private; 91 struct radeon_encoder_atom_dig *dig; 92 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 93 int index; 94 95 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 96 return; 97 98 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 99 radeon_encoder->enc_priv) { 100 dig = radeon_encoder->enc_priv; 101 dig->backlight_level = level; 102 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 103 104 switch (radeon_encoder->encoder_id) { 105 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 106 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 107 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 108 if (dig->backlight_level == 0) { 109 args.ucAction = ATOM_LCD_BLOFF; 110 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 111 } else { 112 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 113 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 114 args.ucAction = ATOM_LCD_BLON; 115 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 116 } 117 break; 118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 119 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 120 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 121 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 122 if (dig->backlight_level == 0) 123 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 124 else { 125 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 126 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 127 } 128 break; 129 default: 130 break; 131 } 132 } 133 } 134 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 136 137 static u8 radeon_atom_bl_level(struct backlight_device *bd) 138 { 139 u8 level; 140 141 /* Convert brightness to hardware level */ 142 if (bd->props.brightness < 0) 143 level = 0; 144 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 145 level = RADEON_MAX_BL_LEVEL; 146 else 147 level = bd->props.brightness; 148 149 return level; 150 } 151 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 153 { 154 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 155 struct radeon_encoder *radeon_encoder = pdata->encoder; 156 157 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 158 159 return 0; 160 } 161 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 163 { 164 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 165 struct radeon_encoder *radeon_encoder = pdata->encoder; 166 struct drm_device *dev = radeon_encoder->base.dev; 167 struct radeon_device *rdev = dev->dev_private; 168 169 return radeon_atom_get_backlight_level_from_reg(rdev); 170 } 171 172 static const struct backlight_ops radeon_atom_backlight_ops = { 173 .get_brightness = radeon_atom_backlight_get_brightness, 174 .update_status = radeon_atom_backlight_update_status, 175 }; 176 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 178 struct drm_connector *drm_connector) 179 { 180 struct drm_device *dev = radeon_encoder->base.dev; 181 struct radeon_device *rdev = dev->dev_private; 182 struct backlight_device *bd; 183 struct backlight_properties props; 184 struct radeon_backlight_privdata *pdata; 185 struct radeon_encoder_atom_dig *dig; 186 u8 backlight_level; 187 char bl_name[16]; 188 189 if (!radeon_encoder->enc_priv) 190 return; 191 192 if (!rdev->is_atom_bios) 193 return; 194 195 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 196 return; 197 198 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 199 if (!pdata) { 200 DRM_ERROR("Memory allocation failed\n"); 201 goto error; 202 } 203 204 memset(&props, 0, sizeof(props)); 205 props.max_brightness = RADEON_MAX_BL_LEVEL; 206 props.type = BACKLIGHT_RAW; 207 snprintf(bl_name, sizeof(bl_name), 208 "radeon_bl%d", dev->primary->index); 209 bd = backlight_device_register(bl_name, &drm_connector->kdev, 210 pdata, &radeon_atom_backlight_ops, &props); 211 if (IS_ERR(bd)) { 212 DRM_ERROR("Backlight registration failed\n"); 213 goto error; 214 } 215 216 pdata->encoder = radeon_encoder; 217 218 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 219 220 dig = radeon_encoder->enc_priv; 221 dig->bl_dev = bd; 222 223 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 224 bd->props.power = FB_BLANK_UNBLANK; 225 backlight_update_status(bd); 226 227 DRM_INFO("radeon atom DIG backlight initialized\n"); 228 229 return; 230 231 error: 232 kfree(pdata); 233 return; 234 } 235 236 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 237 { 238 struct drm_device *dev = radeon_encoder->base.dev; 239 struct radeon_device *rdev = dev->dev_private; 240 struct backlight_device *bd = NULL; 241 struct radeon_encoder_atom_dig *dig; 242 243 if (!radeon_encoder->enc_priv) 244 return; 245 246 if (!rdev->is_atom_bios) 247 return; 248 249 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 250 return; 251 252 dig = radeon_encoder->enc_priv; 253 bd = dig->bl_dev; 254 dig->bl_dev = NULL; 255 256 if (bd) { 257 struct radeon_legacy_backlight_privdata *pdata; 258 259 pdata = bl_get_data(bd); 260 backlight_device_unregister(bd); 261 kfree(pdata); 262 263 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 264 } 265 } 266 267 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 268 269 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 270 { 271 } 272 273 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 274 { 275 } 276 277 #endif 278 279 /* evil but including atombios.h is much worse */ 280 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 281 struct drm_display_mode *mode); 282 283 284 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 285 { 286 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 287 switch (radeon_encoder->encoder_id) { 288 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 289 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 290 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 291 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 292 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 293 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 294 case ENCODER_OBJECT_ID_INTERNAL_DDI: 295 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 296 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 297 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 299 return true; 300 default: 301 return false; 302 } 303 } 304 305 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 306 const struct drm_display_mode *mode, 307 struct drm_display_mode *adjusted_mode) 308 { 309 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 310 struct drm_device *dev = encoder->dev; 311 struct radeon_device *rdev = dev->dev_private; 312 313 /* set the active encoder to connector routing */ 314 radeon_encoder_set_active_device(encoder); 315 drm_mode_set_crtcinfo(adjusted_mode, 0); 316 317 /* hw bug */ 318 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 319 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 320 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 321 322 /* get the native mode for LVDS */ 323 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 324 radeon_panel_mode_fixup(encoder, adjusted_mode); 325 326 /* get the native mode for TV */ 327 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 328 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 329 if (tv_dac) { 330 if (tv_dac->tv_std == TV_STD_NTSC || 331 tv_dac->tv_std == TV_STD_NTSC_J || 332 tv_dac->tv_std == TV_STD_PAL_M) 333 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 334 else 335 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 336 } 337 } 338 339 if (ASIC_IS_DCE3(rdev) && 340 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 341 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 342 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 343 radeon_dp_set_link_config(connector, adjusted_mode); 344 } 345 346 return true; 347 } 348 349 static void 350 atombios_dac_setup(struct drm_encoder *encoder, int action) 351 { 352 struct drm_device *dev = encoder->dev; 353 struct radeon_device *rdev = dev->dev_private; 354 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 355 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 356 int index = 0; 357 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 358 359 memset(&args, 0, sizeof(args)); 360 361 switch (radeon_encoder->encoder_id) { 362 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 363 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 364 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 365 break; 366 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 367 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 368 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 369 break; 370 } 371 372 args.ucAction = action; 373 374 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 375 args.ucDacStandard = ATOM_DAC1_PS2; 376 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 377 args.ucDacStandard = ATOM_DAC1_CV; 378 else { 379 switch (dac_info->tv_std) { 380 case TV_STD_PAL: 381 case TV_STD_PAL_M: 382 case TV_STD_SCART_PAL: 383 case TV_STD_SECAM: 384 case TV_STD_PAL_CN: 385 args.ucDacStandard = ATOM_DAC1_PAL; 386 break; 387 case TV_STD_NTSC: 388 case TV_STD_NTSC_J: 389 case TV_STD_PAL_60: 390 default: 391 args.ucDacStandard = ATOM_DAC1_NTSC; 392 break; 393 } 394 } 395 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 396 397 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 398 399 } 400 401 static void 402 atombios_tv_setup(struct drm_encoder *encoder, int action) 403 { 404 struct drm_device *dev = encoder->dev; 405 struct radeon_device *rdev = dev->dev_private; 406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 407 TV_ENCODER_CONTROL_PS_ALLOCATION args; 408 int index = 0; 409 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 410 411 memset(&args, 0, sizeof(args)); 412 413 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 414 415 args.sTVEncoder.ucAction = action; 416 417 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 418 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 419 else { 420 switch (dac_info->tv_std) { 421 case TV_STD_NTSC: 422 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 423 break; 424 case TV_STD_PAL: 425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 426 break; 427 case TV_STD_PAL_M: 428 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 429 break; 430 case TV_STD_PAL_60: 431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 432 break; 433 case TV_STD_NTSC_J: 434 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 435 break; 436 case TV_STD_SCART_PAL: 437 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 438 break; 439 case TV_STD_SECAM: 440 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 441 break; 442 case TV_STD_PAL_CN: 443 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 444 break; 445 default: 446 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 447 break; 448 } 449 } 450 451 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 452 453 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 454 455 } 456 457 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 458 { 459 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 460 int bpc = 8; 461 462 if (connector) 463 bpc = radeon_get_monitor_bpc(connector); 464 465 switch (bpc) { 466 case 0: 467 return PANEL_BPC_UNDEFINE; 468 case 6: 469 return PANEL_6BIT_PER_COLOR; 470 case 8: 471 default: 472 return PANEL_8BIT_PER_COLOR; 473 case 10: 474 return PANEL_10BIT_PER_COLOR; 475 case 12: 476 return PANEL_12BIT_PER_COLOR; 477 case 16: 478 return PANEL_16BIT_PER_COLOR; 479 } 480 } 481 482 483 union dvo_encoder_control { 484 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 485 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 486 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 487 }; 488 489 void 490 atombios_dvo_setup(struct drm_encoder *encoder, int action) 491 { 492 struct drm_device *dev = encoder->dev; 493 struct radeon_device *rdev = dev->dev_private; 494 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 495 union dvo_encoder_control args; 496 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 497 uint8_t frev, crev; 498 499 memset(&args, 0, sizeof(args)); 500 501 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 502 return; 503 504 /* some R4xx chips have the wrong frev */ 505 if (rdev->family <= CHIP_RV410) 506 frev = 1; 507 508 switch (frev) { 509 case 1: 510 switch (crev) { 511 case 1: 512 /* R4xx, R5xx */ 513 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 514 515 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 516 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 517 518 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 519 break; 520 case 2: 521 /* RS600/690/740 */ 522 args.dvo.sDVOEncoder.ucAction = action; 523 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 524 /* DFP1, CRT1, TV1 depending on the type of port */ 525 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 526 527 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 528 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 529 break; 530 case 3: 531 /* R6xx */ 532 args.dvo_v3.ucAction = action; 533 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 534 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 535 break; 536 default: 537 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 538 break; 539 } 540 break; 541 default: 542 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 543 break; 544 } 545 546 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 547 } 548 549 union lvds_encoder_control { 550 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 551 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 552 }; 553 554 void 555 atombios_digital_setup(struct drm_encoder *encoder, int action) 556 { 557 struct drm_device *dev = encoder->dev; 558 struct radeon_device *rdev = dev->dev_private; 559 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 560 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 561 union lvds_encoder_control args; 562 int index = 0; 563 int hdmi_detected = 0; 564 uint8_t frev, crev; 565 566 if (!dig) 567 return; 568 569 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 570 hdmi_detected = 1; 571 572 memset(&args, 0, sizeof(args)); 573 574 switch (radeon_encoder->encoder_id) { 575 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 576 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 577 break; 578 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 579 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 580 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 581 break; 582 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 583 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 584 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 585 else 586 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 587 break; 588 } 589 590 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 591 return; 592 593 switch (frev) { 594 case 1: 595 case 2: 596 switch (crev) { 597 case 1: 598 args.v1.ucMisc = 0; 599 args.v1.ucAction = action; 600 if (hdmi_detected) 601 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 602 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 604 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 605 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 606 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 607 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 608 } else { 609 if (dig->linkb) 610 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 611 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 612 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 613 /*if (pScrn->rgbBits == 8) */ 614 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 615 } 616 break; 617 case 2: 618 case 3: 619 args.v2.ucMisc = 0; 620 args.v2.ucAction = action; 621 if (crev == 3) { 622 if (dig->coherent_mode) 623 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 624 } 625 if (hdmi_detected) 626 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 627 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 628 args.v2.ucTruncate = 0; 629 args.v2.ucSpatial = 0; 630 args.v2.ucTemporal = 0; 631 args.v2.ucFRC = 0; 632 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 633 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 634 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 635 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 636 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 637 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 638 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 639 } 640 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 641 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 642 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 643 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 644 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 645 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 646 } 647 } else { 648 if (dig->linkb) 649 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 650 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 651 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 652 } 653 break; 654 default: 655 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 656 break; 657 } 658 break; 659 default: 660 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 661 break; 662 } 663 664 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 665 } 666 667 int 668 atombios_get_encoder_mode(struct drm_encoder *encoder) 669 { 670 struct drm_device *dev = encoder->dev; 671 struct radeon_device *rdev = dev->dev_private; 672 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 673 struct drm_connector *connector; 674 struct radeon_connector *radeon_connector; 675 struct radeon_connector_atom_dig *dig_connector; 676 677 /* dp bridges are always DP */ 678 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 679 return ATOM_ENCODER_MODE_DP; 680 681 /* DVO is always DVO */ 682 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 683 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 684 return ATOM_ENCODER_MODE_DVO; 685 686 connector = radeon_get_connector_for_encoder(encoder); 687 /* if we don't have an active device yet, just use one of 688 * the connectors tied to the encoder. 689 */ 690 if (!connector) 691 connector = radeon_get_connector_for_encoder_init(encoder); 692 radeon_connector = to_radeon_connector(connector); 693 694 switch (connector->connector_type) { 695 case DRM_MODE_CONNECTOR_DVII: 696 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 697 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 698 radeon_audio && 699 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 700 return ATOM_ENCODER_MODE_HDMI; 701 else if (radeon_connector->use_digital) 702 return ATOM_ENCODER_MODE_DVI; 703 else 704 return ATOM_ENCODER_MODE_CRT; 705 break; 706 case DRM_MODE_CONNECTOR_DVID: 707 case DRM_MODE_CONNECTOR_HDMIA: 708 default: 709 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 710 radeon_audio && 711 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 712 return ATOM_ENCODER_MODE_HDMI; 713 else 714 return ATOM_ENCODER_MODE_DVI; 715 break; 716 case DRM_MODE_CONNECTOR_LVDS: 717 return ATOM_ENCODER_MODE_LVDS; 718 break; 719 case DRM_MODE_CONNECTOR_DisplayPort: 720 dig_connector = radeon_connector->con_priv; 721 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 722 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 723 return ATOM_ENCODER_MODE_DP; 724 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 725 radeon_audio && 726 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 727 return ATOM_ENCODER_MODE_HDMI; 728 else 729 return ATOM_ENCODER_MODE_DVI; 730 break; 731 case DRM_MODE_CONNECTOR_eDP: 732 return ATOM_ENCODER_MODE_DP; 733 case DRM_MODE_CONNECTOR_DVIA: 734 case DRM_MODE_CONNECTOR_VGA: 735 return ATOM_ENCODER_MODE_CRT; 736 break; 737 case DRM_MODE_CONNECTOR_Composite: 738 case DRM_MODE_CONNECTOR_SVIDEO: 739 case DRM_MODE_CONNECTOR_9PinDIN: 740 /* fix me */ 741 return ATOM_ENCODER_MODE_TV; 742 /*return ATOM_ENCODER_MODE_CV;*/ 743 break; 744 } 745 } 746 747 /* 748 * DIG Encoder/Transmitter Setup 749 * 750 * DCE 3.0/3.1 751 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 752 * Supports up to 3 digital outputs 753 * - 2 DIG encoder blocks. 754 * DIG1 can drive UNIPHY link A or link B 755 * DIG2 can drive UNIPHY link B or LVTMA 756 * 757 * DCE 3.2 758 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 759 * Supports up to 5 digital outputs 760 * - 2 DIG encoder blocks. 761 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 762 * 763 * DCE 4.0/5.0/6.0 764 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 765 * Supports up to 6 digital outputs 766 * - 6 DIG encoder blocks. 767 * - DIG to PHY mapping is hardcoded 768 * DIG1 drives UNIPHY0 link A, A+B 769 * DIG2 drives UNIPHY0 link B 770 * DIG3 drives UNIPHY1 link A, A+B 771 * DIG4 drives UNIPHY1 link B 772 * DIG5 drives UNIPHY2 link A, A+B 773 * DIG6 drives UNIPHY2 link B 774 * 775 * DCE 4.1 776 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 777 * Supports up to 6 digital outputs 778 * - 2 DIG encoder blocks. 779 * llano 780 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 781 * ontario 782 * DIG1 drives UNIPHY0/1/2 link A 783 * DIG2 drives UNIPHY0/1/2 link B 784 * 785 * Routing 786 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 787 * Examples: 788 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 789 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 790 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 791 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 792 */ 793 794 union dig_encoder_control { 795 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 796 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 797 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 798 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 799 }; 800 801 void 802 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 803 { 804 struct drm_device *dev = encoder->dev; 805 struct radeon_device *rdev = dev->dev_private; 806 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 807 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 808 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 809 union dig_encoder_control args; 810 int index = 0; 811 uint8_t frev, crev; 812 int dp_clock = 0; 813 int dp_lane_count = 0; 814 int hpd_id = RADEON_HPD_NONE; 815 816 if (connector) { 817 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 818 struct radeon_connector_atom_dig *dig_connector = 819 radeon_connector->con_priv; 820 821 dp_clock = dig_connector->dp_clock; 822 dp_lane_count = dig_connector->dp_lane_count; 823 hpd_id = radeon_connector->hpd.hpd; 824 } 825 826 /* no dig encoder assigned */ 827 if (dig->dig_encoder == -1) 828 return; 829 830 memset(&args, 0, sizeof(args)); 831 832 if (ASIC_IS_DCE4(rdev)) 833 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 834 else { 835 if (dig->dig_encoder) 836 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 837 else 838 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 839 } 840 841 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 842 return; 843 844 switch (frev) { 845 case 1: 846 switch (crev) { 847 case 1: 848 args.v1.ucAction = action; 849 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 850 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 851 args.v3.ucPanelMode = panel_mode; 852 else 853 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 854 855 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 856 args.v1.ucLaneNum = dp_lane_count; 857 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 858 args.v1.ucLaneNum = 8; 859 else 860 args.v1.ucLaneNum = 4; 861 862 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 863 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 864 switch (radeon_encoder->encoder_id) { 865 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 866 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 867 break; 868 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 869 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 870 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 871 break; 872 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 873 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 874 break; 875 } 876 if (dig->linkb) 877 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 878 else 879 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 880 break; 881 case 2: 882 case 3: 883 args.v3.ucAction = action; 884 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 885 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 886 args.v3.ucPanelMode = panel_mode; 887 else 888 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 889 890 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 891 args.v3.ucLaneNum = dp_lane_count; 892 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 893 args.v3.ucLaneNum = 8; 894 else 895 args.v3.ucLaneNum = 4; 896 897 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 898 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 899 args.v3.acConfig.ucDigSel = dig->dig_encoder; 900 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 901 break; 902 case 4: 903 args.v4.ucAction = action; 904 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 905 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 906 args.v4.ucPanelMode = panel_mode; 907 else 908 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 909 910 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 911 args.v4.ucLaneNum = dp_lane_count; 912 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 913 args.v4.ucLaneNum = 8; 914 else 915 args.v4.ucLaneNum = 4; 916 917 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 918 if (dp_clock == 270000) 919 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 920 else if (dp_clock == 540000) 921 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 922 } 923 args.v4.acConfig.ucDigSel = dig->dig_encoder; 924 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 925 if (hpd_id == RADEON_HPD_NONE) 926 args.v4.ucHPD_ID = 0; 927 else 928 args.v4.ucHPD_ID = hpd_id + 1; 929 break; 930 default: 931 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 932 break; 933 } 934 break; 935 default: 936 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 937 break; 938 } 939 940 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 941 942 } 943 944 union dig_transmitter_control { 945 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 946 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 947 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 948 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 949 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 950 }; 951 952 void 953 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 954 { 955 struct drm_device *dev = encoder->dev; 956 struct radeon_device *rdev = dev->dev_private; 957 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 958 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 959 struct drm_connector *connector; 960 union dig_transmitter_control args; 961 int index = 0; 962 uint8_t frev, crev; 963 bool is_dp = false; 964 int pll_id = 0; 965 int dp_clock = 0; 966 int dp_lane_count = 0; 967 int connector_object_id = 0; 968 int igp_lane_info = 0; 969 int dig_encoder = dig->dig_encoder; 970 int hpd_id = RADEON_HPD_NONE; 971 972 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 973 connector = radeon_get_connector_for_encoder_init(encoder); 974 /* just needed to avoid bailing in the encoder check. the encoder 975 * isn't used for init 976 */ 977 dig_encoder = 0; 978 } else 979 connector = radeon_get_connector_for_encoder(encoder); 980 981 if (connector) { 982 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 983 struct radeon_connector_atom_dig *dig_connector = 984 radeon_connector->con_priv; 985 986 hpd_id = radeon_connector->hpd.hpd; 987 dp_clock = dig_connector->dp_clock; 988 dp_lane_count = dig_connector->dp_lane_count; 989 connector_object_id = 990 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 991 igp_lane_info = dig_connector->igp_lane_info; 992 } 993 994 if (encoder->crtc) { 995 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 996 pll_id = radeon_crtc->pll_id; 997 } 998 999 /* no dig encoder assigned */ 1000 if (dig_encoder == -1) 1001 return; 1002 1003 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1004 is_dp = true; 1005 1006 memset(&args, 0, sizeof(args)); 1007 1008 switch (radeon_encoder->encoder_id) { 1009 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1010 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1011 break; 1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1013 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1014 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1015 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1016 break; 1017 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1018 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1019 break; 1020 } 1021 1022 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1023 return; 1024 1025 switch (frev) { 1026 case 1: 1027 switch (crev) { 1028 case 1: 1029 args.v1.ucAction = action; 1030 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1031 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1032 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1033 args.v1.asMode.ucLaneSel = lane_num; 1034 args.v1.asMode.ucLaneSet = lane_set; 1035 } else { 1036 if (is_dp) 1037 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1038 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1039 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1040 else 1041 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1042 } 1043 1044 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1045 1046 if (dig_encoder) 1047 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1048 else 1049 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1050 1051 if ((rdev->flags & RADEON_IS_IGP) && 1052 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1053 if (is_dp || 1054 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1055 if (igp_lane_info & 0x1) 1056 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1057 else if (igp_lane_info & 0x2) 1058 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1059 else if (igp_lane_info & 0x4) 1060 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1061 else if (igp_lane_info & 0x8) 1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1063 } else { 1064 if (igp_lane_info & 0x3) 1065 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1066 else if (igp_lane_info & 0xc) 1067 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1068 } 1069 } 1070 1071 if (dig->linkb) 1072 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1073 else 1074 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1075 1076 if (is_dp) 1077 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1078 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1079 if (dig->coherent_mode) 1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1081 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1082 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1083 } 1084 break; 1085 case 2: 1086 args.v2.ucAction = action; 1087 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1088 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1089 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1090 args.v2.asMode.ucLaneSel = lane_num; 1091 args.v2.asMode.ucLaneSet = lane_set; 1092 } else { 1093 if (is_dp) 1094 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1095 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1096 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1097 else 1098 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1099 } 1100 1101 args.v2.acConfig.ucEncoderSel = dig_encoder; 1102 if (dig->linkb) 1103 args.v2.acConfig.ucLinkSel = 1; 1104 1105 switch (radeon_encoder->encoder_id) { 1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1107 args.v2.acConfig.ucTransmitterSel = 0; 1108 break; 1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1110 args.v2.acConfig.ucTransmitterSel = 1; 1111 break; 1112 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1113 args.v2.acConfig.ucTransmitterSel = 2; 1114 break; 1115 } 1116 1117 if (is_dp) { 1118 args.v2.acConfig.fCoherentMode = 1; 1119 args.v2.acConfig.fDPConnector = 1; 1120 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1121 if (dig->coherent_mode) 1122 args.v2.acConfig.fCoherentMode = 1; 1123 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1124 args.v2.acConfig.fDualLinkConnector = 1; 1125 } 1126 break; 1127 case 3: 1128 args.v3.ucAction = action; 1129 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1130 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1131 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1132 args.v3.asMode.ucLaneSel = lane_num; 1133 args.v3.asMode.ucLaneSet = lane_set; 1134 } else { 1135 if (is_dp) 1136 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1137 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1138 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1139 else 1140 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1141 } 1142 1143 if (is_dp) 1144 args.v3.ucLaneNum = dp_lane_count; 1145 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1146 args.v3.ucLaneNum = 8; 1147 else 1148 args.v3.ucLaneNum = 4; 1149 1150 if (dig->linkb) 1151 args.v3.acConfig.ucLinkSel = 1; 1152 if (dig_encoder & 1) 1153 args.v3.acConfig.ucEncoderSel = 1; 1154 1155 /* Select the PLL for the PHY 1156 * DP PHY should be clocked from external src if there is 1157 * one. 1158 */ 1159 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1160 if (is_dp && rdev->clock.dp_extclk) 1161 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1162 else 1163 args.v3.acConfig.ucRefClkSource = pll_id; 1164 1165 switch (radeon_encoder->encoder_id) { 1166 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1167 args.v3.acConfig.ucTransmitterSel = 0; 1168 break; 1169 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1170 args.v3.acConfig.ucTransmitterSel = 1; 1171 break; 1172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1173 args.v3.acConfig.ucTransmitterSel = 2; 1174 break; 1175 } 1176 1177 if (is_dp) 1178 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1179 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1180 if (dig->coherent_mode) 1181 args.v3.acConfig.fCoherentMode = 1; 1182 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1183 args.v3.acConfig.fDualLinkConnector = 1; 1184 } 1185 break; 1186 case 4: 1187 args.v4.ucAction = action; 1188 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1189 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1190 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1191 args.v4.asMode.ucLaneSel = lane_num; 1192 args.v4.asMode.ucLaneSet = lane_set; 1193 } else { 1194 if (is_dp) 1195 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1196 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1197 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1198 else 1199 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1200 } 1201 1202 if (is_dp) 1203 args.v4.ucLaneNum = dp_lane_count; 1204 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1205 args.v4.ucLaneNum = 8; 1206 else 1207 args.v4.ucLaneNum = 4; 1208 1209 if (dig->linkb) 1210 args.v4.acConfig.ucLinkSel = 1; 1211 if (dig_encoder & 1) 1212 args.v4.acConfig.ucEncoderSel = 1; 1213 1214 /* Select the PLL for the PHY 1215 * DP PHY should be clocked from external src if there is 1216 * one. 1217 */ 1218 /* On DCE5 DCPLL usually generates the DP ref clock */ 1219 if (is_dp) { 1220 if (rdev->clock.dp_extclk) 1221 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1222 else 1223 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1224 } else 1225 args.v4.acConfig.ucRefClkSource = pll_id; 1226 1227 switch (radeon_encoder->encoder_id) { 1228 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1229 args.v4.acConfig.ucTransmitterSel = 0; 1230 break; 1231 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1232 args.v4.acConfig.ucTransmitterSel = 1; 1233 break; 1234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1235 args.v4.acConfig.ucTransmitterSel = 2; 1236 break; 1237 } 1238 1239 if (is_dp) 1240 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1241 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1242 if (dig->coherent_mode) 1243 args.v4.acConfig.fCoherentMode = 1; 1244 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1245 args.v4.acConfig.fDualLinkConnector = 1; 1246 } 1247 break; 1248 case 5: 1249 args.v5.ucAction = action; 1250 if (is_dp) 1251 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1252 else 1253 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1254 1255 switch (radeon_encoder->encoder_id) { 1256 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1257 if (dig->linkb) 1258 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1259 else 1260 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1261 break; 1262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1263 if (dig->linkb) 1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1265 else 1266 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1267 break; 1268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1269 if (dig->linkb) 1270 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1271 else 1272 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1273 break; 1274 } 1275 if (is_dp) 1276 args.v5.ucLaneNum = dp_lane_count; 1277 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1278 args.v5.ucLaneNum = 8; 1279 else 1280 args.v5.ucLaneNum = 4; 1281 args.v5.ucConnObjId = connector_object_id; 1282 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1283 1284 if (is_dp && rdev->clock.dp_extclk) 1285 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1286 else 1287 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1288 1289 if (is_dp) 1290 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1291 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1292 if (dig->coherent_mode) 1293 args.v5.asConfig.ucCoherentMode = 1; 1294 } 1295 if (hpd_id == RADEON_HPD_NONE) 1296 args.v5.asConfig.ucHPDSel = 0; 1297 else 1298 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1299 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1300 args.v5.ucDPLaneSet = lane_set; 1301 break; 1302 default: 1303 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1304 break; 1305 } 1306 break; 1307 default: 1308 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1309 break; 1310 } 1311 1312 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1313 } 1314 1315 bool 1316 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1317 { 1318 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1319 struct drm_device *dev = radeon_connector->base.dev; 1320 struct radeon_device *rdev = dev->dev_private; 1321 union dig_transmitter_control args; 1322 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1323 uint8_t frev, crev; 1324 1325 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1326 goto done; 1327 1328 if (!ASIC_IS_DCE4(rdev)) 1329 goto done; 1330 1331 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1332 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1333 goto done; 1334 1335 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1336 goto done; 1337 1338 memset(&args, 0, sizeof(args)); 1339 1340 args.v1.ucAction = action; 1341 1342 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1343 1344 /* wait for the panel to power up */ 1345 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1346 int i; 1347 1348 for (i = 0; i < 300; i++) { 1349 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1350 return true; 1351 mdelay(1); 1352 } 1353 return false; 1354 } 1355 done: 1356 return true; 1357 } 1358 1359 union external_encoder_control { 1360 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1361 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1362 }; 1363 1364 static void 1365 atombios_external_encoder_setup(struct drm_encoder *encoder, 1366 struct drm_encoder *ext_encoder, 1367 int action) 1368 { 1369 struct drm_device *dev = encoder->dev; 1370 struct radeon_device *rdev = dev->dev_private; 1371 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1372 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1373 union external_encoder_control args; 1374 struct drm_connector *connector; 1375 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1376 u8 frev, crev; 1377 int dp_clock = 0; 1378 int dp_lane_count = 0; 1379 int connector_object_id = 0; 1380 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1381 1382 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1383 connector = radeon_get_connector_for_encoder_init(encoder); 1384 else 1385 connector = radeon_get_connector_for_encoder(encoder); 1386 1387 if (connector) { 1388 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1389 struct radeon_connector_atom_dig *dig_connector = 1390 radeon_connector->con_priv; 1391 1392 dp_clock = dig_connector->dp_clock; 1393 dp_lane_count = dig_connector->dp_lane_count; 1394 connector_object_id = 1395 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1396 } 1397 1398 memset(&args, 0, sizeof(args)); 1399 1400 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1401 return; 1402 1403 switch (frev) { 1404 case 1: 1405 /* no params on frev 1 */ 1406 break; 1407 case 2: 1408 switch (crev) { 1409 case 1: 1410 case 2: 1411 args.v1.sDigEncoder.ucAction = action; 1412 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1413 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1414 1415 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1416 if (dp_clock == 270000) 1417 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1418 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1419 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1420 args.v1.sDigEncoder.ucLaneNum = 8; 1421 else 1422 args.v1.sDigEncoder.ucLaneNum = 4; 1423 break; 1424 case 3: 1425 args.v3.sExtEncoder.ucAction = action; 1426 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1427 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1428 else 1429 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1430 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1431 1432 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1433 if (dp_clock == 270000) 1434 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1435 else if (dp_clock == 540000) 1436 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1437 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1438 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1439 args.v3.sExtEncoder.ucLaneNum = 8; 1440 else 1441 args.v3.sExtEncoder.ucLaneNum = 4; 1442 switch (ext_enum) { 1443 case GRAPH_OBJECT_ENUM_ID1: 1444 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1445 break; 1446 case GRAPH_OBJECT_ENUM_ID2: 1447 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1448 break; 1449 case GRAPH_OBJECT_ENUM_ID3: 1450 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1451 break; 1452 } 1453 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1454 break; 1455 default: 1456 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1457 return; 1458 } 1459 break; 1460 default: 1461 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1462 return; 1463 } 1464 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1465 } 1466 1467 static void 1468 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1469 { 1470 struct drm_device *dev = encoder->dev; 1471 struct radeon_device *rdev = dev->dev_private; 1472 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1473 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1474 ENABLE_YUV_PS_ALLOCATION args; 1475 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1476 uint32_t temp, reg; 1477 1478 memset(&args, 0, sizeof(args)); 1479 1480 if (rdev->family >= CHIP_R600) 1481 reg = R600_BIOS_3_SCRATCH; 1482 else 1483 reg = RADEON_BIOS_3_SCRATCH; 1484 1485 /* XXX: fix up scratch reg handling */ 1486 temp = RREG32(reg); 1487 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1488 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1489 (radeon_crtc->crtc_id << 18))); 1490 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1491 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1492 else 1493 WREG32(reg, 0); 1494 1495 if (enable) 1496 args.ucEnable = ATOM_ENABLE; 1497 args.ucCRTC = radeon_crtc->crtc_id; 1498 1499 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1500 1501 WREG32(reg, temp); 1502 } 1503 1504 static void 1505 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1506 { 1507 struct drm_device *dev = encoder->dev; 1508 struct radeon_device *rdev = dev->dev_private; 1509 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1510 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1511 int index = 0; 1512 1513 memset(&args, 0, sizeof(args)); 1514 1515 switch (radeon_encoder->encoder_id) { 1516 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1518 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1519 break; 1520 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1521 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1522 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1523 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1524 break; 1525 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1526 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1527 break; 1528 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1529 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1530 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1531 else 1532 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1533 break; 1534 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1535 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1536 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1537 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1538 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1539 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1540 else 1541 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1542 break; 1543 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1544 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1545 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1546 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1547 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1548 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1549 else 1550 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1551 break; 1552 default: 1553 return; 1554 } 1555 1556 switch (mode) { 1557 case DRM_MODE_DPMS_ON: 1558 args.ucAction = ATOM_ENABLE; 1559 /* workaround for DVOOutputControl on some RS690 systems */ 1560 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1561 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1562 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1563 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1564 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1565 } else 1566 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1567 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1568 args.ucAction = ATOM_LCD_BLON; 1569 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1570 } 1571 break; 1572 case DRM_MODE_DPMS_STANDBY: 1573 case DRM_MODE_DPMS_SUSPEND: 1574 case DRM_MODE_DPMS_OFF: 1575 args.ucAction = ATOM_DISABLE; 1576 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1577 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1578 args.ucAction = ATOM_LCD_BLOFF; 1579 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1580 } 1581 break; 1582 } 1583 } 1584 1585 static void 1586 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1587 { 1588 struct drm_device *dev = encoder->dev; 1589 struct radeon_device *rdev = dev->dev_private; 1590 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1591 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1592 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1593 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1594 struct radeon_connector *radeon_connector = NULL; 1595 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1596 1597 if (connector) { 1598 radeon_connector = to_radeon_connector(connector); 1599 radeon_dig_connector = radeon_connector->con_priv; 1600 } 1601 1602 switch (mode) { 1603 case DRM_MODE_DPMS_ON: 1604 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1605 if (!connector) 1606 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1607 else 1608 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1609 1610 /* setup and enable the encoder */ 1611 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1612 atombios_dig_encoder_setup(encoder, 1613 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1614 dig->panel_mode); 1615 if (ext_encoder) { 1616 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1617 atombios_external_encoder_setup(encoder, ext_encoder, 1618 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1619 } 1620 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1621 } else if (ASIC_IS_DCE4(rdev)) { 1622 /* setup and enable the encoder */ 1623 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1624 /* enable the transmitter */ 1625 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1627 } else { 1628 /* setup and enable the encoder and transmitter */ 1629 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1630 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1631 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1632 /* some dce3.x boards have a bug in their transmitter control table. 1633 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE 1634 * does the same thing and more. 1635 */ 1636 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) && 1637 (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880)) 1638 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1639 } 1640 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1641 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1642 atombios_set_edp_panel_power(connector, 1643 ATOM_TRANSMITTER_ACTION_POWER_ON); 1644 radeon_dig_connector->edp_on = true; 1645 } 1646 radeon_dp_link_train(encoder, connector); 1647 if (ASIC_IS_DCE4(rdev)) 1648 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1649 } 1650 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1651 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1652 break; 1653 case DRM_MODE_DPMS_STANDBY: 1654 case DRM_MODE_DPMS_SUSPEND: 1655 case DRM_MODE_DPMS_OFF: 1656 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1657 /* disable the transmitter */ 1658 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1659 } else if (ASIC_IS_DCE4(rdev)) { 1660 /* disable the transmitter */ 1661 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1662 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1663 } else { 1664 /* disable the encoder and transmitter */ 1665 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1666 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1667 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1668 } 1669 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1670 if (ASIC_IS_DCE4(rdev)) 1671 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1672 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1673 atombios_set_edp_panel_power(connector, 1674 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1675 radeon_dig_connector->edp_on = false; 1676 } 1677 } 1678 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1679 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1680 break; 1681 } 1682 } 1683 1684 static void 1685 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1686 struct drm_encoder *ext_encoder, 1687 int mode) 1688 { 1689 struct drm_device *dev = encoder->dev; 1690 struct radeon_device *rdev = dev->dev_private; 1691 1692 switch (mode) { 1693 case DRM_MODE_DPMS_ON: 1694 default: 1695 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1696 atombios_external_encoder_setup(encoder, ext_encoder, 1697 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1698 atombios_external_encoder_setup(encoder, ext_encoder, 1699 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1700 } else 1701 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1702 break; 1703 case DRM_MODE_DPMS_STANDBY: 1704 case DRM_MODE_DPMS_SUSPEND: 1705 case DRM_MODE_DPMS_OFF: 1706 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1707 atombios_external_encoder_setup(encoder, ext_encoder, 1708 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1709 atombios_external_encoder_setup(encoder, ext_encoder, 1710 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1711 } else 1712 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1713 break; 1714 } 1715 } 1716 1717 static void 1718 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1719 { 1720 struct drm_device *dev = encoder->dev; 1721 struct radeon_device *rdev = dev->dev_private; 1722 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1723 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1724 1725 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1726 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1727 radeon_encoder->active_device); 1728 switch (radeon_encoder->encoder_id) { 1729 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1730 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1731 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1732 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1733 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1734 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1735 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1736 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1737 radeon_atom_encoder_dpms_avivo(encoder, mode); 1738 break; 1739 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1740 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1741 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1742 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1743 radeon_atom_encoder_dpms_dig(encoder, mode); 1744 break; 1745 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1746 if (ASIC_IS_DCE5(rdev)) { 1747 switch (mode) { 1748 case DRM_MODE_DPMS_ON: 1749 atombios_dvo_setup(encoder, ATOM_ENABLE); 1750 break; 1751 case DRM_MODE_DPMS_STANDBY: 1752 case DRM_MODE_DPMS_SUSPEND: 1753 case DRM_MODE_DPMS_OFF: 1754 atombios_dvo_setup(encoder, ATOM_DISABLE); 1755 break; 1756 } 1757 } else if (ASIC_IS_DCE3(rdev)) 1758 radeon_atom_encoder_dpms_dig(encoder, mode); 1759 else 1760 radeon_atom_encoder_dpms_avivo(encoder, mode); 1761 break; 1762 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1763 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1764 if (ASIC_IS_DCE5(rdev)) { 1765 switch (mode) { 1766 case DRM_MODE_DPMS_ON: 1767 atombios_dac_setup(encoder, ATOM_ENABLE); 1768 break; 1769 case DRM_MODE_DPMS_STANDBY: 1770 case DRM_MODE_DPMS_SUSPEND: 1771 case DRM_MODE_DPMS_OFF: 1772 atombios_dac_setup(encoder, ATOM_DISABLE); 1773 break; 1774 } 1775 } else 1776 radeon_atom_encoder_dpms_avivo(encoder, mode); 1777 break; 1778 default: 1779 return; 1780 } 1781 1782 if (ext_encoder) 1783 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1784 1785 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1786 1787 } 1788 1789 union crtc_source_param { 1790 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1791 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1792 }; 1793 1794 static void 1795 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1796 { 1797 struct drm_device *dev = encoder->dev; 1798 struct radeon_device *rdev = dev->dev_private; 1799 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1800 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1801 union crtc_source_param args; 1802 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1803 uint8_t frev, crev; 1804 struct radeon_encoder_atom_dig *dig; 1805 1806 memset(&args, 0, sizeof(args)); 1807 1808 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1809 return; 1810 1811 switch (frev) { 1812 case 1: 1813 switch (crev) { 1814 case 1: 1815 default: 1816 if (ASIC_IS_AVIVO(rdev)) 1817 args.v1.ucCRTC = radeon_crtc->crtc_id; 1818 else { 1819 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1820 args.v1.ucCRTC = radeon_crtc->crtc_id; 1821 } else { 1822 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1823 } 1824 } 1825 switch (radeon_encoder->encoder_id) { 1826 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1827 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1828 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1829 break; 1830 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1831 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1832 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1833 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1834 else 1835 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1836 break; 1837 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1838 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1839 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1840 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1841 break; 1842 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1843 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1844 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1845 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1846 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1847 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1848 else 1849 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1850 break; 1851 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1852 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1853 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1854 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1855 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1856 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1857 else 1858 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1859 break; 1860 } 1861 break; 1862 case 2: 1863 args.v2.ucCRTC = radeon_crtc->crtc_id; 1864 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1865 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1866 1867 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1868 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1869 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1870 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1871 else 1872 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1873 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1874 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1875 } else { 1876 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1877 } 1878 switch (radeon_encoder->encoder_id) { 1879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1881 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1882 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1883 dig = radeon_encoder->enc_priv; 1884 switch (dig->dig_encoder) { 1885 case 0: 1886 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1887 break; 1888 case 1: 1889 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1890 break; 1891 case 2: 1892 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1893 break; 1894 case 3: 1895 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1896 break; 1897 case 4: 1898 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1899 break; 1900 case 5: 1901 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1902 break; 1903 } 1904 break; 1905 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1906 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1907 break; 1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1909 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1910 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1911 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1912 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1913 else 1914 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1915 break; 1916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1917 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1918 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1919 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1920 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1921 else 1922 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1923 break; 1924 } 1925 break; 1926 } 1927 break; 1928 default: 1929 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1930 return; 1931 } 1932 1933 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1934 1935 /* update scratch regs with new routing */ 1936 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1937 } 1938 1939 static void 1940 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1941 struct drm_display_mode *mode) 1942 { 1943 struct drm_device *dev = encoder->dev; 1944 struct radeon_device *rdev = dev->dev_private; 1945 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1946 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1947 1948 /* Funky macbooks */ 1949 if ((dev->pdev->device == 0x71C5) && 1950 (dev->pdev->subsystem_vendor == 0x106b) && 1951 (dev->pdev->subsystem_device == 0x0080)) { 1952 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1953 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1954 1955 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1956 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1957 1958 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1959 } 1960 } 1961 1962 /* set scaler clears this on some chips */ 1963 if (ASIC_IS_AVIVO(rdev) && 1964 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1965 if (ASIC_IS_DCE4(rdev)) { 1966 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1967 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1968 EVERGREEN_INTERLEAVE_EN); 1969 else 1970 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1971 } else { 1972 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1973 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1974 AVIVO_D1MODE_INTERLEAVE_EN); 1975 else 1976 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1977 } 1978 } 1979 } 1980 1981 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1982 { 1983 struct drm_device *dev = encoder->dev; 1984 struct radeon_device *rdev = dev->dev_private; 1985 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1986 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1987 struct drm_encoder *test_encoder; 1988 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1989 uint32_t dig_enc_in_use = 0; 1990 1991 if (ASIC_IS_DCE6(rdev)) { 1992 /* DCE6 */ 1993 switch (radeon_encoder->encoder_id) { 1994 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1995 if (dig->linkb) 1996 return 1; 1997 else 1998 return 0; 1999 break; 2000 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2001 if (dig->linkb) 2002 return 3; 2003 else 2004 return 2; 2005 break; 2006 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2007 if (dig->linkb) 2008 return 5; 2009 else 2010 return 4; 2011 break; 2012 } 2013 } else if (ASIC_IS_DCE4(rdev)) { 2014 /* DCE4/5 */ 2015 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2016 /* ontario follows DCE4 */ 2017 if (rdev->family == CHIP_PALM) { 2018 if (dig->linkb) 2019 return 1; 2020 else 2021 return 0; 2022 } else 2023 /* llano follows DCE3.2 */ 2024 return radeon_crtc->crtc_id; 2025 } else { 2026 switch (radeon_encoder->encoder_id) { 2027 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2028 if (dig->linkb) 2029 return 1; 2030 else 2031 return 0; 2032 break; 2033 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2034 if (dig->linkb) 2035 return 3; 2036 else 2037 return 2; 2038 break; 2039 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2040 if (dig->linkb) 2041 return 5; 2042 else 2043 return 4; 2044 break; 2045 } 2046 } 2047 } 2048 2049 /* on DCE32 and encoder can driver any block so just crtc id */ 2050 if (ASIC_IS_DCE32(rdev)) { 2051 return radeon_crtc->crtc_id; 2052 } 2053 2054 /* on DCE3 - LVTMA can only be driven by DIGB */ 2055 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2056 struct radeon_encoder *radeon_test_encoder; 2057 2058 if (encoder == test_encoder) 2059 continue; 2060 2061 if (!radeon_encoder_is_digital(test_encoder)) 2062 continue; 2063 2064 radeon_test_encoder = to_radeon_encoder(test_encoder); 2065 dig = radeon_test_encoder->enc_priv; 2066 2067 if (dig->dig_encoder >= 0) 2068 dig_enc_in_use |= (1 << dig->dig_encoder); 2069 } 2070 2071 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2072 if (dig_enc_in_use & 0x2) 2073 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2074 return 1; 2075 } 2076 if (!(dig_enc_in_use & 1)) 2077 return 0; 2078 return 1; 2079 } 2080 2081 /* This only needs to be called once at startup */ 2082 void 2083 radeon_atom_encoder_init(struct radeon_device *rdev) 2084 { 2085 struct drm_device *dev = rdev->ddev; 2086 struct drm_encoder *encoder; 2087 2088 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2089 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2090 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2091 2092 switch (radeon_encoder->encoder_id) { 2093 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2094 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2095 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2096 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2097 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2098 break; 2099 default: 2100 break; 2101 } 2102 2103 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2104 atombios_external_encoder_setup(encoder, ext_encoder, 2105 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2106 } 2107 } 2108 2109 static void 2110 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2111 struct drm_display_mode *mode, 2112 struct drm_display_mode *adjusted_mode) 2113 { 2114 struct drm_device *dev = encoder->dev; 2115 struct radeon_device *rdev = dev->dev_private; 2116 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2117 2118 radeon_encoder->pixel_clock = adjusted_mode->clock; 2119 2120 /* need to call this here rather than in prepare() since we need some crtc info */ 2121 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2122 2123 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2124 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2125 atombios_yuv_setup(encoder, true); 2126 else 2127 atombios_yuv_setup(encoder, false); 2128 } 2129 2130 switch (radeon_encoder->encoder_id) { 2131 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2132 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2133 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2134 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2135 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2136 break; 2137 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2138 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2139 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2140 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2141 /* handled in dpms */ 2142 break; 2143 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2144 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2145 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2146 atombios_dvo_setup(encoder, ATOM_ENABLE); 2147 break; 2148 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2149 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2150 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2151 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2152 atombios_dac_setup(encoder, ATOM_ENABLE); 2153 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2154 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2155 atombios_tv_setup(encoder, ATOM_ENABLE); 2156 else 2157 atombios_tv_setup(encoder, ATOM_DISABLE); 2158 } 2159 break; 2160 } 2161 2162 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2163 2164 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2165 r600_hdmi_enable(encoder); 2166 if (ASIC_IS_DCE6(rdev)) 2167 ; /* TODO (use pointers instead of if-s?) */ 2168 else if (ASIC_IS_DCE4(rdev)) 2169 evergreen_hdmi_setmode(encoder, adjusted_mode); 2170 else 2171 r600_hdmi_setmode(encoder, adjusted_mode); 2172 } 2173 } 2174 2175 static bool 2176 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2177 { 2178 struct drm_device *dev = encoder->dev; 2179 struct radeon_device *rdev = dev->dev_private; 2180 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2181 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2182 2183 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2184 ATOM_DEVICE_CV_SUPPORT | 2185 ATOM_DEVICE_CRT_SUPPORT)) { 2186 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2187 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2188 uint8_t frev, crev; 2189 2190 memset(&args, 0, sizeof(args)); 2191 2192 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2193 return false; 2194 2195 args.sDacload.ucMisc = 0; 2196 2197 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2198 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2199 args.sDacload.ucDacType = ATOM_DAC_A; 2200 else 2201 args.sDacload.ucDacType = ATOM_DAC_B; 2202 2203 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2204 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2205 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2206 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2207 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2208 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2209 if (crev >= 3) 2210 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2211 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2212 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2213 if (crev >= 3) 2214 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2215 } 2216 2217 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2218 2219 return true; 2220 } else 2221 return false; 2222 } 2223 2224 static enum drm_connector_status 2225 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2226 { 2227 struct drm_device *dev = encoder->dev; 2228 struct radeon_device *rdev = dev->dev_private; 2229 #ifdef DRMDEBUG 2230 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2231 #endif 2232 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2233 uint32_t bios_0_scratch; 2234 2235 if (!atombios_dac_load_detect(encoder, connector)) { 2236 DRM_DEBUG_KMS("detect returned false \n"); 2237 return connector_status_unknown; 2238 } 2239 2240 if (rdev->family >= CHIP_R600) 2241 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2242 else 2243 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2244 2245 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2246 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2247 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2248 return connector_status_connected; 2249 } 2250 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2251 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2252 return connector_status_connected; 2253 } 2254 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2255 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2256 return connector_status_connected; 2257 } 2258 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2259 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2260 return connector_status_connected; /* CTV */ 2261 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2262 return connector_status_connected; /* STV */ 2263 } 2264 return connector_status_disconnected; 2265 } 2266 2267 static enum drm_connector_status 2268 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2269 { 2270 struct drm_device *dev = encoder->dev; 2271 struct radeon_device *rdev = dev->dev_private; 2272 #ifdef DRMDEBUG 2273 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2274 #endif 2275 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2276 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2277 u32 bios_0_scratch; 2278 2279 if (!ASIC_IS_DCE4(rdev)) 2280 return connector_status_unknown; 2281 2282 if (!ext_encoder) 2283 return connector_status_unknown; 2284 2285 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2286 return connector_status_unknown; 2287 2288 /* load detect on the dp bridge */ 2289 atombios_external_encoder_setup(encoder, ext_encoder, 2290 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2291 2292 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2293 2294 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2295 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2296 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2297 return connector_status_connected; 2298 } 2299 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2300 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2301 return connector_status_connected; 2302 } 2303 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2304 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2305 return connector_status_connected; 2306 } 2307 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2308 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2309 return connector_status_connected; /* CTV */ 2310 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2311 return connector_status_connected; /* STV */ 2312 } 2313 return connector_status_disconnected; 2314 } 2315 2316 void 2317 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2318 { 2319 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2320 2321 if (ext_encoder) 2322 /* ddc_setup on the dp bridge */ 2323 atombios_external_encoder_setup(encoder, ext_encoder, 2324 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2325 2326 } 2327 2328 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2329 { 2330 struct radeon_device *rdev = encoder->dev->dev_private; 2331 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2332 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2333 2334 if ((radeon_encoder->active_device & 2335 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2336 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2337 ENCODER_OBJECT_ID_NONE)) { 2338 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2339 if (dig) { 2340 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2341 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2342 if (rdev->family >= CHIP_R600) 2343 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2344 else 2345 /* RS600/690/740 have only 1 afmt block */ 2346 dig->afmt = rdev->mode_info.afmt[0]; 2347 } 2348 } 2349 } 2350 2351 radeon_atom_output_lock(encoder, true); 2352 2353 if (connector) { 2354 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2355 2356 /* select the clock/data port if it uses a router */ 2357 if (radeon_connector->router.cd_valid) 2358 radeon_router_select_cd_port(radeon_connector); 2359 2360 /* turn eDP panel on for mode set */ 2361 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2362 atombios_set_edp_panel_power(connector, 2363 ATOM_TRANSMITTER_ACTION_POWER_ON); 2364 } 2365 2366 /* this is needed for the pll/ss setup to work correctly in some cases */ 2367 atombios_set_encoder_crtc_source(encoder); 2368 } 2369 2370 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2371 { 2372 /* need to call this here as we need the crtc set up */ 2373 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2374 radeon_atom_output_lock(encoder, false); 2375 } 2376 2377 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2378 { 2379 struct drm_device *dev = encoder->dev; 2380 struct radeon_device *rdev = dev->dev_private; 2381 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2382 struct radeon_encoder_atom_dig *dig; 2383 2384 /* check for pre-DCE3 cards with shared encoders; 2385 * can't really use the links individually, so don't disable 2386 * the encoder if it's in use by another connector 2387 */ 2388 if (!ASIC_IS_DCE3(rdev)) { 2389 struct drm_encoder *other_encoder; 2390 struct radeon_encoder *other_radeon_encoder; 2391 2392 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2393 other_radeon_encoder = to_radeon_encoder(other_encoder); 2394 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2395 drm_helper_encoder_in_use(other_encoder)) 2396 goto disable_done; 2397 } 2398 } 2399 2400 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2401 2402 switch (radeon_encoder->encoder_id) { 2403 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2404 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2405 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2406 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2407 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2408 break; 2409 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2410 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2411 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2412 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2413 /* handled in dpms */ 2414 break; 2415 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2416 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2417 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2418 atombios_dvo_setup(encoder, ATOM_DISABLE); 2419 break; 2420 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2421 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2422 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2423 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2424 atombios_dac_setup(encoder, ATOM_DISABLE); 2425 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2426 atombios_tv_setup(encoder, ATOM_DISABLE); 2427 break; 2428 } 2429 2430 disable_done: 2431 if (radeon_encoder_is_digital(encoder)) { 2432 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2433 r600_hdmi_disable(encoder); 2434 dig = radeon_encoder->enc_priv; 2435 dig->dig_encoder = -1; 2436 } 2437 radeon_encoder->active_device = 0; 2438 } 2439 2440 /* these are handled by the primary encoders */ 2441 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2442 { 2443 2444 } 2445 2446 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2447 { 2448 2449 } 2450 2451 static void 2452 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2453 struct drm_display_mode *mode, 2454 struct drm_display_mode *adjusted_mode) 2455 { 2456 2457 } 2458 2459 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2460 { 2461 2462 } 2463 2464 static void 2465 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2466 { 2467 2468 } 2469 2470 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2471 const struct drm_display_mode *mode, 2472 struct drm_display_mode *adjusted_mode) 2473 { 2474 return true; 2475 } 2476 2477 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2478 .dpms = radeon_atom_ext_dpms, 2479 .mode_fixup = radeon_atom_ext_mode_fixup, 2480 .prepare = radeon_atom_ext_prepare, 2481 .mode_set = radeon_atom_ext_mode_set, 2482 .commit = radeon_atom_ext_commit, 2483 .disable = radeon_atom_ext_disable, 2484 /* no detect for TMDS/LVDS yet */ 2485 }; 2486 2487 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2488 .dpms = radeon_atom_encoder_dpms, 2489 .mode_fixup = radeon_atom_mode_fixup, 2490 .prepare = radeon_atom_encoder_prepare, 2491 .mode_set = radeon_atom_encoder_mode_set, 2492 .commit = radeon_atom_encoder_commit, 2493 .disable = radeon_atom_encoder_disable, 2494 .detect = radeon_atom_dig_detect, 2495 }; 2496 2497 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2498 .dpms = radeon_atom_encoder_dpms, 2499 .mode_fixup = radeon_atom_mode_fixup, 2500 .prepare = radeon_atom_encoder_prepare, 2501 .mode_set = radeon_atom_encoder_mode_set, 2502 .commit = radeon_atom_encoder_commit, 2503 .detect = radeon_atom_dac_detect, 2504 }; 2505 2506 void radeon_enc_destroy(struct drm_encoder *encoder) 2507 { 2508 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2509 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2510 radeon_atom_backlight_exit(radeon_encoder); 2511 kfree(radeon_encoder->enc_priv); 2512 drm_encoder_cleanup(encoder); 2513 kfree(radeon_encoder); 2514 } 2515 2516 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2517 .destroy = radeon_enc_destroy, 2518 }; 2519 2520 static struct radeon_encoder_atom_dac * 2521 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2522 { 2523 struct drm_device *dev = radeon_encoder->base.dev; 2524 struct radeon_device *rdev = dev->dev_private; 2525 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2526 2527 if (!dac) 2528 return NULL; 2529 2530 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2531 return dac; 2532 } 2533 2534 static struct radeon_encoder_atom_dig * 2535 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2536 { 2537 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2538 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2539 2540 if (!dig) 2541 return NULL; 2542 2543 /* coherent mode by default */ 2544 dig->coherent_mode = true; 2545 dig->dig_encoder = -1; 2546 2547 if (encoder_enum == 2) 2548 dig->linkb = true; 2549 else 2550 dig->linkb = false; 2551 2552 return dig; 2553 } 2554 2555 void 2556 radeon_add_atom_encoder(struct drm_device *dev, 2557 uint32_t encoder_enum, 2558 uint32_t supported_device, 2559 u16 caps) 2560 { 2561 struct radeon_device *rdev = dev->dev_private; 2562 struct drm_encoder *encoder; 2563 struct radeon_encoder *radeon_encoder; 2564 2565 /* see if we already added it */ 2566 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2567 radeon_encoder = to_radeon_encoder(encoder); 2568 if (radeon_encoder->encoder_enum == encoder_enum) { 2569 radeon_encoder->devices |= supported_device; 2570 return; 2571 } 2572 2573 } 2574 2575 /* add a new one */ 2576 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2577 if (!radeon_encoder) 2578 return; 2579 2580 encoder = &radeon_encoder->base; 2581 switch (rdev->num_crtc) { 2582 case 1: 2583 encoder->possible_crtcs = 0x1; 2584 break; 2585 case 2: 2586 default: 2587 encoder->possible_crtcs = 0x3; 2588 break; 2589 case 4: 2590 encoder->possible_crtcs = 0xf; 2591 break; 2592 case 6: 2593 encoder->possible_crtcs = 0x3f; 2594 break; 2595 } 2596 2597 radeon_encoder->enc_priv = NULL; 2598 2599 radeon_encoder->encoder_enum = encoder_enum; 2600 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2601 radeon_encoder->devices = supported_device; 2602 radeon_encoder->rmx_type = RMX_OFF; 2603 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2604 radeon_encoder->is_ext_encoder = false; 2605 radeon_encoder->caps = caps; 2606 2607 switch (radeon_encoder->encoder_id) { 2608 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2609 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2610 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2611 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2612 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2613 radeon_encoder->rmx_type = RMX_FULL; 2614 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2615 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2616 } else { 2617 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2618 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2619 } 2620 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2621 break; 2622 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2623 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2624 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2625 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2626 break; 2627 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2628 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2629 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2630 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2631 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2632 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2633 break; 2634 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2635 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2636 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2637 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2638 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2639 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2640 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2641 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2642 radeon_encoder->rmx_type = RMX_FULL; 2643 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2644 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2645 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2646 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2647 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2648 } else { 2649 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2650 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2651 } 2652 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2653 break; 2654 case ENCODER_OBJECT_ID_SI170B: 2655 case ENCODER_OBJECT_ID_CH7303: 2656 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2657 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2658 case ENCODER_OBJECT_ID_TITFP513: 2659 case ENCODER_OBJECT_ID_VT1623: 2660 case ENCODER_OBJECT_ID_HDMI_SI1930: 2661 case ENCODER_OBJECT_ID_TRAVIS: 2662 case ENCODER_OBJECT_ID_NUTMEG: 2663 /* these are handled by the primary encoders */ 2664 radeon_encoder->is_ext_encoder = true; 2665 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2666 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2667 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2668 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2669 else 2670 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2671 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2672 break; 2673 } 2674 } 2675