1 /* $OpenBSD: atombios_encoders.c,v 1.7 2014/04/12 06:05:53 jsg Exp $ */ 2 /* 3 * Copyright 2007-11 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 #include <dev/pci/drm/drmP.h> 28 #include <dev/pci/drm/drm_crtc_helper.h> 29 #include <dev/pci/drm/radeon_drm.h> 30 #include "radeon.h" 31 #include "atom.h" 32 33 extern int atom_debug; 34 35 u8 atombios_get_backlight_level(struct radeon_encoder *); 36 void atombios_set_backlight_level(struct radeon_encoder *, u8); 37 void radeon_atom_backlight_init(struct radeon_encoder *); 38 void radeon_add_atom_encoder(struct drm_device *, uint32_t, 39 uint32_t, u16); 40 41 static u8 42 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev) 43 { 44 u8 backlight_level; 45 u32 bios_2_scratch; 46 47 if (rdev->family >= CHIP_R600) 48 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 49 else 50 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 51 52 backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >> 53 ATOM_S2_CURRENT_BL_LEVEL_SHIFT); 54 55 return backlight_level; 56 } 57 58 static void 59 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev, 60 u8 backlight_level) 61 { 62 u32 bios_2_scratch; 63 64 if (rdev->family >= CHIP_R600) 65 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); 66 else 67 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); 68 69 bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK; 70 bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) & 71 ATOM_S2_CURRENT_BL_LEVEL_MASK); 72 73 if (rdev->family >= CHIP_R600) 74 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); 75 else 76 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); 77 } 78 79 u8 80 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder) 81 { 82 struct drm_device *dev = radeon_encoder->base.dev; 83 struct radeon_device *rdev = dev->dev_private; 84 85 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 86 return 0; 87 88 return radeon_atom_get_backlight_level_from_reg(rdev); 89 } 90 91 void 92 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 93 { 94 struct drm_encoder *encoder = &radeon_encoder->base; 95 struct drm_device *dev = radeon_encoder->base.dev; 96 struct radeon_device *rdev = dev->dev_private; 97 struct radeon_encoder_atom_dig *dig; 98 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 99 int index; 100 101 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 102 return; 103 104 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && 105 radeon_encoder->enc_priv) { 106 dig = radeon_encoder->enc_priv; 107 dig->backlight_level = level; 108 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level); 109 110 switch (radeon_encoder->encoder_id) { 111 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 112 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 113 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 114 if (dig->backlight_level == 0) { 115 args.ucAction = ATOM_LCD_BLOFF; 116 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 117 } else { 118 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL; 119 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 120 args.ucAction = ATOM_LCD_BLON; 121 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 122 } 123 break; 124 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 125 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 126 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 127 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 128 if (dig->backlight_level == 0) 129 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 130 else { 131 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0); 132 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 133 } 134 break; 135 default: 136 break; 137 } 138 } 139 } 140 141 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 142 143 static u8 radeon_atom_bl_level(struct backlight_device *bd) 144 { 145 u8 level; 146 147 /* Convert brightness to hardware level */ 148 if (bd->props.brightness < 0) 149 level = 0; 150 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 151 level = RADEON_MAX_BL_LEVEL; 152 else 153 level = bd->props.brightness; 154 155 return level; 156 } 157 158 static int radeon_atom_backlight_update_status(struct backlight_device *bd) 159 { 160 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 161 struct radeon_encoder *radeon_encoder = pdata->encoder; 162 163 atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd)); 164 165 return 0; 166 } 167 168 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd) 169 { 170 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 171 struct radeon_encoder *radeon_encoder = pdata->encoder; 172 struct drm_device *dev = radeon_encoder->base.dev; 173 struct radeon_device *rdev = dev->dev_private; 174 175 return radeon_atom_get_backlight_level_from_reg(rdev); 176 } 177 178 static const struct backlight_ops radeon_atom_backlight_ops = { 179 .get_brightness = radeon_atom_backlight_get_brightness, 180 .update_status = radeon_atom_backlight_update_status, 181 }; 182 183 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder, 184 struct drm_connector *drm_connector) 185 { 186 struct drm_device *dev = radeon_encoder->base.dev; 187 struct radeon_device *rdev = dev->dev_private; 188 struct backlight_device *bd; 189 struct backlight_properties props; 190 struct radeon_backlight_privdata *pdata; 191 struct radeon_encoder_atom_dig *dig; 192 u8 backlight_level; 193 char bl_name[16]; 194 195 if (!radeon_encoder->enc_priv) 196 return; 197 198 if (!rdev->is_atom_bios) 199 return; 200 201 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 202 return; 203 204 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 205 if (!pdata) { 206 DRM_ERROR("Memory allocation failed\n"); 207 goto error; 208 } 209 210 memset(&props, 0, sizeof(props)); 211 props.max_brightness = RADEON_MAX_BL_LEVEL; 212 props.type = BACKLIGHT_RAW; 213 snprintf(bl_name, sizeof(bl_name), 214 "radeon_bl%d", dev->primary->index); 215 bd = backlight_device_register(bl_name, &drm_connector->kdev, 216 pdata, &radeon_atom_backlight_ops, &props); 217 if (IS_ERR(bd)) { 218 DRM_ERROR("Backlight registration failed\n"); 219 goto error; 220 } 221 222 pdata->encoder = radeon_encoder; 223 224 backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); 225 226 dig = radeon_encoder->enc_priv; 227 dig->bl_dev = bd; 228 229 bd->props.brightness = radeon_atom_backlight_get_brightness(bd); 230 bd->props.power = FB_BLANK_UNBLANK; 231 backlight_update_status(bd); 232 233 DRM_INFO("radeon atom DIG backlight initialized\n"); 234 235 return; 236 237 error: 238 kfree(pdata); 239 return; 240 } 241 242 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder) 243 { 244 struct drm_device *dev = radeon_encoder->base.dev; 245 struct radeon_device *rdev = dev->dev_private; 246 struct backlight_device *bd = NULL; 247 struct radeon_encoder_atom_dig *dig; 248 249 if (!radeon_encoder->enc_priv) 250 return; 251 252 if (!rdev->is_atom_bios) 253 return; 254 255 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) 256 return; 257 258 dig = radeon_encoder->enc_priv; 259 bd = dig->bl_dev; 260 dig->bl_dev = NULL; 261 262 if (bd) { 263 struct radeon_legacy_backlight_privdata *pdata; 264 265 pdata = bl_get_data(bd); 266 backlight_device_unregister(bd); 267 kfree(pdata); 268 269 DRM_INFO("radeon atom LVDS backlight unloaded\n"); 270 } 271 } 272 273 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 274 275 void radeon_atom_backlight_init(struct radeon_encoder *encoder) 276 { 277 } 278 279 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 280 { 281 } 282 283 #endif 284 285 /* evil but including atombios.h is much worse */ 286 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 287 struct drm_display_mode *mode); 288 289 290 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) 291 { 292 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 293 switch (radeon_encoder->encoder_id) { 294 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 295 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 296 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 297 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 298 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 299 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 300 case ENCODER_OBJECT_ID_INTERNAL_DDI: 301 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 302 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 303 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 304 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 305 return true; 306 default: 307 return false; 308 } 309 } 310 311 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, 312 const struct drm_display_mode *mode, 313 struct drm_display_mode *adjusted_mode) 314 { 315 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 316 struct drm_device *dev = encoder->dev; 317 struct radeon_device *rdev = dev->dev_private; 318 319 /* set the active encoder to connector routing */ 320 radeon_encoder_set_active_device(encoder); 321 drm_mode_set_crtcinfo(adjusted_mode, 0); 322 323 /* hw bug */ 324 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) 325 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 326 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 327 328 /* get the native mode for LVDS */ 329 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 330 radeon_panel_mode_fixup(encoder, adjusted_mode); 331 332 /* get the native mode for TV */ 333 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 334 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 335 if (tv_dac) { 336 if (tv_dac->tv_std == TV_STD_NTSC || 337 tv_dac->tv_std == TV_STD_NTSC_J || 338 tv_dac->tv_std == TV_STD_PAL_M) 339 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode); 340 else 341 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); 342 } 343 } 344 345 if (ASIC_IS_DCE3(rdev) && 346 ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 347 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) { 348 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 349 radeon_dp_set_link_config(connector, adjusted_mode); 350 } 351 352 return true; 353 } 354 355 static void 356 atombios_dac_setup(struct drm_encoder *encoder, int action) 357 { 358 struct drm_device *dev = encoder->dev; 359 struct radeon_device *rdev = dev->dev_private; 360 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 361 DAC_ENCODER_CONTROL_PS_ALLOCATION args; 362 int index = 0; 363 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 364 365 memset(&args, 0, sizeof(args)); 366 367 switch (radeon_encoder->encoder_id) { 368 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 369 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 370 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl); 371 break; 372 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 373 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 374 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl); 375 break; 376 } 377 378 args.ucAction = action; 379 380 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT)) 381 args.ucDacStandard = ATOM_DAC1_PS2; 382 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 383 args.ucDacStandard = ATOM_DAC1_CV; 384 else { 385 switch (dac_info->tv_std) { 386 case TV_STD_PAL: 387 case TV_STD_PAL_M: 388 case TV_STD_SCART_PAL: 389 case TV_STD_SECAM: 390 case TV_STD_PAL_CN: 391 args.ucDacStandard = ATOM_DAC1_PAL; 392 break; 393 case TV_STD_NTSC: 394 case TV_STD_NTSC_J: 395 case TV_STD_PAL_60: 396 default: 397 args.ucDacStandard = ATOM_DAC1_NTSC; 398 break; 399 } 400 } 401 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 402 403 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 404 405 } 406 407 static void 408 atombios_tv_setup(struct drm_encoder *encoder, int action) 409 { 410 struct drm_device *dev = encoder->dev; 411 struct radeon_device *rdev = dev->dev_private; 412 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 413 TV_ENCODER_CONTROL_PS_ALLOCATION args; 414 int index = 0; 415 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv; 416 417 memset(&args, 0, sizeof(args)); 418 419 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl); 420 421 args.sTVEncoder.ucAction = action; 422 423 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 424 args.sTVEncoder.ucTvStandard = ATOM_TV_CV; 425 else { 426 switch (dac_info->tv_std) { 427 case TV_STD_NTSC: 428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 429 break; 430 case TV_STD_PAL: 431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; 432 break; 433 case TV_STD_PAL_M: 434 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM; 435 break; 436 case TV_STD_PAL_60: 437 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60; 438 break; 439 case TV_STD_NTSC_J: 440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ; 441 break; 442 case TV_STD_SCART_PAL: 443 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */ 444 break; 445 case TV_STD_SECAM: 446 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM; 447 break; 448 case TV_STD_PAL_CN: 449 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN; 450 break; 451 default: 452 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC; 453 break; 454 } 455 } 456 457 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 458 459 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 460 461 } 462 463 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) 464 { 465 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 466 int bpc = 8; 467 468 if (connector) 469 bpc = radeon_get_monitor_bpc(connector); 470 471 switch (bpc) { 472 case 0: 473 return PANEL_BPC_UNDEFINE; 474 case 6: 475 return PANEL_6BIT_PER_COLOR; 476 case 8: 477 default: 478 return PANEL_8BIT_PER_COLOR; 479 case 10: 480 return PANEL_10BIT_PER_COLOR; 481 case 12: 482 return PANEL_12BIT_PER_COLOR; 483 case 16: 484 return PANEL_16BIT_PER_COLOR; 485 } 486 } 487 488 489 union dvo_encoder_control { 490 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; 491 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; 492 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; 493 }; 494 495 void 496 atombios_dvo_setup(struct drm_encoder *encoder, int action) 497 { 498 struct drm_device *dev = encoder->dev; 499 struct radeon_device *rdev = dev->dev_private; 500 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 501 union dvo_encoder_control args; 502 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl); 503 uint8_t frev, crev; 504 505 memset(&args, 0, sizeof(args)); 506 507 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 508 return; 509 510 /* some R4xx chips have the wrong frev */ 511 if (rdev->family <= CHIP_RV410) 512 frev = 1; 513 514 switch (frev) { 515 case 1: 516 switch (crev) { 517 case 1: 518 /* R4xx, R5xx */ 519 args.ext_tmds.sXTmdsEncoder.ucEnable = action; 520 521 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 522 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; 523 524 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; 525 break; 526 case 2: 527 /* RS600/690/740 */ 528 args.dvo.sDVOEncoder.ucAction = action; 529 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 530 /* DFP1, CRT1, TV1 depending on the type of port */ 531 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; 532 533 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 534 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; 535 break; 536 case 3: 537 /* R6xx */ 538 args.dvo_v3.ucAction = action; 539 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 540 args.dvo_v3.ucDVOConfig = 0; /* XXX */ 541 break; 542 default: 543 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 544 break; 545 } 546 break; 547 default: 548 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 549 break; 550 } 551 552 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 553 } 554 555 union lvds_encoder_control { 556 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1; 557 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2; 558 }; 559 560 void 561 atombios_digital_setup(struct drm_encoder *encoder, int action) 562 { 563 struct drm_device *dev = encoder->dev; 564 struct radeon_device *rdev = dev->dev_private; 565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 566 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 567 union lvds_encoder_control args; 568 int index = 0; 569 int hdmi_detected = 0; 570 uint8_t frev, crev; 571 572 if (!dig) 573 return; 574 575 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 576 hdmi_detected = 1; 577 578 memset(&args, 0, sizeof(args)); 579 580 switch (radeon_encoder->encoder_id) { 581 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 582 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 583 break; 584 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 585 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 586 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl); 587 break; 588 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 590 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl); 591 else 592 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl); 593 break; 594 } 595 596 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 597 return; 598 599 switch (frev) { 600 case 1: 601 case 2: 602 switch (crev) { 603 case 1: 604 args.v1.ucMisc = 0; 605 args.v1.ucAction = action; 606 if (hdmi_detected) 607 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 608 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 609 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 610 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 611 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 612 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 613 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 614 } else { 615 if (dig->linkb) 616 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 617 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 618 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; 619 /*if (pScrn->rgbBits == 8) */ 620 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; 621 } 622 break; 623 case 2: 624 case 3: 625 args.v2.ucMisc = 0; 626 args.v2.ucAction = action; 627 if (crev == 3) { 628 if (dig->coherent_mode) 629 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 630 } 631 if (hdmi_detected) 632 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 633 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 634 args.v2.ucTruncate = 0; 635 args.v2.ucSpatial = 0; 636 args.v2.ucTemporal = 0; 637 args.v2.ucFRC = 0; 638 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 639 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL) 640 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 641 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) { 642 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN; 643 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 644 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH; 645 } 646 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) { 647 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN; 648 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB) 649 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH; 650 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2) 651 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4; 652 } 653 } else { 654 if (dig->linkb) 655 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; 656 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 657 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; 658 } 659 break; 660 default: 661 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 662 break; 663 } 664 break; 665 default: 666 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 667 break; 668 } 669 670 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 671 } 672 673 int 674 atombios_get_encoder_mode(struct drm_encoder *encoder) 675 { 676 struct drm_device *dev = encoder->dev; 677 struct radeon_device *rdev = dev->dev_private; 678 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 679 struct drm_connector *connector; 680 struct radeon_connector *radeon_connector; 681 struct radeon_connector_atom_dig *dig_connector; 682 683 /* dp bridges are always DP */ 684 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) 685 return ATOM_ENCODER_MODE_DP; 686 687 /* DVO is always DVO */ 688 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) || 689 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 690 return ATOM_ENCODER_MODE_DVO; 691 692 connector = radeon_get_connector_for_encoder(encoder); 693 /* if we don't have an active device yet, just use one of 694 * the connectors tied to the encoder. 695 */ 696 if (!connector) 697 connector = radeon_get_connector_for_encoder_init(encoder); 698 radeon_connector = to_radeon_connector(connector); 699 700 switch (connector->connector_type) { 701 case DRM_MODE_CONNECTOR_DVII: 702 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 703 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 704 radeon_audio && 705 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 706 return ATOM_ENCODER_MODE_HDMI; 707 else if (radeon_connector->use_digital) 708 return ATOM_ENCODER_MODE_DVI; 709 else 710 return ATOM_ENCODER_MODE_CRT; 711 break; 712 case DRM_MODE_CONNECTOR_DVID: 713 case DRM_MODE_CONNECTOR_HDMIA: 714 default: 715 if (drm_detect_hdmi_monitor(radeon_connector->edid) && 716 radeon_audio && 717 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 718 return ATOM_ENCODER_MODE_HDMI; 719 else 720 return ATOM_ENCODER_MODE_DVI; 721 break; 722 case DRM_MODE_CONNECTOR_LVDS: 723 return ATOM_ENCODER_MODE_LVDS; 724 break; 725 case DRM_MODE_CONNECTOR_DisplayPort: 726 dig_connector = radeon_connector->con_priv; 727 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 728 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) 729 return ATOM_ENCODER_MODE_DP; 730 else if (drm_detect_hdmi_monitor(radeon_connector->edid) && 731 radeon_audio && 732 !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ 733 return ATOM_ENCODER_MODE_HDMI; 734 else 735 return ATOM_ENCODER_MODE_DVI; 736 break; 737 case DRM_MODE_CONNECTOR_eDP: 738 return ATOM_ENCODER_MODE_DP; 739 case DRM_MODE_CONNECTOR_DVIA: 740 case DRM_MODE_CONNECTOR_VGA: 741 return ATOM_ENCODER_MODE_CRT; 742 break; 743 case DRM_MODE_CONNECTOR_Composite: 744 case DRM_MODE_CONNECTOR_SVIDEO: 745 case DRM_MODE_CONNECTOR_9PinDIN: 746 /* fix me */ 747 return ATOM_ENCODER_MODE_TV; 748 /*return ATOM_ENCODER_MODE_CV;*/ 749 break; 750 } 751 } 752 753 /* 754 * DIG Encoder/Transmitter Setup 755 * 756 * DCE 3.0/3.1 757 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA. 758 * Supports up to 3 digital outputs 759 * - 2 DIG encoder blocks. 760 * DIG1 can drive UNIPHY link A or link B 761 * DIG2 can drive UNIPHY link B or LVTMA 762 * 763 * DCE 3.2 764 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B). 765 * Supports up to 5 digital outputs 766 * - 2 DIG encoder blocks. 767 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 768 * 769 * DCE 4.0/5.0/6.0 770 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 771 * Supports up to 6 digital outputs 772 * - 6 DIG encoder blocks. 773 * - DIG to PHY mapping is hardcoded 774 * DIG1 drives UNIPHY0 link A, A+B 775 * DIG2 drives UNIPHY0 link B 776 * DIG3 drives UNIPHY1 link A, A+B 777 * DIG4 drives UNIPHY1 link B 778 * DIG5 drives UNIPHY2 link A, A+B 779 * DIG6 drives UNIPHY2 link B 780 * 781 * DCE 4.1 782 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). 783 * Supports up to 6 digital outputs 784 * - 2 DIG encoder blocks. 785 * llano 786 * DIG1/2 can drive UNIPHY0/1/2 link A or link B 787 * ontario 788 * DIG1 drives UNIPHY0/1/2 link A 789 * DIG2 drives UNIPHY0/1/2 link B 790 * 791 * Routing 792 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) 793 * Examples: 794 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI 795 * crtc1 -> dig1 -> UNIPHY0 link B -> DP 796 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS 797 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI 798 */ 799 800 union dig_encoder_control { 801 DIG_ENCODER_CONTROL_PS_ALLOCATION v1; 802 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2; 803 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; 804 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4; 805 }; 806 807 void 808 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode) 809 { 810 struct drm_device *dev = encoder->dev; 811 struct radeon_device *rdev = dev->dev_private; 812 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 813 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 814 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 815 union dig_encoder_control args; 816 int index = 0; 817 uint8_t frev, crev; 818 int dp_clock = 0; 819 int dp_lane_count = 0; 820 int hpd_id = RADEON_HPD_NONE; 821 822 if (connector) { 823 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 824 struct radeon_connector_atom_dig *dig_connector = 825 radeon_connector->con_priv; 826 827 dp_clock = dig_connector->dp_clock; 828 dp_lane_count = dig_connector->dp_lane_count; 829 hpd_id = radeon_connector->hpd.hpd; 830 } 831 832 /* no dig encoder assigned */ 833 if (dig->dig_encoder == -1) 834 return; 835 836 memset(&args, 0, sizeof(args)); 837 838 if (ASIC_IS_DCE4(rdev)) 839 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl); 840 else { 841 if (dig->dig_encoder) 842 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 843 else 844 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 845 } 846 847 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 848 return; 849 850 switch (frev) { 851 case 1: 852 switch (crev) { 853 case 1: 854 args.v1.ucAction = action; 855 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 856 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 857 args.v3.ucPanelMode = panel_mode; 858 else 859 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 860 861 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 862 args.v1.ucLaneNum = dp_lane_count; 863 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 864 args.v1.ucLaneNum = 8; 865 else 866 args.v1.ucLaneNum = 4; 867 868 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 869 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 870 switch (radeon_encoder->encoder_id) { 871 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 872 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1; 873 break; 874 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 875 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 876 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2; 877 break; 878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 879 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3; 880 break; 881 } 882 if (dig->linkb) 883 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 884 else 885 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 886 break; 887 case 2: 888 case 3: 889 args.v3.ucAction = action; 890 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 891 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 892 args.v3.ucPanelMode = panel_mode; 893 else 894 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); 895 896 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) 897 args.v3.ucLaneNum = dp_lane_count; 898 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 899 args.v3.ucLaneNum = 8; 900 else 901 args.v3.ucLaneNum = 4; 902 903 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000)) 904 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 905 args.v3.acConfig.ucDigSel = dig->dig_encoder; 906 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder); 907 break; 908 case 4: 909 args.v4.ucAction = action; 910 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 911 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 912 args.v4.ucPanelMode = panel_mode; 913 else 914 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder); 915 916 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) 917 args.v4.ucLaneNum = dp_lane_count; 918 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 919 args.v4.ucLaneNum = 8; 920 else 921 args.v4.ucLaneNum = 4; 922 923 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { 924 if (dp_clock == 270000) 925 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 926 else if (dp_clock == 540000) 927 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 928 } 929 args.v4.acConfig.ucDigSel = dig->dig_encoder; 930 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); 931 if (hpd_id == RADEON_HPD_NONE) 932 args.v4.ucHPD_ID = 0; 933 else 934 args.v4.ucHPD_ID = hpd_id + 1; 935 break; 936 default: 937 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 938 break; 939 } 940 break; 941 default: 942 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 943 break; 944 } 945 946 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 947 948 } 949 950 union dig_transmitter_control { 951 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; 952 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; 953 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; 954 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; 955 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5; 956 }; 957 958 void 959 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set) 960 { 961 struct drm_device *dev = encoder->dev; 962 struct radeon_device *rdev = dev->dev_private; 963 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 964 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 965 struct drm_connector *connector; 966 union dig_transmitter_control args; 967 int index = 0; 968 uint8_t frev, crev; 969 bool is_dp = false; 970 int pll_id = 0; 971 int dp_clock = 0; 972 int dp_lane_count = 0; 973 int connector_object_id = 0; 974 int igp_lane_info = 0; 975 int dig_encoder = dig->dig_encoder; 976 int hpd_id = RADEON_HPD_NONE; 977 978 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 979 connector = radeon_get_connector_for_encoder_init(encoder); 980 /* just needed to avoid bailing in the encoder check. the encoder 981 * isn't used for init 982 */ 983 dig_encoder = 0; 984 } else 985 connector = radeon_get_connector_for_encoder(encoder); 986 987 if (connector) { 988 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 989 struct radeon_connector_atom_dig *dig_connector = 990 radeon_connector->con_priv; 991 992 hpd_id = radeon_connector->hpd.hpd; 993 dp_clock = dig_connector->dp_clock; 994 dp_lane_count = dig_connector->dp_lane_count; 995 connector_object_id = 996 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 997 igp_lane_info = dig_connector->igp_lane_info; 998 } 999 1000 if (encoder->crtc) { 1001 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1002 pll_id = radeon_crtc->pll_id; 1003 } 1004 1005 /* no dig encoder assigned */ 1006 if (dig_encoder == -1) 1007 return; 1008 1009 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder))) 1010 is_dp = true; 1011 1012 memset(&args, 0, sizeof(args)); 1013 1014 switch (radeon_encoder->encoder_id) { 1015 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1016 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1017 break; 1018 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1019 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1020 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1021 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1022 break; 1023 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1024 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl); 1025 break; 1026 } 1027 1028 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1029 return; 1030 1031 switch (frev) { 1032 case 1: 1033 switch (crev) { 1034 case 1: 1035 args.v1.ucAction = action; 1036 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1037 args.v1.usInitInfo = cpu_to_le16(connector_object_id); 1038 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1039 args.v1.asMode.ucLaneSel = lane_num; 1040 args.v1.asMode.ucLaneSet = lane_set; 1041 } else { 1042 if (is_dp) 1043 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); 1044 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1045 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1046 else 1047 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1048 } 1049 1050 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1051 1052 if (dig_encoder) 1053 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1054 else 1055 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1056 1057 if ((rdev->flags & RADEON_IS_IGP) && 1058 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 1059 if (is_dp || 1060 !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) { 1061 if (igp_lane_info & 0x1) 1062 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; 1063 else if (igp_lane_info & 0x2) 1064 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7; 1065 else if (igp_lane_info & 0x4) 1066 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11; 1067 else if (igp_lane_info & 0x8) 1068 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15; 1069 } else { 1070 if (igp_lane_info & 0x3) 1071 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7; 1072 else if (igp_lane_info & 0xc) 1073 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15; 1074 } 1075 } 1076 1077 if (dig->linkb) 1078 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB; 1079 else 1080 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA; 1081 1082 if (is_dp) 1083 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1084 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1085 if (dig->coherent_mode) 1086 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; 1087 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1088 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; 1089 } 1090 break; 1091 case 2: 1092 args.v2.ucAction = action; 1093 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1094 args.v2.usInitInfo = cpu_to_le16(connector_object_id); 1095 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1096 args.v2.asMode.ucLaneSel = lane_num; 1097 args.v2.asMode.ucLaneSet = lane_set; 1098 } else { 1099 if (is_dp) 1100 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); 1101 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1102 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1103 else 1104 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1105 } 1106 1107 args.v2.acConfig.ucEncoderSel = dig_encoder; 1108 if (dig->linkb) 1109 args.v2.acConfig.ucLinkSel = 1; 1110 1111 switch (radeon_encoder->encoder_id) { 1112 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1113 args.v2.acConfig.ucTransmitterSel = 0; 1114 break; 1115 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1116 args.v2.acConfig.ucTransmitterSel = 1; 1117 break; 1118 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1119 args.v2.acConfig.ucTransmitterSel = 2; 1120 break; 1121 } 1122 1123 if (is_dp) { 1124 args.v2.acConfig.fCoherentMode = 1; 1125 args.v2.acConfig.fDPConnector = 1; 1126 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1127 if (dig->coherent_mode) 1128 args.v2.acConfig.fCoherentMode = 1; 1129 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1130 args.v2.acConfig.fDualLinkConnector = 1; 1131 } 1132 break; 1133 case 3: 1134 args.v3.ucAction = action; 1135 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1136 args.v3.usInitInfo = cpu_to_le16(connector_object_id); 1137 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1138 args.v3.asMode.ucLaneSel = lane_num; 1139 args.v3.asMode.ucLaneSet = lane_set; 1140 } else { 1141 if (is_dp) 1142 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); 1143 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1144 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1145 else 1146 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1147 } 1148 1149 if (is_dp) 1150 args.v3.ucLaneNum = dp_lane_count; 1151 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1152 args.v3.ucLaneNum = 8; 1153 else 1154 args.v3.ucLaneNum = 4; 1155 1156 if (dig->linkb) 1157 args.v3.acConfig.ucLinkSel = 1; 1158 if (dig_encoder & 1) 1159 args.v3.acConfig.ucEncoderSel = 1; 1160 1161 /* Select the PLL for the PHY 1162 * DP PHY should be clocked from external src if there is 1163 * one. 1164 */ 1165 /* On DCE4, if there is an external clock, it generates the DP ref clock */ 1166 if (is_dp && rdev->clock.dp_extclk) 1167 args.v3.acConfig.ucRefClkSource = 2; /* external src */ 1168 else 1169 args.v3.acConfig.ucRefClkSource = pll_id; 1170 1171 switch (radeon_encoder->encoder_id) { 1172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1173 args.v3.acConfig.ucTransmitterSel = 0; 1174 break; 1175 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1176 args.v3.acConfig.ucTransmitterSel = 1; 1177 break; 1178 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1179 args.v3.acConfig.ucTransmitterSel = 2; 1180 break; 1181 } 1182 1183 if (is_dp) 1184 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1185 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1186 if (dig->coherent_mode) 1187 args.v3.acConfig.fCoherentMode = 1; 1188 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1189 args.v3.acConfig.fDualLinkConnector = 1; 1190 } 1191 break; 1192 case 4: 1193 args.v4.ucAction = action; 1194 if (action == ATOM_TRANSMITTER_ACTION_INIT) { 1195 args.v4.usInitInfo = cpu_to_le16(connector_object_id); 1196 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) { 1197 args.v4.asMode.ucLaneSel = lane_num; 1198 args.v4.asMode.ucLaneSet = lane_set; 1199 } else { 1200 if (is_dp) 1201 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); 1202 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1203 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); 1204 else 1205 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1206 } 1207 1208 if (is_dp) 1209 args.v4.ucLaneNum = dp_lane_count; 1210 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1211 args.v4.ucLaneNum = 8; 1212 else 1213 args.v4.ucLaneNum = 4; 1214 1215 if (dig->linkb) 1216 args.v4.acConfig.ucLinkSel = 1; 1217 if (dig_encoder & 1) 1218 args.v4.acConfig.ucEncoderSel = 1; 1219 1220 /* Select the PLL for the PHY 1221 * DP PHY should be clocked from external src if there is 1222 * one. 1223 */ 1224 /* On DCE5 DCPLL usually generates the DP ref clock */ 1225 if (is_dp) { 1226 if (rdev->clock.dp_extclk) 1227 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; 1228 else 1229 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; 1230 } else 1231 args.v4.acConfig.ucRefClkSource = pll_id; 1232 1233 switch (radeon_encoder->encoder_id) { 1234 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1235 args.v4.acConfig.ucTransmitterSel = 0; 1236 break; 1237 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1238 args.v4.acConfig.ucTransmitterSel = 1; 1239 break; 1240 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1241 args.v4.acConfig.ucTransmitterSel = 2; 1242 break; 1243 } 1244 1245 if (is_dp) 1246 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ 1247 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1248 if (dig->coherent_mode) 1249 args.v4.acConfig.fCoherentMode = 1; 1250 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1251 args.v4.acConfig.fDualLinkConnector = 1; 1252 } 1253 break; 1254 case 5: 1255 args.v5.ucAction = action; 1256 if (is_dp) 1257 args.v5.usSymClock = cpu_to_le16(dp_clock / 10); 1258 else 1259 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1260 1261 switch (radeon_encoder->encoder_id) { 1262 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1263 if (dig->linkb) 1264 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB; 1265 else 1266 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA; 1267 break; 1268 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1269 if (dig->linkb) 1270 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD; 1271 else 1272 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC; 1273 break; 1274 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1275 if (dig->linkb) 1276 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF; 1277 else 1278 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; 1279 break; 1280 } 1281 if (is_dp) 1282 args.v5.ucLaneNum = dp_lane_count; 1283 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1284 args.v5.ucLaneNum = 8; 1285 else 1286 args.v5.ucLaneNum = 4; 1287 args.v5.ucConnObjId = connector_object_id; 1288 args.v5.ucDigMode = atombios_get_encoder_mode(encoder); 1289 1290 if (is_dp && rdev->clock.dp_extclk) 1291 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK; 1292 else 1293 args.v5.asConfig.ucPhyClkSrcId = pll_id; 1294 1295 if (is_dp) 1296 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ 1297 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 1298 if (dig->coherent_mode) 1299 args.v5.asConfig.ucCoherentMode = 1; 1300 } 1301 if (hpd_id == RADEON_HPD_NONE) 1302 args.v5.asConfig.ucHPDSel = 0; 1303 else 1304 args.v5.asConfig.ucHPDSel = hpd_id + 1; 1305 args.v5.ucDigEncoderSel = 1 << dig_encoder; 1306 args.v5.ucDPLaneSet = lane_set; 1307 break; 1308 default: 1309 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1310 break; 1311 } 1312 break; 1313 default: 1314 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1315 break; 1316 } 1317 1318 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1319 } 1320 1321 bool 1322 atombios_set_edp_panel_power(struct drm_connector *connector, int action) 1323 { 1324 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1325 struct drm_device *dev = radeon_connector->base.dev; 1326 struct radeon_device *rdev = dev->dev_private; 1327 union dig_transmitter_control args; 1328 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); 1329 uint8_t frev, crev; 1330 1331 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP) 1332 goto done; 1333 1334 if (!ASIC_IS_DCE4(rdev)) 1335 goto done; 1336 1337 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) && 1338 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF)) 1339 goto done; 1340 1341 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1342 goto done; 1343 1344 memset(&args, 0, sizeof(args)); 1345 1346 args.v1.ucAction = action; 1347 1348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1349 1350 /* wait for the panel to power up */ 1351 if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) { 1352 int i; 1353 1354 for (i = 0; i < 300; i++) { 1355 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) 1356 return true; 1357 mdelay(1); 1358 } 1359 return false; 1360 } 1361 done: 1362 return true; 1363 } 1364 1365 union external_encoder_control { 1366 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1; 1367 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3; 1368 }; 1369 1370 static void 1371 atombios_external_encoder_setup(struct drm_encoder *encoder, 1372 struct drm_encoder *ext_encoder, 1373 int action) 1374 { 1375 struct drm_device *dev = encoder->dev; 1376 struct radeon_device *rdev = dev->dev_private; 1377 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1378 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder); 1379 union external_encoder_control args; 1380 struct drm_connector *connector; 1381 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl); 1382 u8 frev, crev; 1383 int dp_clock = 0; 1384 int dp_lane_count = 0; 1385 int connector_object_id = 0; 1386 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 1387 1388 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1389 connector = radeon_get_connector_for_encoder_init(encoder); 1390 else 1391 connector = radeon_get_connector_for_encoder(encoder); 1392 1393 if (connector) { 1394 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 1395 struct radeon_connector_atom_dig *dig_connector = 1396 radeon_connector->con_priv; 1397 1398 dp_clock = dig_connector->dp_clock; 1399 dp_lane_count = dig_connector->dp_lane_count; 1400 connector_object_id = 1401 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1402 } 1403 1404 memset(&args, 0, sizeof(args)); 1405 1406 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1407 return; 1408 1409 switch (frev) { 1410 case 1: 1411 /* no params on frev 1 */ 1412 break; 1413 case 2: 1414 switch (crev) { 1415 case 1: 1416 case 2: 1417 args.v1.sDigEncoder.ucAction = action; 1418 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1419 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1420 1421 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) { 1422 if (dp_clock == 270000) 1423 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; 1424 args.v1.sDigEncoder.ucLaneNum = dp_lane_count; 1425 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1426 args.v1.sDigEncoder.ucLaneNum = 8; 1427 else 1428 args.v1.sDigEncoder.ucLaneNum = 4; 1429 break; 1430 case 3: 1431 args.v3.sExtEncoder.ucAction = action; 1432 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT) 1433 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id); 1434 else 1435 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 1436 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder); 1437 1438 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) { 1439 if (dp_clock == 270000) 1440 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 1441 else if (dp_clock == 540000) 1442 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; 1443 args.v3.sExtEncoder.ucLaneNum = dp_lane_count; 1444 } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) 1445 args.v3.sExtEncoder.ucLaneNum = 8; 1446 else 1447 args.v3.sExtEncoder.ucLaneNum = 4; 1448 switch (ext_enum) { 1449 case GRAPH_OBJECT_ENUM_ID1: 1450 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1; 1451 break; 1452 case GRAPH_OBJECT_ENUM_ID2: 1453 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2; 1454 break; 1455 case GRAPH_OBJECT_ENUM_ID3: 1456 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3; 1457 break; 1458 } 1459 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder); 1460 break; 1461 default: 1462 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1463 return; 1464 } 1465 break; 1466 default: 1467 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1468 return; 1469 } 1470 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1471 } 1472 1473 static void 1474 atombios_yuv_setup(struct drm_encoder *encoder, bool enable) 1475 { 1476 struct drm_device *dev = encoder->dev; 1477 struct radeon_device *rdev = dev->dev_private; 1478 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1479 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1480 ENABLE_YUV_PS_ALLOCATION args; 1481 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV); 1482 uint32_t temp, reg; 1483 1484 memset(&args, 0, sizeof(args)); 1485 1486 if (rdev->family >= CHIP_R600) 1487 reg = R600_BIOS_3_SCRATCH; 1488 else 1489 reg = RADEON_BIOS_3_SCRATCH; 1490 1491 /* XXX: fix up scratch reg handling */ 1492 temp = RREG32(reg); 1493 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1494 WREG32(reg, (ATOM_S3_TV1_ACTIVE | 1495 (radeon_crtc->crtc_id << 18))); 1496 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1497 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); 1498 else 1499 WREG32(reg, 0); 1500 1501 if (enable) 1502 args.ucEnable = ATOM_ENABLE; 1503 args.ucCRTC = radeon_crtc->crtc_id; 1504 1505 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1506 1507 WREG32(reg, temp); 1508 } 1509 1510 static void 1511 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) 1512 { 1513 struct drm_device *dev = encoder->dev; 1514 struct radeon_device *rdev = dev->dev_private; 1515 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1516 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 1517 int index = 0; 1518 1519 memset(&args, 0, sizeof(args)); 1520 1521 switch (radeon_encoder->encoder_id) { 1522 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1523 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1524 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl); 1525 break; 1526 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1527 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1528 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1529 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl); 1530 break; 1531 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1532 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1533 break; 1534 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1535 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1536 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl); 1537 else 1538 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl); 1539 break; 1540 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1541 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1542 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1543 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1544 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1545 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1546 else 1547 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 1548 break; 1549 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1550 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1551 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1552 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 1553 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1554 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 1555 else 1556 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 1557 break; 1558 default: 1559 return; 1560 } 1561 1562 switch (mode) { 1563 case DRM_MODE_DPMS_ON: 1564 args.ucAction = ATOM_ENABLE; 1565 /* workaround for DVOOutputControl on some RS690 systems */ 1566 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) { 1567 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH); 1568 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); 1569 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1570 WREG32(RADEON_BIOS_3_SCRATCH, reg); 1571 } else 1572 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1573 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1574 args.ucAction = ATOM_LCD_BLON; 1575 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1576 } 1577 break; 1578 case DRM_MODE_DPMS_STANDBY: 1579 case DRM_MODE_DPMS_SUSPEND: 1580 case DRM_MODE_DPMS_OFF: 1581 args.ucAction = ATOM_DISABLE; 1582 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1583 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1584 args.ucAction = ATOM_LCD_BLOFF; 1585 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1586 } 1587 break; 1588 } 1589 } 1590 1591 static void 1592 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) 1593 { 1594 struct drm_device *dev = encoder->dev; 1595 struct radeon_device *rdev = dev->dev_private; 1596 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1597 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1598 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1599 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1600 struct radeon_connector *radeon_connector = NULL; 1601 struct radeon_connector_atom_dig *radeon_dig_connector = NULL; 1602 1603 if (connector) { 1604 radeon_connector = to_radeon_connector(connector); 1605 radeon_dig_connector = radeon_connector->con_priv; 1606 } 1607 1608 switch (mode) { 1609 case DRM_MODE_DPMS_ON: 1610 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1611 if (!connector) 1612 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 1613 else 1614 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector); 1615 1616 /* setup and enable the encoder */ 1617 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1618 atombios_dig_encoder_setup(encoder, 1619 ATOM_ENCODER_CMD_SETUP_PANEL_MODE, 1620 dig->panel_mode); 1621 if (ext_encoder) { 1622 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 1623 atombios_external_encoder_setup(encoder, ext_encoder, 1624 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); 1625 } 1626 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1627 } else if (ASIC_IS_DCE4(rdev)) { 1628 /* setup and enable the encoder */ 1629 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); 1630 /* enable the transmitter */ 1631 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1632 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1633 } else { 1634 /* setup and enable the encoder and transmitter */ 1635 atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); 1636 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); 1637 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); 1638 /* some dce3.x boards have a bug in their transmitter control table. 1639 * ACTION_ENABLE_OUTPUT can probably be dropped since ACTION_ENABLE 1640 * does the same thing and more. 1641 */ 1642 if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) && 1643 (rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880)) 1644 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); 1645 } 1646 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1647 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1648 atombios_set_edp_panel_power(connector, 1649 ATOM_TRANSMITTER_ACTION_POWER_ON); 1650 radeon_dig_connector->edp_on = true; 1651 } 1652 radeon_dp_link_train(encoder, connector); 1653 if (ASIC_IS_DCE4(rdev)) 1654 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); 1655 } 1656 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1657 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); 1658 break; 1659 case DRM_MODE_DPMS_STANDBY: 1660 case DRM_MODE_DPMS_SUSPEND: 1661 case DRM_MODE_DPMS_OFF: 1662 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { 1663 /* disable the transmitter */ 1664 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1665 } else if (ASIC_IS_DCE4(rdev)) { 1666 /* disable the transmitter */ 1667 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1668 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1669 } else { 1670 /* disable the encoder and transmitter */ 1671 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); 1672 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); 1673 atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); 1674 } 1675 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { 1676 if (ASIC_IS_DCE4(rdev)) 1677 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); 1678 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 1679 atombios_set_edp_panel_power(connector, 1680 ATOM_TRANSMITTER_ACTION_POWER_OFF); 1681 radeon_dig_connector->edp_on = false; 1682 } 1683 } 1684 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 1685 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); 1686 break; 1687 } 1688 } 1689 1690 static void 1691 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, 1692 struct drm_encoder *ext_encoder, 1693 int mode) 1694 { 1695 struct drm_device *dev = encoder->dev; 1696 struct radeon_device *rdev = dev->dev_private; 1697 1698 switch (mode) { 1699 case DRM_MODE_DPMS_ON: 1700 default: 1701 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1702 atombios_external_encoder_setup(encoder, ext_encoder, 1703 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); 1704 atombios_external_encoder_setup(encoder, ext_encoder, 1705 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); 1706 } else 1707 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); 1708 break; 1709 case DRM_MODE_DPMS_STANDBY: 1710 case DRM_MODE_DPMS_SUSPEND: 1711 case DRM_MODE_DPMS_OFF: 1712 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { 1713 atombios_external_encoder_setup(encoder, ext_encoder, 1714 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); 1715 atombios_external_encoder_setup(encoder, ext_encoder, 1716 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); 1717 } else 1718 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); 1719 break; 1720 } 1721 } 1722 1723 static void 1724 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) 1725 { 1726 struct drm_device *dev = encoder->dev; 1727 struct radeon_device *rdev = dev->dev_private; 1728 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1729 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 1730 1731 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 1732 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 1733 radeon_encoder->active_device); 1734 switch (radeon_encoder->encoder_id) { 1735 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1736 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1737 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1738 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1739 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1740 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1741 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1742 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1743 radeon_atom_encoder_dpms_avivo(encoder, mode); 1744 break; 1745 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1746 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1747 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1748 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1749 radeon_atom_encoder_dpms_dig(encoder, mode); 1750 break; 1751 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1752 if (ASIC_IS_DCE5(rdev)) { 1753 switch (mode) { 1754 case DRM_MODE_DPMS_ON: 1755 atombios_dvo_setup(encoder, ATOM_ENABLE); 1756 break; 1757 case DRM_MODE_DPMS_STANDBY: 1758 case DRM_MODE_DPMS_SUSPEND: 1759 case DRM_MODE_DPMS_OFF: 1760 atombios_dvo_setup(encoder, ATOM_DISABLE); 1761 break; 1762 } 1763 } else if (ASIC_IS_DCE3(rdev)) 1764 radeon_atom_encoder_dpms_dig(encoder, mode); 1765 else 1766 radeon_atom_encoder_dpms_avivo(encoder, mode); 1767 break; 1768 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1769 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1770 if (ASIC_IS_DCE5(rdev)) { 1771 switch (mode) { 1772 case DRM_MODE_DPMS_ON: 1773 atombios_dac_setup(encoder, ATOM_ENABLE); 1774 break; 1775 case DRM_MODE_DPMS_STANDBY: 1776 case DRM_MODE_DPMS_SUSPEND: 1777 case DRM_MODE_DPMS_OFF: 1778 atombios_dac_setup(encoder, ATOM_DISABLE); 1779 break; 1780 } 1781 } else 1782 radeon_atom_encoder_dpms_avivo(encoder, mode); 1783 break; 1784 default: 1785 return; 1786 } 1787 1788 if (ext_encoder) 1789 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); 1790 1791 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1792 1793 } 1794 1795 union crtc_source_param { 1796 SELECT_CRTC_SOURCE_PS_ALLOCATION v1; 1797 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2; 1798 }; 1799 1800 static void 1801 atombios_set_encoder_crtc_source(struct drm_encoder *encoder) 1802 { 1803 struct drm_device *dev = encoder->dev; 1804 struct radeon_device *rdev = dev->dev_private; 1805 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1806 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1807 union crtc_source_param args; 1808 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1809 uint8_t frev, crev; 1810 struct radeon_encoder_atom_dig *dig; 1811 1812 memset(&args, 0, sizeof(args)); 1813 1814 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 1815 return; 1816 1817 switch (frev) { 1818 case 1: 1819 switch (crev) { 1820 case 1: 1821 default: 1822 if (ASIC_IS_AVIVO(rdev)) 1823 args.v1.ucCRTC = radeon_crtc->crtc_id; 1824 else { 1825 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) { 1826 args.v1.ucCRTC = radeon_crtc->crtc_id; 1827 } else { 1828 args.v1.ucCRTC = radeon_crtc->crtc_id << 2; 1829 } 1830 } 1831 switch (radeon_encoder->encoder_id) { 1832 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1833 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 1834 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX; 1835 break; 1836 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1837 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 1838 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) 1839 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX; 1840 else 1841 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX; 1842 break; 1843 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1844 case ENCODER_OBJECT_ID_INTERNAL_DDI: 1845 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1846 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX; 1847 break; 1848 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1849 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1850 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1851 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1852 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1853 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1854 else 1855 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX; 1856 break; 1857 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1858 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1859 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1860 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX; 1861 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1862 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX; 1863 else 1864 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX; 1865 break; 1866 } 1867 break; 1868 case 2: 1869 args.v2.ucCRTC = radeon_crtc->crtc_id; 1870 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) { 1871 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 1872 1873 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) 1874 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; 1875 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA) 1876 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; 1877 else 1878 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1879 } else 1880 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); 1881 switch (radeon_encoder->encoder_id) { 1882 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1883 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1884 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1885 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 1886 dig = radeon_encoder->enc_priv; 1887 switch (dig->dig_encoder) { 1888 case 0: 1889 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1890 break; 1891 case 1: 1892 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1893 break; 1894 case 2: 1895 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID; 1896 break; 1897 case 3: 1898 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID; 1899 break; 1900 case 4: 1901 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID; 1902 break; 1903 case 5: 1904 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; 1905 break; 1906 } 1907 break; 1908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1909 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1910 break; 1911 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1912 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1913 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1914 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1915 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1916 else 1917 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID; 1918 break; 1919 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 1920 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1921 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1922 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT)) 1923 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1924 else 1925 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID; 1926 break; 1927 } 1928 break; 1929 } 1930 break; 1931 default: 1932 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev); 1933 return; 1934 } 1935 1936 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1937 1938 /* update scratch regs with new routing */ 1939 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1940 } 1941 1942 static void 1943 atombios_apply_encoder_quirks(struct drm_encoder *encoder, 1944 struct drm_display_mode *mode) 1945 { 1946 struct drm_device *dev = encoder->dev; 1947 struct radeon_device *rdev = dev->dev_private; 1948 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1949 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1950 1951 /* Funky macbooks */ 1952 if ((dev->pdev->device == 0x71C5) && 1953 (dev->pdev->subsystem_vendor == 0x106b) && 1954 (dev->pdev->subsystem_device == 0x0080)) { 1955 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 1956 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL); 1957 1958 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN; 1959 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN; 1960 1961 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); 1962 } 1963 } 1964 1965 /* set scaler clears this on some chips */ 1966 if (ASIC_IS_AVIVO(rdev) && 1967 (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { 1968 if (ASIC_IS_DCE4(rdev)) { 1969 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1970 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 1971 EVERGREEN_INTERLEAVE_EN); 1972 else 1973 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1974 } else { 1975 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1976 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 1977 AVIVO_D1MODE_INTERLEAVE_EN); 1978 else 1979 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); 1980 } 1981 } 1982 } 1983 1984 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) 1985 { 1986 struct drm_device *dev = encoder->dev; 1987 struct radeon_device *rdev = dev->dev_private; 1988 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1989 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1990 struct drm_encoder *test_encoder; 1991 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 1992 uint32_t dig_enc_in_use = 0; 1993 1994 if (ASIC_IS_DCE6(rdev)) { 1995 /* DCE6 */ 1996 switch (radeon_encoder->encoder_id) { 1997 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1998 if (dig->linkb) 1999 return 1; 2000 else 2001 return 0; 2002 break; 2003 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2004 if (dig->linkb) 2005 return 3; 2006 else 2007 return 2; 2008 break; 2009 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2010 if (dig->linkb) 2011 return 5; 2012 else 2013 return 4; 2014 break; 2015 } 2016 } else if (ASIC_IS_DCE4(rdev)) { 2017 /* DCE4/5 */ 2018 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) { 2019 /* ontario follows DCE4 */ 2020 if (rdev->family == CHIP_PALM) { 2021 if (dig->linkb) 2022 return 1; 2023 else 2024 return 0; 2025 } else 2026 /* llano follows DCE3.2 */ 2027 return radeon_crtc->crtc_id; 2028 } else { 2029 switch (radeon_encoder->encoder_id) { 2030 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2031 if (dig->linkb) 2032 return 1; 2033 else 2034 return 0; 2035 break; 2036 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2037 if (dig->linkb) 2038 return 3; 2039 else 2040 return 2; 2041 break; 2042 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2043 if (dig->linkb) 2044 return 5; 2045 else 2046 return 4; 2047 break; 2048 } 2049 } 2050 } 2051 2052 /* on DCE32 and encoder can driver any block so just crtc id */ 2053 if (ASIC_IS_DCE32(rdev)) { 2054 return radeon_crtc->crtc_id; 2055 } 2056 2057 /* on DCE3 - LVTMA can only be driven by DIGB */ 2058 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 2059 struct radeon_encoder *radeon_test_encoder; 2060 2061 if (encoder == test_encoder) 2062 continue; 2063 2064 if (!radeon_encoder_is_digital(test_encoder)) 2065 continue; 2066 2067 radeon_test_encoder = to_radeon_encoder(test_encoder); 2068 dig = radeon_test_encoder->enc_priv; 2069 2070 if (dig->dig_encoder >= 0) 2071 dig_enc_in_use |= (1 << dig->dig_encoder); 2072 } 2073 2074 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) { 2075 if (dig_enc_in_use & 0x2) 2076 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n"); 2077 return 1; 2078 } 2079 if (!(dig_enc_in_use & 1)) 2080 return 0; 2081 return 1; 2082 } 2083 2084 /* This only needs to be called once at startup */ 2085 void 2086 radeon_atom_encoder_init(struct radeon_device *rdev) 2087 { 2088 struct drm_device *dev = rdev->ddev; 2089 struct drm_encoder *encoder; 2090 2091 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2092 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2093 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2094 2095 switch (radeon_encoder->encoder_id) { 2096 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2097 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2098 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2099 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2100 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); 2101 break; 2102 default: 2103 break; 2104 } 2105 2106 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))) 2107 atombios_external_encoder_setup(encoder, ext_encoder, 2108 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); 2109 } 2110 } 2111 2112 static void 2113 radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 2114 struct drm_display_mode *mode, 2115 struct drm_display_mode *adjusted_mode) 2116 { 2117 struct drm_device *dev = encoder->dev; 2118 struct radeon_device *rdev = dev->dev_private; 2119 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2120 2121 radeon_encoder->pixel_clock = adjusted_mode->clock; 2122 2123 /* need to call this here rather than in prepare() since we need some crtc info */ 2124 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2125 2126 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) { 2127 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT)) 2128 atombios_yuv_setup(encoder, true); 2129 else 2130 atombios_yuv_setup(encoder, false); 2131 } 2132 2133 switch (radeon_encoder->encoder_id) { 2134 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2136 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2137 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2138 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 2139 break; 2140 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2143 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2144 /* handled in dpms */ 2145 break; 2146 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2147 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2148 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2149 atombios_dvo_setup(encoder, ATOM_ENABLE); 2150 break; 2151 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2152 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2153 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2154 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2155 atombios_dac_setup(encoder, ATOM_ENABLE); 2156 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) { 2157 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2158 atombios_tv_setup(encoder, ATOM_ENABLE); 2159 else 2160 atombios_tv_setup(encoder, ATOM_DISABLE); 2161 } 2162 break; 2163 } 2164 2165 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2166 2167 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2168 r600_hdmi_enable(encoder); 2169 if (ASIC_IS_DCE6(rdev)) 2170 ; /* TODO (use pointers instead of if-s?) */ 2171 else if (ASIC_IS_DCE4(rdev)) 2172 evergreen_hdmi_setmode(encoder, adjusted_mode); 2173 else 2174 r600_hdmi_setmode(encoder, adjusted_mode); 2175 } 2176 } 2177 2178 static bool 2179 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2180 { 2181 struct drm_device *dev = encoder->dev; 2182 struct radeon_device *rdev = dev->dev_private; 2183 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2184 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2185 2186 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | 2187 ATOM_DEVICE_CV_SUPPORT | 2188 ATOM_DEVICE_CRT_SUPPORT)) { 2189 DAC_LOAD_DETECTION_PS_ALLOCATION args; 2190 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection); 2191 uint8_t frev, crev; 2192 2193 memset(&args, 0, sizeof(args)); 2194 2195 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 2196 return false; 2197 2198 args.sDacload.ucMisc = 0; 2199 2200 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) || 2201 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1)) 2202 args.sDacload.ucDacType = ATOM_DAC_A; 2203 else 2204 args.sDacload.ucDacType = ATOM_DAC_B; 2205 2206 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) 2207 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT); 2208 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) 2209 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT); 2210 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2211 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT); 2212 if (crev >= 3) 2213 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2214 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2215 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT); 2216 if (crev >= 3) 2217 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb; 2218 } 2219 2220 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2221 2222 return true; 2223 } else 2224 return false; 2225 } 2226 2227 static enum drm_connector_status 2228 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2229 { 2230 struct drm_device *dev = encoder->dev; 2231 struct radeon_device *rdev = dev->dev_private; 2232 #ifdef DRMDEBUG 2233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2234 #endif 2235 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2236 uint32_t bios_0_scratch; 2237 2238 if (!atombios_dac_load_detect(encoder, connector)) { 2239 DRM_DEBUG_KMS("detect returned false \n"); 2240 return connector_status_unknown; 2241 } 2242 2243 if (rdev->family >= CHIP_R600) 2244 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2245 else 2246 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 2247 2248 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2249 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2250 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2251 return connector_status_connected; 2252 } 2253 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2254 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2255 return connector_status_connected; 2256 } 2257 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2258 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2259 return connector_status_connected; 2260 } 2261 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2262 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2263 return connector_status_connected; /* CTV */ 2264 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2265 return connector_status_connected; /* STV */ 2266 } 2267 return connector_status_disconnected; 2268 } 2269 2270 static enum drm_connector_status 2271 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector) 2272 { 2273 struct drm_device *dev = encoder->dev; 2274 struct radeon_device *rdev = dev->dev_private; 2275 #ifdef DRMDEBUG 2276 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2277 #endif 2278 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2279 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2280 u32 bios_0_scratch; 2281 2282 if (!ASIC_IS_DCE4(rdev)) 2283 return connector_status_unknown; 2284 2285 if (!ext_encoder) 2286 return connector_status_unknown; 2287 2288 if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0) 2289 return connector_status_unknown; 2290 2291 /* load detect on the dp bridge */ 2292 atombios_external_encoder_setup(encoder, ext_encoder, 2293 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION); 2294 2295 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); 2296 2297 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices); 2298 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) { 2299 if (bios_0_scratch & ATOM_S0_CRT1_MASK) 2300 return connector_status_connected; 2301 } 2302 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) { 2303 if (bios_0_scratch & ATOM_S0_CRT2_MASK) 2304 return connector_status_connected; 2305 } 2306 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) { 2307 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A)) 2308 return connector_status_connected; 2309 } 2310 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) { 2311 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A)) 2312 return connector_status_connected; /* CTV */ 2313 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A)) 2314 return connector_status_connected; /* STV */ 2315 } 2316 return connector_status_disconnected; 2317 } 2318 2319 void 2320 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder) 2321 { 2322 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); 2323 2324 if (ext_encoder) 2325 /* ddc_setup on the dp bridge */ 2326 atombios_external_encoder_setup(encoder, ext_encoder, 2327 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 2328 2329 } 2330 2331 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) 2332 { 2333 struct radeon_device *rdev = encoder->dev->dev_private; 2334 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2335 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 2336 2337 if ((radeon_encoder->active_device & 2338 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2339 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 2340 ENCODER_OBJECT_ID_NONE)) { 2341 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 2342 if (dig) { 2343 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder); 2344 if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) { 2345 if (rdev->family >= CHIP_R600) 2346 dig->afmt = rdev->mode_info.afmt[dig->dig_encoder]; 2347 else 2348 /* RS600/690/740 have only 1 afmt block */ 2349 dig->afmt = rdev->mode_info.afmt[0]; 2350 } 2351 } 2352 } 2353 2354 radeon_atom_output_lock(encoder, true); 2355 2356 if (connector) { 2357 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 2358 2359 /* select the clock/data port if it uses a router */ 2360 if (radeon_connector->router.cd_valid) 2361 radeon_router_select_cd_port(radeon_connector); 2362 2363 /* turn eDP panel on for mode set */ 2364 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2365 atombios_set_edp_panel_power(connector, 2366 ATOM_TRANSMITTER_ACTION_POWER_ON); 2367 } 2368 2369 /* this is needed for the pll/ss setup to work correctly in some cases */ 2370 atombios_set_encoder_crtc_source(encoder); 2371 } 2372 2373 static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 2374 { 2375 /* need to call this here as we need the crtc set up */ 2376 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2377 radeon_atom_output_lock(encoder, false); 2378 } 2379 2380 static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 2381 { 2382 struct drm_device *dev = encoder->dev; 2383 struct radeon_device *rdev = dev->dev_private; 2384 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2385 struct radeon_encoder_atom_dig *dig; 2386 2387 /* check for pre-DCE3 cards with shared encoders; 2388 * can't really use the links individually, so don't disable 2389 * the encoder if it's in use by another connector 2390 */ 2391 if (!ASIC_IS_DCE3(rdev)) { 2392 struct drm_encoder *other_encoder; 2393 struct radeon_encoder *other_radeon_encoder; 2394 2395 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) { 2396 other_radeon_encoder = to_radeon_encoder(other_encoder); 2397 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) && 2398 drm_helper_encoder_in_use(other_encoder)) 2399 goto disable_done; 2400 } 2401 } 2402 2403 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2404 2405 switch (radeon_encoder->encoder_id) { 2406 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2407 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2408 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2409 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2410 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE); 2411 break; 2412 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2413 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2414 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2415 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2416 /* handled in dpms */ 2417 break; 2418 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2419 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2420 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2421 atombios_dvo_setup(encoder, ATOM_DISABLE); 2422 break; 2423 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2424 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2425 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2426 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2427 atombios_dac_setup(encoder, ATOM_DISABLE); 2428 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2429 atombios_tv_setup(encoder, ATOM_DISABLE); 2430 break; 2431 } 2432 2433 disable_done: 2434 if (radeon_encoder_is_digital(encoder)) { 2435 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2436 r600_hdmi_disable(encoder); 2437 dig = radeon_encoder->enc_priv; 2438 dig->dig_encoder = -1; 2439 } 2440 radeon_encoder->active_device = 0; 2441 } 2442 2443 /* these are handled by the primary encoders */ 2444 static void radeon_atom_ext_prepare(struct drm_encoder *encoder) 2445 { 2446 2447 } 2448 2449 static void radeon_atom_ext_commit(struct drm_encoder *encoder) 2450 { 2451 2452 } 2453 2454 static void 2455 radeon_atom_ext_mode_set(struct drm_encoder *encoder, 2456 struct drm_display_mode *mode, 2457 struct drm_display_mode *adjusted_mode) 2458 { 2459 2460 } 2461 2462 static void radeon_atom_ext_disable(struct drm_encoder *encoder) 2463 { 2464 2465 } 2466 2467 static void 2468 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode) 2469 { 2470 2471 } 2472 2473 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder, 2474 const struct drm_display_mode *mode, 2475 struct drm_display_mode *adjusted_mode) 2476 { 2477 return true; 2478 } 2479 2480 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = { 2481 .dpms = radeon_atom_ext_dpms, 2482 .mode_fixup = radeon_atom_ext_mode_fixup, 2483 .prepare = radeon_atom_ext_prepare, 2484 .mode_set = radeon_atom_ext_mode_set, 2485 .commit = radeon_atom_ext_commit, 2486 .disable = radeon_atom_ext_disable, 2487 /* no detect for TMDS/LVDS yet */ 2488 }; 2489 2490 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = { 2491 .dpms = radeon_atom_encoder_dpms, 2492 .mode_fixup = radeon_atom_mode_fixup, 2493 .prepare = radeon_atom_encoder_prepare, 2494 .mode_set = radeon_atom_encoder_mode_set, 2495 .commit = radeon_atom_encoder_commit, 2496 .disable = radeon_atom_encoder_disable, 2497 .detect = radeon_atom_dig_detect, 2498 }; 2499 2500 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = { 2501 .dpms = radeon_atom_encoder_dpms, 2502 .mode_fixup = radeon_atom_mode_fixup, 2503 .prepare = radeon_atom_encoder_prepare, 2504 .mode_set = radeon_atom_encoder_mode_set, 2505 .commit = radeon_atom_encoder_commit, 2506 .detect = radeon_atom_dac_detect, 2507 }; 2508 2509 void radeon_enc_destroy(struct drm_encoder *encoder) 2510 { 2511 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2512 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2513 radeon_atom_backlight_exit(radeon_encoder); 2514 kfree(radeon_encoder->enc_priv); 2515 drm_encoder_cleanup(encoder); 2516 kfree(radeon_encoder); 2517 } 2518 2519 static const struct drm_encoder_funcs radeon_atom_enc_funcs = { 2520 .destroy = radeon_enc_destroy, 2521 }; 2522 2523 static struct radeon_encoder_atom_dac * 2524 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder) 2525 { 2526 struct drm_device *dev = radeon_encoder->base.dev; 2527 struct radeon_device *rdev = dev->dev_private; 2528 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL); 2529 2530 if (!dac) 2531 return NULL; 2532 2533 dac->tv_std = radeon_atombios_get_tv_info(rdev); 2534 return dac; 2535 } 2536 2537 static struct radeon_encoder_atom_dig * 2538 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder) 2539 { 2540 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT; 2541 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); 2542 2543 if (!dig) 2544 return NULL; 2545 2546 /* coherent mode by default */ 2547 dig->coherent_mode = true; 2548 dig->dig_encoder = -1; 2549 2550 if (encoder_enum == 2) 2551 dig->linkb = true; 2552 else 2553 dig->linkb = false; 2554 2555 return dig; 2556 } 2557 2558 void 2559 radeon_add_atom_encoder(struct drm_device *dev, 2560 uint32_t encoder_enum, 2561 uint32_t supported_device, 2562 u16 caps) 2563 { 2564 struct radeon_device *rdev = dev->dev_private; 2565 struct drm_encoder *encoder; 2566 struct radeon_encoder *radeon_encoder; 2567 2568 /* see if we already added it */ 2569 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2570 radeon_encoder = to_radeon_encoder(encoder); 2571 if (radeon_encoder->encoder_enum == encoder_enum) { 2572 radeon_encoder->devices |= supported_device; 2573 return; 2574 } 2575 2576 } 2577 2578 /* add a new one */ 2579 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 2580 if (!radeon_encoder) 2581 return; 2582 2583 encoder = &radeon_encoder->base; 2584 switch (rdev->num_crtc) { 2585 case 1: 2586 encoder->possible_crtcs = 0x1; 2587 break; 2588 case 2: 2589 default: 2590 encoder->possible_crtcs = 0x3; 2591 break; 2592 case 4: 2593 encoder->possible_crtcs = 0xf; 2594 break; 2595 case 6: 2596 encoder->possible_crtcs = 0x3f; 2597 break; 2598 } 2599 2600 radeon_encoder->enc_priv = NULL; 2601 2602 radeon_encoder->encoder_enum = encoder_enum; 2603 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2604 radeon_encoder->devices = supported_device; 2605 radeon_encoder->rmx_type = RMX_OFF; 2606 radeon_encoder->underscan_type = UNDERSCAN_OFF; 2607 radeon_encoder->is_ext_encoder = false; 2608 radeon_encoder->caps = caps; 2609 2610 switch (radeon_encoder->encoder_id) { 2611 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 2612 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 2613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 2614 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 2615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2616 radeon_encoder->rmx_type = RMX_FULL; 2617 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2618 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2619 } else { 2620 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2621 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2622 } 2623 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2624 break; 2625 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 2626 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2627 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2628 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2629 break; 2630 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 2631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2632 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2633 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC); 2634 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder); 2635 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs); 2636 break; 2637 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 2638 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2639 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2640 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2641 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2642 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2643 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2644 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2645 radeon_encoder->rmx_type = RMX_FULL; 2646 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2647 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 2648 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2649 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2650 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2651 } else { 2652 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2653 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder); 2654 } 2655 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs); 2656 break; 2657 case ENCODER_OBJECT_ID_SI170B: 2658 case ENCODER_OBJECT_ID_CH7303: 2659 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 2660 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 2661 case ENCODER_OBJECT_ID_TITFP513: 2662 case ENCODER_OBJECT_ID_VT1623: 2663 case ENCODER_OBJECT_ID_HDMI_SI1930: 2664 case ENCODER_OBJECT_ID_TRAVIS: 2665 case ENCODER_OBJECT_ID_NUTMEG: 2666 /* these are handled by the primary encoders */ 2667 radeon_encoder->is_ext_encoder = true; 2668 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2669 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); 2670 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 2671 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC); 2672 else 2673 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS); 2674 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs); 2675 break; 2676 } 2677 } 2678