1 /* $OpenBSD: atombios_crtc.c,v 1.6 2014/08/08 16:33:27 jsg Exp $ */ 2 /* 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 #include <dev/pci/drm/drmP.h> 28 #include <dev/pci/drm/drm_crtc_helper.h> 29 #include <dev/pci/drm/radeon_drm.h> 30 #include <dev/pci/drm/drm_fixed.h> 31 #include "radeon.h" 32 #include "atom.h" 33 #include "atom-bits.h" 34 35 static void atombios_overscan_setup(struct drm_crtc *crtc, 36 struct drm_display_mode *mode, 37 struct drm_display_mode *adjusted_mode) 38 { 39 struct drm_device *dev = crtc->dev; 40 struct radeon_device *rdev = dev->dev_private; 41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 42 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 44 int a1, a2; 45 46 memset(&args, 0, sizeof(args)); 47 48 args.ucCRTC = radeon_crtc->crtc_id; 49 50 switch (radeon_crtc->rmx_type) { 51 case RMX_CENTER: 52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 56 break; 57 case RMX_ASPECT: 58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 60 61 if (a1 > a2) { 62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 64 } else if (a2 > a1) { 65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 67 } 68 break; 69 case RMX_FULL: 70 default: 71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 75 break; 76 } 77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 78 } 79 80 static void atombios_scaler_setup(struct drm_crtc *crtc) 81 { 82 struct drm_device *dev = crtc->dev; 83 struct radeon_device *rdev = dev->dev_private; 84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 85 ENABLE_SCALER_PS_ALLOCATION args; 86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 87 struct radeon_encoder *radeon_encoder = 88 to_radeon_encoder(radeon_crtc->encoder); 89 /* fixme - fill in enc_priv for atom dac */ 90 enum radeon_tv_std tv_std = TV_STD_NTSC; 91 bool is_tv = false, is_cv = false; 92 93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 94 return; 95 96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 98 tv_std = tv_dac->tv_std; 99 is_tv = true; 100 } 101 102 memset(&args, 0, sizeof(args)); 103 104 args.ucScaler = radeon_crtc->crtc_id; 105 106 if (is_tv) { 107 switch (tv_std) { 108 case TV_STD_NTSC: 109 default: 110 args.ucTVStandard = ATOM_TV_NTSC; 111 break; 112 case TV_STD_PAL: 113 args.ucTVStandard = ATOM_TV_PAL; 114 break; 115 case TV_STD_PAL_M: 116 args.ucTVStandard = ATOM_TV_PALM; 117 break; 118 case TV_STD_PAL_60: 119 args.ucTVStandard = ATOM_TV_PAL60; 120 break; 121 case TV_STD_NTSC_J: 122 args.ucTVStandard = ATOM_TV_NTSCJ; 123 break; 124 case TV_STD_SCART_PAL: 125 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 126 break; 127 case TV_STD_SECAM: 128 args.ucTVStandard = ATOM_TV_SECAM; 129 break; 130 case TV_STD_PAL_CN: 131 args.ucTVStandard = ATOM_TV_PALCN; 132 break; 133 } 134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 135 } else if (is_cv) { 136 args.ucTVStandard = ATOM_TV_CV; 137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 138 } else { 139 switch (radeon_crtc->rmx_type) { 140 case RMX_FULL: 141 args.ucEnable = ATOM_SCALER_EXPANSION; 142 break; 143 case RMX_CENTER: 144 args.ucEnable = ATOM_SCALER_CENTER; 145 break; 146 case RMX_ASPECT: 147 args.ucEnable = ATOM_SCALER_EXPANSION; 148 break; 149 default: 150 if (ASIC_IS_AVIVO(rdev)) 151 args.ucEnable = ATOM_SCALER_DISABLE; 152 else 153 args.ucEnable = ATOM_SCALER_CENTER; 154 break; 155 } 156 } 157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 158 if ((is_tv || is_cv) 159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 160 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 161 } 162 } 163 164 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 165 { 166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 167 struct drm_device *dev = crtc->dev; 168 struct radeon_device *rdev = dev->dev_private; 169 int index = 170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 171 ENABLE_CRTC_PS_ALLOCATION args; 172 173 memset(&args, 0, sizeof(args)); 174 175 args.ucCRTC = radeon_crtc->crtc_id; 176 args.ucEnable = lock; 177 178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 179 } 180 181 static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 182 { 183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 184 struct drm_device *dev = crtc->dev; 185 struct radeon_device *rdev = dev->dev_private; 186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 187 ENABLE_CRTC_PS_ALLOCATION args; 188 189 memset(&args, 0, sizeof(args)); 190 191 args.ucCRTC = radeon_crtc->crtc_id; 192 args.ucEnable = state; 193 194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 195 } 196 197 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 198 { 199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 200 struct drm_device *dev = crtc->dev; 201 struct radeon_device *rdev = dev->dev_private; 202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 203 ENABLE_CRTC_PS_ALLOCATION args; 204 205 memset(&args, 0, sizeof(args)); 206 207 args.ucCRTC = radeon_crtc->crtc_id; 208 args.ucEnable = state; 209 210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 211 } 212 213 static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 214 { 215 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 216 struct drm_device *dev = crtc->dev; 217 struct radeon_device *rdev = dev->dev_private; 218 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 219 BLANK_CRTC_PS_ALLOCATION args; 220 221 memset(&args, 0, sizeof(args)); 222 223 args.ucCRTC = radeon_crtc->crtc_id; 224 args.ucBlanking = state; 225 226 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 227 } 228 229 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 230 { 231 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 232 struct drm_device *dev = crtc->dev; 233 struct radeon_device *rdev = dev->dev_private; 234 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 235 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 236 237 memset(&args, 0, sizeof(args)); 238 239 args.ucDispPipeId = radeon_crtc->crtc_id; 240 args.ucEnable = state; 241 242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 243 } 244 245 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 246 { 247 struct drm_device *dev = crtc->dev; 248 struct radeon_device *rdev = dev->dev_private; 249 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 250 251 switch (mode) { 252 case DRM_MODE_DPMS_ON: 253 radeon_crtc->enabled = true; 254 /* adjust pm to dpms changes BEFORE enabling crtcs */ 255 radeon_pm_compute_clocks(rdev); 256 atombios_enable_crtc(crtc, ATOM_ENABLE); 257 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 258 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 259 atombios_blank_crtc(crtc, ATOM_DISABLE); 260 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); 261 radeon_crtc_load_lut(crtc); 262 break; 263 case DRM_MODE_DPMS_STANDBY: 264 case DRM_MODE_DPMS_SUSPEND: 265 case DRM_MODE_DPMS_OFF: 266 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); 267 if (radeon_crtc->enabled) 268 atombios_blank_crtc(crtc, ATOM_ENABLE); 269 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 270 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 271 atombios_enable_crtc(crtc, ATOM_DISABLE); 272 radeon_crtc->enabled = false; 273 /* adjust pm to dpms changes AFTER disabling crtcs */ 274 radeon_pm_compute_clocks(rdev); 275 break; 276 } 277 } 278 279 static void 280 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 281 struct drm_display_mode *mode) 282 { 283 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 284 struct drm_device *dev = crtc->dev; 285 struct radeon_device *rdev = dev->dev_private; 286 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 287 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 288 u16 misc = 0; 289 290 memset(&args, 0, sizeof(args)); 291 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 292 args.usH_Blanking_Time = 293 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 294 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 295 args.usV_Blanking_Time = 296 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 297 args.usH_SyncOffset = 298 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 299 args.usH_SyncWidth = 300 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 301 args.usV_SyncOffset = 302 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 303 args.usV_SyncWidth = 304 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 305 args.ucH_Border = radeon_crtc->h_border; 306 args.ucV_Border = radeon_crtc->v_border; 307 308 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 309 misc |= ATOM_VSYNC_POLARITY; 310 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 311 misc |= ATOM_HSYNC_POLARITY; 312 if (mode->flags & DRM_MODE_FLAG_CSYNC) 313 misc |= ATOM_COMPOSITESYNC; 314 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 315 misc |= ATOM_INTERLACE; 316 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 317 misc |= ATOM_DOUBLE_CLOCK_MODE; 318 319 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 320 args.ucCRTC = radeon_crtc->crtc_id; 321 322 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 323 } 324 325 static void atombios_crtc_set_timing(struct drm_crtc *crtc, 326 struct drm_display_mode *mode) 327 { 328 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 329 struct drm_device *dev = crtc->dev; 330 struct radeon_device *rdev = dev->dev_private; 331 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 332 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 333 u16 misc = 0; 334 335 memset(&args, 0, sizeof(args)); 336 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 337 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 338 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 339 args.usH_SyncWidth = 340 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 341 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 342 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 343 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 344 args.usV_SyncWidth = 345 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 346 347 args.ucOverscanRight = radeon_crtc->h_border; 348 args.ucOverscanLeft = radeon_crtc->h_border; 349 args.ucOverscanBottom = radeon_crtc->v_border; 350 args.ucOverscanTop = radeon_crtc->v_border; 351 352 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 353 misc |= ATOM_VSYNC_POLARITY; 354 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 355 misc |= ATOM_HSYNC_POLARITY; 356 if (mode->flags & DRM_MODE_FLAG_CSYNC) 357 misc |= ATOM_COMPOSITESYNC; 358 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 359 misc |= ATOM_INTERLACE; 360 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 361 misc |= ATOM_DOUBLE_CLOCK_MODE; 362 363 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 364 args.ucCRTC = radeon_crtc->crtc_id; 365 366 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 367 } 368 369 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 370 { 371 u32 ss_cntl; 372 373 if (ASIC_IS_DCE4(rdev)) { 374 switch (pll_id) { 375 case ATOM_PPLL1: 376 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 377 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 378 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 379 break; 380 case ATOM_PPLL2: 381 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 382 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 383 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 384 break; 385 case ATOM_DCPLL: 386 case ATOM_PPLL_INVALID: 387 return; 388 } 389 } else if (ASIC_IS_AVIVO(rdev)) { 390 switch (pll_id) { 391 case ATOM_PPLL1: 392 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 393 ss_cntl &= ~1; 394 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 395 break; 396 case ATOM_PPLL2: 397 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 398 ss_cntl &= ~1; 399 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 400 break; 401 case ATOM_DCPLL: 402 case ATOM_PPLL_INVALID: 403 return; 404 } 405 } 406 } 407 408 409 union atom_enable_ss { 410 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 411 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 412 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 413 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 414 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 415 }; 416 417 static void atombios_crtc_program_ss(struct radeon_device *rdev, 418 int enable, 419 int pll_id, 420 int crtc_id, 421 struct radeon_atom_ss *ss) 422 { 423 unsigned i; 424 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 425 union atom_enable_ss args; 426 427 if (!enable) { 428 for (i = 0; i < rdev->num_crtc; i++) { 429 if (rdev->mode_info.crtcs[i] && 430 rdev->mode_info.crtcs[i]->enabled && 431 i != crtc_id && 432 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 433 /* one other crtc is using this pll don't turn 434 * off spread spectrum as it might turn off 435 * display on active crtc 436 */ 437 return; 438 } 439 } 440 } 441 442 memset(&args, 0, sizeof(args)); 443 444 if (ASIC_IS_DCE5(rdev)) { 445 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 446 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 447 switch (pll_id) { 448 case ATOM_PPLL1: 449 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 450 break; 451 case ATOM_PPLL2: 452 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 453 break; 454 case ATOM_DCPLL: 455 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 456 break; 457 case ATOM_PPLL_INVALID: 458 return; 459 } 460 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 461 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 462 args.v3.ucEnable = enable; 463 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) 464 args.v3.ucEnable = ATOM_DISABLE; 465 } else if (ASIC_IS_DCE4(rdev)) { 466 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 467 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 468 switch (pll_id) { 469 case ATOM_PPLL1: 470 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 471 break; 472 case ATOM_PPLL2: 473 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 474 break; 475 case ATOM_DCPLL: 476 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 477 break; 478 case ATOM_PPLL_INVALID: 479 return; 480 } 481 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 482 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 483 args.v2.ucEnable = enable; 484 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev)) 485 args.v2.ucEnable = ATOM_DISABLE; 486 } else if (ASIC_IS_DCE3(rdev)) { 487 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 488 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 489 args.v1.ucSpreadSpectrumStep = ss->step; 490 args.v1.ucSpreadSpectrumDelay = ss->delay; 491 args.v1.ucSpreadSpectrumRange = ss->range; 492 args.v1.ucPpll = pll_id; 493 args.v1.ucEnable = enable; 494 } else if (ASIC_IS_AVIVO(rdev)) { 495 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 496 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 497 atombios_disable_ss(rdev, pll_id); 498 return; 499 } 500 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 501 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 502 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 503 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 504 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 505 args.lvds_ss_2.ucEnable = enable; 506 } else { 507 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 508 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 509 atombios_disable_ss(rdev, pll_id); 510 return; 511 } 512 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 513 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 514 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 515 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 516 args.lvds_ss.ucEnable = enable; 517 } 518 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 519 } 520 521 union adjust_pixel_clock { 522 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 523 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 524 }; 525 526 static u32 atombios_adjust_pll(struct drm_crtc *crtc, 527 struct drm_display_mode *mode) 528 { 529 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 530 struct drm_device *dev = crtc->dev; 531 struct radeon_device *rdev = dev->dev_private; 532 struct drm_encoder *encoder = radeon_crtc->encoder; 533 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 534 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 535 u32 adjusted_clock = mode->clock; 536 int encoder_mode = atombios_get_encoder_mode(encoder); 537 u32 dp_clock = mode->clock; 538 int bpc = radeon_get_monitor_bpc(connector); 539 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 540 541 /* reset the pll flags */ 542 radeon_crtc->pll_flags = 0; 543 544 if (ASIC_IS_AVIVO(rdev)) { 545 if ((rdev->family == CHIP_RS600) || 546 (rdev->family == CHIP_RS690) || 547 (rdev->family == CHIP_RS740)) 548 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 549 RADEON_PLL_PREFER_CLOSEST_LOWER); 550 551 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 552 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 553 else 554 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 555 556 if (rdev->family < CHIP_RV770) 557 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 558 /* use frac fb div on APUs */ 559 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) 560 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 561 /* use frac fb div on RS780/RS880 */ 562 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 563 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 564 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 565 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 566 } else { 567 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 568 569 if (mode->clock > 200000) /* range limits??? */ 570 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 571 else 572 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 573 } 574 575 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 576 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 577 if (connector) { 578 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 579 struct radeon_connector_atom_dig *dig_connector = 580 radeon_connector->con_priv; 581 582 dp_clock = dig_connector->dp_clock; 583 } 584 } 585 586 /* use recommended ref_div for ss */ 587 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 588 if (radeon_crtc->ss_enabled) { 589 if (radeon_crtc->ss.refdiv) { 590 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 591 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 592 if (ASIC_IS_AVIVO(rdev)) 593 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 594 } 595 } 596 } 597 598 if (ASIC_IS_AVIVO(rdev)) { 599 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 600 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 601 adjusted_clock = mode->clock * 2; 602 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 603 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 604 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 605 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 606 } else { 607 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 608 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 609 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 610 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 611 } 612 613 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 614 * accordingly based on the encoder/transmitter to work around 615 * special hw requirements. 616 */ 617 if (ASIC_IS_DCE3(rdev)) { 618 union adjust_pixel_clock args; 619 u8 frev, crev; 620 int index; 621 622 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 623 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 624 &crev)) 625 return adjusted_clock; 626 627 memset(&args, 0, sizeof(args)); 628 629 switch (frev) { 630 case 1: 631 switch (crev) { 632 case 1: 633 case 2: 634 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); 635 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 636 args.v1.ucEncodeMode = encoder_mode; 637 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 638 args.v1.ucConfig |= 639 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 640 641 atom_execute_table(rdev->mode_info.atom_context, 642 index, (uint32_t *)&args); 643 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 644 break; 645 case 3: 646 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10); 647 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 648 args.v3.sInput.ucEncodeMode = encoder_mode; 649 args.v3.sInput.ucDispPllConfig = 0; 650 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 651 args.v3.sInput.ucDispPllConfig |= 652 DISPPLL_CONFIG_SS_ENABLE; 653 if (ENCODER_MODE_IS_DP(encoder_mode)) { 654 args.v3.sInput.ucDispPllConfig |= 655 DISPPLL_CONFIG_COHERENT_MODE; 656 /* 16200 or 27000 */ 657 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 658 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 659 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 660 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) 661 /* deep color support */ 662 args.v3.sInput.usPixelClock = 663 cpu_to_le16((mode->clock * bpc / 8) / 10); 664 if (dig->coherent_mode) 665 args.v3.sInput.ucDispPllConfig |= 666 DISPPLL_CONFIG_COHERENT_MODE; 667 if (is_duallink) 668 args.v3.sInput.ucDispPllConfig |= 669 DISPPLL_CONFIG_DUAL_LINK; 670 } 671 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 672 ENCODER_OBJECT_ID_NONE) 673 args.v3.sInput.ucExtTransmitterID = 674 radeon_encoder_get_dp_bridge_encoder_id(encoder); 675 else 676 args.v3.sInput.ucExtTransmitterID = 0; 677 678 atom_execute_table(rdev->mode_info.atom_context, 679 index, (uint32_t *)&args); 680 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 681 if (args.v3.sOutput.ucRefDiv) { 682 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 683 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 684 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 685 } 686 if (args.v3.sOutput.ucPostDiv) { 687 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 688 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 689 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 690 } 691 break; 692 default: 693 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 694 return adjusted_clock; 695 } 696 break; 697 default: 698 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 699 return adjusted_clock; 700 } 701 } 702 return adjusted_clock; 703 } 704 705 union set_pixel_clock { 706 SET_PIXEL_CLOCK_PS_ALLOCATION base; 707 PIXEL_CLOCK_PARAMETERS v1; 708 PIXEL_CLOCK_PARAMETERS_V2 v2; 709 PIXEL_CLOCK_PARAMETERS_V3 v3; 710 PIXEL_CLOCK_PARAMETERS_V5 v5; 711 PIXEL_CLOCK_PARAMETERS_V6 v6; 712 }; 713 714 /* on DCE5, make sure the voltage is high enough to support the 715 * required disp clk. 716 */ 717 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 718 u32 dispclk) 719 { 720 u8 frev, crev; 721 int index; 722 union set_pixel_clock args; 723 724 memset(&args, 0, sizeof(args)); 725 726 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 727 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 728 &crev)) 729 return; 730 731 switch (frev) { 732 case 1: 733 switch (crev) { 734 case 5: 735 /* if the default dcpll clock is specified, 736 * SetPixelClock provides the dividers 737 */ 738 args.v5.ucCRTC = ATOM_CRTC_INVALID; 739 args.v5.usPixelClock = cpu_to_le16(dispclk); 740 args.v5.ucPpll = ATOM_DCPLL; 741 break; 742 case 6: 743 /* if the default dcpll clock is specified, 744 * SetPixelClock provides the dividers 745 */ 746 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 747 if (ASIC_IS_DCE61(rdev)) 748 args.v6.ucPpll = ATOM_EXT_PLL1; 749 else if (ASIC_IS_DCE6(rdev)) 750 args.v6.ucPpll = ATOM_PPLL0; 751 else 752 args.v6.ucPpll = ATOM_DCPLL; 753 break; 754 default: 755 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 756 return; 757 } 758 break; 759 default: 760 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 761 return; 762 } 763 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 764 } 765 766 static void atombios_crtc_program_pll(struct drm_crtc *crtc, 767 u32 crtc_id, 768 int pll_id, 769 u32 encoder_mode, 770 u32 encoder_id, 771 u32 clock, 772 u32 ref_div, 773 u32 fb_div, 774 u32 frac_fb_div, 775 u32 post_div, 776 int bpc, 777 bool ss_enabled, 778 struct radeon_atom_ss *ss) 779 { 780 struct drm_device *dev = crtc->dev; 781 struct radeon_device *rdev = dev->dev_private; 782 u8 frev, crev; 783 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 784 union set_pixel_clock args; 785 786 memset(&args, 0, sizeof(args)); 787 788 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 789 &crev)) 790 return; 791 792 switch (frev) { 793 case 1: 794 switch (crev) { 795 case 1: 796 if (clock == ATOM_DISABLE) 797 return; 798 args.v1.usPixelClock = cpu_to_le16(clock / 10); 799 args.v1.usRefDiv = cpu_to_le16(ref_div); 800 args.v1.usFbDiv = cpu_to_le16(fb_div); 801 args.v1.ucFracFbDiv = frac_fb_div; 802 args.v1.ucPostDiv = post_div; 803 args.v1.ucPpll = pll_id; 804 args.v1.ucCRTC = crtc_id; 805 args.v1.ucRefDivSrc = 1; 806 break; 807 case 2: 808 args.v2.usPixelClock = cpu_to_le16(clock / 10); 809 args.v2.usRefDiv = cpu_to_le16(ref_div); 810 args.v2.usFbDiv = cpu_to_le16(fb_div); 811 args.v2.ucFracFbDiv = frac_fb_div; 812 args.v2.ucPostDiv = post_div; 813 args.v2.ucPpll = pll_id; 814 args.v2.ucCRTC = crtc_id; 815 args.v2.ucRefDivSrc = 1; 816 break; 817 case 3: 818 args.v3.usPixelClock = cpu_to_le16(clock / 10); 819 args.v3.usRefDiv = cpu_to_le16(ref_div); 820 args.v3.usFbDiv = cpu_to_le16(fb_div); 821 args.v3.ucFracFbDiv = frac_fb_div; 822 args.v3.ucPostDiv = post_div; 823 args.v3.ucPpll = pll_id; 824 if (crtc_id == ATOM_CRTC2) 825 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 826 else 827 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 828 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 829 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 830 args.v3.ucTransmitterId = encoder_id; 831 args.v3.ucEncoderMode = encoder_mode; 832 break; 833 case 5: 834 args.v5.ucCRTC = crtc_id; 835 args.v5.usPixelClock = cpu_to_le16(clock / 10); 836 args.v5.ucRefDiv = ref_div; 837 args.v5.usFbDiv = cpu_to_le16(fb_div); 838 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 839 args.v5.ucPostDiv = post_div; 840 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 841 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 842 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 843 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 844 switch (bpc) { 845 case 8: 846 default: 847 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 848 break; 849 case 10: 850 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 851 break; 852 } 853 } 854 args.v5.ucTransmitterID = encoder_id; 855 args.v5.ucEncoderMode = encoder_mode; 856 args.v5.ucPpll = pll_id; 857 break; 858 case 6: 859 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 860 args.v6.ucRefDiv = ref_div; 861 args.v6.usFbDiv = cpu_to_le16(fb_div); 862 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 863 args.v6.ucPostDiv = post_div; 864 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 865 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 866 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 867 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 868 switch (bpc) { 869 case 8: 870 default: 871 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 872 break; 873 case 10: 874 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 875 break; 876 case 12: 877 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 878 break; 879 case 16: 880 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 881 break; 882 } 883 } 884 args.v6.ucTransmitterID = encoder_id; 885 args.v6.ucEncoderMode = encoder_mode; 886 args.v6.ucPpll = pll_id; 887 break; 888 default: 889 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 890 return; 891 } 892 break; 893 default: 894 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 895 return; 896 } 897 898 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 899 } 900 901 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 902 { 903 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 904 struct drm_device *dev = crtc->dev; 905 struct radeon_device *rdev = dev->dev_private; 906 struct radeon_encoder *radeon_encoder = 907 to_radeon_encoder(radeon_crtc->encoder); 908 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 909 910 radeon_crtc->bpc = 8; 911 radeon_crtc->ss_enabled = false; 912 913 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 914 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 915 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 916 struct drm_connector *connector = 917 radeon_get_connector_for_encoder(radeon_crtc->encoder); 918 struct radeon_connector *radeon_connector = 919 to_radeon_connector(connector); 920 struct radeon_connector_atom_dig *dig_connector = 921 radeon_connector->con_priv; 922 int dp_clock; 923 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 924 925 switch (encoder_mode) { 926 case ATOM_ENCODER_MODE_DP_MST: 927 case ATOM_ENCODER_MODE_DP: 928 /* DP/eDP */ 929 dp_clock = dig_connector->dp_clock / 10; 930 if (ASIC_IS_DCE4(rdev)) 931 radeon_crtc->ss_enabled = 932 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 933 ASIC_INTERNAL_SS_ON_DP, 934 dp_clock); 935 else { 936 if (dp_clock == 16200) { 937 radeon_crtc->ss_enabled = 938 radeon_atombios_get_ppll_ss_info(rdev, 939 &radeon_crtc->ss, 940 ATOM_DP_SS_ID2); 941 if (!radeon_crtc->ss_enabled) 942 radeon_crtc->ss_enabled = 943 radeon_atombios_get_ppll_ss_info(rdev, 944 &radeon_crtc->ss, 945 ATOM_DP_SS_ID1); 946 } else { 947 radeon_crtc->ss_enabled = 948 radeon_atombios_get_ppll_ss_info(rdev, 949 &radeon_crtc->ss, 950 ATOM_DP_SS_ID1); 951 } 952 /* disable spread spectrum on DCE3 DP */ 953 radeon_crtc->ss_enabled = false; 954 } 955 break; 956 case ATOM_ENCODER_MODE_LVDS: 957 if (ASIC_IS_DCE4(rdev)) 958 radeon_crtc->ss_enabled = 959 radeon_atombios_get_asic_ss_info(rdev, 960 &radeon_crtc->ss, 961 dig->lcd_ss_id, 962 mode->clock / 10); 963 else 964 radeon_crtc->ss_enabled = 965 radeon_atombios_get_ppll_ss_info(rdev, 966 &radeon_crtc->ss, 967 dig->lcd_ss_id); 968 break; 969 case ATOM_ENCODER_MODE_DVI: 970 if (ASIC_IS_DCE4(rdev)) 971 radeon_crtc->ss_enabled = 972 radeon_atombios_get_asic_ss_info(rdev, 973 &radeon_crtc->ss, 974 ASIC_INTERNAL_SS_ON_TMDS, 975 mode->clock / 10); 976 break; 977 case ATOM_ENCODER_MODE_HDMI: 978 if (ASIC_IS_DCE4(rdev)) 979 radeon_crtc->ss_enabled = 980 radeon_atombios_get_asic_ss_info(rdev, 981 &radeon_crtc->ss, 982 ASIC_INTERNAL_SS_ON_HDMI, 983 mode->clock / 10); 984 break; 985 default: 986 break; 987 } 988 } 989 990 /* adjust pixel clock as needed */ 991 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 992 993 return true; 994 } 995 996 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 997 { 998 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 999 struct drm_device *dev = crtc->dev; 1000 struct radeon_device *rdev = dev->dev_private; 1001 struct radeon_encoder *radeon_encoder = 1002 to_radeon_encoder(radeon_crtc->encoder); 1003 u32 pll_clock = mode->clock; 1004 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 1005 struct radeon_pll *pll; 1006 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1007 1008 switch (radeon_crtc->pll_id) { 1009 case ATOM_PPLL1: 1010 pll = &rdev->clock.p1pll; 1011 break; 1012 case ATOM_PPLL2: 1013 pll = &rdev->clock.p2pll; 1014 break; 1015 case ATOM_DCPLL: 1016 case ATOM_PPLL_INVALID: 1017 default: 1018 pll = &rdev->clock.dcpll; 1019 break; 1020 } 1021 1022 /* update pll params */ 1023 pll->flags = radeon_crtc->pll_flags; 1024 pll->reference_div = radeon_crtc->pll_reference_div; 1025 pll->post_div = radeon_crtc->pll_post_div; 1026 1027 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1028 /* TV seems to prefer the legacy algo on some boards */ 1029 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1030 &fb_div, &frac_fb_div, &ref_div, &post_div); 1031 else if (ASIC_IS_AVIVO(rdev)) 1032 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1033 &fb_div, &frac_fb_div, &ref_div, &post_div); 1034 else 1035 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1036 &fb_div, &frac_fb_div, &ref_div, &post_div); 1037 1038 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1039 radeon_crtc->crtc_id, &radeon_crtc->ss); 1040 1041 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1042 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1043 ref_div, fb_div, frac_fb_div, post_div, 1044 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1045 1046 if (radeon_crtc->ss_enabled) { 1047 /* calculate ss amount and step size */ 1048 if (ASIC_IS_DCE4(rdev)) { 1049 u32 step_size; 1050 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000; 1051 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1052 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1053 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1054 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1055 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1056 (125 * 25 * pll->reference_freq / 100); 1057 else 1058 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) / 1059 (125 * 25 * pll->reference_freq / 100); 1060 radeon_crtc->ss.step = step_size; 1061 } 1062 1063 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1064 radeon_crtc->crtc_id, &radeon_crtc->ss); 1065 } 1066 } 1067 1068 static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1069 struct drm_framebuffer *fb, 1070 int x, int y, int atomic) 1071 { 1072 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1073 struct drm_device *dev = crtc->dev; 1074 struct radeon_device *rdev = dev->dev_private; 1075 struct radeon_framebuffer *radeon_fb; 1076 struct drm_framebuffer *target_fb; 1077 struct drm_gem_object *obj; 1078 struct radeon_bo *rbo; 1079 uint64_t fb_location; 1080 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1081 unsigned bankw, bankh, mtaspect, tile_split; 1082 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1083 u32 tmp, viewport_w, viewport_h; 1084 int r; 1085 1086 /* no fb bound */ 1087 if (!atomic && !crtc->fb) { 1088 DRM_DEBUG_KMS("No FB bound\n"); 1089 return 0; 1090 } 1091 1092 if (atomic) { 1093 radeon_fb = to_radeon_framebuffer(fb); 1094 target_fb = fb; 1095 } 1096 else { 1097 radeon_fb = to_radeon_framebuffer(crtc->fb); 1098 target_fb = crtc->fb; 1099 } 1100 1101 /* If atomic, assume fb object is pinned & idle & fenced and 1102 * just update base pointers 1103 */ 1104 obj = radeon_fb->obj; 1105 rbo = gem_to_radeon_bo(obj); 1106 r = radeon_bo_reserve(rbo, false); 1107 if (unlikely(r != 0)) 1108 return r; 1109 1110 if (atomic) 1111 fb_location = radeon_bo_gpu_offset(rbo); 1112 else { 1113 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1114 if (unlikely(r != 0)) { 1115 radeon_bo_unreserve(rbo); 1116 return -EINVAL; 1117 } 1118 } 1119 1120 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1121 radeon_bo_unreserve(rbo); 1122 1123 switch (target_fb->bits_per_pixel) { 1124 case 8: 1125 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1126 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1127 break; 1128 case 15: 1129 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1130 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1131 break; 1132 case 16: 1133 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1134 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1135 #ifdef __BIG_ENDIAN 1136 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1137 #endif 1138 break; 1139 case 24: 1140 case 32: 1141 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1142 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1143 #ifdef __BIG_ENDIAN 1144 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1145 #endif 1146 break; 1147 default: 1148 DRM_ERROR("Unsupported screen depth %d\n", 1149 target_fb->bits_per_pixel); 1150 return -EINVAL; 1151 } 1152 1153 if (tiling_flags & RADEON_TILING_MACRO) { 1154 if (rdev->family >= CHIP_TAHITI) 1155 tmp = rdev->config.si.tile_config; 1156 else if (rdev->family >= CHIP_CAYMAN) 1157 tmp = rdev->config.cayman.tile_config; 1158 else 1159 tmp = rdev->config.evergreen.tile_config; 1160 1161 switch ((tmp & 0xf0) >> 4) { 1162 case 0: /* 4 banks */ 1163 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1164 break; 1165 case 1: /* 8 banks */ 1166 default: 1167 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1168 break; 1169 case 2: /* 16 banks */ 1170 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1171 break; 1172 } 1173 1174 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1175 1176 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1177 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1178 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1179 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1180 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1181 } else if (tiling_flags & RADEON_TILING_MICRO) 1182 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1183 1184 if ((rdev->family == CHIP_TAHITI) || 1185 (rdev->family == CHIP_PITCAIRN)) 1186 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1187 else if (rdev->family == CHIP_VERDE) 1188 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1189 1190 switch (radeon_crtc->crtc_id) { 1191 case 0: 1192 WREG32(AVIVO_D1VGA_CONTROL, 0); 1193 break; 1194 case 1: 1195 WREG32(AVIVO_D2VGA_CONTROL, 0); 1196 break; 1197 case 2: 1198 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1199 break; 1200 case 3: 1201 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1202 break; 1203 case 4: 1204 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1205 break; 1206 case 5: 1207 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1208 break; 1209 default: 1210 break; 1211 } 1212 1213 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1214 upper_32_bits(fb_location)); 1215 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1216 upper_32_bits(fb_location)); 1217 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1218 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1219 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1220 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1221 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1222 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1223 1224 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1225 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1226 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1227 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1228 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1229 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1230 1231 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1232 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1233 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1234 1235 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1236 target_fb->height); 1237 x &= ~3; 1238 y &= ~1; 1239 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1240 (x << 16) | y); 1241 viewport_w = crtc->mode.hdisplay; 1242 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1243 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1244 (viewport_w << 16) | viewport_h); 1245 1246 /* pageflip setup */ 1247 /* make sure flip is at vb rather than hb */ 1248 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1249 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1250 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1251 1252 /* set pageflip to happen anywhere in vblank interval */ 1253 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1254 1255 if (!atomic && fb && fb != crtc->fb) { 1256 radeon_fb = to_radeon_framebuffer(fb); 1257 rbo = gem_to_radeon_bo(radeon_fb->obj); 1258 r = radeon_bo_reserve(rbo, false); 1259 if (unlikely(r != 0)) 1260 return r; 1261 radeon_bo_unpin(rbo); 1262 radeon_bo_unreserve(rbo); 1263 } 1264 1265 /* Bytes per pixel may have changed */ 1266 radeon_bandwidth_update(rdev); 1267 1268 return 0; 1269 } 1270 1271 static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1272 struct drm_framebuffer *fb, 1273 int x, int y, int atomic) 1274 { 1275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1276 struct drm_device *dev = crtc->dev; 1277 struct radeon_device *rdev = dev->dev_private; 1278 struct radeon_framebuffer *radeon_fb; 1279 struct drm_gem_object *obj; 1280 struct radeon_bo *rbo; 1281 struct drm_framebuffer *target_fb; 1282 uint64_t fb_location; 1283 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1284 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1285 u32 tmp, viewport_w, viewport_h; 1286 int r; 1287 1288 /* no fb bound */ 1289 if (!atomic && !crtc->fb) { 1290 DRM_DEBUG_KMS("No FB bound\n"); 1291 return 0; 1292 } 1293 1294 if (atomic) { 1295 radeon_fb = to_radeon_framebuffer(fb); 1296 target_fb = fb; 1297 } 1298 else { 1299 radeon_fb = to_radeon_framebuffer(crtc->fb); 1300 target_fb = crtc->fb; 1301 } 1302 1303 obj = radeon_fb->obj; 1304 rbo = gem_to_radeon_bo(obj); 1305 r = radeon_bo_reserve(rbo, false); 1306 if (unlikely(r != 0)) 1307 return r; 1308 1309 /* If atomic, assume fb object is pinned & idle & fenced and 1310 * just update base pointers 1311 */ 1312 if (atomic) 1313 fb_location = radeon_bo_gpu_offset(rbo); 1314 else { 1315 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1316 if (unlikely(r != 0)) { 1317 radeon_bo_unreserve(rbo); 1318 return -EINVAL; 1319 } 1320 } 1321 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1322 radeon_bo_unreserve(rbo); 1323 1324 switch (target_fb->bits_per_pixel) { 1325 case 8: 1326 fb_format = 1327 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1328 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1329 break; 1330 case 15: 1331 fb_format = 1332 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1333 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1334 break; 1335 case 16: 1336 fb_format = 1337 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1338 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1339 #ifdef __BIG_ENDIAN 1340 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1341 #endif 1342 break; 1343 case 24: 1344 case 32: 1345 fb_format = 1346 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1347 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1348 #ifdef __BIG_ENDIAN 1349 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1350 #endif 1351 break; 1352 default: 1353 DRM_ERROR("Unsupported screen depth %d\n", 1354 target_fb->bits_per_pixel); 1355 return -EINVAL; 1356 } 1357 1358 if (rdev->family >= CHIP_R600) { 1359 if (tiling_flags & RADEON_TILING_MACRO) 1360 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1361 else if (tiling_flags & RADEON_TILING_MICRO) 1362 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1363 } else { 1364 if (tiling_flags & RADEON_TILING_MACRO) 1365 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1366 1367 if (tiling_flags & RADEON_TILING_MICRO) 1368 fb_format |= AVIVO_D1GRPH_TILED; 1369 } 1370 1371 if (radeon_crtc->crtc_id == 0) 1372 WREG32(AVIVO_D1VGA_CONTROL, 0); 1373 else 1374 WREG32(AVIVO_D2VGA_CONTROL, 0); 1375 1376 if (rdev->family >= CHIP_RV770) { 1377 if (radeon_crtc->crtc_id) { 1378 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1379 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1380 } else { 1381 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1382 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1383 } 1384 } 1385 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1386 (u32) fb_location); 1387 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1388 radeon_crtc->crtc_offset, (u32) fb_location); 1389 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1390 if (rdev->family >= CHIP_R600) 1391 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1392 1393 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1394 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1395 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1396 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1397 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1398 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1399 1400 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 1401 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1402 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1403 1404 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1405 target_fb->height); 1406 x &= ~3; 1407 y &= ~1; 1408 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1409 (x << 16) | y); 1410 viewport_w = crtc->mode.hdisplay; 1411 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1412 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1413 (viewport_w << 16) | viewport_h); 1414 1415 /* pageflip setup */ 1416 /* make sure flip is at vb rather than hb */ 1417 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset); 1418 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 1419 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp); 1420 1421 /* set pageflip to happen anywhere in vblank interval */ 1422 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1423 1424 if (!atomic && fb && fb != crtc->fb) { 1425 radeon_fb = to_radeon_framebuffer(fb); 1426 rbo = gem_to_radeon_bo(radeon_fb->obj); 1427 r = radeon_bo_reserve(rbo, false); 1428 if (unlikely(r != 0)) 1429 return r; 1430 radeon_bo_unpin(rbo); 1431 radeon_bo_unreserve(rbo); 1432 } 1433 1434 /* Bytes per pixel may have changed */ 1435 radeon_bandwidth_update(rdev); 1436 1437 return 0; 1438 } 1439 1440 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1441 struct drm_framebuffer *old_fb) 1442 { 1443 struct drm_device *dev = crtc->dev; 1444 struct radeon_device *rdev = dev->dev_private; 1445 1446 if (ASIC_IS_DCE4(rdev)) 1447 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1448 else if (ASIC_IS_AVIVO(rdev)) 1449 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1450 else 1451 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1452 } 1453 1454 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1455 struct drm_framebuffer *fb, 1456 int x, int y, enum mode_set_atomic state) 1457 { 1458 struct drm_device *dev = crtc->dev; 1459 struct radeon_device *rdev = dev->dev_private; 1460 1461 if (ASIC_IS_DCE4(rdev)) 1462 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1463 else if (ASIC_IS_AVIVO(rdev)) 1464 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1465 else 1466 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1467 } 1468 1469 /* properly set additional regs when using atombios */ 1470 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1471 { 1472 struct drm_device *dev = crtc->dev; 1473 struct radeon_device *rdev = dev->dev_private; 1474 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1475 u32 disp_merge_cntl; 1476 1477 switch (radeon_crtc->crtc_id) { 1478 case 0: 1479 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1480 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1481 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1482 break; 1483 case 1: 1484 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1485 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1486 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1487 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1488 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1489 break; 1490 } 1491 } 1492 1493 /** 1494 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1495 * 1496 * @crtc: drm crtc 1497 * 1498 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1499 */ 1500 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1501 { 1502 struct drm_device *dev = crtc->dev; 1503 struct drm_crtc *test_crtc; 1504 struct radeon_crtc *test_radeon_crtc; 1505 u32 pll_in_use = 0; 1506 1507 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1508 if (crtc == test_crtc) 1509 continue; 1510 1511 test_radeon_crtc = to_radeon_crtc(test_crtc); 1512 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1513 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1514 } 1515 return pll_in_use; 1516 } 1517 1518 /** 1519 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1520 * 1521 * @crtc: drm crtc 1522 * 1523 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1524 * also in DP mode. For DP, a single PPLL can be used for all DP 1525 * crtcs/encoders. 1526 */ 1527 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1528 { 1529 struct drm_device *dev = crtc->dev; 1530 struct drm_crtc *test_crtc; 1531 struct radeon_crtc *test_radeon_crtc; 1532 1533 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1534 if (crtc == test_crtc) 1535 continue; 1536 test_radeon_crtc = to_radeon_crtc(test_crtc); 1537 if (test_radeon_crtc->encoder && 1538 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1539 /* for DP use the same PLL for all */ 1540 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1541 return test_radeon_crtc->pll_id; 1542 } 1543 } 1544 return ATOM_PPLL_INVALID; 1545 } 1546 1547 /** 1548 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1549 * 1550 * @crtc: drm crtc 1551 * @encoder: drm encoder 1552 * 1553 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1554 * be shared (i.e., same clock). 1555 */ 1556 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1557 { 1558 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1559 struct drm_device *dev = crtc->dev; 1560 struct drm_crtc *test_crtc; 1561 struct radeon_crtc *test_radeon_crtc; 1562 u32 adjusted_clock, test_adjusted_clock; 1563 1564 adjusted_clock = radeon_crtc->adjusted_clock; 1565 1566 if (adjusted_clock == 0) 1567 return ATOM_PPLL_INVALID; 1568 1569 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1570 if (crtc == test_crtc) 1571 continue; 1572 test_radeon_crtc = to_radeon_crtc(test_crtc); 1573 if (test_radeon_crtc->encoder && 1574 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1575 /* check if we are already driving this connector with another crtc */ 1576 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1577 /* if we are, return that pll */ 1578 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1579 return test_radeon_crtc->pll_id; 1580 } 1581 /* for non-DP check the clock */ 1582 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1583 if ((crtc->mode.clock == test_crtc->mode.clock) && 1584 (adjusted_clock == test_adjusted_clock) && 1585 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1586 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1587 return test_radeon_crtc->pll_id; 1588 } 1589 } 1590 return ATOM_PPLL_INVALID; 1591 } 1592 1593 /** 1594 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1595 * 1596 * @crtc: drm crtc 1597 * 1598 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1599 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1600 * monitors a dedicated PPLL must be used. If a particular board has 1601 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1602 * as there is no need to program the PLL itself. If we are not able to 1603 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1604 * avoid messing up an existing monitor. 1605 * 1606 * Asic specific PLL information 1607 * 1608 * DCE 6.1 1609 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1610 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1611 * 1612 * DCE 6.0 1613 * - PPLL0 is available to all UNIPHY (DP only) 1614 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1615 * 1616 * DCE 5.0 1617 * - DCPLL is available to all UNIPHY (DP only) 1618 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1619 * 1620 * DCE 3.0/4.0/4.1 1621 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1622 * 1623 */ 1624 static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1625 { 1626 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1627 struct drm_device *dev = crtc->dev; 1628 struct radeon_device *rdev = dev->dev_private; 1629 struct radeon_encoder *radeon_encoder = 1630 to_radeon_encoder(radeon_crtc->encoder); 1631 u32 pll_in_use; 1632 int pll; 1633 1634 if (ASIC_IS_DCE61(rdev)) { 1635 struct radeon_encoder_atom_dig *dig = 1636 radeon_encoder->enc_priv; 1637 1638 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1639 (dig->linkb == false)) 1640 /* UNIPHY A uses PPLL2 */ 1641 return ATOM_PPLL2; 1642 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1643 /* UNIPHY B/C/D/E/F */ 1644 if (rdev->clock.dp_extclk) 1645 /* skip PPLL programming if using ext clock */ 1646 return ATOM_PPLL_INVALID; 1647 else { 1648 /* use the same PPLL for all DP monitors */ 1649 pll = radeon_get_shared_dp_ppll(crtc); 1650 if (pll != ATOM_PPLL_INVALID) 1651 return pll; 1652 } 1653 } else { 1654 /* use the same PPLL for all monitors with the same clock */ 1655 pll = radeon_get_shared_nondp_ppll(crtc); 1656 if (pll != ATOM_PPLL_INVALID) 1657 return pll; 1658 } 1659 /* UNIPHY B/C/D/E/F */ 1660 pll_in_use = radeon_get_pll_use_mask(crtc); 1661 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1662 return ATOM_PPLL0; 1663 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1664 return ATOM_PPLL1; 1665 DRM_ERROR("unable to allocate a PPLL\n"); 1666 return ATOM_PPLL_INVALID; 1667 } else if (ASIC_IS_DCE41(rdev)) { 1668 /* Don't share PLLs on DCE4.1 chips */ 1669 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1670 if (rdev->clock.dp_extclk) 1671 /* skip PPLL programming if using ext clock */ 1672 return ATOM_PPLL_INVALID; 1673 } 1674 pll_in_use = radeon_get_pll_use_mask(crtc); 1675 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1676 return ATOM_PPLL1; 1677 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1678 return ATOM_PPLL2; 1679 DRM_ERROR("unable to allocate a PPLL\n"); 1680 return ATOM_PPLL_INVALID; 1681 } else if (ASIC_IS_DCE4(rdev)) { 1682 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1683 * depending on the asic: 1684 * DCE4: PPLL or ext clock 1685 * DCE5: PPLL, DCPLL, or ext clock 1686 * DCE6: PPLL, PPLL0, or ext clock 1687 * 1688 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1689 * PPLL/DCPLL programming and only program the DP DTO for the 1690 * crtc virtual pixel clock. 1691 */ 1692 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1693 if (rdev->clock.dp_extclk) 1694 /* skip PPLL programming if using ext clock */ 1695 return ATOM_PPLL_INVALID; 1696 else if (ASIC_IS_DCE6(rdev)) 1697 /* use PPLL0 for all DP */ 1698 return ATOM_PPLL0; 1699 else if (ASIC_IS_DCE5(rdev)) 1700 /* use DCPLL for all DP */ 1701 return ATOM_DCPLL; 1702 else { 1703 /* use the same PPLL for all DP monitors */ 1704 pll = radeon_get_shared_dp_ppll(crtc); 1705 if (pll != ATOM_PPLL_INVALID) 1706 return pll; 1707 } 1708 } else { 1709 /* use the same PPLL for all monitors with the same clock */ 1710 pll = radeon_get_shared_nondp_ppll(crtc); 1711 if (pll != ATOM_PPLL_INVALID) 1712 return pll; 1713 } 1714 /* all other cases */ 1715 pll_in_use = radeon_get_pll_use_mask(crtc); 1716 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1717 return ATOM_PPLL1; 1718 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1719 return ATOM_PPLL2; 1720 DRM_ERROR("unable to allocate a PPLL\n"); 1721 return ATOM_PPLL_INVALID; 1722 } else { 1723 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 1724 /* some atombios (observed in some DCE2/DCE3) code have a bug, 1725 * the matching btw pll and crtc is done through 1726 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 1727 * pll (1 or 2) to select which register to write. ie if using 1728 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 1729 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 1730 * choose which value to write. Which is reverse order from 1731 * register logic. So only case that works is when pllid is 1732 * same as crtcid or when both pll and crtc are enabled and 1733 * both use same clock. 1734 * 1735 * So just return crtc id as if crtc and pll were hard linked 1736 * together even if they aren't 1737 */ 1738 return radeon_crtc->crtc_id; 1739 } 1740 } 1741 1742 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 1743 { 1744 /* always set DCPLL */ 1745 if (ASIC_IS_DCE6(rdev)) 1746 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1747 else if (ASIC_IS_DCE4(rdev)) { 1748 struct radeon_atom_ss ss; 1749 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 1750 ASIC_INTERNAL_SS_ON_DCPLL, 1751 rdev->clock.default_dispclk); 1752 if (ss_enabled) 1753 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 1754 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1755 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1756 if (ss_enabled) 1757 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 1758 } 1759 1760 } 1761 1762 int atombios_crtc_mode_set(struct drm_crtc *crtc, 1763 struct drm_display_mode *mode, 1764 struct drm_display_mode *adjusted_mode, 1765 int x, int y, struct drm_framebuffer *old_fb) 1766 { 1767 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1768 struct drm_device *dev = crtc->dev; 1769 struct radeon_device *rdev = dev->dev_private; 1770 struct radeon_encoder *radeon_encoder = 1771 to_radeon_encoder(radeon_crtc->encoder); 1772 bool is_tvcv = false; 1773 1774 if (radeon_encoder->active_device & 1775 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 1776 is_tvcv = true; 1777 1778 atombios_crtc_set_pll(crtc, adjusted_mode); 1779 1780 if (ASIC_IS_DCE4(rdev)) 1781 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1782 else if (ASIC_IS_AVIVO(rdev)) { 1783 if (is_tvcv) 1784 atombios_crtc_set_timing(crtc, adjusted_mode); 1785 else 1786 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1787 } else { 1788 atombios_crtc_set_timing(crtc, adjusted_mode); 1789 if (radeon_crtc->crtc_id == 0) 1790 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 1791 radeon_legacy_atom_fixup(crtc); 1792 } 1793 atombios_crtc_set_base(crtc, x, y, old_fb); 1794 atombios_overscan_setup(crtc, mode, adjusted_mode); 1795 atombios_scaler_setup(crtc); 1796 return 0; 1797 } 1798 1799 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 1800 const struct drm_display_mode *mode, 1801 struct drm_display_mode *adjusted_mode) 1802 { 1803 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1804 struct drm_device *dev = crtc->dev; 1805 struct drm_encoder *encoder; 1806 1807 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 1808 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1809 if (encoder->crtc == crtc) { 1810 radeon_crtc->encoder = encoder; 1811 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 1812 break; 1813 } 1814 } 1815 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 1816 radeon_crtc->encoder = NULL; 1817 radeon_crtc->connector = NULL; 1818 return false; 1819 } 1820 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 1821 return false; 1822 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 1823 return false; 1824 /* pick pll */ 1825 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 1826 /* if we can't get a PPLL for a non-DP encoder, fail */ 1827 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 1828 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 1829 return false; 1830 1831 return true; 1832 } 1833 1834 static void atombios_crtc_prepare(struct drm_crtc *crtc) 1835 { 1836 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1837 struct drm_device *dev = crtc->dev; 1838 struct radeon_device *rdev = dev->dev_private; 1839 1840 radeon_crtc->in_mode_set = true; 1841 1842 /* disable crtc pair power gating before programming */ 1843 if (ASIC_IS_DCE6(rdev)) 1844 atombios_powergate_crtc(crtc, ATOM_DISABLE); 1845 1846 atombios_lock_crtc(crtc, ATOM_ENABLE); 1847 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1848 } 1849 1850 static void atombios_crtc_commit(struct drm_crtc *crtc) 1851 { 1852 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1853 1854 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 1855 atombios_lock_crtc(crtc, ATOM_DISABLE); 1856 radeon_crtc->in_mode_set = false; 1857 } 1858 1859 static void atombios_crtc_disable(struct drm_crtc *crtc) 1860 { 1861 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1862 struct drm_device *dev = crtc->dev; 1863 struct radeon_device *rdev = dev->dev_private; 1864 struct radeon_atom_ss ss; 1865 int i; 1866 1867 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1868 if (ASIC_IS_DCE6(rdev)) 1869 atombios_powergate_crtc(crtc, ATOM_ENABLE); 1870 1871 for (i = 0; i < rdev->num_crtc; i++) { 1872 if (rdev->mode_info.crtcs[i] && 1873 rdev->mode_info.crtcs[i]->enabled && 1874 i != radeon_crtc->crtc_id && 1875 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 1876 /* one other crtc is using this pll don't turn 1877 * off the pll 1878 */ 1879 goto done; 1880 } 1881 } 1882 1883 switch (radeon_crtc->pll_id) { 1884 case ATOM_PPLL1: 1885 case ATOM_PPLL2: 1886 /* disable the ppll */ 1887 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1888 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1889 break; 1890 case ATOM_PPLL0: 1891 /* disable the ppll */ 1892 if (ASIC_IS_DCE61(rdev)) 1893 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1894 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 1895 break; 1896 default: 1897 break; 1898 } 1899 done: 1900 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1901 radeon_crtc->adjusted_clock = 0; 1902 radeon_crtc->encoder = NULL; 1903 radeon_crtc->connector = NULL; 1904 } 1905 1906 static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1907 .dpms = atombios_crtc_dpms, 1908 .mode_fixup = atombios_crtc_mode_fixup, 1909 .mode_set = atombios_crtc_mode_set, 1910 .mode_set_base = atombios_crtc_set_base, 1911 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 1912 .prepare = atombios_crtc_prepare, 1913 .commit = atombios_crtc_commit, 1914 .load_lut = radeon_crtc_load_lut, 1915 .disable = atombios_crtc_disable, 1916 }; 1917 1918 void radeon_atombios_init_crtc(struct drm_device *dev, 1919 struct radeon_crtc *radeon_crtc) 1920 { 1921 struct radeon_device *rdev = dev->dev_private; 1922 1923 if (ASIC_IS_DCE4(rdev)) { 1924 switch (radeon_crtc->crtc_id) { 1925 case 0: 1926 default: 1927 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 1928 break; 1929 case 1: 1930 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 1931 break; 1932 case 2: 1933 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 1934 break; 1935 case 3: 1936 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 1937 break; 1938 case 4: 1939 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 1940 break; 1941 case 5: 1942 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 1943 break; 1944 } 1945 } else { 1946 if (radeon_crtc->crtc_id == 1) 1947 radeon_crtc->crtc_offset = 1948 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 1949 else 1950 radeon_crtc->crtc_offset = 0; 1951 } 1952 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 1953 radeon_crtc->adjusted_clock = 0; 1954 radeon_crtc->encoder = NULL; 1955 radeon_crtc->connector = NULL; 1956 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1957 } 1958