1 /* $OpenBSD: atombios.h,v 1.1 2013/08/12 04:11:53 jsg Exp $ */ 2 /* 3 * Copyright 2006-2007 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 25 /****************************************************************************/ 26 /*Portion I: Definitions shared between VBIOS and Driver */ 27 /****************************************************************************/ 28 29 30 #ifndef _ATOMBIOS_H 31 #define _ATOMBIOS_H 32 33 #define ATOM_VERSION_MAJOR 0x00020000 34 #define ATOM_VERSION_MINOR 0x00000002 35 36 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 37 38 /* Endianness should be specified before inclusion, 39 * default to little endian 40 */ 41 #ifndef ATOM_BIG_ENDIAN 42 #error Endian not specified 43 #endif 44 45 #ifdef _H2INC 46 #ifndef ULONG 47 typedef unsigned long ULONG; 48 #endif 49 50 #ifndef UCHAR 51 typedef unsigned char UCHAR; 52 #endif 53 54 #ifndef USHORT 55 typedef unsigned short USHORT; 56 #endif 57 #endif 58 59 #define ATOM_DAC_A 0 60 #define ATOM_DAC_B 1 61 #define ATOM_EXT_DAC 2 62 63 #define ATOM_CRTC1 0 64 #define ATOM_CRTC2 1 65 #define ATOM_CRTC3 2 66 #define ATOM_CRTC4 3 67 #define ATOM_CRTC5 4 68 #define ATOM_CRTC6 5 69 #define ATOM_CRTC_INVALID 0xFF 70 71 #define ATOM_DIGA 0 72 #define ATOM_DIGB 1 73 74 #define ATOM_PPLL1 0 75 #define ATOM_PPLL2 1 76 #define ATOM_DCPLL 2 77 #define ATOM_PPLL0 2 78 #define ATOM_EXT_PLL1 8 79 #define ATOM_EXT_PLL2 9 80 #define ATOM_EXT_CLOCK 10 81 #define ATOM_PPLL_INVALID 0xFF 82 83 #define ENCODER_REFCLK_SRC_P1PLL 0 84 #define ENCODER_REFCLK_SRC_P2PLL 1 85 #define ENCODER_REFCLK_SRC_DCPLL 2 86 #define ENCODER_REFCLK_SRC_EXTCLK 3 87 #define ENCODER_REFCLK_SRC_INVALID 0xFF 88 89 #define ATOM_SCALER1 0 90 #define ATOM_SCALER2 1 91 92 #define ATOM_SCALER_DISABLE 0 93 #define ATOM_SCALER_CENTER 1 94 #define ATOM_SCALER_EXPANSION 2 95 #define ATOM_SCALER_MULTI_EX 3 96 97 #define ATOM_DISABLE 0 98 #define ATOM_ENABLE 1 99 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 100 #define ATOM_LCD_BLON (ATOM_ENABLE+2) 101 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 102 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 103 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 104 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 105 #define ATOM_INIT (ATOM_DISABLE+7) 106 #define ATOM_GET_STATUS (ATOM_DISABLE+8) 107 108 #define ATOM_BLANKING 1 109 #define ATOM_BLANKING_OFF 0 110 111 #define ATOM_CURSOR1 0 112 #define ATOM_CURSOR2 1 113 114 #define ATOM_ICON1 0 115 #define ATOM_ICON2 1 116 117 #define ATOM_CRT1 0 118 #define ATOM_CRT2 1 119 120 #define ATOM_TV_NTSC 1 121 #define ATOM_TV_NTSCJ 2 122 #define ATOM_TV_PAL 3 123 #define ATOM_TV_PALM 4 124 #define ATOM_TV_PALCN 5 125 #define ATOM_TV_PALN 6 126 #define ATOM_TV_PAL60 7 127 #define ATOM_TV_SECAM 8 128 #define ATOM_TV_CV 16 129 130 #define ATOM_DAC1_PS2 1 131 #define ATOM_DAC1_CV 2 132 #define ATOM_DAC1_NTSC 3 133 #define ATOM_DAC1_PAL 4 134 135 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 136 #define ATOM_DAC2_CV ATOM_DAC1_CV 137 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 138 #define ATOM_DAC2_PAL ATOM_DAC1_PAL 139 140 #define ATOM_PM_ON 0 141 #define ATOM_PM_STANDBY 1 142 #define ATOM_PM_SUSPEND 2 143 #define ATOM_PM_OFF 3 144 145 /* Bit0:{=0:single, =1:dual}, 146 Bit1 {=0:666RGB, =1:888RGB}, 147 Bit2:3:{Grey level} 148 Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ 149 150 #define ATOM_PANEL_MISC_DUAL 0x00000001 151 #define ATOM_PANEL_MISC_888RGB 0x00000002 152 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 153 #define ATOM_PANEL_MISC_FPDI 0x00000010 154 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 155 #define ATOM_PANEL_MISC_SPATIAL 0x00000020 156 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 157 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 158 159 160 #define MEMTYPE_DDR1 "DDR1" 161 #define MEMTYPE_DDR2 "DDR2" 162 #define MEMTYPE_DDR3 "DDR3" 163 #define MEMTYPE_DDR4 "DDR4" 164 165 #define ASIC_BUS_TYPE_PCI "PCI" 166 #define ASIC_BUS_TYPE_AGP "AGP" 167 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 168 169 /* Maximum size of that FireGL flag string */ 170 171 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 172 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 173 174 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 175 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 176 177 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 178 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 179 180 #define HW_ASSISTED_I2C_STATUS_FAILURE 2 181 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 182 183 #pragma pack(1) /* BIOS data must use byte aligment */ 184 185 /* Define offset to location of ROM header. */ 186 187 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 188 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 189 190 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 191 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ 192 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 193 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 194 195 /* Common header for all ROM Data tables. 196 Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 197 And the pointer actually points to this header. */ 198 199 typedef struct _ATOM_COMMON_TABLE_HEADER 200 { 201 USHORT usStructureSize; 202 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ 203 UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ 204 /*Image can't be updated, while Driver needs to carry the new table! */ 205 }ATOM_COMMON_TABLE_HEADER; 206 207 /****************************************************************************/ 208 // Structure stores the ROM header. 209 /****************************************************************************/ 210 typedef struct _ATOM_ROM_HEADER 211 { 212 ATOM_COMMON_TABLE_HEADER sHeader; 213 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, 214 atombios should init it as "ATOM", don't change the position */ 215 USHORT usBiosRuntimeSegmentAddress; 216 USHORT usProtectedModeInfoOffset; 217 USHORT usConfigFilenameOffset; 218 USHORT usCRC_BlockOffset; 219 USHORT usBIOS_BootupMessageOffset; 220 USHORT usInt10Offset; 221 USHORT usPciBusDevInitCode; 222 USHORT usIoBaseAddress; 223 USHORT usSubsystemVendorID; 224 USHORT usSubsystemID; 225 USHORT usPCI_InfoOffset; 226 USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ 227 USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ 228 UCHAR ucExtendedFunctionCode; 229 UCHAR ucReserved; 230 }ATOM_ROM_HEADER; 231 232 /*==============================Command Table Portion==================================== */ 233 234 #ifdef UEFI_BUILD 235 #define UTEMP USHORT 236 #define USHORT void* 237 #endif 238 239 /****************************************************************************/ 240 // Structures used in Command.mtb 241 /****************************************************************************/ 242 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 243 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 244 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 245 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 246 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 247 USHORT DIGxEncoderControl; //Only used by Bios 248 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 249 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 250 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 251 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 252 USHORT GPIOPinControl; //Atomic Table, only used by Bios 253 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 254 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 255 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 256 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 257 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 258 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 259 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 260 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 261 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 262 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 263 USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios 264 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 265 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 266 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 267 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 268 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 269 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 270 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 271 USHORT GetConditionalGoldenSetting; //Only used by Bios 272 USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 273 USHORT PatchMCSetting; //only used by BIOS 274 USHORT MC_SEQ_Control; //only used by BIOS 275 USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 276 USHORT EnableScaler; //Atomic Table, used only by Bios 277 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 278 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 279 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 280 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 281 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 282 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 283 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 284 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 285 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 286 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 287 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 288 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 289 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 290 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 291 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 292 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 293 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 294 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 295 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 296 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 297 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 298 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 299 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 300 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 301 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 302 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 303 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 304 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 305 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 306 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 307 USHORT MemoryTraining; //Atomic Table, used only by Bios 308 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 309 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 310 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 311 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 312 USHORT DAC2OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 313 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 314 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 315 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 316 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 317 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 318 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 319 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 320 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 321 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 322 USHORT DPEncoderService; //Function Table,only used by Bios 323 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 324 }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 325 326 // For backward compatible 327 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 328 #define DPTranslatorControl DIG2EncoderControl 329 #define UNIPHYTransmitterControl DIG1TransmitterControl 330 #define LVTMATransmitterControl DIG2TransmitterControl 331 #define SetCRTC_DPM_State GetConditionalGoldenSetting 332 #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange 333 #define HPDInterruptService ReadHWAssistedI2CStatus 334 #define EnableVGA_Access GetSCLKOverMCLKRatio 335 #define EnableYUV GetDispObjectInfo 336 #define DynamicClockGating EnableDispPowerGating 337 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam 338 339 #define TMDSAEncoderControl PatchMCSetting 340 #define LVDSEncoderControl MC_SEQ_Control 341 #define LCD1OutputControl HW_Misc_Operation 342 343 344 typedef struct _ATOM_MASTER_COMMAND_TABLE 345 { 346 ATOM_COMMON_TABLE_HEADER sHeader; 347 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 348 }ATOM_MASTER_COMMAND_TABLE; 349 350 /****************************************************************************/ 351 // Structures used in every command table 352 /****************************************************************************/ 353 typedef struct _ATOM_TABLE_ATTRIBUTE 354 { 355 #if ATOM_BIG_ENDIAN 356 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 357 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 358 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 359 #else 360 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 361 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 362 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 363 #endif 364 }ATOM_TABLE_ATTRIBUTE; 365 366 typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS 367 { 368 ATOM_TABLE_ATTRIBUTE sbfAccess; 369 USHORT susAccess; 370 }ATOM_TABLE_ATTRIBUTE_ACCESS; 371 372 /****************************************************************************/ 373 // Common header for all command tables. 374 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 375 // And the pointer actually points to this header. 376 /****************************************************************************/ 377 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 378 { 379 ATOM_COMMON_TABLE_HEADER CommonHeader; 380 ATOM_TABLE_ATTRIBUTE TableAttribute; 381 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 382 383 /****************************************************************************/ 384 // Structures used by ComputeMemoryEnginePLLTable 385 /****************************************************************************/ 386 #define COMPUTE_MEMORY_PLL_PARAM 1 387 #define COMPUTE_ENGINE_PLL_PARAM 2 388 #define ADJUST_MC_SETTING_PARAM 3 389 390 /****************************************************************************/ 391 // Structures used by AdjustMemoryControllerTable 392 /****************************************************************************/ 393 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 394 { 395 #if ATOM_BIG_ENDIAN 396 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 397 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 398 ULONG ulClockFreq:24; 399 #else 400 ULONG ulClockFreq:24; 401 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 402 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 403 #endif 404 }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 405 #define POINTER_RETURN_FLAG 0x80 406 407 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 408 { 409 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 410 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 411 UCHAR ucReserved; //may expand to return larger Fbdiv later 412 UCHAR ucFbDiv; //return value 413 UCHAR ucPostDiv; //return value 414 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 415 416 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 417 { 418 ULONG ulClock; //When return, [23:0] return real clock 419 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 420 USHORT usFbDiv; //return Feedback value to be written to register 421 UCHAR ucPostDiv; //return post div to be written to register 422 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 423 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 424 425 426 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 427 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 428 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 429 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 430 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 431 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 432 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 433 434 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 435 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 436 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 437 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 438 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 439 440 typedef struct _ATOM_COMPUTE_CLOCK_FREQ 441 { 442 #if ATOM_BIG_ENDIAN 443 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 444 ULONG ulClockFreq:24; // in unit of 10kHz 445 #else 446 ULONG ulClockFreq:24; // in unit of 10kHz 447 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 448 #endif 449 }ATOM_COMPUTE_CLOCK_FREQ; 450 451 typedef struct _ATOM_S_MPLL_FB_DIVIDER 452 { 453 USHORT usFbDivFrac; 454 USHORT usFbDiv; 455 }ATOM_S_MPLL_FB_DIVIDER; 456 457 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 458 { 459 union 460 { 461 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 462 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 463 }; 464 UCHAR ucRefDiv; //Output Parameter 465 UCHAR ucPostDiv; //Output Parameter 466 UCHAR ucCntlFlag; //Output Parameter 467 UCHAR ucReserved; 468 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 469 470 // ucCntlFlag 471 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 472 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 473 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 474 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 475 476 477 // V4 are only used for APU which PLL outside GPU 478 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 479 { 480 #if ATOM_BIG_ENDIAN 481 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 482 ULONG ulClock:24; //Input= target clock, output = actual clock 483 #else 484 ULONG ulClock:24; //Input= target clock, output = actual clock 485 ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly 486 #endif 487 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 488 489 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 490 { 491 union 492 { 493 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 494 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 495 }; 496 UCHAR ucRefDiv; //Output Parameter 497 UCHAR ucPostDiv; //Output Parameter 498 union 499 { 500 UCHAR ucCntlFlag; //Output Flags 501 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 502 }; 503 UCHAR ucReserved; 504 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 505 506 // ucInputFlag 507 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 508 509 // use for ComputeMemoryClockParamTable 510 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 511 { 512 union 513 { 514 ULONG ulClock; 515 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 516 }; 517 UCHAR ucDllSpeed; //Output 518 UCHAR ucPostDiv; //Output 519 union{ 520 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 521 UCHAR ucPllCntlFlag; //Output: 522 }; 523 UCHAR ucBWCntl; 524 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 525 526 // definition of ucInputFlag 527 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 528 // definition of ucPllCntlFlag 529 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 530 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 531 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 532 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 533 534 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 535 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 536 537 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 538 { 539 ATOM_COMPUTE_CLOCK_FREQ ulClock; 540 ULONG ulReserved[2]; 541 }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 542 543 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 544 { 545 ATOM_COMPUTE_CLOCK_FREQ ulClock; 546 ULONG ulMemoryClock; 547 ULONG ulReserved; 548 }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 549 550 /****************************************************************************/ 551 // Structures used by SetEngineClockTable 552 /****************************************************************************/ 553 typedef struct _SET_ENGINE_CLOCK_PARAMETERS 554 { 555 ULONG ulTargetEngineClock; //In 10Khz unit 556 }SET_ENGINE_CLOCK_PARAMETERS; 557 558 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 559 { 560 ULONG ulTargetEngineClock; //In 10Khz unit 561 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 562 }SET_ENGINE_CLOCK_PS_ALLOCATION; 563 564 /****************************************************************************/ 565 // Structures used by SetMemoryClockTable 566 /****************************************************************************/ 567 typedef struct _SET_MEMORY_CLOCK_PARAMETERS 568 { 569 ULONG ulTargetMemoryClock; //In 10Khz unit 570 }SET_MEMORY_CLOCK_PARAMETERS; 571 572 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 573 { 574 ULONG ulTargetMemoryClock; //In 10Khz unit 575 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 576 }SET_MEMORY_CLOCK_PS_ALLOCATION; 577 578 /****************************************************************************/ 579 // Structures used by ASIC_Init.ctb 580 /****************************************************************************/ 581 typedef struct _ASIC_INIT_PARAMETERS 582 { 583 ULONG ulDefaultEngineClock; //In 10Khz unit 584 ULONG ulDefaultMemoryClock; //In 10Khz unit 585 }ASIC_INIT_PARAMETERS; 586 587 typedef struct _ASIC_INIT_PS_ALLOCATION 588 { 589 ASIC_INIT_PARAMETERS sASICInitClocks; 590 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 591 }ASIC_INIT_PS_ALLOCATION; 592 593 /****************************************************************************/ 594 // Structure used by DynamicClockGatingTable.ctb 595 /****************************************************************************/ 596 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 597 { 598 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 599 UCHAR ucPadding[3]; 600 }DYNAMIC_CLOCK_GATING_PARAMETERS; 601 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 602 603 /****************************************************************************/ 604 // Structure used by EnableDispPowerGatingTable.ctb 605 /****************************************************************************/ 606 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 607 { 608 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 609 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 610 UCHAR ucPadding[2]; 611 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 612 613 /****************************************************************************/ 614 // Structure used by EnableASIC_StaticPwrMgtTable.ctb 615 /****************************************************************************/ 616 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 617 { 618 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 619 UCHAR ucPadding[3]; 620 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 621 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 622 623 /****************************************************************************/ 624 // Structures used by DAC_LoadDetectionTable.ctb 625 /****************************************************************************/ 626 typedef struct _DAC_LOAD_DETECTION_PARAMETERS 627 { 628 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 629 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 630 UCHAR ucMisc; //Valid only when table revision =1.3 and above 631 }DAC_LOAD_DETECTION_PARAMETERS; 632 633 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 634 #define DAC_LOAD_MISC_YPrPb 0x01 635 636 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 637 { 638 DAC_LOAD_DETECTION_PARAMETERS sDacload; 639 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 640 }DAC_LOAD_DETECTION_PS_ALLOCATION; 641 642 /****************************************************************************/ 643 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 644 /****************************************************************************/ 645 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 646 { 647 USHORT usPixelClock; // in 10KHz; for bios convenient 648 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 649 UCHAR ucAction; // 0: turn off encoder 650 // 1: setup and turn on encoder 651 // 7: ATOM_ENCODER_INIT Initialize DAC 652 }DAC_ENCODER_CONTROL_PARAMETERS; 653 654 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 655 656 /****************************************************************************/ 657 // Structures used by DIG1EncoderControlTable 658 // DIG2EncoderControlTable 659 // ExternalEncoderControlTable 660 /****************************************************************************/ 661 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 662 { 663 USHORT usPixelClock; // in 10KHz; for bios convenient 664 UCHAR ucConfig; 665 // [2] Link Select: 666 // =0: PHY linkA if bfLane<3 667 // =1: PHY linkB if bfLanes<3 668 // =0: PHY linkA+B if bfLanes=3 669 // [3] Transmitter Sel 670 // =0: UNIPHY or PCIEPHY 671 // =1: LVTMA 672 UCHAR ucAction; // =0: turn off encoder 673 // =1: turn on encoder 674 UCHAR ucEncoderMode; 675 // =0: DP encoder 676 // =1: LVDS encoder 677 // =2: DVI encoder 678 // =3: HDMI encoder 679 // =4: SDVO encoder 680 UCHAR ucLaneNum; // how many lanes to enable 681 UCHAR ucReserved[2]; 682 }DIG_ENCODER_CONTROL_PARAMETERS; 683 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 684 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 685 686 //ucConfig 687 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 688 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 689 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 690 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 691 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 692 #define ATOM_ENCODER_CONFIG_LINKA 0x00 693 #define ATOM_ENCODER_CONFIG_LINKB 0x04 694 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 695 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 696 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 697 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 698 #define ATOM_ENCODER_CONFIG_LVTMA 0x08 699 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 700 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 701 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 702 // ucAction 703 // ATOM_ENABLE: Enable Encoder 704 // ATOM_DISABLE: Disable Encoder 705 706 //ucEncoderMode 707 #define ATOM_ENCODER_MODE_DP 0 708 #define ATOM_ENCODER_MODE_LVDS 1 709 #define ATOM_ENCODER_MODE_DVI 2 710 #define ATOM_ENCODER_MODE_HDMI 3 711 #define ATOM_ENCODER_MODE_SDVO 4 712 #define ATOM_ENCODER_MODE_DP_AUDIO 5 713 #define ATOM_ENCODER_MODE_TV 13 714 #define ATOM_ENCODER_MODE_CV 14 715 #define ATOM_ENCODER_MODE_CRT 15 716 #define ATOM_ENCODER_MODE_DVO 16 717 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 718 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 719 720 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 721 { 722 #if ATOM_BIG_ENDIAN 723 UCHAR ucReserved1:2; 724 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 725 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 726 UCHAR ucReserved:1; 727 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 728 #else 729 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 730 UCHAR ucReserved:1; 731 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 732 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 733 UCHAR ucReserved1:2; 734 #endif 735 }ATOM_DIG_ENCODER_CONFIG_V2; 736 737 738 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 739 { 740 USHORT usPixelClock; // in 10KHz; for bios convenient 741 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 742 UCHAR ucAction; 743 UCHAR ucEncoderMode; 744 // =0: DP encoder 745 // =1: LVDS encoder 746 // =2: DVI encoder 747 // =3: HDMI encoder 748 // =4: SDVO encoder 749 UCHAR ucLaneNum; // how many lanes to enable 750 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 751 UCHAR ucReserved; 752 }DIG_ENCODER_CONTROL_PARAMETERS_V2; 753 754 //ucConfig 755 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 756 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 757 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 758 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 759 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 760 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 761 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 762 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 763 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 764 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 765 766 // ucAction: 767 // ATOM_DISABLE 768 // ATOM_ENABLE 769 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 770 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 771 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 772 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 773 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 774 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 775 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 776 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 777 #define ATOM_ENCODER_CMD_SETUP 0x0f 778 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 779 780 // ucStatus 781 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 782 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 783 784 //ucTableFormatRevision=1 785 //ucTableContentRevision=3 786 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 787 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 788 { 789 #if ATOM_BIG_ENDIAN 790 UCHAR ucReserved1:1; 791 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 792 UCHAR ucReserved:3; 793 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 794 #else 795 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 796 UCHAR ucReserved:3; 797 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 798 UCHAR ucReserved1:1; 799 #endif 800 }ATOM_DIG_ENCODER_CONFIG_V3; 801 802 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 803 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 804 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 805 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 806 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 807 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 808 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 809 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 810 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 811 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 812 813 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 814 { 815 USHORT usPixelClock; // in 10KHz; for bios convenient 816 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 817 UCHAR ucAction; 818 union { 819 UCHAR ucEncoderMode; 820 // =0: DP encoder 821 // =1: LVDS encoder 822 // =2: DVI encoder 823 // =3: HDMI encoder 824 // =4: SDVO encoder 825 // =5: DP audio 826 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 827 // =0: external DP 828 // =1: internal DP2 829 // =0x11: internal DP1 for NutMeg/Travis DP translator 830 }; 831 UCHAR ucLaneNum; // how many lanes to enable 832 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 833 UCHAR ucReserved; 834 }DIG_ENCODER_CONTROL_PARAMETERS_V3; 835 836 //ucTableFormatRevision=1 837 //ucTableContentRevision=4 838 // start from NI 839 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 840 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 841 { 842 #if ATOM_BIG_ENDIAN 843 UCHAR ucReserved1:1; 844 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 845 UCHAR ucReserved:2; 846 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 847 #else 848 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 849 UCHAR ucReserved:2; 850 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 851 UCHAR ucReserved1:1; 852 #endif 853 }ATOM_DIG_ENCODER_CONFIG_V4; 854 855 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 856 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 857 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 858 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 859 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 860 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 861 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 862 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 863 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 864 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 865 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 866 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 867 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 868 869 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 870 { 871 USHORT usPixelClock; // in 10KHz; for bios convenient 872 union{ 873 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 874 UCHAR ucConfig; 875 }; 876 UCHAR ucAction; 877 union { 878 UCHAR ucEncoderMode; 879 // =0: DP encoder 880 // =1: LVDS encoder 881 // =2: DVI encoder 882 // =3: HDMI encoder 883 // =4: SDVO encoder 884 // =5: DP audio 885 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 886 // =0: external DP 887 // =1: internal DP2 888 // =0x11: internal DP1 for NutMeg/Travis DP translator 889 }; 890 UCHAR ucLaneNum; // how many lanes to enable 891 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 892 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 893 }DIG_ENCODER_CONTROL_PARAMETERS_V4; 894 895 // define ucBitPerColor: 896 #define PANEL_BPC_UNDEFINE 0x00 897 #define PANEL_6BIT_PER_COLOR 0x01 898 #define PANEL_8BIT_PER_COLOR 0x02 899 #define PANEL_10BIT_PER_COLOR 0x03 900 #define PANEL_12BIT_PER_COLOR 0x04 901 #define PANEL_16BIT_PER_COLOR 0x05 902 903 //define ucPanelMode 904 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 905 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 906 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 907 908 /****************************************************************************/ 909 // Structures used by UNIPHYTransmitterControlTable 910 // LVTMATransmitterControlTable 911 // DVOOutputControlTable 912 /****************************************************************************/ 913 typedef struct _ATOM_DP_VS_MODE 914 { 915 UCHAR ucLaneSel; 916 UCHAR ucLaneSet; 917 }ATOM_DP_VS_MODE; 918 919 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 920 { 921 union 922 { 923 USHORT usPixelClock; // in 10KHz; for bios convenient 924 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 925 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 926 }; 927 UCHAR ucConfig; 928 // [0]=0: 4 lane Link, 929 // =1: 8 lane Link ( Dual Links TMDS ) 930 // [1]=0: InCoherent mode 931 // =1: Coherent Mode 932 // [2] Link Select: 933 // =0: PHY linkA if bfLane<3 934 // =1: PHY linkB if bfLanes<3 935 // =0: PHY linkA+B if bfLanes=3 936 // [5:4]PCIE lane Sel 937 // =0: lane 0~3 or 0~7 938 // =1: lane 4~7 939 // =2: lane 8~11 or 8~15 940 // =3: lane 12~15 941 UCHAR ucAction; // =0: turn off encoder 942 // =1: turn on encoder 943 UCHAR ucReserved[4]; 944 }DIG_TRANSMITTER_CONTROL_PARAMETERS; 945 946 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 947 948 //ucInitInfo 949 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 950 951 //ucConfig 952 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 953 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 954 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 955 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 956 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 957 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 958 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 959 960 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 961 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 962 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 963 964 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 965 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 966 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 967 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 968 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 969 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 970 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 971 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 972 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 973 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 974 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 975 976 //ucAction 977 #define ATOM_TRANSMITTER_ACTION_DISABLE 0 978 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 979 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 980 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 981 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 982 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 983 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 984 #define ATOM_TRANSMITTER_ACTION_INIT 7 985 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 986 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 987 #define ATOM_TRANSMITTER_ACTION_SETUP 10 988 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 989 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 990 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 991 992 // Following are used for DigTransmitterControlTable ver1.2 993 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 994 { 995 #if ATOM_BIG_ENDIAN 996 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 997 // =1 Dig Transmitter 2 ( Uniphy CD ) 998 // =2 Dig Transmitter 3 ( Uniphy EF ) 999 UCHAR ucReserved:1; 1000 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1001 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1002 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1003 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1004 1005 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1006 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1007 #else 1008 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1009 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1010 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1011 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1012 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1013 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1014 UCHAR ucReserved:1; 1015 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1016 // =1 Dig Transmitter 2 ( Uniphy CD ) 1017 // =2 Dig Transmitter 3 ( Uniphy EF ) 1018 #endif 1019 }ATOM_DIG_TRANSMITTER_CONFIG_V2; 1020 1021 //ucConfig 1022 //Bit0 1023 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1024 1025 //Bit1 1026 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1027 1028 //Bit2 1029 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1030 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1031 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1032 1033 // Bit3 1034 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1035 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1036 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1037 1038 // Bit4 1039 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1040 1041 // Bit7:6 1042 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1043 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1044 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1045 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1046 1047 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1048 { 1049 union 1050 { 1051 USHORT usPixelClock; // in 10KHz; for bios convenient 1052 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1053 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1054 }; 1055 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1056 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1057 UCHAR ucReserved[4]; 1058 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1059 1060 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1061 { 1062 #if ATOM_BIG_ENDIAN 1063 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1064 // =1 Dig Transmitter 2 ( Uniphy CD ) 1065 // =2 Dig Transmitter 3 ( Uniphy EF ) 1066 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1067 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1068 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1069 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1070 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1071 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1072 #else 1073 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1074 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1075 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1076 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1077 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1078 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1079 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1080 // =1 Dig Transmitter 2 ( Uniphy CD ) 1081 // =2 Dig Transmitter 3 ( Uniphy EF ) 1082 #endif 1083 }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1084 1085 1086 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1087 { 1088 union 1089 { 1090 USHORT usPixelClock; // in 10KHz; for bios convenient 1091 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1092 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1093 }; 1094 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1095 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1096 UCHAR ucLaneNum; 1097 UCHAR ucReserved[3]; 1098 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1099 1100 //ucConfig 1101 //Bit0 1102 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1103 1104 //Bit1 1105 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1106 1107 //Bit2 1108 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1109 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1110 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1111 1112 // Bit3 1113 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1114 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1115 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1116 1117 // Bit5:4 1118 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1119 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1120 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1121 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1122 1123 // Bit7:6 1124 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1125 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1126 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1127 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1128 1129 1130 /****************************************************************************/ 1131 // Structures used by UNIPHYTransmitterControlTable V1.4 1132 // ASIC Families: NI 1133 // ucTableFormatRevision=1 1134 // ucTableContentRevision=4 1135 /****************************************************************************/ 1136 typedef struct _ATOM_DP_VS_MODE_V4 1137 { 1138 UCHAR ucLaneSel; 1139 union 1140 { 1141 UCHAR ucLaneSet; 1142 struct { 1143 #if ATOM_BIG_ENDIAN 1144 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1145 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1146 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1147 #else 1148 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1149 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1150 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1151 #endif 1152 }; 1153 }; 1154 }ATOM_DP_VS_MODE_V4; 1155 1156 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1157 { 1158 #if ATOM_BIG_ENDIAN 1159 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1160 // =1 Dig Transmitter 2 ( Uniphy CD ) 1161 // =2 Dig Transmitter 3 ( Uniphy EF ) 1162 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1163 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1164 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1165 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1166 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1167 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1168 #else 1169 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1170 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1171 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1172 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1173 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1174 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1175 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1176 // =1 Dig Transmitter 2 ( Uniphy CD ) 1177 // =2 Dig Transmitter 3 ( Uniphy EF ) 1178 #endif 1179 }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1180 1181 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1182 { 1183 union 1184 { 1185 USHORT usPixelClock; // in 10KHz; for bios convenient 1186 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1187 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1188 }; 1189 union 1190 { 1191 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1192 UCHAR ucConfig; 1193 }; 1194 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1195 UCHAR ucLaneNum; 1196 UCHAR ucReserved[3]; 1197 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1198 1199 //ucConfig 1200 //Bit0 1201 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1202 //Bit1 1203 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1204 //Bit2 1205 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1206 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1207 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1208 // Bit3 1209 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1210 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1211 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1212 // Bit5:4 1213 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1214 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1215 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1216 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1217 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1218 // Bit7:6 1219 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1220 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1221 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1222 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1223 1224 1225 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1226 { 1227 #if ATOM_BIG_ENDIAN 1228 UCHAR ucReservd1:1; 1229 UCHAR ucHPDSel:3; 1230 UCHAR ucPhyClkSrcId:2; 1231 UCHAR ucCoherentMode:1; 1232 UCHAR ucReserved:1; 1233 #else 1234 UCHAR ucReserved:1; 1235 UCHAR ucCoherentMode:1; 1236 UCHAR ucPhyClkSrcId:2; 1237 UCHAR ucHPDSel:3; 1238 UCHAR ucReservd1:1; 1239 #endif 1240 }ATOM_DIG_TRANSMITTER_CONFIG_V5; 1241 1242 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1243 { 1244 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1245 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1246 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1247 UCHAR ucLaneNum; // indicate lane number 1-8 1248 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1249 UCHAR ucDigMode; // indicate DIG mode 1250 union{ 1251 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1252 UCHAR ucConfig; 1253 }; 1254 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1255 UCHAR ucDPLaneSet; 1256 UCHAR ucReserved; 1257 UCHAR ucReserved1; 1258 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1259 1260 //ucPhyId 1261 #define ATOM_PHY_ID_UNIPHYA 0 1262 #define ATOM_PHY_ID_UNIPHYB 1 1263 #define ATOM_PHY_ID_UNIPHYC 2 1264 #define ATOM_PHY_ID_UNIPHYD 3 1265 #define ATOM_PHY_ID_UNIPHYE 4 1266 #define ATOM_PHY_ID_UNIPHYF 5 1267 #define ATOM_PHY_ID_UNIPHYG 6 1268 1269 // ucDigEncoderSel 1270 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1271 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1272 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1273 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1274 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1275 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1276 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1277 1278 // ucDigMode 1279 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1280 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1281 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1282 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1283 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1284 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1285 1286 // ucDPLaneSet 1287 #define DP_LANE_SET__0DB_0_4V 0x00 1288 #define DP_LANE_SET__0DB_0_6V 0x01 1289 #define DP_LANE_SET__0DB_0_8V 0x02 1290 #define DP_LANE_SET__0DB_1_2V 0x03 1291 #define DP_LANE_SET__3_5DB_0_4V 0x08 1292 #define DP_LANE_SET__3_5DB_0_6V 0x09 1293 #define DP_LANE_SET__3_5DB_0_8V 0x0a 1294 #define DP_LANE_SET__6DB_0_4V 0x10 1295 #define DP_LANE_SET__6DB_0_6V 0x11 1296 #define DP_LANE_SET__9_5DB_0_4V 0x18 1297 1298 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1299 // Bit1 1300 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1301 1302 // Bit3:2 1303 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1304 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1305 1306 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1307 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1308 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1309 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1310 // Bit6:4 1311 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1312 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1313 1314 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1315 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1316 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1317 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1318 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1319 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1320 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1321 1322 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1323 1324 1325 /****************************************************************************/ 1326 // Structures used by ExternalEncoderControlTable V1.3 1327 // ASIC Families: Evergreen, Llano, NI 1328 // ucTableFormatRevision=1 1329 // ucTableContentRevision=3 1330 /****************************************************************************/ 1331 1332 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1333 { 1334 union{ 1335 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1336 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1337 }; 1338 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1339 UCHAR ucAction; // 1340 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1341 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1342 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1343 UCHAR ucReserved; 1344 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1345 1346 // ucAction 1347 #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1348 #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1349 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1350 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1351 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1352 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1353 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1354 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1355 1356 // ucConfig 1357 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1358 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1359 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1360 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1361 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 1362 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1363 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1364 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1365 1366 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1367 { 1368 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1369 ULONG ulReserved[2]; 1370 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1371 1372 1373 /****************************************************************************/ 1374 // Structures used by DAC1OuputControlTable 1375 // DAC2OuputControlTable 1376 // LVTMAOutputControlTable (Before DEC30) 1377 // TMDSAOutputControlTable (Before DEC30) 1378 /****************************************************************************/ 1379 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1380 { 1381 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1382 // When the display is LCD, in addition to above: 1383 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1384 // ATOM_LCD_SELFTEST_STOP 1385 1386 UCHAR aucPadding[3]; // padding to DWORD aligned 1387 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1388 1389 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1390 1391 1392 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1393 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1394 1395 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1396 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1397 1398 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1399 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1400 1401 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1402 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1403 1404 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1405 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1406 1407 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1408 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1409 1410 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1411 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1412 1413 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1414 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1415 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1416 1417 /****************************************************************************/ 1418 // Structures used by BlankCRTCTable 1419 /****************************************************************************/ 1420 typedef struct _BLANK_CRTC_PARAMETERS 1421 { 1422 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1423 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1424 USHORT usBlackColorRCr; 1425 USHORT usBlackColorGY; 1426 USHORT usBlackColorBCb; 1427 }BLANK_CRTC_PARAMETERS; 1428 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1429 1430 /****************************************************************************/ 1431 // Structures used by EnableCRTCTable 1432 // EnableCRTCMemReqTable 1433 // UpdateCRTC_DoubleBufferRegistersTable 1434 /****************************************************************************/ 1435 typedef struct _ENABLE_CRTC_PARAMETERS 1436 { 1437 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1438 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1439 UCHAR ucPadding[2]; 1440 }ENABLE_CRTC_PARAMETERS; 1441 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1442 1443 /****************************************************************************/ 1444 // Structures used by SetCRTC_OverScanTable 1445 /****************************************************************************/ 1446 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1447 { 1448 USHORT usOverscanRight; // right 1449 USHORT usOverscanLeft; // left 1450 USHORT usOverscanBottom; // bottom 1451 USHORT usOverscanTop; // top 1452 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1453 UCHAR ucPadding[3]; 1454 }SET_CRTC_OVERSCAN_PARAMETERS; 1455 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1456 1457 /****************************************************************************/ 1458 // Structures used by SetCRTC_ReplicationTable 1459 /****************************************************************************/ 1460 typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1461 { 1462 UCHAR ucH_Replication; // horizontal replication 1463 UCHAR ucV_Replication; // vertical replication 1464 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1465 UCHAR ucPadding; 1466 }SET_CRTC_REPLICATION_PARAMETERS; 1467 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1468 1469 /****************************************************************************/ 1470 // Structures used by SelectCRTC_SourceTable 1471 /****************************************************************************/ 1472 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1473 { 1474 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1475 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1476 UCHAR ucPadding[2]; 1477 }SELECT_CRTC_SOURCE_PARAMETERS; 1478 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1479 1480 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1481 { 1482 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1483 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1484 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1485 UCHAR ucPadding; 1486 }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1487 1488 //ucEncoderID 1489 //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1490 //#define ASIC_INT_TV_ENCODER_ID 0x02 1491 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1492 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1493 //#define ASIC_EXT_TV_ENCODER_ID 0x06 1494 //#define ASIC_INT_DVO_ENCODER_ID 0x07 1495 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1496 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1497 1498 //ucEncodeMode 1499 //#define ATOM_ENCODER_MODE_DP 0 1500 //#define ATOM_ENCODER_MODE_LVDS 1 1501 //#define ATOM_ENCODER_MODE_DVI 2 1502 //#define ATOM_ENCODER_MODE_HDMI 3 1503 //#define ATOM_ENCODER_MODE_SDVO 4 1504 //#define ATOM_ENCODER_MODE_TV 13 1505 //#define ATOM_ENCODER_MODE_CV 14 1506 //#define ATOM_ENCODER_MODE_CRT 15 1507 1508 /****************************************************************************/ 1509 // Structures used by SetPixelClockTable 1510 // GetPixelClockTable 1511 /****************************************************************************/ 1512 //Major revision=1., Minor revision=1 1513 typedef struct _PIXEL_CLOCK_PARAMETERS 1514 { 1515 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1516 // 0 means disable PPLL 1517 USHORT usRefDiv; // Reference divider 1518 USHORT usFbDiv; // feedback divider 1519 UCHAR ucPostDiv; // post divider 1520 UCHAR ucFracFbDiv; // fractional feedback divider 1521 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1522 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1523 UCHAR ucCRTC; // Which CRTC uses this Ppll 1524 UCHAR ucPadding; 1525 }PIXEL_CLOCK_PARAMETERS; 1526 1527 //Major revision=1., Minor revision=2, add ucMiscIfno 1528 //ucMiscInfo: 1529 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1530 #define MISC_DEVICE_INDEX_MASK 0xF0 1531 #define MISC_DEVICE_INDEX_SHIFT 4 1532 1533 typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1534 { 1535 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1536 // 0 means disable PPLL 1537 USHORT usRefDiv; // Reference divider 1538 USHORT usFbDiv; // feedback divider 1539 UCHAR ucPostDiv; // post divider 1540 UCHAR ucFracFbDiv; // fractional feedback divider 1541 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1542 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1543 UCHAR ucCRTC; // Which CRTC uses this Ppll 1544 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1545 }PIXEL_CLOCK_PARAMETERS_V2; 1546 1547 //Major revision=1., Minor revision=3, structure/definition change 1548 //ucEncoderMode: 1549 //ATOM_ENCODER_MODE_DP 1550 //ATOM_ENOCDER_MODE_LVDS 1551 //ATOM_ENOCDER_MODE_DVI 1552 //ATOM_ENOCDER_MODE_HDMI 1553 //ATOM_ENOCDER_MODE_SDVO 1554 //ATOM_ENCODER_MODE_TV 13 1555 //ATOM_ENCODER_MODE_CV 14 1556 //ATOM_ENCODER_MODE_CRT 15 1557 1558 //ucDVOConfig 1559 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1560 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1561 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1562 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1563 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1564 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1565 //#define DVO_ENCODER_CONFIG_24BIT 0x08 1566 1567 //ucMiscInfo: also changed, see below 1568 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1569 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1570 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1571 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1572 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1573 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1574 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1575 // V1.4 for RoadRunner 1576 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1577 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1578 1579 1580 typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1581 { 1582 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1583 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1584 USHORT usRefDiv; // Reference divider 1585 USHORT usFbDiv; // feedback divider 1586 UCHAR ucPostDiv; // post divider 1587 UCHAR ucFracFbDiv; // fractional feedback divider 1588 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1589 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1590 union 1591 { 1592 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1593 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1594 }; 1595 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1596 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1597 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1598 }PIXEL_CLOCK_PARAMETERS_V3; 1599 1600 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1601 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1602 1603 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1604 { 1605 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1606 // drive the pixel clock. not used for DCPLL case. 1607 union{ 1608 UCHAR ucReserved; 1609 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1610 }; 1611 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1612 // 0 means disable PPLL/DCPLL. 1613 USHORT usFbDiv; // feedback divider integer part. 1614 UCHAR ucPostDiv; // post divider. 1615 UCHAR ucRefDiv; // Reference divider 1616 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1617 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1618 // indicate which graphic encoder will be used. 1619 UCHAR ucEncoderMode; // Encoder mode: 1620 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1621 // bit[1]= when VGA timing is used. 1622 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1623 // bit[4]= RefClock source for PPLL. 1624 // =0: XTLAIN( default mode ) 1625 // =1: other external clock source, which is pre-defined 1626 // by VBIOS depend on the feature required. 1627 // bit[7:5]: reserved. 1628 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1629 1630 }PIXEL_CLOCK_PARAMETERS_V5; 1631 1632 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1633 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1634 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1635 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1636 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1637 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1638 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1639 1640 typedef struct _CRTC_PIXEL_CLOCK_FREQ 1641 { 1642 #if ATOM_BIG_ENDIAN 1643 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1644 // drive the pixel clock. not used for DCPLL case. 1645 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1646 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1647 #else 1648 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1649 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1650 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1651 // drive the pixel clock. not used for DCPLL case. 1652 #endif 1653 }CRTC_PIXEL_CLOCK_FREQ; 1654 1655 typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1656 { 1657 union{ 1658 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1659 ULONG ulDispEngClkFreq; // dispclk frequency 1660 }; 1661 USHORT usFbDiv; // feedback divider integer part. 1662 UCHAR ucPostDiv; // post divider. 1663 UCHAR ucRefDiv; // Reference divider 1664 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1665 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1666 // indicate which graphic encoder will be used. 1667 UCHAR ucEncoderMode; // Encoder mode: 1668 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1669 // bit[1]= when VGA timing is used. 1670 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1671 // bit[4]= RefClock source for PPLL. 1672 // =0: XTLAIN( default mode ) 1673 // =1: other external clock source, which is pre-defined 1674 // by VBIOS depend on the feature required. 1675 // bit[7:5]: reserved. 1676 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1677 1678 }PIXEL_CLOCK_PARAMETERS_V6; 1679 1680 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1681 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1682 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1683 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1684 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1685 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1686 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1687 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1688 1689 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1690 { 1691 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1692 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1693 1694 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1695 { 1696 UCHAR ucStatus; 1697 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1698 UCHAR ucReserved[2]; 1699 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1700 1701 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1702 { 1703 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1704 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1705 1706 /****************************************************************************/ 1707 // Structures used by AdjustDisplayPllTable 1708 /****************************************************************************/ 1709 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1710 { 1711 USHORT usPixelClock; 1712 UCHAR ucTransmitterID; 1713 UCHAR ucEncodeMode; 1714 union 1715 { 1716 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1717 UCHAR ucConfig; //if none DVO, not defined yet 1718 }; 1719 UCHAR ucReserved[3]; 1720 }ADJUST_DISPLAY_PLL_PARAMETERS; 1721 1722 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1723 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1724 1725 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1726 { 1727 USHORT usPixelClock; // target pixel clock 1728 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1729 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1730 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1731 UCHAR ucExtTransmitterID; // external encoder id. 1732 UCHAR ucReserved[2]; 1733 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1734 1735 // usDispPllConfig v1.2 for RoadRunner 1736 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1737 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1738 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1739 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1740 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1741 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1742 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1743 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1744 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1745 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1746 1747 1748 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1749 { 1750 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1751 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1752 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1753 UCHAR ucReserved[2]; 1754 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1755 1756 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1757 { 1758 union 1759 { 1760 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1761 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1762 }; 1763 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1764 1765 /****************************************************************************/ 1766 // Structures used by EnableYUVTable 1767 /****************************************************************************/ 1768 typedef struct _ENABLE_YUV_PARAMETERS 1769 { 1770 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1771 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1772 UCHAR ucPadding[2]; 1773 }ENABLE_YUV_PARAMETERS; 1774 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1775 1776 /****************************************************************************/ 1777 // Structures used by GetMemoryClockTable 1778 /****************************************************************************/ 1779 typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1780 { 1781 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1782 } GET_MEMORY_CLOCK_PARAMETERS; 1783 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1784 1785 /****************************************************************************/ 1786 // Structures used by GetEngineClockTable 1787 /****************************************************************************/ 1788 typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1789 { 1790 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1791 } GET_ENGINE_CLOCK_PARAMETERS; 1792 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1793 1794 /****************************************************************************/ 1795 // Following Structures and constant may be obsolete 1796 /****************************************************************************/ 1797 //Maxium 8 bytes,the data read in will be placed in the parameter space. 1798 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1799 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1800 { 1801 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1802 USHORT usVRAMAddress; //Address in Frame Buffer where to pace raw EDID 1803 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1804 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1805 UCHAR ucSlaveAddr; //Read from which slave 1806 UCHAR ucLineNumber; //Read from which HW assisted line 1807 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1808 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1809 1810 1811 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1812 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1813 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1814 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1815 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1816 1817 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1818 { 1819 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1820 USHORT usByteOffset; //Write to which byte 1821 //Upper portion of usByteOffset is Format of data 1822 //1bytePS+offsetPS 1823 //2bytesPS+offsetPS 1824 //blockID+offsetPS 1825 //blockID+offsetID 1826 //blockID+counterID+offsetID 1827 UCHAR ucData; //PS data1 1828 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1829 UCHAR ucSlaveAddr; //Write to which slave 1830 UCHAR ucLineNumber; //Write from which HW assisted line 1831 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1832 1833 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1834 1835 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1836 { 1837 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1838 UCHAR ucSlaveAddr; //Write to which slave 1839 UCHAR ucLineNumber; //Write from which HW assisted line 1840 }SET_UP_HW_I2C_DATA_PARAMETERS; 1841 1842 1843 /**************************************************************************/ 1844 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1845 1846 1847 /****************************************************************************/ 1848 // Structures used by PowerConnectorDetectionTable 1849 /****************************************************************************/ 1850 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1851 { 1852 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1853 UCHAR ucPwrBehaviorId; 1854 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1855 }POWER_CONNECTOR_DETECTION_PARAMETERS; 1856 1857 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1858 { 1859 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1860 UCHAR ucReserved; 1861 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1862 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1863 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1864 1865 /****************************LVDS SS Command Table Definitions**********************/ 1866 1867 /****************************************************************************/ 1868 // Structures used by EnableSpreadSpectrumOnPPLLTable 1869 /****************************************************************************/ 1870 typedef struct _ENABLE_LVDS_SS_PARAMETERS 1871 { 1872 USHORT usSpreadSpectrumPercentage; 1873 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1874 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1875 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1876 UCHAR ucPadding[3]; 1877 }ENABLE_LVDS_SS_PARAMETERS; 1878 1879 //ucTableFormatRevision=1,ucTableContentRevision=2 1880 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1881 { 1882 USHORT usSpreadSpectrumPercentage; 1883 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1884 UCHAR ucSpreadSpectrumStep; // 1885 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1886 UCHAR ucSpreadSpectrumDelay; 1887 UCHAR ucSpreadSpectrumRange; 1888 UCHAR ucPadding; 1889 }ENABLE_LVDS_SS_PARAMETERS_V2; 1890 1891 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1892 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1893 { 1894 USHORT usSpreadSpectrumPercentage; 1895 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1896 UCHAR ucSpreadSpectrumStep; // 1897 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1898 UCHAR ucSpreadSpectrumDelay; 1899 UCHAR ucSpreadSpectrumRange; 1900 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1901 }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1902 1903 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1904 { 1905 USHORT usSpreadSpectrumPercentage; 1906 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1907 // Bit[1]: 1-Ext. 0-Int. 1908 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1909 // Bits[7:4] reserved 1910 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1911 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1912 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1913 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1914 1915 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1916 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1917 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1918 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1919 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1920 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1921 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1922 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 1923 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 1924 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 1925 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 1926 1927 // Used by DCE5.0 1928 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 1929 { 1930 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 1931 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1932 // Bit[1]: 1-Ext. 0-Int. 1933 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1934 // Bits[7:4] reserved 1935 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1936 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1937 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1938 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 1939 1940 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 1941 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 1942 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 1943 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 1944 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 1945 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 1946 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 1947 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 1948 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 1949 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 1950 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 1951 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 1952 1953 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 1954 1955 /**************************************************************************/ 1956 1957 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 1958 { 1959 PIXEL_CLOCK_PARAMETERS sPCLKInput; 1960 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 1961 }SET_PIXEL_CLOCK_PS_ALLOCATION; 1962 1963 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 1964 1965 /****************************************************************************/ 1966 // Structures used by ### 1967 /****************************************************************************/ 1968 typedef struct _MEMORY_TRAINING_PARAMETERS 1969 { 1970 ULONG ulTargetMemoryClock; //In 10Khz unit 1971 }MEMORY_TRAINING_PARAMETERS; 1972 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 1973 1974 1975 /****************************LVDS and other encoder command table definitions **********************/ 1976 1977 1978 /****************************************************************************/ 1979 // Structures used by LVDSEncoderControlTable (Before DCE30) 1980 // LVTMAEncoderControlTable (Before DCE30) 1981 // TMDSAEncoderControlTable (Before DCE30) 1982 /****************************************************************************/ 1983 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 1984 { 1985 USHORT usPixelClock; // in 10KHz; for bios convenient 1986 UCHAR ucMisc; // bit0=0: Enable single link 1987 // =1: Enable dual link 1988 // Bit1=0: 666RGB 1989 // =1: 888RGB 1990 UCHAR ucAction; // 0: turn off encoder 1991 // 1: setup and turn on encoder 1992 }LVDS_ENCODER_CONTROL_PARAMETERS; 1993 1994 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 1995 1996 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 1997 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 1998 1999 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2000 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2001 2002 2003 //ucTableFormatRevision=1,ucTableContentRevision=2 2004 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2005 { 2006 USHORT usPixelClock; // in 10KHz; for bios convenient 2007 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2008 UCHAR ucAction; // 0: turn off encoder 2009 // 1: setup and turn on encoder 2010 UCHAR ucTruncate; // bit0=0: Disable truncate 2011 // =1: Enable truncate 2012 // bit4=0: 666RGB 2013 // =1: 888RGB 2014 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2015 // =1: Enable spatial dithering 2016 // bit4=0: 666RGB 2017 // =1: 888RGB 2018 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2019 // =1: Enable temporal dithering 2020 // bit4=0: 666RGB 2021 // =1: 888RGB 2022 // bit5=0: Gray level 2 2023 // =1: Gray level 4 2024 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2025 // =1: 25FRC_SEL pattern F 2026 // bit6:5=0: 50FRC_SEL pattern A 2027 // =1: 50FRC_SEL pattern B 2028 // =2: 50FRC_SEL pattern C 2029 // =3: 50FRC_SEL pattern D 2030 // bit7=0: 75FRC_SEL pattern E 2031 // =1: 75FRC_SEL pattern F 2032 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2033 2034 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2035 2036 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2037 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2038 2039 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2040 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2041 2042 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2043 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2044 2045 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2046 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2047 2048 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2049 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2050 2051 /****************************************************************************/ 2052 // Structures used by ### 2053 /****************************************************************************/ 2054 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2055 { 2056 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2057 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2058 UCHAR ucPadding[2]; 2059 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2060 2061 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2062 { 2063 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2064 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2065 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2066 2067 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2068 2069 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2070 { 2071 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2072 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2073 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2074 2075 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2076 { 2077 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2078 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2079 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2080 2081 /****************************************************************************/ 2082 // Structures used by DVOEncoderControlTable 2083 /****************************************************************************/ 2084 //ucTableFormatRevision=1,ucTableContentRevision=3 2085 2086 //ucDVOConfig: 2087 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2088 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2089 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2090 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2091 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2092 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2093 #define DVO_ENCODER_CONFIG_24BIT 0x08 2094 2095 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2096 { 2097 USHORT usPixelClock; 2098 UCHAR ucDVOConfig; 2099 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2100 UCHAR ucReseved[4]; 2101 }DVO_ENCODER_CONTROL_PARAMETERS_V3; 2102 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2103 2104 //ucTableFormatRevision=1 2105 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2106 // bit1=0: non-coherent mode 2107 // =1: coherent mode 2108 2109 //========================================================================================== 2110 //Only change is here next time when changing encoder parameter definitions again! 2111 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2112 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2113 2114 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2115 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2116 2117 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2118 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2119 2120 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2121 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2122 2123 //========================================================================================== 2124 #define PANEL_ENCODER_MISC_DUAL 0x01 2125 #define PANEL_ENCODER_MISC_COHERENT 0x02 2126 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2127 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2128 2129 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2130 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2131 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2132 2133 #define PANEL_ENCODER_TRUNCATE_EN 0x01 2134 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2135 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2136 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2137 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2138 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2139 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2140 #define PANEL_ENCODER_25FRC_MASK 0x10 2141 #define PANEL_ENCODER_25FRC_E 0x00 2142 #define PANEL_ENCODER_25FRC_F 0x10 2143 #define PANEL_ENCODER_50FRC_MASK 0x60 2144 #define PANEL_ENCODER_50FRC_A 0x00 2145 #define PANEL_ENCODER_50FRC_B 0x20 2146 #define PANEL_ENCODER_50FRC_C 0x40 2147 #define PANEL_ENCODER_50FRC_D 0x60 2148 #define PANEL_ENCODER_75FRC_MASK 0x80 2149 #define PANEL_ENCODER_75FRC_E 0x00 2150 #define PANEL_ENCODER_75FRC_F 0x80 2151 2152 /****************************************************************************/ 2153 // Structures used by SetVoltageTable 2154 /****************************************************************************/ 2155 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2156 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2157 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2158 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2159 #define SET_VOLTAGE_INIT_MODE 5 2160 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2161 2162 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2163 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2164 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2165 2166 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2167 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2168 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2169 2170 typedef struct _SET_VOLTAGE_PARAMETERS 2171 { 2172 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2173 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2174 UCHAR ucVoltageIndex; // An index to tell which voltage level 2175 UCHAR ucReserved; 2176 }SET_VOLTAGE_PARAMETERS; 2177 2178 typedef struct _SET_VOLTAGE_PARAMETERS_V2 2179 { 2180 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2181 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2182 USHORT usVoltageLevel; // real voltage level 2183 }SET_VOLTAGE_PARAMETERS_V2; 2184 2185 2186 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2187 { 2188 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2189 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2190 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2191 }SET_VOLTAGE_PARAMETERS_V1_3; 2192 2193 //ucVoltageType 2194 #define VOLTAGE_TYPE_VDDC 1 2195 #define VOLTAGE_TYPE_MVDDC 2 2196 #define VOLTAGE_TYPE_MVDDQ 3 2197 #define VOLTAGE_TYPE_VDDCI 4 2198 2199 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2200 #define ATOM_SET_VOLTAGE 0 //Set voltage Level 2201 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2202 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase 2203 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3 2204 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID 2205 2206 // define vitual voltage id in usVoltageLevel 2207 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2208 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2209 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2210 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2211 2212 typedef struct _SET_VOLTAGE_PS_ALLOCATION 2213 { 2214 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2215 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2216 }SET_VOLTAGE_PS_ALLOCATION; 2217 2218 // New Added from SI for GetVoltageInfoTable, input parameter structure 2219 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2220 { 2221 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2222 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2223 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2224 ULONG ulReserved; 2225 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2226 2227 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2228 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2229 { 2230 ULONG ulVotlageGpioState; 2231 ULONG ulVoltageGPioMask; 2232 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2233 2234 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2235 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2236 { 2237 USHORT usVoltageLevel; 2238 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2239 ULONG ulReseved; 2240 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2241 2242 2243 // GetVoltageInfo v1.1 ucVoltageMode 2244 #define ATOM_GET_VOLTAGE_VID 0x00 2245 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2246 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2247 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2248 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2249 2250 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2251 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2252 // undefined power state 2253 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2254 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2255 2256 /****************************************************************************/ 2257 // Structures used by TVEncoderControlTable 2258 /****************************************************************************/ 2259 typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2260 { 2261 USHORT usPixelClock; // in 10KHz; for bios convenient 2262 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2263 UCHAR ucAction; // 0: turn off encoder 2264 // 1: setup and turn on encoder 2265 }TV_ENCODER_CONTROL_PARAMETERS; 2266 2267 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2268 { 2269 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2270 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2271 }TV_ENCODER_CONTROL_PS_ALLOCATION; 2272 2273 //==============================Data Table Portion==================================== 2274 2275 /****************************************************************************/ 2276 // Structure used in Data.mtb 2277 /****************************************************************************/ 2278 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2279 { 2280 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2281 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2282 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2283 USHORT StandardVESA_Timing; // Only used by Bios 2284 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2285 USHORT PaletteData; // Only used by BIOS 2286 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2287 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2288 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2289 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2290 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2291 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2292 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2293 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2294 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2295 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2296 USHORT CompassionateData; // Will be obsolete from R600 2297 USHORT SaveRestoreInfo; // Only used by Bios 2298 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2299 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2300 USHORT XTMDS_Info; // Will be obsolete from R600 2301 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2302 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2303 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2304 USHORT MC_InitParameter; // Only used by command table 2305 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2306 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2307 USHORT TV_VideoMode; // Only used by command table 2308 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2309 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2310 USHORT IntegratedSystemInfo; // Shared by various SW components 2311 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2312 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2313 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2314 }ATOM_MASTER_LIST_OF_DATA_TABLES; 2315 2316 typedef struct _ATOM_MASTER_DATA_TABLE 2317 { 2318 ATOM_COMMON_TABLE_HEADER sHeader; 2319 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2320 }ATOM_MASTER_DATA_TABLE; 2321 2322 // For backward compatible 2323 #define LVDS_Info LCD_Info 2324 #define DAC_Info PaletteData 2325 #define TMDS_Info DIGTransmitterInfo 2326 2327 /****************************************************************************/ 2328 // Structure used in MultimediaCapabilityInfoTable 2329 /****************************************************************************/ 2330 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2331 { 2332 ATOM_COMMON_TABLE_HEADER sHeader; 2333 ULONG ulSignature; // HW info table signature string "$ATI" 2334 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2335 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2336 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2337 UCHAR ucHostPortInfo; // Provides host port configuration information 2338 }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2339 2340 /****************************************************************************/ 2341 // Structure used in MultimediaConfigInfoTable 2342 /****************************************************************************/ 2343 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2344 { 2345 ATOM_COMMON_TABLE_HEADER sHeader; 2346 ULONG ulSignature; // MM info table signature sting "$MMT" 2347 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2348 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2349 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2350 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2351 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2352 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2353 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2354 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2355 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2356 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2357 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2358 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2359 }ATOM_MULTIMEDIA_CONFIG_INFO; 2360 2361 2362 /****************************************************************************/ 2363 // Structures used in FirmwareInfoTable 2364 /****************************************************************************/ 2365 2366 // usBIOSCapability Definition: 2367 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2368 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2369 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2370 // Others: Reserved 2371 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2372 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2373 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2374 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2375 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2376 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2377 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2378 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2379 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2380 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2381 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2382 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2383 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2384 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2385 2386 #ifndef _H2INC 2387 2388 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2389 typedef struct _ATOM_FIRMWARE_CAPABILITY 2390 { 2391 #if ATOM_BIG_ENDIAN 2392 USHORT Reserved:1; 2393 USHORT SCL2Redefined:1; 2394 USHORT PostWithoutModeSet:1; 2395 USHORT HyperMemory_Size:4; 2396 USHORT HyperMemory_Support:1; 2397 USHORT PPMode_Assigned:1; 2398 USHORT WMI_SUPPORT:1; 2399 USHORT GPUControlsBL:1; 2400 USHORT EngineClockSS_Support:1; 2401 USHORT MemoryClockSS_Support:1; 2402 USHORT ExtendedDesktopSupport:1; 2403 USHORT DualCRTC_Support:1; 2404 USHORT FirmwarePosted:1; 2405 #else 2406 USHORT FirmwarePosted:1; 2407 USHORT DualCRTC_Support:1; 2408 USHORT ExtendedDesktopSupport:1; 2409 USHORT MemoryClockSS_Support:1; 2410 USHORT EngineClockSS_Support:1; 2411 USHORT GPUControlsBL:1; 2412 USHORT WMI_SUPPORT:1; 2413 USHORT PPMode_Assigned:1; 2414 USHORT HyperMemory_Support:1; 2415 USHORT HyperMemory_Size:4; 2416 USHORT PostWithoutModeSet:1; 2417 USHORT SCL2Redefined:1; 2418 USHORT Reserved:1; 2419 #endif 2420 }ATOM_FIRMWARE_CAPABILITY; 2421 2422 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2423 { 2424 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2425 USHORT susAccess; 2426 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2427 2428 #else 2429 2430 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2431 { 2432 USHORT susAccess; 2433 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2434 2435 #endif 2436 2437 typedef struct _ATOM_FIRMWARE_INFO 2438 { 2439 ATOM_COMMON_TABLE_HEADER sHeader; 2440 ULONG ulFirmwareRevision; 2441 ULONG ulDefaultEngineClock; //In 10Khz unit 2442 ULONG ulDefaultMemoryClock; //In 10Khz unit 2443 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2444 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2445 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2446 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2447 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2448 ULONG ulASICMaxEngineClock; //In 10Khz unit 2449 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2450 UCHAR ucASICMaxTemperature; 2451 UCHAR ucPadding[3]; //Don't use them 2452 ULONG aulReservedForBIOS[3]; //Don't use them 2453 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2454 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2455 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2456 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2457 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2458 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2459 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2460 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2461 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2462 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2463 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2464 USHORT usReferenceClock; //In 10Khz unit 2465 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2466 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2467 UCHAR ucDesign_ID; //Indicate what is the board design 2468 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2469 }ATOM_FIRMWARE_INFO; 2470 2471 typedef struct _ATOM_FIRMWARE_INFO_V1_2 2472 { 2473 ATOM_COMMON_TABLE_HEADER sHeader; 2474 ULONG ulFirmwareRevision; 2475 ULONG ulDefaultEngineClock; //In 10Khz unit 2476 ULONG ulDefaultMemoryClock; //In 10Khz unit 2477 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2478 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2479 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2480 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2481 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2482 ULONG ulASICMaxEngineClock; //In 10Khz unit 2483 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2484 UCHAR ucASICMaxTemperature; 2485 UCHAR ucMinAllowedBL_Level; 2486 UCHAR ucPadding[2]; //Don't use them 2487 ULONG aulReservedForBIOS[2]; //Don't use them 2488 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2489 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2490 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2491 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2492 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2493 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2494 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2495 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2496 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2497 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2498 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2499 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2500 USHORT usReferenceClock; //In 10Khz unit 2501 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2502 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2503 UCHAR ucDesign_ID; //Indicate what is the board design 2504 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2505 }ATOM_FIRMWARE_INFO_V1_2; 2506 2507 typedef struct _ATOM_FIRMWARE_INFO_V1_3 2508 { 2509 ATOM_COMMON_TABLE_HEADER sHeader; 2510 ULONG ulFirmwareRevision; 2511 ULONG ulDefaultEngineClock; //In 10Khz unit 2512 ULONG ulDefaultMemoryClock; //In 10Khz unit 2513 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2514 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2515 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2516 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2517 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2518 ULONG ulASICMaxEngineClock; //In 10Khz unit 2519 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2520 UCHAR ucASICMaxTemperature; 2521 UCHAR ucMinAllowedBL_Level; 2522 UCHAR ucPadding[2]; //Don't use them 2523 ULONG aulReservedForBIOS; //Don't use them 2524 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2525 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2526 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2527 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2528 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2529 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2530 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2531 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2532 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2533 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2534 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2535 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2536 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2537 USHORT usReferenceClock; //In 10Khz unit 2538 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2539 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2540 UCHAR ucDesign_ID; //Indicate what is the board design 2541 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2542 }ATOM_FIRMWARE_INFO_V1_3; 2543 2544 typedef struct _ATOM_FIRMWARE_INFO_V1_4 2545 { 2546 ATOM_COMMON_TABLE_HEADER sHeader; 2547 ULONG ulFirmwareRevision; 2548 ULONG ulDefaultEngineClock; //In 10Khz unit 2549 ULONG ulDefaultMemoryClock; //In 10Khz unit 2550 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2551 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2552 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2553 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2554 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2555 ULONG ulASICMaxEngineClock; //In 10Khz unit 2556 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2557 UCHAR ucASICMaxTemperature; 2558 UCHAR ucMinAllowedBL_Level; 2559 USHORT usBootUpVDDCVoltage; //In MV unit 2560 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2561 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2562 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2563 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2564 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2565 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2566 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2567 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2568 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2569 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2570 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2571 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2572 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2573 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2574 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2575 USHORT usReferenceClock; //In 10Khz unit 2576 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2577 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2578 UCHAR ucDesign_ID; //Indicate what is the board design 2579 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2580 }ATOM_FIRMWARE_INFO_V1_4; 2581 2582 //the structure below to be used from Cypress 2583 typedef struct _ATOM_FIRMWARE_INFO_V2_1 2584 { 2585 ATOM_COMMON_TABLE_HEADER sHeader; 2586 ULONG ulFirmwareRevision; 2587 ULONG ulDefaultEngineClock; //In 10Khz unit 2588 ULONG ulDefaultMemoryClock; //In 10Khz unit 2589 ULONG ulReserved1; 2590 ULONG ulReserved2; 2591 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2592 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2593 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2594 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2595 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2596 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2597 UCHAR ucMinAllowedBL_Level; 2598 USHORT usBootUpVDDCVoltage; //In MV unit 2599 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2600 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2601 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2602 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2603 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2604 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2605 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2606 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2607 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2608 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2609 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2610 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2611 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2612 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2613 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2614 USHORT usCoreReferenceClock; //In 10Khz unit 2615 USHORT usMemoryReferenceClock; //In 10Khz unit 2616 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2617 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2618 UCHAR ucReserved4[3]; 2619 }ATOM_FIRMWARE_INFO_V2_1; 2620 2621 //the structure below to be used from NI 2622 //ucTableFormatRevision=2 2623 //ucTableContentRevision=2 2624 typedef struct _ATOM_FIRMWARE_INFO_V2_2 2625 { 2626 ATOM_COMMON_TABLE_HEADER sHeader; 2627 ULONG ulFirmwareRevision; 2628 ULONG ulDefaultEngineClock; //In 10Khz unit 2629 ULONG ulDefaultMemoryClock; //In 10Khz unit 2630 ULONG ulReserved[2]; 2631 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2632 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2633 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2634 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2635 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2636 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2637 UCHAR ucMinAllowedBL_Level; 2638 USHORT usBootUpVDDCVoltage; //In MV unit 2639 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2640 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2641 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2642 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2643 UCHAR ucRemoteDisplayConfig; 2644 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2645 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2646 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2647 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2648 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2649 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2650 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2651 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2652 USHORT usCoreReferenceClock; //In 10Khz unit 2653 USHORT usMemoryReferenceClock; //In 10Khz unit 2654 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2655 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2656 UCHAR ucReserved9[3]; 2657 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2658 USHORT usReserved12; 2659 ULONG ulReserved10[3]; // New added comparing to previous version 2660 }ATOM_FIRMWARE_INFO_V2_2; 2661 2662 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2663 2664 2665 // definition of ucRemoteDisplayConfig 2666 #define REMOTE_DISPLAY_DISABLE 0x00 2667 #define REMOTE_DISPLAY_ENABLE 0x01 2668 2669 /****************************************************************************/ 2670 // Structures used in IntegratedSystemInfoTable 2671 /****************************************************************************/ 2672 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2673 #define IGP_CAP_FLAG_AC_CARD 0x4 2674 #define IGP_CAP_FLAG_SDVO_CARD 0x8 2675 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2676 2677 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2678 { 2679 ATOM_COMMON_TABLE_HEADER sHeader; 2680 ULONG ulBootUpEngineClock; //in 10kHz unit 2681 ULONG ulBootUpMemoryClock; //in 10kHz unit 2682 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2683 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2684 UCHAR ucNumberOfCyclesInPeriodHi; 2685 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2686 USHORT usReserved1; 2687 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2688 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2689 ULONG ulReserved[2]; 2690 2691 USHORT usFSBClock; //In MHz unit 2692 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2693 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2694 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2695 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2696 USHORT usK8MemoryClock; //in MHz unit 2697 USHORT usK8SyncStartDelay; //in 0.01 us unit 2698 USHORT usK8DataReturnTime; //in 0.01 us unit 2699 UCHAR ucMaxNBVoltage; 2700 UCHAR ucMinNBVoltage; 2701 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2702 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2703 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2704 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2705 UCHAR ucMaxNBVoltageHigh; 2706 UCHAR ucMinNBVoltageHigh; 2707 }ATOM_INTEGRATED_SYSTEM_INFO; 2708 2709 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2710 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2711 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2712 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2713 For AMD IGP,for now this can be 0 2714 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2715 For AMD IGP,for now this can be 0 2716 2717 usFSBClock: For Intel IGP,it's FSB Freq 2718 For AMD IGP,it's HT Link Speed 2719 2720 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2721 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2722 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2723 2724 VC:Voltage Control 2725 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2726 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2727 2728 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2729 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2730 2731 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2732 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2733 2734 2735 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2736 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2737 */ 2738 2739 2740 /* 2741 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2742 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2743 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2744 2745 SW components can access the IGP system infor structure in the same way as before 2746 */ 2747 2748 2749 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2750 { 2751 ATOM_COMMON_TABLE_HEADER sHeader; 2752 ULONG ulBootUpEngineClock; //in 10kHz unit 2753 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2754 ULONG ulBootUpUMAClock; //in 10kHz unit 2755 ULONG ulBootUpSidePortClock; //in 10kHz unit 2756 ULONG ulMinSidePortClock; //in 10kHz unit 2757 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2758 ULONG ulSystemConfig; //see explanation below 2759 ULONG ulBootUpReqDisplayVector; 2760 ULONG ulOtherDisplayMisc; 2761 ULONG ulDDISlot1Config; 2762 ULONG ulDDISlot2Config; 2763 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2764 UCHAR ucUMAChannelNumber; 2765 UCHAR ucDockingPinBit; 2766 UCHAR ucDockingPinPolarity; 2767 ULONG ulDockingPinCFGInfo; 2768 ULONG ulCPUCapInfo; 2769 USHORT usNumberOfCyclesInPeriod; 2770 USHORT usMaxNBVoltage; 2771 USHORT usMinNBVoltage; 2772 USHORT usBootUpNBVoltage; 2773 ULONG ulHTLinkFreq; //in 10Khz 2774 USHORT usMinHTLinkWidth; 2775 USHORT usMaxHTLinkWidth; 2776 USHORT usUMASyncStartDelay; 2777 USHORT usUMADataReturnTime; 2778 USHORT usLinkStatusZeroTime; 2779 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2780 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2781 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2782 USHORT usMaxUpStreamHTLinkWidth; 2783 USHORT usMaxDownStreamHTLinkWidth; 2784 USHORT usMinUpStreamHTLinkWidth; 2785 USHORT usMinDownStreamHTLinkWidth; 2786 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2787 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2788 ULONG ulReserved3[96]; //must be 0x0 2789 }ATOM_INTEGRATED_SYSTEM_INFO_V2; 2790 2791 /* 2792 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2793 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2794 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2795 2796 ulSystemConfig: 2797 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2798 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2799 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2800 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2801 Bit[3]=1: Only one power state(Performance) will be supported. 2802 =0: Multiple power states supported from PowerPlay table. 2803 Bit[4]=1: CLMC is supported and enabled on current system. 2804 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2805 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2806 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2807 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2808 =0: Voltage settings is determined by powerplay table. 2809 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2810 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2811 Bit[8]=1: CDLF is supported and enabled on current system. 2812 =0: CDLF is not supported or enabled on current system. 2813 Bit[9]=1: DLL Shut Down feature is enabled on current system. 2814 =0: DLL Shut Down feature is not enabled or supported on current system. 2815 2816 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2817 2818 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2819 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSupportedStd definition; 2820 2821 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2822 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2823 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2824 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2825 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2826 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2827 2828 [15:8] - Lane configuration attribute; 2829 [23:16]- Connector type, possible value: 2830 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2831 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2832 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2833 CONNECTOR_OBJECT_ID_DISPLAYPORT 2834 CONNECTOR_OBJECT_ID_eDP 2835 [31:24]- Reserved 2836 2837 ulDDISlot2Config: Same as Slot1. 2838 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2839 For IGP, Hypermemory is the only memory type showed in CCC. 2840 2841 ucUMAChannelNumber: how many channels for the UMA; 2842 2843 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2844 ucDockingPinBit: which bit in this register to read the pin status; 2845 ucDockingPinPolarity:Polarity of the pin when docked; 2846 2847 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 2848 2849 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 2850 2851 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 2852 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 2853 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 2854 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 2855 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 2856 2857 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 2858 2859 ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 2860 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 2861 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2862 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 2863 If CDLW enabled, both upstream and downstream width should be the same during bootup. 2864 2865 usUMASyncStartDelay: Memory access latency, required for watermark calculation 2866 usUMADataReturnTime: Memory access latency, required for watermark calculation 2867 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 2868 for Griffin or Greyhound. SBIOS needs to convert to actual time by: 2869 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 2870 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 2871 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 2872 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 2873 2874 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 2875 This must be less than or equal to ulHTLinkFreq(bootup frequency). 2876 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 2877 This must be less than or equal to ulHighVoltageHTLinkFreq. 2878 2879 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 2880 usMaxDownStreamHTLinkWidth: same as above. 2881 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 2882 usMinDownStreamHTLinkWidth: same as above. 2883 */ 2884 2885 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 2886 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 2887 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 2888 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 2889 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 2890 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 2891 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 2892 2893 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 2894 2895 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 2896 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 2897 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 2898 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 2899 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 2900 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 2901 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 2902 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 2903 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 2904 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 2905 2906 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 2907 2908 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 2909 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 2910 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 2911 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 2912 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 2913 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 2914 2915 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 2916 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 2917 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 2918 2919 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 2920 2921 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 2922 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 2923 { 2924 ATOM_COMMON_TABLE_HEADER sHeader; 2925 ULONG ulBootUpEngineClock; //in 10kHz unit 2926 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 2927 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 2928 ULONG ulBootUpUMAClock; //in 10kHz unit 2929 ULONG ulReserved1[8]; //must be 0x0 for the reserved 2930 ULONG ulBootUpReqDisplayVector; 2931 ULONG ulOtherDisplayMisc; 2932 ULONG ulReserved2[4]; //must be 0x0 for the reserved 2933 ULONG ulSystemConfig; //TBD 2934 ULONG ulCPUCapInfo; //TBD 2935 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2936 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 2937 USHORT usBootUpNBVoltage; //boot up NB voltage 2938 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 2939 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 2940 ULONG ulReserved3[4]; //must be 0x0 for the reserved 2941 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 2942 ULONG ulDDISlot2Config; 2943 ULONG ulDDISlot3Config; 2944 ULONG ulDDISlot4Config; 2945 ULONG ulReserved4[4]; //must be 0x0 for the reserved 2946 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2947 UCHAR ucUMAChannelNumber; 2948 USHORT usReserved; 2949 ULONG ulReserved5[4]; //must be 0x0 for the reserved 2950 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 2951 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 2952 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 2953 ULONG ulReserved6[61]; //must be 0x0 2954 }ATOM_INTEGRATED_SYSTEM_INFO_V5; 2955 2956 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 2957 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 2958 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 2959 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 2960 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 2961 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 2962 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 2963 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 2964 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 2965 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 2966 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 2967 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 2968 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 2969 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 2970 2971 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 2972 #define ASIC_INT_DAC1_ENCODER_ID 0x00 2973 #define ASIC_INT_TV_ENCODER_ID 0x02 2974 #define ASIC_INT_DIG1_ENCODER_ID 0x03 2975 #define ASIC_INT_DAC2_ENCODER_ID 0x04 2976 #define ASIC_EXT_TV_ENCODER_ID 0x06 2977 #define ASIC_INT_DVO_ENCODER_ID 0x07 2978 #define ASIC_INT_DIG2_ENCODER_ID 0x09 2979 #define ASIC_EXT_DIG_ENCODER_ID 0x05 2980 #define ASIC_EXT_DIG2_ENCODER_ID 0x08 2981 #define ASIC_INT_DIG3_ENCODER_ID 0x0a 2982 #define ASIC_INT_DIG4_ENCODER_ID 0x0b 2983 #define ASIC_INT_DIG5_ENCODER_ID 0x0c 2984 #define ASIC_INT_DIG6_ENCODER_ID 0x0d 2985 #define ASIC_INT_DIG7_ENCODER_ID 0x0e 2986 2987 //define Encoder attribute 2988 #define ATOM_ANALOG_ENCODER 0 2989 #define ATOM_DIGITAL_ENCODER 1 2990 #define ATOM_DP_ENCODER 2 2991 2992 #define ATOM_ENCODER_ENUM_MASK 0x70 2993 #define ATOM_ENCODER_ENUM_ID1 0x00 2994 #define ATOM_ENCODER_ENUM_ID2 0x10 2995 #define ATOM_ENCODER_ENUM_ID3 0x20 2996 #define ATOM_ENCODER_ENUM_ID4 0x30 2997 #define ATOM_ENCODER_ENUM_ID5 0x40 2998 #define ATOM_ENCODER_ENUM_ID6 0x50 2999 3000 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 3001 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 3002 #define ATOM_DEVICE_TV1_INDEX 0x00000002 3003 #define ATOM_DEVICE_DFP1_INDEX 0x00000003 3004 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 3005 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 3006 #define ATOM_DEVICE_DFP6_INDEX 0x00000006 3007 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 3008 #define ATOM_DEVICE_CV_INDEX 0x00000008 3009 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 3010 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3011 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3012 3013 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3014 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3015 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3016 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3017 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3018 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3019 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3020 3021 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3022 3023 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3024 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3025 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3026 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3027 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3028 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3029 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3030 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3031 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3032 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3033 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3034 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3035 3036 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3037 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3038 #define ATOM_DEVICE_TV_SUPPORT (ATOM_DEVICE_TV1_SUPPORT) 3039 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3040 3041 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3042 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3043 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3044 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3045 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3046 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3047 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3048 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3049 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3050 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3051 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3052 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3053 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3054 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3055 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3056 3057 3058 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3059 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3060 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3061 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3062 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3063 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3064 3065 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3066 3067 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3068 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3069 3070 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3071 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3072 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3073 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3074 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3075 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3076 3077 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3078 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3079 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3080 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3081 3082 // usDeviceSupport: 3083 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3084 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3085 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3086 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3087 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3088 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3089 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3090 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3091 // Bit 8 = 0 - no CV support= 1- CV is supported 3092 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3093 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported 3094 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported 3095 // 3096 // 3097 3098 /****************************************************************************/ 3099 /* Structure used in MclkSS_InfoTable */ 3100 /****************************************************************************/ 3101 // ucI2C_ConfigID 3102 // [7:0] - I2C LINE Associate ID 3103 // = 0 - no I2C 3104 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3105 // = 0, [6:0]=SW assisted I2C ID 3106 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3107 // = 2, HW engine for Multimedia use 3108 // = 3-7 Reserved for future I2C engines 3109 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3110 3111 typedef struct _ATOM_I2C_ID_CONFIG 3112 { 3113 #if ATOM_BIG_ENDIAN 3114 UCHAR bfHW_Capable:1; 3115 UCHAR bfHW_EngineID:3; 3116 UCHAR bfI2C_LineMux:4; 3117 #else 3118 UCHAR bfI2C_LineMux:4; 3119 UCHAR bfHW_EngineID:3; 3120 UCHAR bfHW_Capable:1; 3121 #endif 3122 }ATOM_I2C_ID_CONFIG; 3123 3124 typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3125 { 3126 ATOM_I2C_ID_CONFIG sbfAccess; 3127 UCHAR ucAccess; 3128 }ATOM_I2C_ID_CONFIG_ACCESS; 3129 3130 3131 /****************************************************************************/ 3132 // Structure used in GPIO_I2C_InfoTable 3133 /****************************************************************************/ 3134 typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3135 { 3136 USHORT usClkMaskRegisterIndex; 3137 USHORT usClkEnRegisterIndex; 3138 USHORT usClkY_RegisterIndex; 3139 USHORT usClkA_RegisterIndex; 3140 USHORT usDataMaskRegisterIndex; 3141 USHORT usDataEnRegisterIndex; 3142 USHORT usDataY_RegisterIndex; 3143 USHORT usDataA_RegisterIndex; 3144 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3145 UCHAR ucClkMaskShift; 3146 UCHAR ucClkEnShift; 3147 UCHAR ucClkY_Shift; 3148 UCHAR ucClkA_Shift; 3149 UCHAR ucDataMaskShift; 3150 UCHAR ucDataEnShift; 3151 UCHAR ucDataY_Shift; 3152 UCHAR ucDataA_Shift; 3153 UCHAR ucReserved1; 3154 UCHAR ucReserved2; 3155 }ATOM_GPIO_I2C_ASSIGMENT; 3156 3157 typedef struct _ATOM_GPIO_I2C_INFO 3158 { 3159 ATOM_COMMON_TABLE_HEADER sHeader; 3160 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3161 }ATOM_GPIO_I2C_INFO; 3162 3163 /****************************************************************************/ 3164 // Common Structure used in other structures 3165 /****************************************************************************/ 3166 3167 #ifndef _H2INC 3168 3169 //Please don't add or expand this bitfield structure below, this one will retire soon.! 3170 typedef struct _ATOM_MODE_MISC_INFO 3171 { 3172 #if ATOM_BIG_ENDIAN 3173 USHORT Reserved:6; 3174 USHORT RGB888:1; 3175 USHORT DoubleClock:1; 3176 USHORT Interlace:1; 3177 USHORT CompositeSync:1; 3178 USHORT V_ReplicationBy2:1; 3179 USHORT H_ReplicationBy2:1; 3180 USHORT VerticalCutOff:1; 3181 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3182 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3183 USHORT HorizontalCutOff:1; 3184 #else 3185 USHORT HorizontalCutOff:1; 3186 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3187 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3188 USHORT VerticalCutOff:1; 3189 USHORT H_ReplicationBy2:1; 3190 USHORT V_ReplicationBy2:1; 3191 USHORT CompositeSync:1; 3192 USHORT Interlace:1; 3193 USHORT DoubleClock:1; 3194 USHORT RGB888:1; 3195 USHORT Reserved:6; 3196 #endif 3197 }ATOM_MODE_MISC_INFO; 3198 3199 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3200 { 3201 ATOM_MODE_MISC_INFO sbfAccess; 3202 USHORT usAccess; 3203 }ATOM_MODE_MISC_INFO_ACCESS; 3204 3205 #else 3206 3207 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3208 { 3209 USHORT usAccess; 3210 }ATOM_MODE_MISC_INFO_ACCESS; 3211 3212 #endif 3213 3214 // usModeMiscInfo- 3215 #define ATOM_H_CUTOFF 0x01 3216 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3217 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3218 #define ATOM_V_CUTOFF 0x08 3219 #define ATOM_H_REPLICATIONBY2 0x10 3220 #define ATOM_V_REPLICATIONBY2 0x20 3221 #define ATOM_COMPOSITESYNC 0x40 3222 #define ATOM_INTERLACE 0x80 3223 #define ATOM_DOUBLE_CLOCK_MODE 0x100 3224 #define ATOM_RGB888_MODE 0x200 3225 3226 //usRefreshRate- 3227 #define ATOM_REFRESH_43 43 3228 #define ATOM_REFRESH_47 47 3229 #define ATOM_REFRESH_56 56 3230 #define ATOM_REFRESH_60 60 3231 #define ATOM_REFRESH_65 65 3232 #define ATOM_REFRESH_70 70 3233 #define ATOM_REFRESH_72 72 3234 #define ATOM_REFRESH_75 75 3235 #define ATOM_REFRESH_85 85 3236 3237 // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3238 // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3239 // 3240 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3241 // = EDID_HA + EDID_HBL 3242 // VESA_HDISP = VESA_ACTIVE = EDID_HA 3243 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3244 // = EDID_HA + EDID_HSO 3245 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3246 // VESA_BORDER = EDID_BORDER 3247 3248 /****************************************************************************/ 3249 // Structure used in SetCRTC_UsingDTDTimingTable 3250 /****************************************************************************/ 3251 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3252 { 3253 USHORT usH_Size; 3254 USHORT usH_Blanking_Time; 3255 USHORT usV_Size; 3256 USHORT usV_Blanking_Time; 3257 USHORT usH_SyncOffset; 3258 USHORT usH_SyncWidth; 3259 USHORT usV_SyncOffset; 3260 USHORT usV_SyncWidth; 3261 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3262 UCHAR ucH_Border; // From DFP EDID 3263 UCHAR ucV_Border; 3264 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3265 UCHAR ucPadding[3]; 3266 }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3267 3268 /****************************************************************************/ 3269 // Structure used in SetCRTC_TimingTable 3270 /****************************************************************************/ 3271 typedef struct _SET_CRTC_TIMING_PARAMETERS 3272 { 3273 USHORT usH_Total; // horizontal total 3274 USHORT usH_Disp; // horizontal display 3275 USHORT usH_SyncStart; // horozontal Sync start 3276 USHORT usH_SyncWidth; // horizontal Sync width 3277 USHORT usV_Total; // vertical total 3278 USHORT usV_Disp; // vertical display 3279 USHORT usV_SyncStart; // vertical Sync start 3280 USHORT usV_SyncWidth; // vertical Sync width 3281 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3282 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3283 UCHAR ucOverscanRight; // right 3284 UCHAR ucOverscanLeft; // left 3285 UCHAR ucOverscanBottom; // bottom 3286 UCHAR ucOverscanTop; // top 3287 UCHAR ucReserved; 3288 }SET_CRTC_TIMING_PARAMETERS; 3289 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3290 3291 /****************************************************************************/ 3292 // Structure used in StandardVESA_TimingTable 3293 // AnalogTV_InfoTable 3294 // ComponentVideoInfoTable 3295 /****************************************************************************/ 3296 typedef struct _ATOM_MODE_TIMING 3297 { 3298 USHORT usCRTC_H_Total; 3299 USHORT usCRTC_H_Disp; 3300 USHORT usCRTC_H_SyncStart; 3301 USHORT usCRTC_H_SyncWidth; 3302 USHORT usCRTC_V_Total; 3303 USHORT usCRTC_V_Disp; 3304 USHORT usCRTC_V_SyncStart; 3305 USHORT usCRTC_V_SyncWidth; 3306 USHORT usPixelClock; //in 10Khz unit 3307 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3308 USHORT usCRTC_OverscanRight; 3309 USHORT usCRTC_OverscanLeft; 3310 USHORT usCRTC_OverscanBottom; 3311 USHORT usCRTC_OverscanTop; 3312 USHORT usReserve; 3313 UCHAR ucInternalModeNumber; 3314 UCHAR ucRefreshRate; 3315 }ATOM_MODE_TIMING; 3316 3317 typedef struct _ATOM_DTD_FORMAT 3318 { 3319 USHORT usPixClk; 3320 USHORT usHActive; 3321 USHORT usHBlanking_Time; 3322 USHORT usVActive; 3323 USHORT usVBlanking_Time; 3324 USHORT usHSyncOffset; 3325 USHORT usHSyncWidth; 3326 USHORT usVSyncOffset; 3327 USHORT usVSyncWidth; 3328 USHORT usImageHSize; 3329 USHORT usImageVSize; 3330 UCHAR ucHBorder; 3331 UCHAR ucVBorder; 3332 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3333 UCHAR ucInternalModeNumber; 3334 UCHAR ucRefreshRate; 3335 }ATOM_DTD_FORMAT; 3336 3337 /****************************************************************************/ 3338 // Structure used in LVDS_InfoTable 3339 // * Need a document to describe this table 3340 /****************************************************************************/ 3341 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3342 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3343 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3344 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3345 3346 //ucTableFormatRevision=1 3347 //ucTableContentRevision=1 3348 typedef struct _ATOM_LVDS_INFO 3349 { 3350 ATOM_COMMON_TABLE_HEADER sHeader; 3351 ATOM_DTD_FORMAT sLCDTiming; 3352 USHORT usModePatchTableOffset; 3353 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3354 USHORT usOffDelayInMs; 3355 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3356 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3357 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3358 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3359 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3360 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3361 UCHAR ucPanelDefaultRefreshRate; 3362 UCHAR ucPanelIdentification; 3363 UCHAR ucSS_Id; 3364 }ATOM_LVDS_INFO; 3365 3366 //ucTableFormatRevision=1 3367 //ucTableContentRevision=2 3368 typedef struct _ATOM_LVDS_INFO_V12 3369 { 3370 ATOM_COMMON_TABLE_HEADER sHeader; 3371 ATOM_DTD_FORMAT sLCDTiming; 3372 USHORT usExtInfoTableOffset; 3373 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3374 USHORT usOffDelayInMs; 3375 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3376 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3377 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3378 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3379 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3380 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3381 UCHAR ucPanelDefaultRefreshRate; 3382 UCHAR ucPanelIdentification; 3383 UCHAR ucSS_Id; 3384 USHORT usLCDVenderID; 3385 USHORT usLCDProductID; 3386 UCHAR ucLCDPanel_SpecialHandlingCap; 3387 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3388 UCHAR ucReserved[2]; 3389 }ATOM_LVDS_INFO_V12; 3390 3391 //Definitions for ucLCDPanel_SpecialHandlingCap: 3392 3393 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3394 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3395 #define LCDPANEL_CAP_READ_EDID 0x1 3396 3397 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3398 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3399 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3400 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3401 3402 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3403 #define LCDPANEL_CAP_eDP 0x4 3404 3405 3406 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3407 //Bit 6 5 4 3408 // 0 0 0 - Color bit depth is undefined 3409 // 0 0 1 - 6 Bits per Primary Color 3410 // 0 1 0 - 8 Bits per Primary Color 3411 // 0 1 1 - 10 Bits per Primary Color 3412 // 1 0 0 - 12 Bits per Primary Color 3413 // 1 0 1 - 14 Bits per Primary Color 3414 // 1 1 0 - 16 Bits per Primary Color 3415 // 1 1 1 - Reserved 3416 3417 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3418 3419 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3420 #define PANEL_RANDOM_DITHER 0x80 3421 #define PANEL_RANDOM_DITHER_MASK 0x80 3422 3423 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3424 3425 /****************************************************************************/ 3426 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3427 // ASIC Families: NI 3428 // ucTableFormatRevision=1 3429 // ucTableContentRevision=3 3430 /****************************************************************************/ 3431 typedef struct _ATOM_LCD_INFO_V13 3432 { 3433 ATOM_COMMON_TABLE_HEADER sHeader; 3434 ATOM_DTD_FORMAT sLCDTiming; 3435 USHORT usExtInfoTableOffset; 3436 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3437 ULONG ulReserved0; 3438 UCHAR ucLCD_Misc; // Reorganized in V13 3439 // Bit0: {=0:single, =1:dual}, 3440 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3441 // Bit3:2: {Grey level} 3442 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3443 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3444 UCHAR ucPanelDefaultRefreshRate; 3445 UCHAR ucPanelIdentification; 3446 UCHAR ucSS_Id; 3447 USHORT usLCDVenderID; 3448 USHORT usLCDProductID; 3449 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3450 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3451 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3452 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3453 // Bit7-3: Reserved 3454 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3455 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3456 3457 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3458 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3459 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3460 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3461 3462 UCHAR ucOffDelay_in4Ms; 3463 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3464 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3465 UCHAR ucReserved1; 3466 3467 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3468 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3469 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3470 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3471 3472 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3473 UCHAR uceDPToLVDSRxId; 3474 UCHAR ucLcdReservd; 3475 ULONG ulReserved[2]; 3476 }ATOM_LCD_INFO_V13; 3477 3478 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3479 3480 //Definitions for ucLCD_Misc 3481 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3482 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3483 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3484 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3485 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3486 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3487 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3488 3489 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3490 //Bit 6 5 4 3491 // 0 0 0 - Color bit depth is undefined 3492 // 0 0 1 - 6 Bits per Primary Color 3493 // 0 1 0 - 8 Bits per Primary Color 3494 // 0 1 1 - 10 Bits per Primary Color 3495 // 1 0 0 - 12 Bits per Primary Color 3496 // 1 0 1 - 14 Bits per Primary Color 3497 // 1 1 0 - 16 Bits per Primary Color 3498 // 1 1 1 - Reserved 3499 3500 //Definitions for ucLCDPanel_SpecialHandlingCap: 3501 3502 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3503 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3504 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3505 3506 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3507 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3508 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3509 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3510 3511 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3512 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3513 3514 //uceDPToLVDSRxId 3515 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3516 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3517 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init 3518 3519 typedef struct _ATOM_PATCH_RECORD_MODE 3520 { 3521 UCHAR ucRecordType; 3522 USHORT usHDisp; 3523 USHORT usVDisp; 3524 }ATOM_PATCH_RECORD_MODE; 3525 3526 typedef struct _ATOM_LCD_RTS_RECORD 3527 { 3528 UCHAR ucRecordType; 3529 UCHAR ucRTSValue; 3530 }ATOM_LCD_RTS_RECORD; 3531 3532 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3533 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3534 typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3535 { 3536 UCHAR ucRecordType; 3537 USHORT usLCDCap; 3538 }ATOM_LCD_MODE_CONTROL_CAP; 3539 3540 #define LCD_MODE_CAP_BL_OFF 1 3541 #define LCD_MODE_CAP_CRTC_OFF 2 3542 #define LCD_MODE_CAP_PANEL_OFF 4 3543 3544 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3545 { 3546 UCHAR ucRecordType; 3547 UCHAR ucFakeEDIDLength; 3548 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3549 } ATOM_FAKE_EDID_PATCH_RECORD; 3550 3551 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3552 { 3553 UCHAR ucRecordType; 3554 USHORT usHSize; 3555 USHORT usVSize; 3556 }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3557 3558 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3559 #define LCD_RTS_RECORD_TYPE 2 3560 #define LCD_CAP_RECORD_TYPE 3 3561 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3562 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3563 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3564 #define ATOM_RECORD_END_TYPE 0xFF 3565 3566 /****************************Spread Spectrum Info Table Definitions **********************/ 3567 3568 //ucTableFormatRevision=1 3569 //ucTableContentRevision=2 3570 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3571 { 3572 USHORT usSpreadSpectrumPercentage; 3573 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3574 UCHAR ucSS_Step; 3575 UCHAR ucSS_Delay; 3576 UCHAR ucSS_Id; 3577 UCHAR ucRecommendedRef_Div; 3578 UCHAR ucSS_Range; //it was reserved for V11 3579 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3580 3581 #define ATOM_MAX_SS_ENTRY 16 3582 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3583 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3584 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3585 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3586 3587 3588 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3589 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3590 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3591 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3592 #define ATOM_INTERNAL_SS_MASK 0x00000000 3593 #define ATOM_EXTERNAL_SS_MASK 0x00000002 3594 #define EXEC_SS_STEP_SIZE_SHIFT 2 3595 #define EXEC_SS_DELAY_SHIFT 4 3596 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3597 3598 typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3599 { 3600 ATOM_COMMON_TABLE_HEADER sHeader; 3601 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3602 }ATOM_SPREAD_SPECTRUM_INFO; 3603 3604 /****************************************************************************/ 3605 // Structure used in AnalogTV_InfoTable (Top level) 3606 /****************************************************************************/ 3607 //ucTVBootUpDefaultStd definition: 3608 3609 //ATOM_TV_NTSC 1 3610 //ATOM_TV_NTSCJ 2 3611 //ATOM_TV_PAL 3 3612 //ATOM_TV_PALM 4 3613 //ATOM_TV_PALCN 5 3614 //ATOM_TV_PALN 6 3615 //ATOM_TV_PAL60 7 3616 //ATOM_TV_SECAM 8 3617 3618 //ucTVSupportedStd definition: 3619 #define NTSC_SUPPORT 0x1 3620 #define NTSCJ_SUPPORT 0x2 3621 3622 #define PAL_SUPPORT 0x4 3623 #define PALM_SUPPORT 0x8 3624 #define PALCN_SUPPORT 0x10 3625 #define PALN_SUPPORT 0x20 3626 #define PAL60_SUPPORT 0x40 3627 #define SECAM_SUPPORT 0x80 3628 3629 #define MAX_SUPPORTED_TV_TIMING 2 3630 3631 typedef struct _ATOM_ANALOG_TV_INFO 3632 { 3633 ATOM_COMMON_TABLE_HEADER sHeader; 3634 UCHAR ucTV_SupportedStandard; 3635 UCHAR ucTV_BootUpDefaultStandard; 3636 UCHAR ucExt_TV_ASIC_ID; 3637 UCHAR ucExt_TV_ASIC_SlaveAddr; 3638 /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING];*/ 3639 ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3640 }ATOM_ANALOG_TV_INFO; 3641 3642 #define MAX_SUPPORTED_TV_TIMING_V1_2 3 3643 3644 typedef struct _ATOM_ANALOG_TV_INFO_V1_2 3645 { 3646 ATOM_COMMON_TABLE_HEADER sHeader; 3647 UCHAR ucTV_SupportedStandard; 3648 UCHAR ucTV_BootUpDefaultStandard; 3649 UCHAR ucExt_TV_ASIC_ID; 3650 UCHAR ucExt_TV_ASIC_SlaveAddr; 3651 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING_V1_2]; 3652 }ATOM_ANALOG_TV_INFO_V1_2; 3653 3654 typedef struct _ATOM_DPCD_INFO 3655 { 3656 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3657 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3658 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3659 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3660 }ATOM_DPCD_INFO; 3661 3662 #define ATOM_DPCD_MAX_LANE_MASK 0x1F 3663 3664 /**************************************************************************/ 3665 // VRAM usage and their defintions 3666 3667 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3668 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3669 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3670 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3671 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3672 3673 #ifndef VESA_MEMORY_IN_64K_BLOCK 3674 #define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3675 #endif 3676 3677 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3678 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3679 #define ATOM_HWICON_INFOTABLE_SIZE 32 3680 #define MAX_DTD_MODE_IN_VRAM 6 3681 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3682 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3683 //20 bytes for Encoder Type and DPCD in STD EDID area 3684 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3685 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3686 3687 #define ATOM_HWICON1_SURFACE_ADDR 0 3688 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3689 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3690 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3691 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3692 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3693 3694 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3695 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3696 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3697 3698 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3699 3700 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3701 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3702 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3703 3704 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3705 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3706 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3707 3708 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3709 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3710 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3711 3712 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3713 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3714 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3715 3716 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3717 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3718 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3719 3720 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3721 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3722 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3723 3724 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3725 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3726 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3727 3728 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3729 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3730 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3731 3732 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3733 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3734 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3735 3736 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3737 3738 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3739 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3740 3741 //The size below is in Kb! 3742 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3743 3744 #define ATOM_VRAM_RESERVE_V2_SIZE 32 3745 3746 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3747 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3748 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3749 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3750 3751 /***********************************************************************************/ 3752 // Structure used in VRAM_UsageByFirmwareTable 3753 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3754 // at running time. 3755 // note2: From RV770, the memory is more than 32bit addressable, so we will change 3756 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3757 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3758 // (in offset to start of memory address) is KB aligned instead of byte aligend. 3759 /***********************************************************************************/ 3760 // Note3: 3761 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged constant across VGA or non VGA adapter, 3762 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3763 3764 If (ulStartAddrUsedByFirmware!=0) 3765 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3766 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3767 else //Non VGA case 3768 if (FB_Size<=2Gb) 3769 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3770 else 3771 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3772 3773 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3774 3775 /***********************************************************************************/ 3776 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3777 3778 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3779 { 3780 ULONG ulStartAddrUsedByFirmware; 3781 USHORT usFirmwareUseInKb; 3782 USHORT usReserved; 3783 }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3784 3785 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3786 { 3787 ATOM_COMMON_TABLE_HEADER sHeader; 3788 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3789 }ATOM_VRAM_USAGE_BY_FIRMWARE; 3790 3791 // change verion to 1.5, when allow driver to allocate the vram area for command table access. 3792 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3793 { 3794 ULONG ulStartAddrUsedByFirmware; 3795 USHORT usFirmwareUseInKb; 3796 USHORT usFBUsedByDrvInKb; 3797 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3798 3799 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3800 { 3801 ATOM_COMMON_TABLE_HEADER sHeader; 3802 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3803 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3804 3805 /****************************************************************************/ 3806 // Structure used in GPIO_Pin_LUTTable 3807 /****************************************************************************/ 3808 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3809 { 3810 USHORT usGpioPin_AIndex; 3811 UCHAR ucGpioPinBitShift; 3812 UCHAR ucGPIO_ID; 3813 }ATOM_GPIO_PIN_ASSIGNMENT; 3814 3815 typedef struct _ATOM_GPIO_PIN_LUT 3816 { 3817 ATOM_COMMON_TABLE_HEADER sHeader; 3818 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 3819 }ATOM_GPIO_PIN_LUT; 3820 3821 /****************************************************************************/ 3822 // Structure used in ComponentVideoInfoTable 3823 /****************************************************************************/ 3824 #define GPIO_PIN_ACTIVE_HIGH 0x1 3825 3826 #define MAX_SUPPORTED_CV_STANDARDS 5 3827 3828 // definitions for ATOM_D_INFO.ucSettings 3829 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 3830 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 3831 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 3832 3833 typedef struct _ATOM_GPIO_INFO 3834 { 3835 USHORT usAOffset; 3836 UCHAR ucSettings; 3837 UCHAR ucReserved; 3838 }ATOM_GPIO_INFO; 3839 3840 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 3841 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 3842 3843 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 3844 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 3845 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 3846 3847 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 3848 //Line 3 out put 5V. 3849 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 3850 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 3851 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 3852 3853 //Line 3 out put 2.2V 3854 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 3855 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 3856 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 3857 3858 //Line 3 out put 0V 3859 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 3860 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 3861 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 3862 3863 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 3864 3865 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 3866 3867 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 3868 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3869 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 3870 3871 3872 typedef struct _ATOM_COMPONENT_VIDEO_INFO 3873 { 3874 ATOM_COMMON_TABLE_HEADER sHeader; 3875 USHORT usMask_PinRegisterIndex; 3876 USHORT usEN_PinRegisterIndex; 3877 USHORT usY_PinRegisterIndex; 3878 USHORT usA_PinRegisterIndex; 3879 UCHAR ucBitShift; 3880 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 3881 ATOM_DTD_FORMAT sReserved; // must be zeroed out 3882 UCHAR ucMiscInfo; 3883 UCHAR uc480i; 3884 UCHAR uc480p; 3885 UCHAR uc720p; 3886 UCHAR uc1080i; 3887 UCHAR ucLetterBoxMode; 3888 UCHAR ucReserved[3]; 3889 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3890 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3891 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3892 }ATOM_COMPONENT_VIDEO_INFO; 3893 3894 //ucTableFormatRevision=2 3895 //ucTableContentRevision=1 3896 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 3897 { 3898 ATOM_COMMON_TABLE_HEADER sHeader; 3899 UCHAR ucMiscInfo; 3900 UCHAR uc480i; 3901 UCHAR uc480p; 3902 UCHAR uc720p; 3903 UCHAR uc1080i; 3904 UCHAR ucReserved; 3905 UCHAR ucLetterBoxMode; 3906 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 3907 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 3908 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 3909 }ATOM_COMPONENT_VIDEO_INFO_V21; 3910 3911 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 3912 3913 /****************************************************************************/ 3914 // Structure used in object_InfoTable 3915 /****************************************************************************/ 3916 typedef struct _ATOM_OBJECT_HEADER 3917 { 3918 ATOM_COMMON_TABLE_HEADER sHeader; 3919 USHORT usDeviceSupport; 3920 USHORT usConnectorObjectTableOffset; 3921 USHORT usRouterObjectTableOffset; 3922 USHORT usEncoderObjectTableOffset; 3923 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3924 USHORT usDisplayPathTableOffset; 3925 }ATOM_OBJECT_HEADER; 3926 3927 typedef struct _ATOM_OBJECT_HEADER_V3 3928 { 3929 ATOM_COMMON_TABLE_HEADER sHeader; 3930 USHORT usDeviceSupport; 3931 USHORT usConnectorObjectTableOffset; 3932 USHORT usRouterObjectTableOffset; 3933 USHORT usEncoderObjectTableOffset; 3934 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 3935 USHORT usDisplayPathTableOffset; 3936 USHORT usMiscObjectTableOffset; 3937 }ATOM_OBJECT_HEADER_V3; 3938 3939 typedef struct _ATOM_DISPLAY_OBJECT_PATH 3940 { 3941 USHORT usDeviceTag; //supported device 3942 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3943 USHORT usConnObjectId; //Connector Object ID 3944 USHORT usGPUObjectId; //GPU ID 3945 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 3946 }ATOM_DISPLAY_OBJECT_PATH; 3947 3948 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 3949 { 3950 USHORT usDeviceTag; //supported device 3951 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 3952 USHORT usConnObjectId; //Connector Object ID 3953 USHORT usGPUObjectId; //GPU ID 3954 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 3955 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 3956 3957 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 3958 { 3959 UCHAR ucNumOfDispPath; 3960 UCHAR ucVersion; 3961 UCHAR ucPadding[2]; 3962 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 3963 }ATOM_DISPLAY_OBJECT_PATH_TABLE; 3964 3965 3966 typedef struct _ATOM_OBJECT //each object has this structure 3967 { 3968 USHORT usObjectID; 3969 USHORT usSrcDstTableOffset; 3970 USHORT usRecordOffset; //this pointing to a bunch of records defined below 3971 USHORT usReserved; 3972 }ATOM_OBJECT; 3973 3974 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 3975 { 3976 UCHAR ucNumberOfObjects; 3977 UCHAR ucPadding[3]; 3978 ATOM_OBJECT asObjects[1]; 3979 }ATOM_OBJECT_TABLE; 3980 3981 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 3982 { 3983 UCHAR ucNumberOfSrc; 3984 USHORT usSrcObjectID[1]; 3985 UCHAR ucNumberOfDst; 3986 USHORT usDstObjectID[1]; 3987 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 3988 3989 3990 //Two definitions below are for OPM on MXM module designs 3991 3992 #define EXT_HPDPIN_LUTINDEX_0 0 3993 #define EXT_HPDPIN_LUTINDEX_1 1 3994 #define EXT_HPDPIN_LUTINDEX_2 2 3995 #define EXT_HPDPIN_LUTINDEX_3 3 3996 #define EXT_HPDPIN_LUTINDEX_4 4 3997 #define EXT_HPDPIN_LUTINDEX_5 5 3998 #define EXT_HPDPIN_LUTINDEX_6 6 3999 #define EXT_HPDPIN_LUTINDEX_7 7 4000 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4001 4002 #define EXT_AUXDDC_LUTINDEX_0 0 4003 #define EXT_AUXDDC_LUTINDEX_1 1 4004 #define EXT_AUXDDC_LUTINDEX_2 2 4005 #define EXT_AUXDDC_LUTINDEX_3 3 4006 #define EXT_AUXDDC_LUTINDEX_4 4 4007 #define EXT_AUXDDC_LUTINDEX_5 5 4008 #define EXT_AUXDDC_LUTINDEX_6 6 4009 #define EXT_AUXDDC_LUTINDEX_7 7 4010 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4011 4012 //ucChannelMapping are defined as following 4013 //for DP connector, eDP, DP to VGA/LVDS 4014 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4015 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4016 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4017 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4018 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4019 { 4020 #if ATOM_BIG_ENDIAN 4021 UCHAR ucDP_Lane3_Source:2; 4022 UCHAR ucDP_Lane2_Source:2; 4023 UCHAR ucDP_Lane1_Source:2; 4024 UCHAR ucDP_Lane0_Source:2; 4025 #else 4026 UCHAR ucDP_Lane0_Source:2; 4027 UCHAR ucDP_Lane1_Source:2; 4028 UCHAR ucDP_Lane2_Source:2; 4029 UCHAR ucDP_Lane3_Source:2; 4030 #endif 4031 }ATOM_DP_CONN_CHANNEL_MAPPING; 4032 4033 //for DVI/HDMI, in dual link case, both links have to have same mapping. 4034 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4035 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4036 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4037 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4038 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4039 { 4040 #if ATOM_BIG_ENDIAN 4041 UCHAR ucDVI_CLK_Source:2; 4042 UCHAR ucDVI_DATA0_Source:2; 4043 UCHAR ucDVI_DATA1_Source:2; 4044 UCHAR ucDVI_DATA2_Source:2; 4045 #else 4046 UCHAR ucDVI_DATA2_Source:2; 4047 UCHAR ucDVI_DATA1_Source:2; 4048 UCHAR ucDVI_DATA0_Source:2; 4049 UCHAR ucDVI_CLK_Source:2; 4050 #endif 4051 }ATOM_DVI_CONN_CHANNEL_MAPPING; 4052 4053 typedef struct _EXT_DISPLAY_PATH 4054 { 4055 USHORT usDeviceTag; //A bit vector to show what devices are supported 4056 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4057 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4058 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4059 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4060 USHORT usExtEncoderObjId; //external encoder object id 4061 union{ 4062 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4063 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4064 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4065 }; 4066 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4067 USHORT usCaps; 4068 USHORT usReserved; 4069 }EXT_DISPLAY_PATH; 4070 4071 #define NUMBER_OF_UCHAR_FOR_GUID 16 4072 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4073 4074 //usCaps 4075 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4076 4077 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4078 { 4079 ATOM_COMMON_TABLE_HEADER sHeader; 4080 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4081 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4082 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4083 UCHAR uc3DStereoPinId; // use for eDP panel 4084 UCHAR ucRemoteDisplayConfig; 4085 UCHAR uceDPToLVDSRxId; 4086 UCHAR Reserved[4]; // for potential expansion 4087 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4088 4089 //Related definitions, all records are different but they have a commond header 4090 typedef struct _ATOM_COMMON_RECORD_HEADER 4091 { 4092 UCHAR ucRecordType; //An emun to indicate the record type 4093 UCHAR ucRecordSize; //The size of the whole record in byte 4094 }ATOM_COMMON_RECORD_HEADER; 4095 4096 4097 #define ATOM_I2C_RECORD_TYPE 1 4098 #define ATOM_HPD_INT_RECORD_TYPE 2 4099 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4100 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4101 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4102 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4103 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4104 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4105 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4106 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4107 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4108 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4109 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4110 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4111 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4112 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4113 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4114 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4115 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4116 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4117 4118 4119 //Must be updated when new record type is added,equal to that record definition! 4120 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4121 4122 typedef struct _ATOM_I2C_RECORD 4123 { 4124 ATOM_COMMON_RECORD_HEADER sheader; 4125 ATOM_I2C_ID_CONFIG sucI2cId; 4126 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4127 }ATOM_I2C_RECORD; 4128 4129 typedef struct _ATOM_HPD_INT_RECORD 4130 { 4131 ATOM_COMMON_RECORD_HEADER sheader; 4132 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4133 UCHAR ucPlugged_PinState; 4134 }ATOM_HPD_INT_RECORD; 4135 4136 4137 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4138 { 4139 ATOM_COMMON_RECORD_HEADER sheader; 4140 UCHAR ucProtectionFlag; 4141 UCHAR ucReserved; 4142 }ATOM_OUTPUT_PROTECTION_RECORD; 4143 4144 typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4145 { 4146 ULONG ulACPIDeviceEnum; //Reserved for now 4147 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4148 USHORT usPadding; 4149 }ATOM_CONNECTOR_DEVICE_TAG; 4150 4151 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4152 { 4153 ATOM_COMMON_RECORD_HEADER sheader; 4154 UCHAR ucNumberOfDevice; 4155 UCHAR ucReserved; 4156 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4157 }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4158 4159 4160 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4161 { 4162 ATOM_COMMON_RECORD_HEADER sheader; 4163 UCHAR ucConfigGPIOID; 4164 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4165 UCHAR ucFlowinGPIPID; 4166 UCHAR ucExtInGPIPID; 4167 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4168 4169 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4170 { 4171 ATOM_COMMON_RECORD_HEADER sheader; 4172 UCHAR ucCTL1GPIO_ID; 4173 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4174 UCHAR ucCTL2GPIO_ID; 4175 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4176 UCHAR ucCTL3GPIO_ID; 4177 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4178 UCHAR ucCTLFPGA_IN_ID; 4179 UCHAR ucPadding[3]; 4180 }ATOM_ENCODER_FPGA_CONTROL_RECORD; 4181 4182 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4183 { 4184 ATOM_COMMON_RECORD_HEADER sheader; 4185 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4186 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4187 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4188 4189 typedef struct _ATOM_JTAG_RECORD 4190 { 4191 ATOM_COMMON_RECORD_HEADER sheader; 4192 UCHAR ucTMSGPIO_ID; 4193 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4194 UCHAR ucTCKGPIO_ID; 4195 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4196 UCHAR ucTDOGPIO_ID; 4197 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4198 UCHAR ucTDIGPIO_ID; 4199 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4200 UCHAR ucPadding[2]; 4201 }ATOM_JTAG_RECORD; 4202 4203 4204 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4205 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4206 { 4207 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4208 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4209 }ATOM_GPIO_PIN_CONTROL_PAIR; 4210 4211 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4212 { 4213 ATOM_COMMON_RECORD_HEADER sheader; 4214 UCHAR ucFlags; // Future expnadibility 4215 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4216 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4217 }ATOM_OBJECT_GPIO_CNTL_RECORD; 4218 4219 //Definitions for GPIO pin state 4220 #define GPIO_PIN_TYPE_INPUT 0x00 4221 #define GPIO_PIN_TYPE_OUTPUT 0x10 4222 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 4223 4224 //For GPIO_PIN_TYPE_OUTPUT the following is defined 4225 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4226 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4227 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4228 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4229 4230 // Indexes to GPIO array in GLSync record 4231 // GLSync record is for Frame Lock/Gen Lock feature. 4232 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4233 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4234 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4235 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4236 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4237 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4238 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4239 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4240 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4241 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4242 4243 typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4244 { 4245 ATOM_COMMON_RECORD_HEADER sheader; 4246 ULONG ulStrengthControl; // DVOA strength control for CF 4247 UCHAR ucPadding[2]; 4248 }ATOM_ENCODER_DVO_CF_RECORD; 4249 4250 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4251 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4252 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4253 4254 typedef struct _ATOM_ENCODER_CAP_RECORD 4255 { 4256 ATOM_COMMON_RECORD_HEADER sheader; 4257 union { 4258 USHORT usEncoderCap; 4259 struct { 4260 #if ATOM_BIG_ENDIAN 4261 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4262 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4263 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4264 #else 4265 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4266 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4267 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4268 #endif 4269 }; 4270 }; 4271 }ATOM_ENCODER_CAP_RECORD; 4272 4273 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4274 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4275 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4276 4277 typedef struct _ATOM_CONNECTOR_CF_RECORD 4278 { 4279 ATOM_COMMON_RECORD_HEADER sheader; 4280 USHORT usMaxPixClk; 4281 UCHAR ucFlowCntlGpioId; 4282 UCHAR ucSwapCntlGpioId; 4283 UCHAR ucConnectedDvoBundle; 4284 UCHAR ucPadding; 4285 }ATOM_CONNECTOR_CF_RECORD; 4286 4287 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4288 { 4289 ATOM_COMMON_RECORD_HEADER sheader; 4290 ATOM_DTD_FORMAT asTiming; 4291 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4292 4293 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4294 { 4295 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4296 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4297 UCHAR ucReserved; 4298 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4299 4300 4301 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4302 { 4303 ATOM_COMMON_RECORD_HEADER sheader; 4304 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4305 UCHAR ucMuxControlPin; 4306 UCHAR ucMuxState[2]; //for alligment purpose 4307 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4308 4309 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4310 { 4311 ATOM_COMMON_RECORD_HEADER sheader; 4312 UCHAR ucMuxType; 4313 UCHAR ucMuxControlPin; 4314 UCHAR ucMuxState[2]; //for alligment purpose 4315 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4316 4317 // define ucMuxType 4318 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4319 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4320 4321 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4322 { 4323 ATOM_COMMON_RECORD_HEADER sheader; 4324 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4325 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4326 4327 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4328 { 4329 ATOM_COMMON_RECORD_HEADER sheader; 4330 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4331 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4332 4333 typedef struct _ATOM_OBJECT_LINK_RECORD 4334 { 4335 ATOM_COMMON_RECORD_HEADER sheader; 4336 USHORT usObjectID; //could be connector, encorder or other object in object.h 4337 }ATOM_OBJECT_LINK_RECORD; 4338 4339 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4340 { 4341 ATOM_COMMON_RECORD_HEADER sheader; 4342 USHORT usReserved; 4343 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4344 4345 /****************************************************************************/ 4346 // ASIC voltage data table 4347 /****************************************************************************/ 4348 typedef struct _ATOM_VOLTAGE_INFO_HEADER 4349 { 4350 USHORT usVDDCBaseLevel; //In number of 50mv unit 4351 USHORT usReserved; //For possible extension table offset 4352 UCHAR ucNumOfVoltageEntries; 4353 UCHAR ucBytesPerVoltageEntry; 4354 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4355 UCHAR ucDefaultVoltageEntry; 4356 UCHAR ucVoltageControlI2cLine; 4357 UCHAR ucVoltageControlAddress; 4358 UCHAR ucVoltageControlOffset; 4359 }ATOM_VOLTAGE_INFO_HEADER; 4360 4361 typedef struct _ATOM_VOLTAGE_INFO 4362 { 4363 ATOM_COMMON_TABLE_HEADER sHeader; 4364 ATOM_VOLTAGE_INFO_HEADER viHeader; 4365 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4366 }ATOM_VOLTAGE_INFO; 4367 4368 4369 typedef struct _ATOM_VOLTAGE_FORMULA 4370 { 4371 USHORT usVoltageBaseLevel; // In number of 1mv unit 4372 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4373 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4374 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4375 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4376 UCHAR ucReserved; 4377 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4378 }ATOM_VOLTAGE_FORMULA; 4379 4380 typedef struct _VOLTAGE_LUT_ENTRY 4381 { 4382 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4383 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4384 }VOLTAGE_LUT_ENTRY; 4385 4386 typedef struct _ATOM_VOLTAGE_FORMULA_V2 4387 { 4388 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4389 UCHAR ucReserved[3]; 4390 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4391 }ATOM_VOLTAGE_FORMULA_V2; 4392 4393 typedef struct _ATOM_VOLTAGE_CONTROL 4394 { 4395 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4396 UCHAR ucVoltageControlI2cLine; 4397 UCHAR ucVoltageControlAddress; 4398 UCHAR ucVoltageControlOffset; 4399 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4400 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4401 UCHAR ucReserved; 4402 }ATOM_VOLTAGE_CONTROL; 4403 4404 // Define ucVoltageControlId 4405 #define VOLTAGE_CONTROLLED_BY_HW 0x00 4406 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4407 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4408 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4409 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4410 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4411 #define VOLTAGE_CONTROL_ID_DS4402 0x04 4412 #define VOLTAGE_CONTROL_ID_UP6266 0x05 4413 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4414 #define VOLTAGE_CONTROL_ID_VT1556M 0x07 4415 #define VOLTAGE_CONTROL_ID_CHL822x 0x08 4416 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 4417 #define VOLTAGE_CONTROL_ID_UP1637 0x0A 4418 4419 typedef struct _ATOM_VOLTAGE_OBJECT 4420 { 4421 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4422 UCHAR ucSize; //Size of Object 4423 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4424 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4425 }ATOM_VOLTAGE_OBJECT; 4426 4427 typedef struct _ATOM_VOLTAGE_OBJECT_V2 4428 { 4429 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4430 UCHAR ucSize; //Size of Object 4431 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4432 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4433 }ATOM_VOLTAGE_OBJECT_V2; 4434 4435 typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4436 { 4437 ATOM_COMMON_TABLE_HEADER sHeader; 4438 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4439 }ATOM_VOLTAGE_OBJECT_INFO; 4440 4441 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4442 { 4443 ATOM_COMMON_TABLE_HEADER sHeader; 4444 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4445 }ATOM_VOLTAGE_OBJECT_INFO_V2; 4446 4447 typedef struct _ATOM_LEAKID_VOLTAGE 4448 { 4449 UCHAR ucLeakageId; 4450 UCHAR ucReserved; 4451 USHORT usVoltage; 4452 }ATOM_LEAKID_VOLTAGE; 4453 4454 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4455 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4456 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4457 USHORT usSize; //Size of Object 4458 }ATOM_VOLTAGE_OBJECT_HEADER_V3; 4459 4460 typedef struct _VOLTAGE_LUT_ENTRY_V2 4461 { 4462 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4463 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4464 }VOLTAGE_LUT_ENTRY_V2; 4465 4466 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4467 { 4468 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4469 USHORT usVoltageId; 4470 USHORT usLeakageId; // The corresponding Voltage Value, in mV 4471 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4472 4473 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4474 { 4475 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4476 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4477 UCHAR ucVoltageControlI2cLine; 4478 UCHAR ucVoltageControlAddress; 4479 UCHAR ucVoltageControlOffset; 4480 ULONG ulReserved; 4481 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4482 }ATOM_I2C_VOLTAGE_OBJECT_V3; 4483 4484 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4485 { 4486 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4487 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4488 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4489 UCHAR ucPhaseDelay; // phase delay in unit of micro second 4490 UCHAR ucReserved; 4491 ULONG ulGpioMaskVal; // GPIO Mask value 4492 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 4493 }ATOM_GPIO_VOLTAGE_OBJECT_V3; 4494 4495 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4496 { 4497 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; 4498 UCHAR ucLeakageCntlId; // default is 0 4499 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4500 UCHAR ucReserved[2]; 4501 ULONG ulMaxVoltageLevel; 4502 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 4503 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4504 4505 typedef union _ATOM_VOLTAGE_OBJECT_V3{ 4506 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4507 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4508 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4509 }ATOM_VOLTAGE_OBJECT_V3; 4510 4511 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4512 { 4513 ATOM_COMMON_TABLE_HEADER sHeader; 4514 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4515 }ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4516 4517 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4518 { 4519 UCHAR ucProfileId; 4520 UCHAR ucReserved; 4521 USHORT usSize; 4522 USHORT usEfuseSpareStartAddr; 4523 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4524 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4525 }ATOM_ASIC_PROFILE_VOLTAGE; 4526 4527 //ucProfileId 4528 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4529 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4530 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4531 4532 typedef struct _ATOM_ASIC_PROFILING_INFO 4533 { 4534 ATOM_COMMON_TABLE_HEADER asHeader; 4535 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4536 }ATOM_ASIC_PROFILING_INFO; 4537 4538 typedef struct _ATOM_POWER_SOURCE_OBJECT 4539 { 4540 UCHAR ucPwrSrcId; // Power source 4541 UCHAR ucPwrSensorType; // GPIO, I2C or none 4542 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4543 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4544 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 4545 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 4546 UCHAR ucPwrSensActiveState; // high active or low active 4547 UCHAR ucReserve[3]; // reserve 4548 USHORT usSensPwr; // in unit of watt 4549 }ATOM_POWER_SOURCE_OBJECT; 4550 4551 typedef struct _ATOM_POWER_SOURCE_INFO 4552 { 4553 ATOM_COMMON_TABLE_HEADER asHeader; 4554 UCHAR asPwrbehave[16]; 4555 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 4556 }ATOM_POWER_SOURCE_INFO; 4557 4558 4559 //Define ucPwrSrcId 4560 #define POWERSOURCE_PCIE_ID1 0x00 4561 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 4562 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 4563 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 4564 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 4565 4566 //define ucPwrSensorId 4567 #define POWER_SENSOR_ALWAYS 0x00 4568 #define POWER_SENSOR_GPIO 0x01 4569 #define POWER_SENSOR_I2C 0x02 4570 4571 typedef struct _ATOM_CLK_VOLT_CAPABILITY 4572 { 4573 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 4574 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4575 }ATOM_CLK_VOLT_CAPABILITY; 4576 4577 typedef struct _ATOM_AVAILABLE_SCLK_LIST 4578 { 4579 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 4580 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 4581 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 4582 }ATOM_AVAILABLE_SCLK_LIST; 4583 4584 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 4585 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 4586 4587 // this IntegrateSystemInfoTable is used for Liano/Ontario APU 4588 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 4589 { 4590 ATOM_COMMON_TABLE_HEADER sHeader; 4591 ULONG ulBootUpEngineClock; 4592 ULONG ulDentistVCOFreq; 4593 ULONG ulBootUpUMAClock; 4594 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4595 ULONG ulBootUpReqDisplayVector; 4596 ULONG ulOtherDisplayMisc; 4597 ULONG ulGPUCapInfo; 4598 ULONG ulSB_MMIO_Base_Addr; 4599 USHORT usRequestedPWMFreqInHz; 4600 UCHAR ucHtcTmpLmt; 4601 UCHAR ucHtcHystLmt; 4602 ULONG ulMinEngineClock; 4603 ULONG ulSystemConfig; 4604 ULONG ulCPUCapInfo; 4605 USHORT usNBP0Voltage; 4606 USHORT usNBP1Voltage; 4607 USHORT usBootUpNBVoltage; 4608 USHORT usExtDispConnInfoOffset; 4609 USHORT usPanelRefreshRateRange; 4610 UCHAR ucMemoryType; 4611 UCHAR ucUMAChannelNumber; 4612 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 4613 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 4614 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 4615 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4616 ULONG ulGMCRestoreResetTime; 4617 ULONG ulMinimumNClk; 4618 ULONG ulIdleNClk; 4619 ULONG ulDDR_DLL_PowerUpTime; 4620 ULONG ulDDR_PLL_PowerUpTime; 4621 USHORT usPCIEClkSSPercentage; 4622 USHORT usPCIEClkSSType; 4623 USHORT usLvdsSSPercentage; 4624 USHORT usLvdsSSpreadRateIn10Hz; 4625 USHORT usHDMISSPercentage; 4626 USHORT usHDMISSpreadRateIn10Hz; 4627 USHORT usDVISSPercentage; 4628 USHORT usDVISSpreadRateIn10Hz; 4629 ULONG SclkDpmBoostMargin; 4630 ULONG SclkDpmThrottleMargin; 4631 USHORT SclkDpmTdpLimitPG; 4632 USHORT SclkDpmTdpLimitBoost; 4633 ULONG ulBoostEngineCLock; 4634 UCHAR ulBoostVid_2bit; 4635 UCHAR EnableBoost; 4636 USHORT GnbTdpLimit; 4637 USHORT usMaxLVDSPclkFreqInSingleLink; 4638 UCHAR ucLvdsMisc; 4639 UCHAR ucLVDSReserved; 4640 ULONG ulReserved3[15]; 4641 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4642 }ATOM_INTEGRATED_SYSTEM_INFO_V6; 4643 4644 // ulGPUCapInfo 4645 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4646 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 4647 4648 //ucLVDSMisc: 4649 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 4650 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 4651 #define SYS_INFO_LVDSMISC__888_BPC 0x04 4652 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 4653 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 4654 4655 // not used any more 4656 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 4657 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 4658 4659 /********************************************************************************************************************** 4660 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 4661 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4662 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4663 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4664 sDISPCLK_Voltage: Report Display clock voltage requirement. 4665 4666 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 4667 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4668 ATOM_DEVICE_CRT2_SUPPORT 0x0010 4669 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4670 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4671 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4672 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4673 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4674 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4675 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4676 ulOtherDisplayMisc: Other display related flags, not defined yet. 4677 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4678 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4679 bit[3]=0: Enable HW AUX mode detection logic 4680 =1: Disable HW AUX mode dettion logic 4681 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4682 4683 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4684 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4685 4686 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4687 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4688 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4689 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4690 and enabling VariBri under the driver environment from PP table is optional. 4691 4692 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4693 that BL control from GPU is expected. 4694 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4695 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4696 it's per platform 4697 and enabling VariBri under the driver environment from PP table is optional. 4698 4699 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4700 Threshold on value to enter HTC_active state. 4701 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4702 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4703 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4704 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4705 =1: PCIE Power Gating Enabled 4706 Bit[1]=0: DDR-DLL shut-down feature disabled. 4707 1: DDR-DLL shut-down feature enabled. 4708 Bit[2]=0: DDR-PLL Power down feature disabled. 4709 1: DDR-PLL Power down feature enabled. 4710 ulCPUCapInfo: TBD 4711 usNBP0Voltage: VID for voltage on NB P0 State 4712 usNBP1Voltage: VID for voltage on NB P1 State 4713 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4714 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4715 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4716 to indicate a range. 4717 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4718 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4719 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4720 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4721 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4722 ucUMAChannelNumber: System memory channel numbers. 4723 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4724 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4725 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4726 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4727 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4728 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4729 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4730 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4731 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4732 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 4733 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4734 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4735 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4736 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4737 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4738 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4739 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4740 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4741 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4742 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4743 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4744 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4745 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4746 **********************************************************************************************************************/ 4747 4748 // this Table is used for Liano/Ontario APU 4749 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 4750 { 4751 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 4752 ULONG ulPowerplayTable[128]; 4753 }ATOM_FUSION_SYSTEM_INFO_V1; 4754 /********************************************************************************************************************** 4755 ATOM_FUSION_SYSTEM_INFO_V1 Description 4756 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 4757 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 4758 **********************************************************************************************************************/ 4759 4760 // this IntegrateSystemInfoTable is used for Trinity APU 4761 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 4762 { 4763 ATOM_COMMON_TABLE_HEADER sHeader; 4764 ULONG ulBootUpEngineClock; 4765 ULONG ulDentistVCOFreq; 4766 ULONG ulBootUpUMAClock; 4767 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 4768 ULONG ulBootUpReqDisplayVector; 4769 ULONG ulOtherDisplayMisc; 4770 ULONG ulGPUCapInfo; 4771 ULONG ulSB_MMIO_Base_Addr; 4772 USHORT usRequestedPWMFreqInHz; 4773 UCHAR ucHtcTmpLmt; 4774 UCHAR ucHtcHystLmt; 4775 ULONG ulMinEngineClock; 4776 ULONG ulSystemConfig; 4777 ULONG ulCPUCapInfo; 4778 USHORT usNBP0Voltage; 4779 USHORT usNBP1Voltage; 4780 USHORT usBootUpNBVoltage; 4781 USHORT usExtDispConnInfoOffset; 4782 USHORT usPanelRefreshRateRange; 4783 UCHAR ucMemoryType; 4784 UCHAR ucUMAChannelNumber; 4785 UCHAR strVBIOSMsg[40]; 4786 ULONG ulReserved[20]; 4787 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 4788 ULONG ulGMCRestoreResetTime; 4789 ULONG ulMinimumNClk; 4790 ULONG ulIdleNClk; 4791 ULONG ulDDR_DLL_PowerUpTime; 4792 ULONG ulDDR_PLL_PowerUpTime; 4793 USHORT usPCIEClkSSPercentage; 4794 USHORT usPCIEClkSSType; 4795 USHORT usLvdsSSPercentage; 4796 USHORT usLvdsSSpreadRateIn10Hz; 4797 USHORT usHDMISSPercentage; 4798 USHORT usHDMISSpreadRateIn10Hz; 4799 USHORT usDVISSPercentage; 4800 USHORT usDVISSpreadRateIn10Hz; 4801 ULONG SclkDpmBoostMargin; 4802 ULONG SclkDpmThrottleMargin; 4803 USHORT SclkDpmTdpLimitPG; 4804 USHORT SclkDpmTdpLimitBoost; 4805 ULONG ulBoostEngineCLock; 4806 UCHAR ulBoostVid_2bit; 4807 UCHAR EnableBoost; 4808 USHORT GnbTdpLimit; 4809 USHORT usMaxLVDSPclkFreqInSingleLink; 4810 UCHAR ucLvdsMisc; 4811 UCHAR ucLVDSReserved; 4812 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 4813 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 4814 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 4815 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 4816 UCHAR ucLVDSOffToOnDelay_in4Ms; 4817 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 4818 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 4819 UCHAR ucLVDSReserved1; 4820 ULONG ulLCDBitDepthControlVal; 4821 ULONG ulNbpStateMemclkFreq[4]; 4822 USHORT usNBP2Voltage; 4823 USHORT usNBP3Voltage; 4824 ULONG ulNbpStateNClkFreq[4]; 4825 UCHAR ucNBDPMEnable; 4826 UCHAR ucReserved[3]; 4827 UCHAR ucDPMState0VclkFid; 4828 UCHAR ucDPMState0DclkFid; 4829 UCHAR ucDPMState1VclkFid; 4830 UCHAR ucDPMState1DclkFid; 4831 UCHAR ucDPMState2VclkFid; 4832 UCHAR ucDPMState2DclkFid; 4833 UCHAR ucDPMState3VclkFid; 4834 UCHAR ucDPMState3DclkFid; 4835 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 4836 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 4837 4838 // ulOtherDisplayMisc 4839 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 4840 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 4841 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 4842 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 4843 4844 // ulGPUCapInfo 4845 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 4846 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 4847 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 4848 4849 /********************************************************************************************************************** 4850 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 4851 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 4852 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 4853 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 4854 sDISPCLK_Voltage: Report Display clock voltage requirement. 4855 4856 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 4857 ATOM_DEVICE_CRT1_SUPPORT 0x0001 4858 ATOM_DEVICE_DFP1_SUPPORT 0x0008 4859 ATOM_DEVICE_DFP6_SUPPORT 0x0040 4860 ATOM_DEVICE_DFP2_SUPPORT 0x0080 4861 ATOM_DEVICE_DFP3_SUPPORT 0x0200 4862 ATOM_DEVICE_DFP4_SUPPORT 0x0400 4863 ATOM_DEVICE_DFP5_SUPPORT 0x0800 4864 ATOM_DEVICE_LCD1_SUPPORT 0x0002 4865 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 4866 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 4867 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 4868 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 4869 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 4870 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 4871 bit[3]=0: VBIOS fast boot is disable 4872 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 4873 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 4874 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 4875 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 4876 =1: DP mode use single PLL mode 4877 bit[3]=0: Enable AUX HW mode detection logic 4878 =1: Disable AUX HW mode detection logic 4879 4880 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 4881 4882 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 4883 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 4884 4885 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 4886 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 4887 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 4888 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 4889 and enabling VariBri under the driver environment from PP table is optional. 4890 4891 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 4892 that BL control from GPU is expected. 4893 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 4894 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 4895 it's per platform 4896 and enabling VariBri under the driver environment from PP table is optional. 4897 4898 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 4899 Threshold on value to enter HTC_active state. 4900 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 4901 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 4902 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 4903 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 4904 =1: PCIE Power Gating Enabled 4905 Bit[1]=0: DDR-DLL shut-down feature disabled. 4906 1: DDR-DLL shut-down feature enabled. 4907 Bit[2]=0: DDR-PLL Power down feature disabled. 4908 1: DDR-PLL Power down feature enabled. 4909 ulCPUCapInfo: TBD 4910 usNBP0Voltage: VID for voltage on NB P0 State 4911 usNBP1Voltage: VID for voltage on NB P1 State 4912 usNBP2Voltage: VID for voltage on NB P2 State 4913 usNBP3Voltage: VID for voltage on NB P3 State 4914 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 4915 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 4916 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 4917 to indicate a range. 4918 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 4919 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 4920 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 4921 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 4922 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 4923 ucUMAChannelNumber: System memory channel numbers. 4924 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 4925 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 4926 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 4927 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 4928 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 4929 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 4930 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 4931 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 4932 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 4933 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 4934 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 4935 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 4936 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4937 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4938 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4939 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 4940 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 4941 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 4942 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 4943 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 4944 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 4945 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 4946 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 4947 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 4948 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 4949 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4950 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 4951 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 4952 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4953 4954 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 4955 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 4956 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4957 4958 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 4959 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 4960 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4961 4962 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 4963 =0 means to use VBIOS default delay which is 125 ( 500ms ). 4964 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4965 4966 ucLVDSPwrOnVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 4967 =0 means to use VBIOS default delay which is 0 ( 0ms ). 4968 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4969 4970 ucLVDSPwrOffBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 4971 =0 means to use VBIOS default delay which is 0 ( 0ms ). 4972 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 4973 4974 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 4975 4976 **********************************************************************************************************************/ 4977 4978 /**************************************************************************/ 4979 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 4980 //Memory SS Info Table 4981 //Define Memory Clock SS chip ID 4982 #define ICS91719 1 4983 #define ICS91720 2 4984 4985 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 4986 typedef struct _ATOM_I2C_DATA_RECORD 4987 { 4988 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 4989 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 4990 }ATOM_I2C_DATA_RECORD; 4991 4992 4993 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 4994 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 4995 { 4996 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 4997 UCHAR ucSSChipID; //SS chip being used 4998 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 4999 UCHAR ucNumOfI2CDataRecords; //number of data block 5000 ATOM_I2C_DATA_RECORD asI2CData[1]; 5001 }ATOM_I2C_DEVICE_SETUP_INFO; 5002 5003 //========================================================================================== 5004 typedef struct _ATOM_ASIC_MVDD_INFO 5005 { 5006 ATOM_COMMON_TABLE_HEADER sHeader; 5007 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 5008 }ATOM_ASIC_MVDD_INFO; 5009 5010 //========================================================================================== 5011 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5012 5013 //========================================================================================== 5014 /**************************************************************************/ 5015 5016 typedef struct _ATOM_ASIC_SS_ASSIGNMENT 5017 { 5018 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5019 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5020 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5021 UCHAR ucClockIndication; //Indicate which clock source needs SS 5022 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5023 UCHAR ucReserved[2]; 5024 }ATOM_ASIC_SS_ASSIGNMENT; 5025 5026 //Define ucClockIndication, SW uses the IDs below to search if the SS is required/enabled on a clock branch/signal type. 5027 //SS is not required or enabled if a match is not found. 5028 #define ASIC_INTERNAL_MEMORY_SS 1 5029 #define ASIC_INTERNAL_ENGINE_SS 2 5030 #define ASIC_INTERNAL_UVD_SS 3 5031 #define ASIC_INTERNAL_SS_ON_TMDS 4 5032 #define ASIC_INTERNAL_SS_ON_HDMI 5 5033 #define ASIC_INTERNAL_SS_ON_LVDS 6 5034 #define ASIC_INTERNAL_SS_ON_DP 7 5035 #define ASIC_INTERNAL_SS_ON_DCPLL 8 5036 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5037 #define ASIC_INTERNAL_VCE_SS 10 5038 5039 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5040 { 5041 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5042 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5043 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5044 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5045 UCHAR ucClockIndication; //Indicate which clock source needs SS 5046 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5047 UCHAR ucReserved[2]; 5048 }ATOM_ASIC_SS_ASSIGNMENT_V2; 5049 5050 //ucSpreadSpectrumMode 5051 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 5052 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 5053 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 5054 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 5055 //#define ATOM_INTERNAL_SS_MASK 0x00000000 5056 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 5057 5058 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 5059 { 5060 ATOM_COMMON_TABLE_HEADER sHeader; 5061 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 5062 }ATOM_ASIC_INTERNAL_SS_INFO; 5063 5064 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 5065 { 5066 ATOM_COMMON_TABLE_HEADER sHeader; 5067 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 5068 }ATOM_ASIC_INTERNAL_SS_INFO_V2; 5069 5070 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 5071 { 5072 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5073 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5074 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5075 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5076 UCHAR ucClockIndication; //Indicate which clock source needs SS 5077 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5078 UCHAR ucReserved[2]; 5079 }ATOM_ASIC_SS_ASSIGNMENT_V3; 5080 5081 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 5082 { 5083 ATOM_COMMON_TABLE_HEADER sHeader; 5084 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 5085 }ATOM_ASIC_INTERNAL_SS_INFO_V3; 5086 5087 5088 //==============================Scratch Pad Definition Portion=============================== 5089 #define ATOM_DEVICE_CONNECT_INFO_DEF 0 5090 #define ATOM_ROM_LOCATION_DEF 1 5091 #define ATOM_TV_STANDARD_DEF 2 5092 #define ATOM_ACTIVE_INFO_DEF 3 5093 #define ATOM_LCD_INFO_DEF 4 5094 #define ATOM_DOS_REQ_INFO_DEF 5 5095 #define ATOM_ACC_CHANGE_INFO_DEF 6 5096 #define ATOM_DOS_MODE_INFO_DEF 7 5097 #define ATOM_I2C_CHANNEL_STATUS_DEF 8 5098 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 5099 #define ATOM_INTERNAL_TIMER_DEF 10 5100 5101 // BIOS_0_SCRATCH Definition 5102 #define ATOM_S0_CRT1_MONO 0x00000001L 5103 #define ATOM_S0_CRT1_COLOR 0x00000002L 5104 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 5105 5106 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 5107 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 5108 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 5109 5110 #define ATOM_S0_CV_A 0x00000010L 5111 #define ATOM_S0_CV_DIN_A 0x00000020L 5112 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 5113 5114 5115 #define ATOM_S0_CRT2_MONO 0x00000100L 5116 #define ATOM_S0_CRT2_COLOR 0x00000200L 5117 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 5118 5119 #define ATOM_S0_TV1_COMPOSITE 0x00000400L 5120 #define ATOM_S0_TV1_SVIDEO 0x00000800L 5121 #define ATOM_S0_TV1_SCART 0x00004000L 5122 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 5123 5124 #define ATOM_S0_CV 0x00001000L 5125 #define ATOM_S0_CV_DIN 0x00002000L 5126 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 5127 5128 #define ATOM_S0_DFP1 0x00010000L 5129 #define ATOM_S0_DFP2 0x00020000L 5130 #define ATOM_S0_LCD1 0x00040000L 5131 #define ATOM_S0_LCD2 0x00080000L 5132 #define ATOM_S0_DFP6 0x00100000L 5133 #define ATOM_S0_DFP3 0x00200000L 5134 #define ATOM_S0_DFP4 0x00400000L 5135 #define ATOM_S0_DFP5 0x00800000L 5136 5137 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 5138 5139 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 5140 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 5141 5142 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 5143 #define ATOM_S0_THERMAL_STATE_SHIFT 26 5144 5145 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 5146 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 5147 5148 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 5149 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 5150 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 5151 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 5152 5153 //Byte aligned definition for BIOS usage 5154 #define ATOM_S0_CRT1_MONOb0 0x01 5155 #define ATOM_S0_CRT1_COLORb0 0x02 5156 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 5157 5158 #define ATOM_S0_TV1_COMPOSITEb0 0x04 5159 #define ATOM_S0_TV1_SVIDEOb0 0x08 5160 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 5161 5162 #define ATOM_S0_CVb0 0x10 5163 #define ATOM_S0_CV_DINb0 0x20 5164 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 5165 5166 #define ATOM_S0_CRT2_MONOb1 0x01 5167 #define ATOM_S0_CRT2_COLORb1 0x02 5168 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 5169 5170 #define ATOM_S0_TV1_COMPOSITEb1 0x04 5171 #define ATOM_S0_TV1_SVIDEOb1 0x08 5172 #define ATOM_S0_TV1_SCARTb1 0x40 5173 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 5174 5175 #define ATOM_S0_CVb1 0x10 5176 #define ATOM_S0_CV_DINb1 0x20 5177 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 5178 5179 #define ATOM_S0_DFP1b2 0x01 5180 #define ATOM_S0_DFP2b2 0x02 5181 #define ATOM_S0_LCD1b2 0x04 5182 #define ATOM_S0_LCD2b2 0x08 5183 #define ATOM_S0_DFP6b2 0x10 5184 #define ATOM_S0_DFP3b2 0x20 5185 #define ATOM_S0_DFP4b2 0x40 5186 #define ATOM_S0_DFP5b2 0x80 5187 5188 5189 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 5190 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 5191 5192 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 5193 #define ATOM_S0_LCD1_SHIFT 18 5194 5195 // BIOS_1_SCRATCH Definition 5196 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 5197 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 5198 5199 // BIOS_2_SCRATCH Definition 5200 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 5201 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 5202 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 5203 5204 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 5205 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 5206 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 5207 5208 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 5209 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 5210 5211 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 5212 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 5213 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 5214 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 5215 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 5216 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 5217 5218 5219 //Byte aligned definition for BIOS usage 5220 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 5221 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 5222 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 5223 5224 #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF 5225 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C 5226 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 5227 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 5228 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 5229 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 5230 5231 5232 // BIOS_3_SCRATCH Definition 5233 #define ATOM_S3_CRT1_ACTIVE 0x00000001L 5234 #define ATOM_S3_LCD1_ACTIVE 0x00000002L 5235 #define ATOM_S3_TV1_ACTIVE 0x00000004L 5236 #define ATOM_S3_DFP1_ACTIVE 0x00000008L 5237 #define ATOM_S3_CRT2_ACTIVE 0x00000010L 5238 #define ATOM_S3_LCD2_ACTIVE 0x00000020L 5239 #define ATOM_S3_DFP6_ACTIVE 0x00000040L 5240 #define ATOM_S3_DFP2_ACTIVE 0x00000080L 5241 #define ATOM_S3_CV_ACTIVE 0x00000100L 5242 #define ATOM_S3_DFP3_ACTIVE 0x00000200L 5243 #define ATOM_S3_DFP4_ACTIVE 0x00000400L 5244 #define ATOM_S3_DFP5_ACTIVE 0x00000800L 5245 5246 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 5247 5248 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 5249 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 5250 5251 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 5252 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 5253 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 5254 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 5255 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 5256 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 5257 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 5258 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 5259 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 5260 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 5261 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 5262 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 5263 5264 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 5265 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 5266 //Below two definitions are not supported in pplib, but in the old powerplay in DAL 5267 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 5268 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 5269 5270 //Byte aligned definition for BIOS usage 5271 #define ATOM_S3_CRT1_ACTIVEb0 0x01 5272 #define ATOM_S3_LCD1_ACTIVEb0 0x02 5273 #define ATOM_S3_TV1_ACTIVEb0 0x04 5274 #define ATOM_S3_DFP1_ACTIVEb0 0x08 5275 #define ATOM_S3_CRT2_ACTIVEb0 0x10 5276 #define ATOM_S3_LCD2_ACTIVEb0 0x20 5277 #define ATOM_S3_DFP6_ACTIVEb0 0x40 5278 #define ATOM_S3_DFP2_ACTIVEb0 0x80 5279 #define ATOM_S3_CV_ACTIVEb1 0x01 5280 #define ATOM_S3_DFP3_ACTIVEb1 0x02 5281 #define ATOM_S3_DFP4_ACTIVEb1 0x04 5282 #define ATOM_S3_DFP5_ACTIVEb1 0x08 5283 5284 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 5285 5286 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 5287 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 5288 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 5289 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 5290 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 5291 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 5292 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 5293 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 5294 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 5295 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 5296 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 5297 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 5298 5299 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 5300 5301 // BIOS_4_SCRATCH Definition 5302 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 5303 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 5304 #define ATOM_S4_LCD1_REFRESH_SHIFT 8 5305 5306 //Byte aligned definition for BIOS usage 5307 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 5308 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 5309 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 5310 5311 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 5312 #define ATOM_S5_DOS_REQ_CRT1b0 0x01 5313 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 5314 #define ATOM_S5_DOS_REQ_TV1b0 0x04 5315 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 5316 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 5317 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 5318 #define ATOM_S5_DOS_REQ_DFP6b0 0x40 5319 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 5320 #define ATOM_S5_DOS_REQ_CVb1 0x01 5321 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 5322 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 5323 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 5324 5325 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 5326 5327 #define ATOM_S5_DOS_REQ_CRT1 0x0001 5328 #define ATOM_S5_DOS_REQ_LCD1 0x0002 5329 #define ATOM_S5_DOS_REQ_TV1 0x0004 5330 #define ATOM_S5_DOS_REQ_DFP1 0x0008 5331 #define ATOM_S5_DOS_REQ_CRT2 0x0010 5332 #define ATOM_S5_DOS_REQ_LCD2 0x0020 5333 #define ATOM_S5_DOS_REQ_DFP6 0x0040 5334 #define ATOM_S5_DOS_REQ_DFP2 0x0080 5335 #define ATOM_S5_DOS_REQ_CV 0x0100 5336 #define ATOM_S5_DOS_REQ_DFP3 0x0200 5337 #define ATOM_S5_DOS_REQ_DFP4 0x0400 5338 #define ATOM_S5_DOS_REQ_DFP5 0x0800 5339 5340 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 5341 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 5342 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 5343 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 5344 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 5345 (ATOM_S5_DOS_FORCE_CVb3<<8)) 5346 5347 // BIOS_6_SCRATCH Definition 5348 #define ATOM_S6_DEVICE_CHANGE 0x00000001L 5349 #define ATOM_S6_SCALER_CHANGE 0x00000002L 5350 #define ATOM_S6_LID_CHANGE 0x00000004L 5351 #define ATOM_S6_DOCKING_CHANGE 0x00000008L 5352 #define ATOM_S6_ACC_MODE 0x00000010L 5353 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 5354 #define ATOM_S6_LID_STATE 0x00000040L 5355 #define ATOM_S6_DOCK_STATE 0x00000080L 5356 #define ATOM_S6_CRITICAL_STATE 0x00000100L 5357 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 5358 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 5359 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 5360 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 5361 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 5362 5363 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 5364 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 5365 5366 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 5367 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 5368 #define ATOM_S6_ACC_REQ_TV1 0x00040000L 5369 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 5370 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 5371 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 5372 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 5373 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 5374 #define ATOM_S6_ACC_REQ_CV 0x01000000L 5375 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 5376 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 5377 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 5378 5379 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 5380 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 5381 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 5382 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 5383 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 5384 5385 //Byte aligned definition for BIOS usage 5386 #define ATOM_S6_DEVICE_CHANGEb0 0x01 5387 #define ATOM_S6_SCALER_CHANGEb0 0x02 5388 #define ATOM_S6_LID_CHANGEb0 0x04 5389 #define ATOM_S6_DOCKING_CHANGEb0 0x08 5390 #define ATOM_S6_ACC_MODEb0 0x10 5391 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 5392 #define ATOM_S6_LID_STATEb0 0x40 5393 #define ATOM_S6_DOCK_STATEb0 0x80 5394 #define ATOM_S6_CRITICAL_STATEb1 0x01 5395 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 5396 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 5397 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 5398 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 5399 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 5400 5401 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 5402 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 5403 #define ATOM_S6_ACC_REQ_TV1b2 0x04 5404 #define ATOM_S6_ACC_REQ_DFP1b2 0x08 5405 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 5406 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 5407 #define ATOM_S6_ACC_REQ_DFP6b2 0x40 5408 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 5409 #define ATOM_S6_ACC_REQ_CVb3 0x01 5410 #define ATOM_S6_ACC_REQ_DFP3b3 0x02 5411 #define ATOM_S6_ACC_REQ_DFP4b3 0x04 5412 #define ATOM_S6_ACC_REQ_DFP5b3 0x08 5413 5414 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 5415 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 5416 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 5417 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 5418 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 5419 5420 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 5421 #define ATOM_S6_SCALER_CHANGE_SHIFT 1 5422 #define ATOM_S6_LID_CHANGE_SHIFT 2 5423 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 5424 #define ATOM_S6_ACC_MODE_SHIFT 4 5425 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 5426 #define ATOM_S6_LID_STATE_SHIFT 6 5427 #define ATOM_S6_DOCK_STATE_SHIFT 7 5428 #define ATOM_S6_CRITICAL_STATE_SHIFT 8 5429 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 5430 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 5431 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 5432 #define ATOM_S6_REQ_SCALER_SHIFT 12 5433 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 5434 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 5435 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 5436 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 5437 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 5438 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 5439 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 5440 5441 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 5442 #define ATOM_S7_DOS_MODE_TYPEb0 0x03 5443 #define ATOM_S7_DOS_MODE_VGAb0 0x00 5444 #define ATOM_S7_DOS_MODE_VESAb0 0x01 5445 #define ATOM_S7_DOS_MODE_EXTb0 0x02 5446 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 5447 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 5448 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 5449 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 5450 5451 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 5452 5453 // BIOS_8_SCRATCH Definition 5454 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 5455 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 5456 5457 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 5458 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 5459 5460 // BIOS_9_SCRATCH Definition 5461 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 5462 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 5463 #endif 5464 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 5465 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 5466 #endif 5467 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 5468 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 5469 #endif 5470 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 5471 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 5472 #endif 5473 5474 5475 #define ATOM_FLAG_SET 0x20 5476 #define ATOM_FLAG_CLEAR 0 5477 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 5478 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 5479 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 5480 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 5481 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 5482 5483 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 5484 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 5485 5486 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 5487 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 5488 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 5489 5490 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 5491 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 5492 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 5493 5494 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 5495 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 5496 5497 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 5498 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 5499 5500 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 5501 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 5502 5503 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5504 5505 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 5506 5507 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 5508 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 5509 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 5510 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 5511 5512 /****************************************************************************/ 5513 //Portion II: Definitinos only used in Driver 5514 /****************************************************************************/ 5515 5516 // Macros used by driver 5517 #ifdef __cplusplus 5518 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 5519 5520 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 5521 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 5522 #else // not __cplusplus 5523 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 5524 5525 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 5526 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 5527 #endif // __cplusplus 5528 5529 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 5530 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 5531 5532 /****************************************************************************/ 5533 //Portion III: Definitinos only used in VBIOS 5534 /****************************************************************************/ 5535 #define ATOM_DAC_SRC 0x80 5536 #define ATOM_SRC_DAC1 0 5537 #define ATOM_SRC_DAC2 0x80 5538 5539 typedef struct _MEMORY_PLLINIT_PARAMETERS 5540 { 5541 ULONG ulTargetMemoryClock; //In 10Khz unit 5542 UCHAR ucAction; //not define yet 5543 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 5544 UCHAR ucFbDiv; //FB value 5545 UCHAR ucPostDiv; //Post div 5546 }MEMORY_PLLINIT_PARAMETERS; 5547 5548 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 5549 5550 5551 #define GPIO_PIN_WRITE 0x01 5552 #define GPIO_PIN_READ 0x00 5553 5554 typedef struct _GPIO_PIN_CONTROL_PARAMETERS 5555 { 5556 UCHAR ucGPIO_ID; //return value, read from GPIO pins 5557 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 5558 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 5559 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 5560 }GPIO_PIN_CONTROL_PARAMETERS; 5561 5562 typedef struct _ENABLE_SCALER_PARAMETERS 5563 { 5564 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 5565 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 5566 UCHAR ucTVStandard; // 5567 UCHAR ucPadding[1]; 5568 }ENABLE_SCALER_PARAMETERS; 5569 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 5570 5571 //ucEnable: 5572 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 5573 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 5574 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 5575 #define SCALER_ENABLE_MULTITAP_MODE 3 5576 5577 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 5578 { 5579 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 5580 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 5581 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 5582 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 5583 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5584 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 5585 5586 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 5587 { 5588 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 5589 ENABLE_CRTC_PARAMETERS sReserved; 5590 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 5591 5592 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 5593 { 5594 USHORT usHight; // Image Hight 5595 USHORT usWidth; // Image Width 5596 UCHAR ucSurface; // Surface 1 or 2 5597 UCHAR ucPadding[3]; 5598 }ENABLE_GRAPH_SURFACE_PARAMETERS; 5599 5600 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 5601 { 5602 USHORT usHight; // Image Hight 5603 USHORT usWidth; // Image Width 5604 UCHAR ucSurface; // Surface 1 or 2 5605 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5606 UCHAR ucPadding[2]; 5607 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 5608 5609 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 5610 { 5611 USHORT usHight; // Image Hight 5612 USHORT usWidth; // Image Width 5613 UCHAR ucSurface; // Surface 1 or 2 5614 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5615 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 5616 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 5617 5618 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 5619 { 5620 USHORT usHight; // Image Hight 5621 USHORT usWidth; // Image Width 5622 USHORT usGraphPitch; 5623 UCHAR ucColorDepth; 5624 UCHAR ucPixelFormat; 5625 UCHAR ucSurface; // Surface 1 or 2 5626 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 5627 UCHAR ucModeType; 5628 UCHAR ucReserved; 5629 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 5630 5631 // ucEnable 5632 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 5633 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 5634 5635 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 5636 { 5637 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 5638 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 5639 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 5640 5641 typedef struct _MEMORY_CLEAN_UP_PARAMETERS 5642 { 5643 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address 5644 USHORT usMemorySize; //8Kb blocks aligned 5645 }MEMORY_CLEAN_UP_PARAMETERS; 5646 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 5647 5648 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 5649 { 5650 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 5651 USHORT usY_Size; 5652 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 5653 5654 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 5655 { 5656 union{ 5657 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 5658 USHORT usSurface; 5659 }; 5660 USHORT usY_Size; 5661 USHORT usDispXStart; 5662 USHORT usDispYStart; 5663 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 5664 5665 5666 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 5667 { 5668 UCHAR ucLutId; 5669 UCHAR ucAction; 5670 USHORT usLutStartIndex; 5671 USHORT usLutLength; 5672 USHORT usLutOffsetInVram; 5673 }PALETTE_DATA_CONTROL_PARAMETERS_V3; 5674 5675 // ucAction: 5676 #define PALETTE_DATA_AUTO_FILL 1 5677 #define PALETTE_DATA_READ 2 5678 #define PALETTE_DATA_WRITE 3 5679 5680 5681 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 5682 { 5683 UCHAR ucInterruptId; 5684 UCHAR ucServiceId; 5685 UCHAR ucStatus; 5686 UCHAR ucReserved; 5687 }INTERRUPT_SERVICE_PARAMETER_V2; 5688 5689 // ucInterruptId 5690 #define HDP1_INTERRUPT_ID 1 5691 #define HDP2_INTERRUPT_ID 2 5692 #define HDP3_INTERRUPT_ID 3 5693 #define HDP4_INTERRUPT_ID 4 5694 #define HDP5_INTERRUPT_ID 5 5695 #define HDP6_INTERRUPT_ID 6 5696 #define SW_INTERRUPT_ID 11 5697 5698 // ucAction 5699 #define INTERRUPT_SERVICE_GEN_SW_INT 1 5700 #define INTERRUPT_SERVICE_GET_STATUS 2 5701 5702 // ucStatus 5703 #define INTERRUPT_STATUS__INT_TRIGGER 1 5704 #define INTERRUPT_STATUS__HPD_HIGH 2 5705 5706 typedef struct _INDIRECT_IO_ACCESS 5707 { 5708 ATOM_COMMON_TABLE_HEADER sHeader; 5709 UCHAR IOAccessSequence[256]; 5710 } INDIRECT_IO_ACCESS; 5711 5712 #define INDIRECT_READ 0x00 5713 #define INDIRECT_WRITE 0x80 5714 5715 #define INDIRECT_IO_MM 0 5716 #define INDIRECT_IO_PLL 1 5717 #define INDIRECT_IO_MC 2 5718 #define INDIRECT_IO_PCIE 3 5719 #define INDIRECT_IO_PCIEP 4 5720 #define INDIRECT_IO_NBMISC 5 5721 5722 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 5723 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 5724 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 5725 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 5726 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 5727 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 5728 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 5729 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 5730 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 5731 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 5732 5733 typedef struct _ATOM_OEM_INFO 5734 { 5735 ATOM_COMMON_TABLE_HEADER sHeader; 5736 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 5737 }ATOM_OEM_INFO; 5738 5739 typedef struct _ATOM_TV_MODE 5740 { 5741 UCHAR ucVMode_Num; //Video mode number 5742 UCHAR ucTV_Mode_Num; //Internal TV mode number 5743 }ATOM_TV_MODE; 5744 5745 typedef struct _ATOM_BIOS_INT_TVSTD_MODE 5746 { 5747 ATOM_COMMON_TABLE_HEADER sHeader; 5748 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 5749 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 5750 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 5751 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5752 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 5753 }ATOM_BIOS_INT_TVSTD_MODE; 5754 5755 5756 typedef struct _ATOM_TV_MODE_SCALER_PTR 5757 { 5758 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 5759 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 5760 UCHAR ucTV_Mode_Num; 5761 }ATOM_TV_MODE_SCALER_PTR; 5762 5763 typedef struct _ATOM_STANDARD_VESA_TIMING 5764 { 5765 ATOM_COMMON_TABLE_HEADER sHeader; 5766 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 5767 }ATOM_STANDARD_VESA_TIMING; 5768 5769 5770 typedef struct _ATOM_STD_FORMAT 5771 { 5772 USHORT usSTD_HDisp; 5773 USHORT usSTD_VDisp; 5774 USHORT usSTD_RefreshRate; 5775 USHORT usReserved; 5776 }ATOM_STD_FORMAT; 5777 5778 typedef struct _ATOM_VESA_TO_EXTENDED_MODE 5779 { 5780 USHORT usVESA_ModeNumber; 5781 USHORT usExtendedModeNumber; 5782 }ATOM_VESA_TO_EXTENDED_MODE; 5783 5784 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 5785 { 5786 ATOM_COMMON_TABLE_HEADER sHeader; 5787 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 5788 }ATOM_VESA_TO_INTENAL_MODE_LUT; 5789 5790 /*************** ATOM Memory Related Data Structure ***********************/ 5791 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 5792 UCHAR ucMemoryType; 5793 UCHAR ucMemoryVendor; 5794 UCHAR ucAdjMCId; 5795 UCHAR ucDynClkId; 5796 ULONG ulDllResetClkRange; 5797 }ATOM_MEMORY_VENDOR_BLOCK; 5798 5799 5800 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 5801 #if ATOM_BIG_ENDIAN 5802 ULONG ucMemBlkId:8; 5803 ULONG ulMemClockRange:24; 5804 #else 5805 ULONG ulMemClockRange:24; 5806 ULONG ucMemBlkId:8; 5807 #endif 5808 }ATOM_MEMORY_SETTING_ID_CONFIG; 5809 5810 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 5811 { 5812 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 5813 ULONG ulAccess; 5814 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 5815 5816 5817 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 5818 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 5819 ULONG aulMemData[1]; 5820 }ATOM_MEMORY_SETTING_DATA_BLOCK; 5821 5822 5823 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 5824 USHORT usRegIndex; // MC register index 5825 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 5826 }ATOM_INIT_REG_INDEX_FORMAT; 5827 5828 5829 typedef struct _ATOM_INIT_REG_BLOCK{ 5830 USHORT usRegIndexTblSize; //size of asRegIndexBuf 5831 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 5832 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 5833 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 5834 }ATOM_INIT_REG_BLOCK; 5835 5836 #define END_OF_REG_INDEX_BLOCK 0x0ffff 5837 #define END_OF_REG_DATA_BLOCK 0x00000000 5838 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 5839 #define CLOCK_RANGE_HIGHEST 0x00ffffff 5840 5841 #define VALUE_DWORD SIZEOF ULONG 5842 #define VALUE_SAME_AS_ABOVE 0 5843 #define VALUE_MASK_DWORD 0x84 5844 5845 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 5846 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 5847 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 5848 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 5849 #define ACCESS_PLACEHOLDER 0x80 5850 5851 typedef struct _ATOM_MC_INIT_PARAM_TABLE 5852 { 5853 ATOM_COMMON_TABLE_HEADER sHeader; 5854 USHORT usAdjustARB_SEQDataOffset; 5855 USHORT usMCInitMemTypeTblOffset; 5856 USHORT usMCInitCommonTblOffset; 5857 USHORT usMCInitPowerDownTblOffset; 5858 ULONG ulARB_SEQDataBuf[32]; 5859 ATOM_INIT_REG_BLOCK asMCInitMemType; 5860 ATOM_INIT_REG_BLOCK asMCInitCommon; 5861 }ATOM_MC_INIT_PARAM_TABLE; 5862 5863 5864 #define _4Mx16 0x2 5865 #define _4Mx32 0x3 5866 #define _8Mx16 0x12 5867 #define _8Mx32 0x13 5868 #define _16Mx16 0x22 5869 #define _16Mx32 0x23 5870 #define _32Mx16 0x32 5871 #define _32Mx32 0x33 5872 #define _64Mx8 0x41 5873 #define _64Mx16 0x42 5874 #define _64Mx32 0x43 5875 #define _128Mx8 0x51 5876 #define _128Mx16 0x52 5877 #define _256Mx8 0x61 5878 #define _256Mx16 0x62 5879 5880 #define SAMSUNG 0x1 5881 #define INFINEON 0x2 5882 #define ELPIDA 0x3 5883 #define ETRON 0x4 5884 #define NANYA 0x5 5885 #define HYNIX 0x6 5886 #define MOSEL 0x7 5887 #define WINBOND 0x8 5888 #define ESMT 0x9 5889 #define MICRON 0xF 5890 5891 #define QIMONDA INFINEON 5892 #define PROMOS MOSEL 5893 #define KRETON INFINEON 5894 #define ELIXIR NANYA 5895 5896 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 5897 5898 #define UCODE_ROM_START_ADDRESS 0x1b800 5899 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 5900 5901 //uCode block header for reference 5902 5903 typedef struct _MCuCodeHeader 5904 { 5905 ULONG ulSignature; 5906 UCHAR ucRevision; 5907 UCHAR ucChecksum; 5908 UCHAR ucReserved1; 5909 UCHAR ucReserved2; 5910 USHORT usParametersLength; 5911 USHORT usUCodeLength; 5912 USHORT usReserved1; 5913 USHORT usReserved2; 5914 } MCuCodeHeader; 5915 5916 ////////////////////////////////////////////////////////////////////////////////// 5917 5918 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 5919 5920 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 5921 typedef struct _ATOM_VRAM_MODULE_V1 5922 { 5923 ULONG ulReserved; 5924 USHORT usEMRSValue; 5925 USHORT usMRSValue; 5926 USHORT usReserved; 5927 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5928 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 5929 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 5930 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5931 UCHAR ucRow; // Number of Row,in power of 2; 5932 UCHAR ucColumn; // Number of Column,in power of 2; 5933 UCHAR ucBank; // Nunber of Bank; 5934 UCHAR ucRank; // Number of Rank, in power of 2 5935 UCHAR ucChannelNum; // Number of channel; 5936 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5937 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5938 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5939 UCHAR ucReserved[2]; 5940 }ATOM_VRAM_MODULE_V1; 5941 5942 5943 typedef struct _ATOM_VRAM_MODULE_V2 5944 { 5945 ULONG ulReserved; 5946 ULONG ulFlags; // To enable/disable functionalities based on memory type 5947 ULONG ulEngineClock; // Override of default engine clock for particular memory type 5948 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 5949 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 5950 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 5951 USHORT usEMRSValue; 5952 USHORT usMRSValue; 5953 USHORT usReserved; 5954 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 5955 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 5956 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 5957 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 5958 UCHAR ucRow; // Number of Row,in power of 2; 5959 UCHAR ucColumn; // Number of Column,in power of 2; 5960 UCHAR ucBank; // Nunber of Bank; 5961 UCHAR ucRank; // Number of Rank, in power of 2 5962 UCHAR ucChannelNum; // Number of channel; 5963 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 5964 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 5965 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 5966 UCHAR ucRefreshRateFactor; 5967 UCHAR ucReserved[3]; 5968 }ATOM_VRAM_MODULE_V2; 5969 5970 5971 typedef struct _ATOM_MEMORY_TIMING_FORMAT 5972 { 5973 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 5974 union{ 5975 USHORT usMRS; // mode register 5976 USHORT usDDR3_MR0; 5977 }; 5978 union{ 5979 USHORT usEMRS; // extended mode register 5980 USHORT usDDR3_MR1; 5981 }; 5982 UCHAR ucCL; // CAS latency 5983 UCHAR ucWL; // WRITE Latency 5984 UCHAR uctRAS; // tRAS 5985 UCHAR uctRC; // tRC 5986 UCHAR uctRFC; // tRFC 5987 UCHAR uctRCDR; // tRCDR 5988 UCHAR uctRCDW; // tRCDW 5989 UCHAR uctRP; // tRP 5990 UCHAR uctRRD; // tRRD 5991 UCHAR uctWR; // tWR 5992 UCHAR uctWTR; // tWTR 5993 UCHAR uctPDIX; // tPDIX 5994 UCHAR uctFAW; // tFAW 5995 UCHAR uctAOND; // tAOND 5996 union 5997 { 5998 struct { 5999 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6000 UCHAR ucReserved; 6001 }; 6002 USHORT usDDR3_MR2; 6003 }; 6004 }ATOM_MEMORY_TIMING_FORMAT; 6005 6006 6007 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 6008 { 6009 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6010 USHORT usMRS; // mode register 6011 USHORT usEMRS; // extended mode register 6012 UCHAR ucCL; // CAS latency 6013 UCHAR ucWL; // WRITE Latency 6014 UCHAR uctRAS; // tRAS 6015 UCHAR uctRC; // tRC 6016 UCHAR uctRFC; // tRFC 6017 UCHAR uctRCDR; // tRCDR 6018 UCHAR uctRCDW; // tRCDW 6019 UCHAR uctRP; // tRP 6020 UCHAR uctRRD; // tRRD 6021 UCHAR uctWR; // tWR 6022 UCHAR uctWTR; // tWTR 6023 UCHAR uctPDIX; // tPDIX 6024 UCHAR uctFAW; // tFAW 6025 UCHAR uctAOND; // tAOND 6026 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6027 ////////////////////////////////////GDDR parameters/////////////////////////////////// 6028 UCHAR uctCCDL; // 6029 UCHAR uctCRCRL; // 6030 UCHAR uctCRCWL; // 6031 UCHAR uctCKE; // 6032 UCHAR uctCKRSE; // 6033 UCHAR uctCKRSX; // 6034 UCHAR uctFAW32; // 6035 UCHAR ucMR5lo; // 6036 UCHAR ucMR5hi; // 6037 UCHAR ucTerminator; 6038 }ATOM_MEMORY_TIMING_FORMAT_V1; 6039 6040 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 6041 { 6042 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6043 USHORT usMRS; // mode register 6044 USHORT usEMRS; // extended mode register 6045 UCHAR ucCL; // CAS latency 6046 UCHAR ucWL; // WRITE Latency 6047 UCHAR uctRAS; // tRAS 6048 UCHAR uctRC; // tRC 6049 UCHAR uctRFC; // tRFC 6050 UCHAR uctRCDR; // tRCDR 6051 UCHAR uctRCDW; // tRCDW 6052 UCHAR uctRP; // tRP 6053 UCHAR uctRRD; // tRRD 6054 UCHAR uctWR; // tWR 6055 UCHAR uctWTR; // tWTR 6056 UCHAR uctPDIX; // tPDIX 6057 UCHAR uctFAW; // tFAW 6058 UCHAR uctAOND; // tAOND 6059 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6060 ////////////////////////////////////GDDR parameters/////////////////////////////////// 6061 UCHAR uctCCDL; // 6062 UCHAR uctCRCRL; // 6063 UCHAR uctCRCWL; // 6064 UCHAR uctCKE; // 6065 UCHAR uctCKRSE; // 6066 UCHAR uctCKRSX; // 6067 UCHAR uctFAW32; // 6068 UCHAR ucMR4lo; // 6069 UCHAR ucMR4hi; // 6070 UCHAR ucMR5lo; // 6071 UCHAR ucMR5hi; // 6072 UCHAR ucTerminator; 6073 UCHAR ucReserved; 6074 }ATOM_MEMORY_TIMING_FORMAT_V2; 6075 6076 typedef struct _ATOM_MEMORY_FORMAT 6077 { 6078 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 6079 union{ 6080 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6081 USHORT usDDR3_Reserved; // Not used for DDR3 memory 6082 }; 6083 union{ 6084 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6085 USHORT usDDR3_MR3; // Used for DDR3 memory 6086 }; 6087 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6088 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6089 UCHAR ucRow; // Number of Row,in power of 2; 6090 UCHAR ucColumn; // Number of Column,in power of 2; 6091 UCHAR ucBank; // Nunber of Bank; 6092 UCHAR ucRank; // Number of Rank, in power of 2 6093 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 6094 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 6095 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 6096 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6097 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble 6098 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 6099 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; //Memory Timing block sort from lower clock to higher clock 6100 }ATOM_MEMORY_FORMAT; 6101 6102 6103 typedef struct _ATOM_VRAM_MODULE_V3 6104 { 6105 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 6106 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 6107 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 6108 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 6109 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6110 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 6111 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 6112 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 6113 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6114 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6115 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 6116 }ATOM_VRAM_MODULE_V3; 6117 6118 6119 //ATOM_VRAM_MODULE_V3.ucNPL_RT 6120 #define NPL_RT_MASK 0x0f 6121 #define BATTERY_ODT_MASK 0xc0 6122 6123 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 6124 6125 typedef struct _ATOM_VRAM_MODULE_V4 6126 { 6127 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6128 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6129 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6130 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6131 USHORT usReserved; 6132 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6133 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6134 UCHAR ucChannelNum; // Number of channels present in this module config 6135 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6136 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6137 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6138 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6139 UCHAR ucVREFI; // board dependent parameter 6140 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6141 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6142 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6143 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6144 UCHAR ucReserved[3]; 6145 6146 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6147 union{ 6148 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6149 USHORT usDDR3_Reserved; 6150 }; 6151 union{ 6152 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6153 USHORT usDDR3_MR3; // Used for DDR3 memory 6154 }; 6155 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6156 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6157 UCHAR ucReserved2[2]; 6158 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6159 }ATOM_VRAM_MODULE_V4; 6160 6161 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 6162 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 6163 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 6164 #define VRAM_MODULE_V4_MISC_BL8 0x4 6165 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 6166 6167 typedef struct _ATOM_VRAM_MODULE_V5 6168 { 6169 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6170 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6171 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6172 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6173 USHORT usReserved; 6174 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6175 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6176 UCHAR ucChannelNum; // Number of channels present in this module config 6177 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6178 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6179 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6180 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6181 UCHAR ucVREFI; // board dependent parameter 6182 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6183 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6184 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6185 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6186 UCHAR ucReserved[3]; 6187 6188 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6189 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6190 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6191 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6192 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6193 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6194 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6195 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6196 }ATOM_VRAM_MODULE_V5; 6197 6198 typedef struct _ATOM_VRAM_MODULE_V6 6199 { 6200 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 6201 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 6202 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6203 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6204 USHORT usReserved; 6205 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6206 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 6207 UCHAR ucChannelNum; // Number of channels present in this module config 6208 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 6209 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6210 UCHAR ucFlag; // To enable/disable functionalities based on memory type 6211 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 6212 UCHAR ucVREFI; // board dependent parameter 6213 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 6214 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6215 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 6216 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6217 UCHAR ucReserved[3]; 6218 6219 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 6220 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6221 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6222 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 6223 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6224 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 6225 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6226 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 6227 }ATOM_VRAM_MODULE_V6; 6228 6229 typedef struct _ATOM_VRAM_MODULE_V7 6230 { 6231 // Design Specific Values 6232 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 6233 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 6234 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 6235 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 6236 UCHAR ucExtMemoryID; // Current memory module ID 6237 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 6238 UCHAR ucChannelNum; // Number of mem. channels supported in this module 6239 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 6240 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 6241 UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. 6242 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 6243 UCHAR ucVREFI; // Not used. 6244 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 6245 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 6246 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 6247 USHORT usSEQSettingOffset; 6248 UCHAR ucReserved; 6249 // Memory Module specific values 6250 USHORT usEMRS2Value; // EMRS2/MR2 Value. 6251 USHORT usEMRS3Value; // EMRS3/MR3 Value. 6252 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 6253 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 6254 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 6255 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 6256 char strMemPNString[20]; // part number end with '0'. 6257 }ATOM_VRAM_MODULE_V7; 6258 6259 typedef struct _ATOM_VRAM_INFO_V2 6260 { 6261 ATOM_COMMON_TABLE_HEADER sHeader; 6262 UCHAR ucNumOfVRAMModule; 6263 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6264 }ATOM_VRAM_INFO_V2; 6265 6266 typedef struct _ATOM_VRAM_INFO_V3 6267 { 6268 ATOM_COMMON_TABLE_HEADER sHeader; 6269 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6270 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6271 USHORT usRerseved; 6272 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 6273 UCHAR ucNumOfVRAMModule; 6274 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6275 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6276 // ATOM_INIT_REG_BLOCK aMemAdjust; 6277 }ATOM_VRAM_INFO_V3; 6278 6279 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 6280 6281 typedef struct _ATOM_VRAM_INFO_V4 6282 { 6283 ATOM_COMMON_TABLE_HEADER sHeader; 6284 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6285 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6286 USHORT usRerseved; 6287 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 6288 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 6289 UCHAR ucReservde[4]; 6290 UCHAR ucNumOfVRAMModule; 6291 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6292 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 6293 // ATOM_INIT_REG_BLOCK aMemAdjust; 6294 }ATOM_VRAM_INFO_V4; 6295 6296 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 6297 { 6298 ATOM_COMMON_TABLE_HEADER sHeader; 6299 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 6300 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 6301 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 6302 USHORT usReserved[3]; 6303 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 6304 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 6305 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 6306 UCHAR ucReserved; 6307 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 6308 }ATOM_VRAM_INFO_HEADER_V2_1; 6309 6310 6311 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 6312 { 6313 ATOM_COMMON_TABLE_HEADER sHeader; 6314 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator 6315 }ATOM_VRAM_GPIO_DETECTION_INFO; 6316 6317 6318 typedef struct _ATOM_MEMORY_TRAINING_INFO 6319 { 6320 ATOM_COMMON_TABLE_HEADER sHeader; 6321 UCHAR ucTrainingLoop; 6322 UCHAR ucReserved[3]; 6323 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 6324 }ATOM_MEMORY_TRAINING_INFO; 6325 6326 6327 typedef struct SW_I2C_CNTL_DATA_PARAMETERS 6328 { 6329 UCHAR ucControl; 6330 UCHAR ucData; 6331 UCHAR ucSatus; 6332 UCHAR ucTemp; 6333 } SW_I2C_CNTL_DATA_PARAMETERS; 6334 6335 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 6336 6337 typedef struct _SW_I2C_IO_DATA_PARAMETERS 6338 { 6339 USHORT GPIO_Info; 6340 UCHAR ucAct; 6341 UCHAR ucData; 6342 } SW_I2C_IO_DATA_PARAMETERS; 6343 6344 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 6345 6346 /****************************SW I2C CNTL DEFINITIONS**********************/ 6347 #define SW_I2C_IO_RESET 0 6348 #define SW_I2C_IO_GET 1 6349 #define SW_I2C_IO_DRIVE 2 6350 #define SW_I2C_IO_SET 3 6351 #define SW_I2C_IO_START 4 6352 6353 #define SW_I2C_IO_CLOCK 0 6354 #define SW_I2C_IO_DATA 0x80 6355 6356 #define SW_I2C_IO_ZERO 0 6357 #define SW_I2C_IO_ONE 0x100 6358 6359 #define SW_I2C_CNTL_READ 0 6360 #define SW_I2C_CNTL_WRITE 1 6361 #define SW_I2C_CNTL_START 2 6362 #define SW_I2C_CNTL_STOP 3 6363 #define SW_I2C_CNTL_OPEN 4 6364 #define SW_I2C_CNTL_CLOSE 5 6365 #define SW_I2C_CNTL_WRITE1BIT 6 6366 6367 //==============================VESA definition Portion=============================== 6368 #define VESA_OEM_PRODUCT_REV "01.00" 6369 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 6370 #define VESA_MODE_WIN_ATTRIBUTE 7 6371 #define VESA_WIN_SIZE 64 6372 6373 typedef struct _PTR_32_BIT_STRUCTURE 6374 { 6375 USHORT Offset16; 6376 USHORT Segment16; 6377 } PTR_32_BIT_STRUCTURE; 6378 6379 typedef union _PTR_32_BIT_UNION 6380 { 6381 PTR_32_BIT_STRUCTURE SegmentOffset; 6382 ULONG Ptr32_Bit; 6383 } PTR_32_BIT_UNION; 6384 6385 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 6386 { 6387 UCHAR VbeSignature[4]; 6388 USHORT VbeVersion; 6389 PTR_32_BIT_UNION OemStringPtr; 6390 UCHAR Capabilities[4]; 6391 PTR_32_BIT_UNION VideoModePtr; 6392 USHORT TotalMemory; 6393 } VBE_1_2_INFO_BLOCK_UPDATABLE; 6394 6395 6396 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 6397 { 6398 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 6399 USHORT OemSoftRev; 6400 PTR_32_BIT_UNION OemVendorNamePtr; 6401 PTR_32_BIT_UNION OemProductNamePtr; 6402 PTR_32_BIT_UNION OemProductRevPtr; 6403 } VBE_2_0_INFO_BLOCK_UPDATABLE; 6404 6405 typedef union _VBE_VERSION_UNION 6406 { 6407 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 6408 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 6409 } VBE_VERSION_UNION; 6410 6411 typedef struct _VBE_INFO_BLOCK 6412 { 6413 VBE_VERSION_UNION UpdatableVBE_Info; 6414 UCHAR Reserved[222]; 6415 UCHAR OemData[256]; 6416 } VBE_INFO_BLOCK; 6417 6418 typedef struct _VBE_FP_INFO 6419 { 6420 USHORT HSize; 6421 USHORT VSize; 6422 USHORT FPType; 6423 UCHAR RedBPP; 6424 UCHAR GreenBPP; 6425 UCHAR BlueBPP; 6426 UCHAR ReservedBPP; 6427 ULONG RsvdOffScrnMemSize; 6428 ULONG RsvdOffScrnMEmPtr; 6429 UCHAR Reserved[14]; 6430 } VBE_FP_INFO; 6431 6432 typedef struct _VESA_MODE_INFO_BLOCK 6433 { 6434 // Mandatory information for all VBE revisions 6435 USHORT ModeAttributes; // dw ? ; mode attributes 6436 UCHAR WinAAttributes; // db ? ; window A attributes 6437 UCHAR WinBAttributes; // db ? ; window B attributes 6438 USHORT WinGranularity; // dw ? ; window granularity 6439 USHORT WinSize; // dw ? ; window size 6440 USHORT WinASegment; // dw ? ; window A start segment 6441 USHORT WinBSegment; // dw ? ; window B start segment 6442 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 6443 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 6444 6445 //; Mandatory information for VBE 1.2 and above 6446 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 6447 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 6448 UCHAR XCharSize; // db ? ; character cell width in pixels 6449 UCHAR YCharSize; // db ? ; character cell height in pixels 6450 UCHAR NumberOfPlanes; // db ? ; number of memory planes 6451 UCHAR BitsPerPixel; // db ? ; bits per pixel 6452 UCHAR NumberOfBanks; // db ? ; number of banks 6453 UCHAR MemoryModel; // db ? ; memory model type 6454 UCHAR BankSize; // db ? ; bank size in KB 6455 UCHAR NumberOfImagePages;// db ? ; number of images 6456 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 6457 6458 //; Direct Color fields(required for direct/6 and YUV/7 memory models) 6459 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 6460 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 6461 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 6462 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 6463 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 6464 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 6465 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 6466 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 6467 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 6468 6469 //; Mandatory information for VBE 2.0 and above 6470 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 6471 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 6472 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 6473 6474 //; Mandatory information for VBE 3.0 and above 6475 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 6476 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 6477 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 6478 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 6479 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 6480 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 6481 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 6482 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 6483 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 6484 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 6485 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 6486 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 6487 UCHAR Reserved; // db 190 dup (0) 6488 } VESA_MODE_INFO_BLOCK; 6489 6490 // BIOS function CALLS 6491 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 6492 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 6493 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 6494 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 6495 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 6496 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 6497 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 6498 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 6499 #define ATOM_BIOS_FUNCTION_STV_STD 0x16 6500 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 6501 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 6502 6503 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 6504 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 6505 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 6506 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 6507 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 6508 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 6509 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 6510 6511 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 6512 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 6513 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 6514 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 6515 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 6516 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 6517 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 6518 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 6519 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 6520 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 6521 6522 6523 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 6524 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 6525 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 6526 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 6527 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 6528 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 6529 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 6530 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 6531 6532 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 6533 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 6534 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 6535 6536 // structure used for VBIOS only 6537 6538 //DispOutInfoTable 6539 typedef struct _ASIC_TRANSMITTER_INFO 6540 { 6541 USHORT usTransmitterObjId; 6542 USHORT usSupportDevice; 6543 UCHAR ucTransmitterCmdTblId; 6544 UCHAR ucConfig; 6545 UCHAR ucEncoderID; //available 1st encoder ( default ) 6546 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 6547 UCHAR uc2ndEncoderID; 6548 UCHAR ucReserved; 6549 }ASIC_TRANSMITTER_INFO; 6550 6551 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 6552 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 6553 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 6554 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 6555 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 6556 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 6557 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 6558 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 6559 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 6560 6561 typedef struct _ASIC_ENCODER_INFO 6562 { 6563 UCHAR ucEncoderID; 6564 UCHAR ucEncoderConfig; 6565 USHORT usEncoderCmdTblId; 6566 }ASIC_ENCODER_INFO; 6567 6568 typedef struct _ATOM_DISP_OUT_INFO 6569 { 6570 ATOM_COMMON_TABLE_HEADER sHeader; 6571 USHORT ptrTransmitterInfo; 6572 USHORT ptrEncoderInfo; 6573 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6574 ASIC_ENCODER_INFO asEncoderInfo[1]; 6575 }ATOM_DISP_OUT_INFO; 6576 6577 typedef struct _ATOM_DISP_OUT_INFO_V2 6578 { 6579 ATOM_COMMON_TABLE_HEADER sHeader; 6580 USHORT ptrTransmitterInfo; 6581 USHORT ptrEncoderInfo; 6582 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6583 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 6584 ASIC_ENCODER_INFO asEncoderInfo[1]; 6585 }ATOM_DISP_OUT_INFO_V2; 6586 6587 6588 typedef struct _ATOM_DISP_CLOCK_ID { 6589 UCHAR ucPpllId; 6590 UCHAR ucPpllAttribute; 6591 }ATOM_DISP_CLOCK_ID; 6592 6593 // ucPpllAttribute 6594 #define CLOCK_SOURCE_SHAREABLE 0x01 6595 #define CLOCK_SOURCE_DP_MODE 0x02 6596 #define CLOCK_SOURCE_NONE_DP_MODE 0x04 6597 6598 //DispOutInfoTable 6599 typedef struct _ASIC_TRANSMITTER_INFO_V2 6600 { 6601 USHORT usTransmitterObjId; 6602 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 6603 UCHAR ucTransmitterCmdTblId; 6604 UCHAR ucConfig; 6605 UCHAR ucEncoderID; // available 1st encoder ( default ) 6606 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 6607 UCHAR uc2ndEncoderID; 6608 UCHAR ucReserved; 6609 }ASIC_TRANSMITTER_INFO_V2; 6610 6611 typedef struct _ATOM_DISP_OUT_INFO_V3 6612 { 6613 ATOM_COMMON_TABLE_HEADER sHeader; 6614 USHORT ptrTransmitterInfo; 6615 USHORT ptrEncoderInfo; 6616 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 6617 USHORT usReserved; 6618 UCHAR ucDCERevision; 6619 UCHAR ucMaxDispEngineNum; 6620 UCHAR ucMaxActiveDispEngineNum; 6621 UCHAR ucMaxPPLLNum; 6622 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 6623 UCHAR ucReserved[3]; 6624 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 6625 }ATOM_DISP_OUT_INFO_V3; 6626 6627 typedef enum CORE_REF_CLK_SOURCE{ 6628 CLOCK_SRC_XTALIN=0, 6629 CLOCK_SRC_XO_IN=1, 6630 CLOCK_SRC_XO_IN2=2, 6631 }CORE_REF_CLK_SOURCE; 6632 6633 // DispDevicePriorityInfo 6634 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 6635 { 6636 ATOM_COMMON_TABLE_HEADER sHeader; 6637 USHORT asDevicePriority[16]; 6638 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 6639 6640 //ProcessAuxChannelTransactionTable 6641 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 6642 { 6643 USHORT lpAuxRequest; 6644 USHORT lpDataOut; 6645 UCHAR ucChannelID; 6646 union 6647 { 6648 UCHAR ucReplyStatus; 6649 UCHAR ucDelay; 6650 }; 6651 UCHAR ucDataOutLen; 6652 UCHAR ucReserved; 6653 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 6654 6655 //ProcessAuxChannelTransactionTable 6656 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 6657 { 6658 USHORT lpAuxRequest; 6659 USHORT lpDataOut; 6660 UCHAR ucChannelID; 6661 union 6662 { 6663 UCHAR ucReplyStatus; 6664 UCHAR ucDelay; 6665 }; 6666 UCHAR ucDataOutLen; 6667 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 6668 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 6669 6670 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 6671 6672 //GetSinkType 6673 6674 typedef struct _DP_ENCODER_SERVICE_PARAMETERS 6675 { 6676 USHORT ucLinkClock; 6677 union 6678 { 6679 UCHAR ucConfig; // for DP training command 6680 UCHAR ucI2cId; // use for GET_SINK_TYPE command 6681 }; 6682 UCHAR ucAction; 6683 UCHAR ucStatus; 6684 UCHAR ucLaneNum; 6685 UCHAR ucReserved[2]; 6686 }DP_ENCODER_SERVICE_PARAMETERS; 6687 6688 // ucAction 6689 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 6690 /* obselete */ 6691 #define ATOM_DP_ACTION_TRAINING_START 0x02 6692 #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 6693 #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 6694 #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 6695 #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 6696 #define ATOM_DP_ACTION_BLANKING 0x07 6697 6698 // ucConfig 6699 #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 6700 #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 6701 #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 6702 #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 6703 #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 6704 #define ATOM_DP_CONFIG_LINK_A 0x00 6705 #define ATOM_DP_CONFIG_LINK_B 0x04 6706 /* /obselete */ 6707 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 6708 6709 6710 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 6711 { 6712 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 6713 UCHAR ucAuxId; 6714 UCHAR ucAction; 6715 UCHAR ucSinkType; // Iput and Output parameters. 6716 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 6717 UCHAR ucReserved[2]; 6718 }DP_ENCODER_SERVICE_PARAMETERS_V2; 6719 6720 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 6721 { 6722 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 6723 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 6724 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 6725 6726 // ucAction 6727 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 6728 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 6729 6730 6731 // DP_TRAINING_TABLE 6732 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 6733 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 6734 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 6735 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 6736 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 6737 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 6738 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 6739 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 6740 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 6741 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 6742 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 6743 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 6744 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 6745 6746 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6747 { 6748 UCHAR ucI2CSpeed; 6749 union 6750 { 6751 UCHAR ucRegIndex; 6752 UCHAR ucStatus; 6753 }; 6754 USHORT lpI2CDataOut; 6755 UCHAR ucFlag; 6756 UCHAR ucTransBytes; 6757 UCHAR ucSlaveAddr; 6758 UCHAR ucLineNumber; 6759 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 6760 6761 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 6762 6763 //ucFlag 6764 #define HW_I2C_WRITE 1 6765 #define HW_I2C_READ 0 6766 #define I2C_2BYTE_ADDR 0x02 6767 6768 /****************************************************************************/ 6769 // Structures used by HW_Misc_OperationTable 6770 /****************************************************************************/ 6771 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 6772 { 6773 UCHAR ucCmd; // Input: To tell which action to take 6774 UCHAR ucReserved[3]; 6775 ULONG ulReserved; 6776 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 6777 6778 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 6779 { 6780 UCHAR ucReturnCode; // Output: Return value base on action was taken 6781 UCHAR ucReserved[3]; 6782 ULONG ulReserved; 6783 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 6784 6785 // Actions code 6786 #define ATOM_GET_SDI_SUPPORT 0xF0 6787 6788 // Return code 6789 #define ATOM_UNKNOWN_CMD 0 6790 #define ATOM_FEATURE_NOT_SUPPORTED 1 6791 #define ATOM_FEATURE_SUPPORTED 2 6792 6793 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 6794 { 6795 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 6796 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 6797 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 6798 6799 /****************************************************************************/ 6800 6801 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 6802 { 6803 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 6804 UCHAR ucReserved[3]; 6805 }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 6806 6807 #define HWBLKINST_INSTANCE_MASK 0x07 6808 #define HWBLKINST_HWBLK_MASK 0xF0 6809 #define HWBLKINST_HWBLK_SHIFT 0x04 6810 6811 //ucHWBlock 6812 #define SELECT_DISP_ENGINE 0 6813 #define SELECT_DISP_PLL 1 6814 #define SELECT_DCIO_UNIPHY_LINK0 2 6815 #define SELECT_DCIO_UNIPHY_LINK1 3 6816 #define SELECT_DCIO_IMPCAL 4 6817 #define SELECT_DCIO_DIG 6 6818 #define SELECT_CRTC_PIXEL_RATE 7 6819 #define SELECT_VGA_BLK 8 6820 6821 // DIGTransmitterInfoTable structure used to program UNIPHY settings 6822 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 6823 ATOM_COMMON_TABLE_HEADER sHeader; 6824 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 6825 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 6826 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 6827 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 6828 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 6829 }DIG_TRANSMITTER_INFO_HEADER_V3_1; 6830 6831 typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 6832 USHORT usRegisterIndex; 6833 UCHAR ucStartBit; 6834 UCHAR ucEndBit; 6835 }CLOCK_CONDITION_REGESTER_INFO; 6836 6837 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 6838 USHORT usMaxClockFreq; 6839 UCHAR ucEncodeMode; 6840 UCHAR ucPhySel; 6841 ULONG ulAnalogSetting[1]; 6842 }CLOCK_CONDITION_SETTING_ENTRY; 6843 6844 typedef struct _CLOCK_CONDITION_SETTING_INFO{ 6845 USHORT usEntrySize; 6846 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 6847 }CLOCK_CONDITION_SETTING_INFO; 6848 6849 typedef struct _PHY_CONDITION_REG_VAL{ 6850 ULONG ulCondition; 6851 ULONG ulRegVal; 6852 }PHY_CONDITION_REG_VAL; 6853 6854 typedef struct _PHY_CONDITION_REG_INFO{ 6855 USHORT usRegIndex; 6856 USHORT usSize; 6857 PHY_CONDITION_REG_VAL asRegVal[1]; 6858 }PHY_CONDITION_REG_INFO; 6859 6860 typedef struct _PHY_ANALOG_SETTING_INFO{ 6861 UCHAR ucEncodeMode; 6862 UCHAR ucPhySel; 6863 USHORT usSize; 6864 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 6865 }PHY_ANALOG_SETTING_INFO; 6866 6867 /****************************************************************************/ 6868 //Portion VI: Definitinos for vbios MC scratch registers that driver used 6869 /****************************************************************************/ 6870 6871 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 6872 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 6873 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 6874 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 6875 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 6876 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 6877 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 6878 6879 /****************************************************************************/ 6880 //Portion VI: Definitinos being oboselete 6881 /****************************************************************************/ 6882 6883 //========================================================================================== 6884 //Remove the definitions below when driver is ready! 6885 typedef struct _ATOM_DAC_INFO 6886 { 6887 ATOM_COMMON_TABLE_HEADER sHeader; 6888 USHORT usMaxFrequency; // in 10kHz unit 6889 USHORT usReserved; 6890 }ATOM_DAC_INFO; 6891 6892 6893 typedef struct _COMPASSIONATE_DATA 6894 { 6895 ATOM_COMMON_TABLE_HEADER sHeader; 6896 6897 //============================== DAC1 portion 6898 UCHAR ucDAC1_BG_Adjustment; 6899 UCHAR ucDAC1_DAC_Adjustment; 6900 USHORT usDAC1_FORCE_Data; 6901 //============================== DAC2 portion 6902 UCHAR ucDAC2_CRT2_BG_Adjustment; 6903 UCHAR ucDAC2_CRT2_DAC_Adjustment; 6904 USHORT usDAC2_CRT2_FORCE_Data; 6905 USHORT usDAC2_CRT2_MUX_RegisterIndex; 6906 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6907 UCHAR ucDAC2_NTSC_BG_Adjustment; 6908 UCHAR ucDAC2_NTSC_DAC_Adjustment; 6909 USHORT usDAC2_TV1_FORCE_Data; 6910 USHORT usDAC2_TV1_MUX_RegisterIndex; 6911 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6912 UCHAR ucDAC2_CV_BG_Adjustment; 6913 UCHAR ucDAC2_CV_DAC_Adjustment; 6914 USHORT usDAC2_CV_FORCE_Data; 6915 USHORT usDAC2_CV_MUX_RegisterIndex; 6916 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 6917 UCHAR ucDAC2_PAL_BG_Adjustment; 6918 UCHAR ucDAC2_PAL_DAC_Adjustment; 6919 USHORT usDAC2_TV2_FORCE_Data; 6920 }COMPASSIONATE_DATA; 6921 6922 /****************************Supported Device Info Table Definitions**********************/ 6923 // ucConnectInfo: 6924 // [7:4] - connector type 6925 // = 1 - VGA connector 6926 // = 2 - DVI-I 6927 // = 3 - DVI-D 6928 // = 4 - DVI-A 6929 // = 5 - SVIDEO 6930 // = 6 - COMPOSITE 6931 // = 7 - LVDS 6932 // = 8 - DIGITAL LINK 6933 // = 9 - SCART 6934 // = 0xA - HDMI_type A 6935 // = 0xB - HDMI_type B 6936 // = 0xE - Special case1 (DVI+DIN) 6937 // Others=TBD 6938 // [3:0] - DAC Associated 6939 // = 0 - no DAC 6940 // = 1 - DACA 6941 // = 2 - DACB 6942 // = 3 - External DAC 6943 // Others=TBD 6944 // 6945 6946 typedef struct _ATOM_CONNECTOR_INFO 6947 { 6948 #if ATOM_BIG_ENDIAN 6949 UCHAR bfConnectorType:4; 6950 UCHAR bfAssociatedDAC:4; 6951 #else 6952 UCHAR bfAssociatedDAC:4; 6953 UCHAR bfConnectorType:4; 6954 #endif 6955 }ATOM_CONNECTOR_INFO; 6956 6957 typedef union _ATOM_CONNECTOR_INFO_ACCESS 6958 { 6959 ATOM_CONNECTOR_INFO sbfAccess; 6960 UCHAR ucAccess; 6961 }ATOM_CONNECTOR_INFO_ACCESS; 6962 6963 typedef struct _ATOM_CONNECTOR_INFO_I2C 6964 { 6965 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 6966 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6967 }ATOM_CONNECTOR_INFO_I2C; 6968 6969 6970 typedef struct _ATOM_SUPPORTED_DEVICES_INFO 6971 { 6972 ATOM_COMMON_TABLE_HEADER sHeader; 6973 USHORT usDeviceSupport; 6974 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 6975 }ATOM_SUPPORTED_DEVICES_INFO; 6976 6977 #define NO_INT_SRC_MAPPED 0xFF 6978 6979 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 6980 { 6981 UCHAR ucIntSrcBitmap; 6982 }ATOM_CONNECTOR_INC_SRC_BITMAP; 6983 6984 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 6985 { 6986 ATOM_COMMON_TABLE_HEADER sHeader; 6987 USHORT usDeviceSupport; 6988 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6989 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 6990 }ATOM_SUPPORTED_DEVICES_INFO_2; 6991 6992 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 6993 { 6994 ATOM_COMMON_TABLE_HEADER sHeader; 6995 USHORT usDeviceSupport; 6996 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 6997 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 6998 }ATOM_SUPPORTED_DEVICES_INFO_2d1; 6999 7000 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 7001 7002 7003 7004 typedef struct _ATOM_MISC_CONTROL_INFO 7005 { 7006 USHORT usFrequency; 7007 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 7008 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 7009 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 7010 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 7011 }ATOM_MISC_CONTROL_INFO; 7012 7013 7014 #define ATOM_MAX_MISC_INFO 4 7015 7016 typedef struct _ATOM_TMDS_INFO 7017 { 7018 ATOM_COMMON_TABLE_HEADER sHeader; 7019 USHORT usMaxFrequency; // in 10Khz 7020 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 7021 }ATOM_TMDS_INFO; 7022 7023 7024 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 7025 { 7026 UCHAR ucTVStandard; //Same as TV standards defined above, 7027 UCHAR ucPadding[1]; 7028 }ATOM_ENCODER_ANALOG_ATTRIBUTE; 7029 7030 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 7031 { 7032 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 7033 UCHAR ucPadding[1]; 7034 }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 7035 7036 typedef union _ATOM_ENCODER_ATTRIBUTE 7037 { 7038 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 7039 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 7040 }ATOM_ENCODER_ATTRIBUTE; 7041 7042 7043 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 7044 { 7045 USHORT usPixelClock; 7046 USHORT usEncoderID; 7047 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 7048 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 7049 ATOM_ENCODER_ATTRIBUTE usDevAttr; 7050 }DVO_ENCODER_CONTROL_PARAMETERS; 7051 7052 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 7053 { 7054 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 7055 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 7056 }DVO_ENCODER_CONTROL_PS_ALLOCATION; 7057 7058 7059 #define ATOM_XTMDS_ASIC_SI164_ID 1 7060 #define ATOM_XTMDS_ASIC_SI178_ID 2 7061 #define ATOM_XTMDS_ASIC_TFP513_ID 3 7062 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 7063 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 7064 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 7065 7066 7067 typedef struct _ATOM_XTMDS_INFO 7068 { 7069 ATOM_COMMON_TABLE_HEADER sHeader; 7070 USHORT usSingleLinkMaxFrequency; 7071 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 7072 UCHAR ucXtransimitterID; 7073 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 7074 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 7075 // due to design. This ID is used to alert driver that the sequence is not "standard"! 7076 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 7077 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 7078 }ATOM_XTMDS_INFO; 7079 7080 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 7081 { 7082 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 7083 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 7084 UCHAR ucPadding[2]; 7085 }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 7086 7087 /****************************Legacy Power Play Table Definitions **********************/ 7088 7089 //Definitions for ulPowerPlayMiscInfo 7090 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 7091 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 7092 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 7093 7094 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 7095 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 7096 7097 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 7098 7099 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 7100 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 7101 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 7102 7103 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 7104 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 7105 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 7106 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 7107 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 7108 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 7109 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 7110 7111 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 7112 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 7113 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 7114 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 7115 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 7116 7117 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 7118 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 7119 7120 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 7121 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 7122 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 7123 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 7124 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 7125 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 7126 7127 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 7128 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 7129 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 7130 7131 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 7132 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 7133 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 7134 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 7135 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 7136 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 7137 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 7138 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 7139 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 7140 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 7141 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 7142 7143 //ucTableFormatRevision=1 7144 //ucTableContentRevision=1 7145 typedef struct _ATOM_POWERMODE_INFO 7146 { 7147 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7148 ULONG ulReserved1; // must set to 0 7149 ULONG ulReserved2; // must set to 0 7150 USHORT usEngineClock; 7151 USHORT usMemoryClock; 7152 UCHAR ucVoltageDropIndex; // index to GPIO table 7153 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7154 UCHAR ucMinTemperature; 7155 UCHAR ucMaxTemperature; 7156 UCHAR ucNumPciELanes; // number of PCIE lanes 7157 }ATOM_POWERMODE_INFO; 7158 7159 //ucTableFormatRevision=2 7160 //ucTableContentRevision=1 7161 typedef struct _ATOM_POWERMODE_INFO_V2 7162 { 7163 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7164 ULONG ulMiscInfo2; 7165 ULONG ulEngineClock; 7166 ULONG ulMemoryClock; 7167 UCHAR ucVoltageDropIndex; // index to GPIO table 7168 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7169 UCHAR ucMinTemperature; 7170 UCHAR ucMaxTemperature; 7171 UCHAR ucNumPciELanes; // number of PCIE lanes 7172 }ATOM_POWERMODE_INFO_V2; 7173 7174 //ucTableFormatRevision=2 7175 //ucTableContentRevision=2 7176 typedef struct _ATOM_POWERMODE_INFO_V3 7177 { 7178 ULONG ulMiscInfo; //The power level should be arranged in ascending order 7179 ULONG ulMiscInfo2; 7180 ULONG ulEngineClock; 7181 ULONG ulMemoryClock; 7182 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 7183 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 7184 UCHAR ucMinTemperature; 7185 UCHAR ucMaxTemperature; 7186 UCHAR ucNumPciELanes; // number of PCIE lanes 7187 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 7188 }ATOM_POWERMODE_INFO_V3; 7189 7190 7191 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 7192 7193 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 7194 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 7195 7196 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 7197 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 7198 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 7199 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 7200 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 7201 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 7202 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 7203 7204 7205 typedef struct _ATOM_POWERPLAY_INFO 7206 { 7207 ATOM_COMMON_TABLE_HEADER sHeader; 7208 UCHAR ucOverdriveThermalController; 7209 UCHAR ucOverdriveI2cLine; 7210 UCHAR ucOverdriveIntBitmap; 7211 UCHAR ucOverdriveControllerAddress; 7212 UCHAR ucSizeOfPowerModeEntry; 7213 UCHAR ucNumOfPowerModeEntries; 7214 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7215 }ATOM_POWERPLAY_INFO; 7216 7217 typedef struct _ATOM_POWERPLAY_INFO_V2 7218 { 7219 ATOM_COMMON_TABLE_HEADER sHeader; 7220 UCHAR ucOverdriveThermalController; 7221 UCHAR ucOverdriveI2cLine; 7222 UCHAR ucOverdriveIntBitmap; 7223 UCHAR ucOverdriveControllerAddress; 7224 UCHAR ucSizeOfPowerModeEntry; 7225 UCHAR ucNumOfPowerModeEntries; 7226 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7227 }ATOM_POWERPLAY_INFO_V2; 7228 7229 typedef struct _ATOM_POWERPLAY_INFO_V3 7230 { 7231 ATOM_COMMON_TABLE_HEADER sHeader; 7232 UCHAR ucOverdriveThermalController; 7233 UCHAR ucOverdriveI2cLine; 7234 UCHAR ucOverdriveIntBitmap; 7235 UCHAR ucOverdriveControllerAddress; 7236 UCHAR ucSizeOfPowerModeEntry; 7237 UCHAR ucNumOfPowerModeEntries; 7238 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 7239 }ATOM_POWERPLAY_INFO_V3; 7240 7241 /* New PPlib */ 7242 /**************************************************************************/ 7243 typedef struct _ATOM_PPLIB_THERMALCONTROLLER 7244 7245 { 7246 UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* 7247 UCHAR ucI2cLine; // as interpreted by DAL I2C 7248 UCHAR ucI2cAddress; 7249 UCHAR ucFanParameters; // Fan Control Parameters. 7250 UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. 7251 UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. 7252 UCHAR ucReserved; // ---- 7253 UCHAR ucFlags; // to be defined 7254 } ATOM_PPLIB_THERMALCONTROLLER; 7255 7256 #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f 7257 #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. 7258 7259 #define ATOM_PP_THERMALCONTROLLER_NONE 0 7260 #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib 7261 #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib 7262 #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib 7263 #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib 7264 #define ATOM_PP_THERMALCONTROLLER_LM64 5 7265 #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib 7266 #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 7267 #define ATOM_PP_THERMALCONTROLLER_RV770 8 7268 #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 7269 #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 7270 #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 7271 #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. 7272 #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally 7273 #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 7274 #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 7275 #define ATOM_PP_THERMALCONTROLLER_LM96163 17 7276 7277 // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. 7278 // We probably should reserve the bit 0x80 for this use. 7279 // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). 7280 // The driver can pick the correct internal controller based on the ASIC. 7281 7282 #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller 7283 #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller 7284 7285 typedef struct _ATOM_PPLIB_STATE 7286 { 7287 UCHAR ucNonClockStateIndex; 7288 UCHAR ucClockStateIndices[1]; // variable-sized 7289 } ATOM_PPLIB_STATE; 7290 7291 7292 typedef struct _ATOM_PPLIB_FANTABLE 7293 { 7294 UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. 7295 UCHAR ucTHyst; // Temperature hysteresis. Integer. 7296 USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. 7297 USHORT usTMed; // The middle temperature where we change slopes. 7298 USHORT usTHigh; // The high point above TMed for adjusting the second slope. 7299 USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). 7300 USHORT usPWMMed; // The PWM value (in percent) at TMed. 7301 USHORT usPWMHigh; // The PWM value at THigh. 7302 } ATOM_PPLIB_FANTABLE; 7303 7304 typedef struct _ATOM_PPLIB_FANTABLE2 7305 { 7306 ATOM_PPLIB_FANTABLE basicTable; 7307 USHORT usTMax; // The max temperature 7308 } ATOM_PPLIB_FANTABLE2; 7309 7310 typedef struct _ATOM_PPLIB_EXTENDEDHEADER 7311 { 7312 USHORT usSize; 7313 ULONG ulMaxEngineClock; // For Overdrive. 7314 ULONG ulMaxMemoryClock; // For Overdrive. 7315 // Add extra system parameters here, always adjust size to include all fields. 7316 USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table 7317 USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table 7318 } ATOM_PPLIB_EXTENDEDHEADER; 7319 7320 //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps 7321 #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 7322 #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 7323 #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 7324 #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 7325 #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 7326 #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 7327 #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 7328 #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 7329 #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 7330 #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 7331 #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 7332 #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 7333 #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 7334 #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. 7335 #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). 7336 #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. 7337 #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. 7338 #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. 7339 7340 7341 typedef struct _ATOM_PPLIB_POWERPLAYTABLE 7342 { 7343 ATOM_COMMON_TABLE_HEADER sHeader; 7344 7345 UCHAR ucDataRevision; 7346 7347 UCHAR ucNumStates; 7348 UCHAR ucStateEntrySize; 7349 UCHAR ucClockInfoSize; 7350 UCHAR ucNonClockSize; 7351 7352 // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures 7353 USHORT usStateArrayOffset; 7354 7355 // offset from start of this table to array of ASIC-specific structures, 7356 // currently ATOM_PPLIB_CLOCK_INFO. 7357 USHORT usClockInfoArrayOffset; 7358 7359 // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO 7360 USHORT usNonClockInfoArrayOffset; 7361 7362 USHORT usBackbiasTime; // in microseconds 7363 USHORT usVoltageTime; // in microseconds 7364 USHORT usTableSize; //the size of this structure, or the extended structure 7365 7366 ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* 7367 7368 ATOM_PPLIB_THERMALCONTROLLER sThermalController; 7369 7370 USHORT usBootClockInfoOffset; 7371 USHORT usBootNonClockInfoOffset; 7372 7373 } ATOM_PPLIB_POWERPLAYTABLE; 7374 7375 typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 7376 { 7377 ATOM_PPLIB_POWERPLAYTABLE basicTable; 7378 UCHAR ucNumCustomThermalPolicy; 7379 USHORT usCustomThermalPolicyArrayOffset; 7380 }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; 7381 7382 typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 7383 { 7384 ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; 7385 USHORT usFormatID; // To be used ONLY by PPGen. 7386 USHORT usFanTableOffset; 7387 USHORT usExtendendedHeaderOffset; 7388 } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; 7389 7390 typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 7391 { 7392 ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; 7393 ULONG ulGoldenPPID; // PPGen use only 7394 ULONG ulGoldenRevision; // PPGen use only 7395 USHORT usVddcDependencyOnSCLKOffset; 7396 USHORT usVddciDependencyOnMCLKOffset; 7397 USHORT usVddcDependencyOnMCLKOffset; 7398 USHORT usMaxClockVoltageOnDCOffset; 7399 USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table 7400 USHORT usReserved; 7401 } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; 7402 7403 typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 7404 { 7405 ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; 7406 ULONG ulTDPLimit; 7407 ULONG ulNearTDPLimit; 7408 ULONG ulSQRampingThreshold; 7409 USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table 7410 ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table 7411 USHORT usTDPODLimit; 7412 USHORT usLoadLineSlope; // in milliOhms * 100 7413 } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; 7414 7415 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification 7416 #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 7417 #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 7418 #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 7419 #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 7420 #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 7421 #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 7422 // 2, 4, 6, 7 are reserved 7423 7424 #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 7425 #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 7426 #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 7427 #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 7428 #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 7429 #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 7430 #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 7431 #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 7432 #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 7433 #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 7434 #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 7435 #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 7436 #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 7437 7438 //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 7439 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 7440 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 7441 #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) 7442 7443 //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings 7444 #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 7445 #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 7446 7447 // 0 is 2.5Gb/s, 1 is 5Gb/s 7448 #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 7449 #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 7450 7451 // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec 7452 #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 7453 #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 7454 7455 // lookup into reduced refresh-rate table 7456 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 7457 #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 7458 7459 #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 7460 #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 7461 // 2-15 TBD as needed. 7462 7463 #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 7464 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 7465 7466 #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 7467 7468 #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 7469 7470 //memory related flags 7471 #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 7472 7473 //M3 Arb //2bits, current 3 sets of parameters in total 7474 #define ATOM_PPLIB_M3ARB_MASK 0x00060000 7475 #define ATOM_PPLIB_M3ARB_SHIFT 17 7476 7477 #define ATOM_PPLIB_ENABLE_DRR 0x00080000 7478 7479 // remaining 16 bits are reserved 7480 typedef struct _ATOM_PPLIB_THERMAL_STATE 7481 { 7482 UCHAR ucMinTemperature; 7483 UCHAR ucMaxTemperature; 7484 UCHAR ucThermalAction; 7485 }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; 7486 7487 // Contained in an array starting at the offset 7488 // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. 7489 // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex 7490 #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 7491 #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 7492 typedef struct _ATOM_PPLIB_NONCLOCK_INFO 7493 { 7494 USHORT usClassification; 7495 UCHAR ucMinTemperature; 7496 UCHAR ucMaxTemperature; 7497 ULONG ulCapsAndSettings; 7498 UCHAR ucRequiredPower; 7499 USHORT usClassification2; 7500 ULONG ulVCLK; 7501 ULONG ulDCLK; 7502 UCHAR ucUnused[5]; 7503 } ATOM_PPLIB_NONCLOCK_INFO; 7504 7505 // Contained in an array starting at the offset 7506 // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. 7507 // referenced from ATOM_PPLIB_STATE::ucClockStateIndices 7508 typedef struct _ATOM_PPLIB_R600_CLOCK_INFO 7509 { 7510 USHORT usEngineClockLow; 7511 UCHAR ucEngineClockHigh; 7512 7513 USHORT usMemoryClockLow; 7514 UCHAR ucMemoryClockHigh; 7515 7516 USHORT usVDDC; 7517 USHORT usUnused1; 7518 USHORT usUnused2; 7519 7520 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 7521 7522 } ATOM_PPLIB_R600_CLOCK_INFO; 7523 7524 // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO 7525 #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 7526 #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 7527 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 7528 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 7529 #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 7530 #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). 7531 7532 typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO 7533 { 7534 USHORT usEngineClockLow; 7535 UCHAR ucEngineClockHigh; 7536 7537 USHORT usMemoryClockLow; 7538 UCHAR ucMemoryClockHigh; 7539 7540 USHORT usVDDC; 7541 USHORT usVDDCI; 7542 USHORT usUnused; 7543 7544 ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* 7545 7546 } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; 7547 7548 typedef struct _ATOM_PPLIB_SI_CLOCK_INFO 7549 { 7550 USHORT usEngineClockLow; 7551 UCHAR ucEngineClockHigh; 7552 7553 USHORT usMemoryClockLow; 7554 UCHAR ucMemoryClockHigh; 7555 7556 USHORT usVDDC; 7557 USHORT usVDDCI; 7558 UCHAR ucPCIEGen; 7559 UCHAR ucUnused1; 7560 7561 ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now 7562 7563 } ATOM_PPLIB_SI_CLOCK_INFO; 7564 7565 7566 typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO 7567 7568 { 7569 USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). 7570 UCHAR ucLowEngineClockHigh; 7571 USHORT usHighEngineClockLow; // High Engine clock in MHz. 7572 UCHAR ucHighEngineClockHigh; 7573 USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. 7574 UCHAR ucMemoryClockHigh; // Currentyl unused. 7575 UCHAR ucPadding; // For proper alignment and size. 7576 USHORT usVDDC; // For the 780, use: None, Low, High, Variable 7577 UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} 7578 UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. 7579 USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). 7580 ULONG ulFlags; 7581 } ATOM_PPLIB_RS780_CLOCK_INFO; 7582 7583 #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 7584 #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 7585 #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 7586 #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 7587 7588 #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. 7589 #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 7590 #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 7591 7592 #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 7593 #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 7594 #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 7595 7596 typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ 7597 USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz 7598 UCHAR ucEngineClockHigh; //clockfrequency >> 16. 7599 UCHAR vddcIndex; //2-bit vddc index; 7600 USHORT tdpLimit; 7601 //please initalize to 0 7602 USHORT rsv1; 7603 //please initialize to 0s 7604 ULONG rsv2[2]; 7605 }ATOM_PPLIB_SUMO_CLOCK_INFO; 7606 7607 7608 7609 typedef struct _ATOM_PPLIB_STATE_V2 7610 { 7611 //number of valid dpm levels in this state; Driver uses it to calculate the whole 7612 //size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) 7613 UCHAR ucNumDPMLevels; 7614 7615 //a index to the array of nonClockInfos 7616 UCHAR nonClockInfoIndex; 7617 /** 7618 * Driver will read the first ucNumDPMLevels in this array 7619 */ 7620 UCHAR clockInfoIndex[1]; 7621 } ATOM_PPLIB_STATE_V2; 7622 7623 typedef struct _StateArray{ 7624 //how many states we have 7625 UCHAR ucNumEntries; 7626 7627 ATOM_PPLIB_STATE_V2 states[1]; 7628 }StateArray; 7629 7630 7631 typedef struct _ClockInfoArray{ 7632 //how many clock levels we have 7633 UCHAR ucNumEntries; 7634 7635 //sizeof(ATOM_PPLIB_CLOCK_INFO) 7636 UCHAR ucEntrySize; 7637 7638 UCHAR clockInfo[1]; 7639 }ClockInfoArray; 7640 7641 typedef struct _NonClockInfoArray{ 7642 7643 //how many non-clock levels we have. normally should be same as number of states 7644 UCHAR ucNumEntries; 7645 //sizeof(ATOM_PPLIB_NONCLOCK_INFO) 7646 UCHAR ucEntrySize; 7647 7648 ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; 7649 }NonClockInfoArray; 7650 7651 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record 7652 { 7653 USHORT usClockLow; 7654 UCHAR ucClockHigh; 7655 USHORT usVoltage; 7656 }ATOM_PPLIB_Clock_Voltage_Dependency_Record; 7657 7658 typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table 7659 { 7660 UCHAR ucNumEntries; // Number of entries. 7661 ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. 7662 }ATOM_PPLIB_Clock_Voltage_Dependency_Table; 7663 7664 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record 7665 { 7666 USHORT usSclkLow; 7667 UCHAR ucSclkHigh; 7668 USHORT usMclkLow; 7669 UCHAR ucMclkHigh; 7670 USHORT usVddc; 7671 USHORT usVddci; 7672 }ATOM_PPLIB_Clock_Voltage_Limit_Record; 7673 7674 typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table 7675 { 7676 UCHAR ucNumEntries; // Number of entries. 7677 ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. 7678 }ATOM_PPLIB_Clock_Voltage_Limit_Table; 7679 7680 typedef struct _ATOM_PPLIB_CAC_Leakage_Record 7681 { 7682 USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations 7683 ULONG ulLeakageValue; 7684 }ATOM_PPLIB_CAC_Leakage_Record; 7685 7686 typedef struct _ATOM_PPLIB_CAC_Leakage_Table 7687 { 7688 UCHAR ucNumEntries; // Number of entries. 7689 ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. 7690 }ATOM_PPLIB_CAC_Leakage_Table; 7691 7692 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record 7693 { 7694 USHORT usVoltage; 7695 USHORT usSclkLow; 7696 UCHAR ucSclkHigh; 7697 USHORT usMclkLow; 7698 UCHAR ucMclkHigh; 7699 }ATOM_PPLIB_PhaseSheddingLimits_Record; 7700 7701 typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table 7702 { 7703 UCHAR ucNumEntries; // Number of entries. 7704 ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. 7705 }ATOM_PPLIB_PhaseSheddingLimits_Table; 7706 7707 typedef struct _VCEClockInfo{ 7708 USHORT usEVClkLow; 7709 UCHAR ucEVClkHigh; 7710 USHORT usECClkLow; 7711 UCHAR ucECClkHigh; 7712 }VCEClockInfo; 7713 7714 typedef struct _VCEClockInfoArray{ 7715 UCHAR ucNumEntries; 7716 VCEClockInfo entries[1]; 7717 }VCEClockInfoArray; 7718 7719 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record 7720 { 7721 USHORT usVoltage; 7722 UCHAR ucVCEClockInfoIndex; 7723 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; 7724 7725 typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table 7726 { 7727 UCHAR numEntries; 7728 ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; 7729 }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; 7730 7731 typedef struct _ATOM_PPLIB_VCE_State_Record 7732 { 7733 UCHAR ucVCEClockInfoIndex; 7734 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 7735 }ATOM_PPLIB_VCE_State_Record; 7736 7737 typedef struct _ATOM_PPLIB_VCE_State_Table 7738 { 7739 UCHAR numEntries; 7740 ATOM_PPLIB_VCE_State_Record entries[1]; 7741 }ATOM_PPLIB_VCE_State_Table; 7742 7743 7744 typedef struct _ATOM_PPLIB_VCE_Table 7745 { 7746 UCHAR revid; 7747 // VCEClockInfoArray array; 7748 // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; 7749 // ATOM_PPLIB_VCE_State_Table states; 7750 }ATOM_PPLIB_VCE_Table; 7751 7752 7753 typedef struct _UVDClockInfo{ 7754 USHORT usVClkLow; 7755 UCHAR ucVClkHigh; 7756 USHORT usDClkLow; 7757 UCHAR ucDClkHigh; 7758 }UVDClockInfo; 7759 7760 typedef struct _UVDClockInfoArray{ 7761 UCHAR ucNumEntries; 7762 UVDClockInfo entries[1]; 7763 }UVDClockInfoArray; 7764 7765 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record 7766 { 7767 USHORT usVoltage; 7768 UCHAR ucUVDClockInfoIndex; 7769 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; 7770 7771 typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table 7772 { 7773 UCHAR numEntries; 7774 ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; 7775 }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; 7776 7777 typedef struct _ATOM_PPLIB_UVD_State_Record 7778 { 7779 UCHAR ucUVDClockInfoIndex; 7780 UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary 7781 }ATOM_PPLIB_UVD_State_Record; 7782 7783 typedef struct _ATOM_PPLIB_UVD_State_Table 7784 { 7785 UCHAR numEntries; 7786 ATOM_PPLIB_UVD_State_Record entries[1]; 7787 }ATOM_PPLIB_UVD_State_Table; 7788 7789 7790 typedef struct _ATOM_PPLIB_UVD_Table 7791 { 7792 UCHAR revid; 7793 // UVDClockInfoArray array; 7794 // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; 7795 // ATOM_PPLIB_UVD_State_Table states; 7796 }ATOM_PPLIB_UVD_Table; 7797 7798 /**************************************************************************/ 7799 7800 7801 // Following definitions are for compatibility issue in different SW components. 7802 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 7803 #define Object_Info Object_Header 7804 #define AdjustARB_SEQ MC_InitParameter 7805 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 7806 #define ASIC_VDDCI_Info ASIC_ProfilingInfo 7807 #define ASIC_MVDDQ_Info MemoryTrainingInfo 7808 #define SS_Info PPLL_SS_Info 7809 #define ASIC_MVDDC_Info ASIC_InternalSS_Info 7810 #define DispDevicePriorityInfo SaveRestoreInfo 7811 #define DispOutInfo TV_VideoMode 7812 7813 7814 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 7815 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 7816 7817 //New device naming, remove them when both DAL/VBIOS is ready 7818 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7819 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 7820 7821 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 7822 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 7823 7824 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 7825 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 7826 7827 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 7828 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 7829 7830 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 7831 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 7832 7833 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 7834 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 7835 7836 #define ATOM_S0_DFP1I ATOM_S0_DFP1 7837 #define ATOM_S0_DFP1X ATOM_S0_DFP2 7838 7839 #define ATOM_S0_DFP2I 0x00200000L 7840 #define ATOM_S0_DFP2Ib2 0x20 7841 7842 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 7843 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 7844 7845 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 7846 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 7847 7848 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 7849 7850 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 7851 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 7852 7853 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 7854 7855 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 7856 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 7857 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 7858 7859 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 7860 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 7861 7862 #define ATOM_S5_DOS_REQ_DFP2I 0x0200 7863 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 7864 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 7865 7866 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 7867 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 7868 7869 #define TMDS1XEncoderControl DVOEncoderControl 7870 #define DFP1XOutputControl DVOOutputControl 7871 7872 #define ExternalDFPOutputControl DFP1XOutputControl 7873 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 7874 7875 #define DFP1IOutputControl TMDSAOutputControl 7876 #define DFP2IOutputControl LVTMAOutputControl 7877 7878 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7879 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7880 7881 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 7882 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 7883 7884 #define ucDac1Standard ucDacStandard 7885 #define ucDac2Standard ucDacStandard 7886 7887 #define TMDS1EncoderControl TMDSAEncoderControl 7888 #define TMDS2EncoderControl LVTMAEncoderControl 7889 7890 #define DFP1OutputControl TMDSAOutputControl 7891 #define DFP2OutputControl LVTMAOutputControl 7892 #define CRT1OutputControl DAC1OutputControl 7893 #define CRT2OutputControl DAC2OutputControl 7894 7895 //These two lines will be removed for sure in a few days, will follow up with Michael V. 7896 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 7897 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 7898 7899 //#define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7900 //#define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7901 //#define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7902 //#define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7903 //#define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 7904 7905 #define ATOM_S6_ACC_REQ_TV2 0x00400000L 7906 #define ATOM_DEVICE_TV2_INDEX 0x00000006 7907 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 7908 #define ATOM_S0_TV2 0x00100000L 7909 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 7910 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 7911 7912 // 7913 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 7914 #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L 7915 #define ATOM_S2_TV1_DPMS_STATE 0x00040000L 7916 #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L 7917 #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L 7918 #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L 7919 #define ATOM_S2_TV2_DPMS_STATE 0x00400000L 7920 #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L 7921 #define ATOM_S2_CV_DPMS_STATE 0x01000000L 7922 #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L 7923 #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L 7924 #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L 7925 7926 #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 7927 #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 7928 #define ATOM_S2_TV1_DPMS_STATEb2 0x04 7929 #define ATOM_S2_DFP1_DPMS_STATEb2 0x08 7930 #define ATOM_S2_CRT2_DPMS_STATEb2 0x10 7931 #define ATOM_S2_LCD2_DPMS_STATEb2 0x20 7932 #define ATOM_S2_TV2_DPMS_STATEb2 0x40 7933 #define ATOM_S2_DFP2_DPMS_STATEb2 0x80 7934 #define ATOM_S2_CV_DPMS_STATEb3 0x01 7935 #define ATOM_S2_DFP3_DPMS_STATEb3 0x02 7936 #define ATOM_S2_DFP4_DPMS_STATEb3 0x04 7937 #define ATOM_S2_DFP5_DPMS_STATEb3 0x08 7938 7939 #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 7940 #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 7941 #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 7942 7943 /*********************************************************************************/ 7944 7945 #pragma pack() // BIOS data must use byte aligment 7946 7947 // 7948 // AMD ACPI Table 7949 // 7950 #pragma pack(1) 7951 7952 typedef struct { 7953 ULONG Signature; 7954 ULONG TableLength; //Length 7955 UCHAR Revision; 7956 UCHAR Checksum; 7957 UCHAR OemId[6]; 7958 UCHAR OemTableId[8]; //UINT64 OemTableId; 7959 ULONG OemRevision; 7960 ULONG CreatorId; 7961 ULONG CreatorRevision; 7962 } AMD_ACPI_DESCRIPTION_HEADER; 7963 /* 7964 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 7965 typedef struct { 7966 UINT32 Signature; //0x0 7967 UINT32 Length; //0x4 7968 UINT8 Revision; //0x8 7969 UINT8 Checksum; //0x9 7970 UINT8 OemId[6]; //0xA 7971 UINT64 OemTableId; //0x10 7972 UINT32 OemRevision; //0x18 7973 UINT32 CreatorId; //0x1C 7974 UINT32 CreatorRevision; //0x20 7975 }EFI_ACPI_DESCRIPTION_HEADER; 7976 */ 7977 typedef struct { 7978 AMD_ACPI_DESCRIPTION_HEADER SHeader; 7979 UCHAR TableUUID[16]; //0x24 7980 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 7981 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 7982 ULONG Reserved[4]; //0x3C 7983 }UEFI_ACPI_VFCT; 7984 7985 typedef struct { 7986 ULONG PCIBus; //0x4C 7987 ULONG PCIDevice; //0x50 7988 ULONG PCIFunction; //0x54 7989 USHORT VendorID; //0x58 7990 USHORT DeviceID; //0x5A 7991 USHORT SSVID; //0x5C 7992 USHORT SSID; //0x5E 7993 ULONG Revision; //0x60 7994 ULONG ImageLength; //0x64 7995 }VFCT_IMAGE_HEADER; 7996 7997 7998 typedef struct { 7999 VFCT_IMAGE_HEADER VbiosHeader; 8000 UCHAR VbiosContent[1]; 8001 }GOP_VBIOS_CONTENT; 8002 8003 typedef struct { 8004 VFCT_IMAGE_HEADER Lib1Header; 8005 UCHAR Lib1Content[1]; 8006 }GOP_LIB1_CONTENT; 8007 8008 #pragma pack() 8009 8010 8011 #endif /* _ATOMBIOS_H */ 8012