1 /* $OpenBSD: atom.c,v 1.4 2014/06/20 06:50:04 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Stanislaw Skowronek 24 */ 25 26 #define ATOM_DEBUG 27 28 #include "atom.h" 29 #include "atom-names.h" 30 #include "atom-bits.h" 31 #include "radeon.h" 32 33 #define ATOM_COND_ABOVE 0 34 #define ATOM_COND_ABOVEOREQUAL 1 35 #define ATOM_COND_ALWAYS 2 36 #define ATOM_COND_BELOW 3 37 #define ATOM_COND_BELOWOREQUAL 4 38 #define ATOM_COND_EQUAL 5 39 #define ATOM_COND_NOTEQUAL 6 40 41 #define ATOM_PORT_ATI 0 42 #define ATOM_PORT_PCI 1 43 #define ATOM_PORT_SYSIO 2 44 45 #define ATOM_UNIT_MICROSEC 0 46 #define ATOM_UNIT_MILLISEC 1 47 48 #define PLL_INDEX 2 49 #define PLL_DATA 3 50 51 typedef struct { 52 struct atom_context *ctx; 53 uint32_t *ps, *ws; 54 int ps_shift; 55 uint16_t start; 56 unsigned last_jump; 57 unsigned long last_jump_jiffies; 58 bool abort; 59 } atom_exec_context; 60 61 int atom_debug = 0; 62 static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); 63 int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 64 65 static uint32_t atom_arg_mask[8] = 66 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 67 0xFF000000 }; 68 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; 69 70 static int atom_dst_to_src[8][4] = { 71 /* translate destination alignment field to the source alignment encoding */ 72 {0, 0, 0, 0}, 73 {1, 2, 3, 0}, 74 {1, 2, 3, 0}, 75 {1, 2, 3, 0}, 76 {4, 5, 6, 7}, 77 {4, 5, 6, 7}, 78 {4, 5, 6, 7}, 79 {4, 5, 6, 7}, 80 }; 81 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; 82 83 extern int ticks; 84 85 static int debug_depth = 0; 86 #ifdef ATOM_DEBUG 87 static void debug_print_spaces(int n) 88 { 89 while (n--) 90 printf(" "); 91 } 92 93 #ifdef DEBUG 94 #undef DEBUG 95 #endif 96 97 #define DEBUG(...) do if (atom_debug) { printf(__FILE__ __VA_ARGS__); } while (0) 98 #define SDEBUG(...) do if (atom_debug) { printf(__FILE__); debug_print_spaces(debug_depth); printf(__VA_ARGS__); } while (0) 99 #else 100 #define DEBUG(...) do { } while (0) 101 #define SDEBUG(...) do { } while (0) 102 #endif 103 104 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, 105 uint32_t index, uint32_t data) 106 { 107 struct radeon_device *rdev = ctx->card->dev->dev_private; 108 uint32_t temp = 0xCDCDCDCD; 109 110 while (1) 111 switch (CU8(base)) { 112 case ATOM_IIO_NOP: 113 base++; 114 break; 115 case ATOM_IIO_READ: 116 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 117 base += 3; 118 break; 119 case ATOM_IIO_WRITE: 120 if (rdev->family == CHIP_RV515) 121 (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 122 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 123 base += 3; 124 break; 125 case ATOM_IIO_CLEAR: 126 temp &= 127 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 128 CU8(base + 2)); 129 base += 3; 130 break; 131 case ATOM_IIO_SET: 132 temp |= 133 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 134 2); 135 base += 3; 136 break; 137 case ATOM_IIO_MOVE_INDEX: 138 temp &= 139 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 140 CU8(base + 3)); 141 temp |= 142 ((index >> CU8(base + 2)) & 143 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 144 3); 145 base += 4; 146 break; 147 case ATOM_IIO_MOVE_DATA: 148 temp &= 149 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 150 CU8(base + 3)); 151 temp |= 152 ((data >> CU8(base + 2)) & 153 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 154 3); 155 base += 4; 156 break; 157 case ATOM_IIO_MOVE_ATTR: 158 temp &= 159 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 160 CU8(base + 3)); 161 temp |= 162 ((ctx-> 163 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - 164 CU8 165 (base 166 + 167 1)))) 168 << CU8(base + 3); 169 base += 4; 170 break; 171 case ATOM_IIO_END: 172 return temp; 173 default: 174 DRM_INFO("Unknown IIO opcode.\n"); 175 return 0; 176 } 177 } 178 179 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, 180 int *ptr, uint32_t *saved, int print) 181 { 182 uint32_t idx, val = 0xCDCDCDCD, align, arg; 183 struct atom_context *gctx = ctx->ctx; 184 arg = attr & 7; 185 align = (attr >> 3) & 7; 186 switch (arg) { 187 case ATOM_ARG_REG: 188 idx = U16(*ptr); 189 (*ptr) += 2; 190 if (print) 191 DEBUG("REG[0x%04X]", idx); 192 idx += gctx->reg_block; 193 switch (gctx->io_mode) { 194 case ATOM_IO_MM: 195 val = gctx->card->reg_read(gctx->card, idx); 196 break; 197 case ATOM_IO_PCI: 198 DRM_INFO( 199 "PCI registers are not implemented.\n"); 200 return 0; 201 case ATOM_IO_SYSIO: 202 DRM_INFO( 203 "SYSIO registers are not implemented.\n"); 204 return 0; 205 default: 206 if (!(gctx->io_mode & 0x80)) { 207 DRM_INFO( "Bad IO mode.\n"); 208 return 0; 209 } 210 if (!gctx->iio[gctx->io_mode & 0x7F]) { 211 DRM_INFO( 212 "Undefined indirect IO read method %d.\n", 213 gctx->io_mode & 0x7F); 214 return 0; 215 } 216 val = 217 atom_iio_execute(gctx, 218 gctx->iio[gctx->io_mode & 0x7F], 219 idx, 0); 220 } 221 break; 222 case ATOM_ARG_PS: 223 idx = U8(*ptr); 224 (*ptr)++; 225 /* get_unaligned_le32 avoids unaligned accesses from atombios 226 * tables, noticed on a DEC Alpha. */ 227 #ifdef notyet 228 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 229 #else 230 val = le32_to_cpu(ctx->ps[idx]); 231 #endif 232 if (print) 233 DEBUG("PS[0x%02X,0x%04X]", idx, val); 234 break; 235 case ATOM_ARG_WS: 236 idx = U8(*ptr); 237 (*ptr)++; 238 if (print) 239 DEBUG("WS[0x%02X]", idx); 240 switch (idx) { 241 case ATOM_WS_QUOTIENT: 242 val = gctx->divmul[0]; 243 break; 244 case ATOM_WS_REMAINDER: 245 val = gctx->divmul[1]; 246 break; 247 case ATOM_WS_DATAPTR: 248 val = gctx->data_block; 249 break; 250 case ATOM_WS_SHIFT: 251 val = gctx->shift; 252 break; 253 case ATOM_WS_OR_MASK: 254 val = 1 << gctx->shift; 255 break; 256 case ATOM_WS_AND_MASK: 257 val = ~(1 << gctx->shift); 258 break; 259 case ATOM_WS_FB_WINDOW: 260 val = gctx->fb_base; 261 break; 262 case ATOM_WS_ATTRIBUTES: 263 val = gctx->io_attr; 264 break; 265 case ATOM_WS_REGPTR: 266 val = gctx->reg_block; 267 break; 268 default: 269 val = ctx->ws[idx]; 270 } 271 break; 272 case ATOM_ARG_ID: 273 idx = U16(*ptr); 274 (*ptr) += 2; 275 if (print) { 276 if (gctx->data_block) 277 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); 278 else 279 DEBUG("ID[0x%04X]", idx); 280 } 281 val = U32(idx + gctx->data_block); 282 break; 283 case ATOM_ARG_FB: 284 idx = U8(*ptr); 285 (*ptr)++; 286 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 287 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", 288 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 289 val = 0; 290 } else 291 val = gctx->scratch[(gctx->fb_base / 4) + idx]; 292 if (print) 293 DEBUG("FB[0x%02X]", idx); 294 break; 295 case ATOM_ARG_IMM: 296 switch (align) { 297 case ATOM_SRC_DWORD: 298 val = U32(*ptr); 299 (*ptr) += 4; 300 if (print) 301 DEBUG("IMM 0x%08X\n", val); 302 return val; 303 case ATOM_SRC_WORD0: 304 case ATOM_SRC_WORD8: 305 case ATOM_SRC_WORD16: 306 val = U16(*ptr); 307 (*ptr) += 2; 308 if (print) 309 DEBUG("IMM 0x%04X\n", val); 310 return val; 311 case ATOM_SRC_BYTE0: 312 case ATOM_SRC_BYTE8: 313 case ATOM_SRC_BYTE16: 314 case ATOM_SRC_BYTE24: 315 val = U8(*ptr); 316 (*ptr)++; 317 if (print) 318 DEBUG("IMM 0x%02X\n", val); 319 return val; 320 } 321 return 0; 322 case ATOM_ARG_PLL: 323 idx = U8(*ptr); 324 (*ptr)++; 325 if (print) 326 DEBUG("PLL[0x%02X]", idx); 327 val = gctx->card->pll_read(gctx->card, idx); 328 break; 329 case ATOM_ARG_MC: 330 idx = U8(*ptr); 331 (*ptr)++; 332 if (print) 333 DEBUG("MC[0x%02X]", idx); 334 val = gctx->card->mc_read(gctx->card, idx); 335 break; 336 } 337 if (saved) 338 *saved = val; 339 val &= atom_arg_mask[align]; 340 val >>= atom_arg_shift[align]; 341 if (print) 342 switch (align) { 343 case ATOM_SRC_DWORD: 344 DEBUG(".[31:0] -> 0x%08X\n", val); 345 break; 346 case ATOM_SRC_WORD0: 347 DEBUG(".[15:0] -> 0x%04X\n", val); 348 break; 349 case ATOM_SRC_WORD8: 350 DEBUG(".[23:8] -> 0x%04X\n", val); 351 break; 352 case ATOM_SRC_WORD16: 353 DEBUG(".[31:16] -> 0x%04X\n", val); 354 break; 355 case ATOM_SRC_BYTE0: 356 DEBUG(".[7:0] -> 0x%02X\n", val); 357 break; 358 case ATOM_SRC_BYTE8: 359 DEBUG(".[15:8] -> 0x%02X\n", val); 360 break; 361 case ATOM_SRC_BYTE16: 362 DEBUG(".[23:16] -> 0x%02X\n", val); 363 break; 364 case ATOM_SRC_BYTE24: 365 DEBUG(".[31:24] -> 0x%02X\n", val); 366 break; 367 } 368 return val; 369 } 370 371 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) 372 { 373 uint32_t align = (attr >> 3) & 7, arg = attr & 7; 374 switch (arg) { 375 case ATOM_ARG_REG: 376 case ATOM_ARG_ID: 377 (*ptr) += 2; 378 break; 379 case ATOM_ARG_PLL: 380 case ATOM_ARG_MC: 381 case ATOM_ARG_PS: 382 case ATOM_ARG_WS: 383 case ATOM_ARG_FB: 384 (*ptr)++; 385 break; 386 case ATOM_ARG_IMM: 387 switch (align) { 388 case ATOM_SRC_DWORD: 389 (*ptr) += 4; 390 return; 391 case ATOM_SRC_WORD0: 392 case ATOM_SRC_WORD8: 393 case ATOM_SRC_WORD16: 394 (*ptr) += 2; 395 return; 396 case ATOM_SRC_BYTE0: 397 case ATOM_SRC_BYTE8: 398 case ATOM_SRC_BYTE16: 399 case ATOM_SRC_BYTE24: 400 (*ptr)++; 401 return; 402 } 403 return; 404 } 405 } 406 407 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) 408 { 409 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 410 } 411 412 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) 413 { 414 uint32_t val = 0xCDCDCDCD; 415 416 switch (align) { 417 case ATOM_SRC_DWORD: 418 val = U32(*ptr); 419 (*ptr) += 4; 420 break; 421 case ATOM_SRC_WORD0: 422 case ATOM_SRC_WORD8: 423 case ATOM_SRC_WORD16: 424 val = U16(*ptr); 425 (*ptr) += 2; 426 break; 427 case ATOM_SRC_BYTE0: 428 case ATOM_SRC_BYTE8: 429 case ATOM_SRC_BYTE16: 430 case ATOM_SRC_BYTE24: 431 val = U8(*ptr); 432 (*ptr)++; 433 break; 434 } 435 return val; 436 } 437 438 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 439 int *ptr, uint32_t *saved, int print) 440 { 441 return atom_get_src_int(ctx, 442 arg | atom_dst_to_src[(attr >> 3) & 443 7][(attr >> 6) & 3] << 3, 444 ptr, saved, print); 445 } 446 447 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) 448 { 449 atom_skip_src_int(ctx, 450 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 451 3] << 3, ptr); 452 } 453 454 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, 455 int *ptr, uint32_t val, uint32_t saved) 456 { 457 uint32_t align = 458 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = 459 val, idx; 460 struct atom_context *gctx = ctx->ctx; 461 old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; 462 val <<= atom_arg_shift[align]; 463 val &= atom_arg_mask[align]; 464 saved &= ~atom_arg_mask[align]; 465 val |= saved; 466 switch (arg) { 467 case ATOM_ARG_REG: 468 idx = U16(*ptr); 469 (*ptr) += 2; 470 DEBUG("REG[0x%04X]", idx); 471 idx += gctx->reg_block; 472 switch (gctx->io_mode) { 473 case ATOM_IO_MM: 474 if (idx == 0) 475 gctx->card->reg_write(gctx->card, idx, 476 val << 2); 477 else 478 gctx->card->reg_write(gctx->card, idx, val); 479 break; 480 case ATOM_IO_PCI: 481 DRM_INFO( 482 "PCI registers are not implemented.\n"); 483 return; 484 case ATOM_IO_SYSIO: 485 DRM_INFO( 486 "SYSIO registers are not implemented.\n"); 487 return; 488 default: 489 if (!(gctx->io_mode & 0x80)) { 490 DRM_INFO( "Bad IO mode.\n"); 491 return; 492 } 493 if (!gctx->iio[gctx->io_mode & 0xFF]) { 494 DRM_INFO( 495 "Undefined indirect IO write method %d.\n", 496 gctx->io_mode & 0x7F); 497 return; 498 } 499 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], 500 idx, val); 501 } 502 break; 503 case ATOM_ARG_PS: 504 idx = U8(*ptr); 505 (*ptr)++; 506 DEBUG("PS[0x%02X]", idx); 507 ctx->ps[idx] = cpu_to_le32(val); 508 break; 509 case ATOM_ARG_WS: 510 idx = U8(*ptr); 511 (*ptr)++; 512 DEBUG("WS[0x%02X]", idx); 513 switch (idx) { 514 case ATOM_WS_QUOTIENT: 515 gctx->divmul[0] = val; 516 break; 517 case ATOM_WS_REMAINDER: 518 gctx->divmul[1] = val; 519 break; 520 case ATOM_WS_DATAPTR: 521 gctx->data_block = val; 522 break; 523 case ATOM_WS_SHIFT: 524 gctx->shift = val; 525 break; 526 case ATOM_WS_OR_MASK: 527 case ATOM_WS_AND_MASK: 528 break; 529 case ATOM_WS_FB_WINDOW: 530 gctx->fb_base = val; 531 break; 532 case ATOM_WS_ATTRIBUTES: 533 gctx->io_attr = val; 534 break; 535 case ATOM_WS_REGPTR: 536 gctx->reg_block = val; 537 break; 538 default: 539 ctx->ws[idx] = val; 540 } 541 break; 542 case ATOM_ARG_FB: 543 idx = U8(*ptr); 544 (*ptr)++; 545 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 546 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", 547 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 548 } else 549 gctx->scratch[(gctx->fb_base / 4) + idx] = val; 550 DEBUG("FB[0x%02X]", idx); 551 break; 552 case ATOM_ARG_PLL: 553 idx = U8(*ptr); 554 (*ptr)++; 555 DEBUG("PLL[0x%02X]", idx); 556 gctx->card->pll_write(gctx->card, idx, val); 557 break; 558 case ATOM_ARG_MC: 559 idx = U8(*ptr); 560 (*ptr)++; 561 DEBUG("MC[0x%02X]", idx); 562 gctx->card->mc_write(gctx->card, idx, val); 563 return; 564 } 565 switch (align) { 566 case ATOM_SRC_DWORD: 567 DEBUG(".[31:0] <- 0x%08X\n", old_val); 568 break; 569 case ATOM_SRC_WORD0: 570 DEBUG(".[15:0] <- 0x%04X\n", old_val); 571 break; 572 case ATOM_SRC_WORD8: 573 DEBUG(".[23:8] <- 0x%04X\n", old_val); 574 break; 575 case ATOM_SRC_WORD16: 576 DEBUG(".[31:16] <- 0x%04X\n", old_val); 577 break; 578 case ATOM_SRC_BYTE0: 579 DEBUG(".[7:0] <- 0x%02X\n", old_val); 580 break; 581 case ATOM_SRC_BYTE8: 582 DEBUG(".[15:8] <- 0x%02X\n", old_val); 583 break; 584 case ATOM_SRC_BYTE16: 585 DEBUG(".[23:16] <- 0x%02X\n", old_val); 586 break; 587 case ATOM_SRC_BYTE24: 588 DEBUG(".[31:24] <- 0x%02X\n", old_val); 589 break; 590 } 591 } 592 593 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) 594 { 595 uint8_t attr = U8((*ptr)++); 596 uint32_t dst, src, saved; 597 int dptr = *ptr; 598 SDEBUG(" dst: "); 599 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 600 SDEBUG(" src: "); 601 src = atom_get_src(ctx, attr, ptr); 602 dst += src; 603 SDEBUG(" dst: "); 604 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 605 } 606 607 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) 608 { 609 uint8_t attr = U8((*ptr)++); 610 uint32_t dst, src, saved; 611 int dptr = *ptr; 612 SDEBUG(" dst: "); 613 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 614 SDEBUG(" src: "); 615 src = atom_get_src(ctx, attr, ptr); 616 dst &= src; 617 SDEBUG(" dst: "); 618 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 619 } 620 621 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) 622 { 623 printf("ATOM BIOS beeped!\n"); 624 } 625 626 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) 627 { 628 int idx = U8((*ptr)++); 629 int r = 0; 630 631 if (idx < ATOM_TABLE_NAMES_CNT) 632 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); 633 else 634 SDEBUG(" table: %d\n", idx); 635 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 636 r = atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 637 if (r) { 638 ctx->abort = true; 639 } 640 } 641 642 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 643 { 644 uint8_t attr = U8((*ptr)++); 645 uint32_t saved; 646 int dptr = *ptr; 647 attr &= 0x38; 648 attr |= atom_def_dst[attr >> 3] << 6; 649 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 650 SDEBUG(" dst: "); 651 atom_put_dst(ctx, arg, attr, &dptr, 0, saved); 652 } 653 654 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 655 { 656 uint8_t attr = U8((*ptr)++); 657 uint32_t dst, src; 658 SDEBUG(" src1: "); 659 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 660 SDEBUG(" src2: "); 661 src = atom_get_src(ctx, attr, ptr); 662 ctx->ctx->cs_equal = (dst == src); 663 ctx->ctx->cs_above = (dst > src); 664 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", 665 ctx->ctx->cs_above ? "GT" : "LE"); 666 } 667 668 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 669 { 670 unsigned count = U8((*ptr)++); 671 SDEBUG(" count: %d\n", count); 672 if (arg == ATOM_UNIT_MICROSEC) 673 udelay(count); 674 else if (!drm_can_sleep()) 675 mdelay(count); 676 else 677 drm_msleep(count, "atomop"); 678 } 679 680 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 681 { 682 uint8_t attr = U8((*ptr)++); 683 uint32_t dst, src; 684 SDEBUG(" src1: "); 685 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 686 SDEBUG(" src2: "); 687 src = atom_get_src(ctx, attr, ptr); 688 if (src != 0) { 689 ctx->ctx->divmul[0] = dst / src; 690 ctx->ctx->divmul[1] = dst % src; 691 } else { 692 ctx->ctx->divmul[0] = 0; 693 ctx->ctx->divmul[1] = 0; 694 } 695 } 696 697 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) 698 { 699 /* functionally, a nop */ 700 } 701 702 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) 703 { 704 int execute = 0, target = U16(*ptr); 705 unsigned long cjiffies; 706 707 (*ptr) += 2; 708 switch (arg) { 709 case ATOM_COND_ABOVE: 710 execute = ctx->ctx->cs_above; 711 break; 712 case ATOM_COND_ABOVEOREQUAL: 713 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; 714 break; 715 case ATOM_COND_ALWAYS: 716 execute = 1; 717 break; 718 case ATOM_COND_BELOW: 719 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); 720 break; 721 case ATOM_COND_BELOWOREQUAL: 722 execute = !ctx->ctx->cs_above; 723 break; 724 case ATOM_COND_EQUAL: 725 execute = ctx->ctx->cs_equal; 726 break; 727 case ATOM_COND_NOTEQUAL: 728 execute = !ctx->ctx->cs_equal; 729 break; 730 } 731 if (arg != ATOM_COND_ALWAYS) 732 SDEBUG(" taken: %s\n", execute ? "yes" : "no"); 733 SDEBUG(" target: 0x%04X\n", target); 734 if (execute) { 735 if (ctx->last_jump == (ctx->start + target)) { 736 cjiffies = ticks; 737 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 738 cjiffies -= ctx->last_jump_jiffies; 739 if ((jiffies_to_msecs(cjiffies) > 5000)) { 740 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n"); 741 ctx->abort = true; 742 } 743 } else { 744 /* jiffies wrap around we will just wait a little longer */ 745 ctx->last_jump_jiffies = ticks; 746 } 747 } else { 748 ctx->last_jump = ctx->start + target; 749 ctx->last_jump_jiffies = ticks; 750 } 751 *ptr = ctx->start + target; 752 } 753 } 754 755 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) 756 { 757 uint8_t attr = U8((*ptr)++); 758 uint32_t dst, mask, src, saved; 759 int dptr = *ptr; 760 SDEBUG(" dst: "); 761 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 762 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); 763 SDEBUG(" mask: 0x%08x", mask); 764 SDEBUG(" src: "); 765 src = atom_get_src(ctx, attr, ptr); 766 dst &= mask; 767 dst |= src; 768 SDEBUG(" dst: "); 769 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 770 } 771 772 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) 773 { 774 uint8_t attr = U8((*ptr)++); 775 uint32_t src, saved; 776 int dptr = *ptr; 777 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) 778 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 779 else { 780 atom_skip_dst(ctx, arg, attr, ptr); 781 saved = 0xCDCDCDCD; 782 } 783 SDEBUG(" src: "); 784 src = atom_get_src(ctx, attr, ptr); 785 SDEBUG(" dst: "); 786 atom_put_dst(ctx, arg, attr, &dptr, src, saved); 787 } 788 789 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) 790 { 791 uint8_t attr = U8((*ptr)++); 792 uint32_t dst, src; 793 SDEBUG(" src1: "); 794 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 795 SDEBUG(" src2: "); 796 src = atom_get_src(ctx, attr, ptr); 797 ctx->ctx->divmul[0] = dst * src; 798 } 799 800 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) 801 { 802 /* nothing */ 803 } 804 805 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) 806 { 807 uint8_t attr = U8((*ptr)++); 808 uint32_t dst, src, saved; 809 int dptr = *ptr; 810 SDEBUG(" dst: "); 811 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 812 SDEBUG(" src: "); 813 src = atom_get_src(ctx, attr, ptr); 814 dst |= src; 815 SDEBUG(" dst: "); 816 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 817 } 818 819 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) 820 { 821 uint8_t val = U8((*ptr)++); 822 SDEBUG("POST card output: 0x%02X\n", val); 823 } 824 825 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) 826 { 827 DRM_INFO( "unimplemented!\n"); 828 } 829 830 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) 831 { 832 DRM_INFO( "unimplemented!\n"); 833 } 834 835 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) 836 { 837 DRM_INFO( "unimplemented!\n"); 838 } 839 840 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) 841 { 842 int idx = U8(*ptr); 843 (*ptr)++; 844 SDEBUG(" block: %d\n", idx); 845 if (!idx) 846 ctx->ctx->data_block = 0; 847 else if (idx == 255) 848 ctx->ctx->data_block = ctx->start; 849 else 850 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); 851 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); 852 } 853 854 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) 855 { 856 uint8_t attr = U8((*ptr)++); 857 SDEBUG(" fb_base: "); 858 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); 859 } 860 861 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) 862 { 863 int port; 864 switch (arg) { 865 case ATOM_PORT_ATI: 866 port = U16(*ptr); 867 if (port < ATOM_IO_NAMES_CNT) 868 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); 869 else 870 SDEBUG(" port: %d\n", port); 871 if (!port) 872 ctx->ctx->io_mode = ATOM_IO_MM; 873 else 874 ctx->ctx->io_mode = ATOM_IO_IIO | port; 875 (*ptr) += 2; 876 break; 877 case ATOM_PORT_PCI: 878 ctx->ctx->io_mode = ATOM_IO_PCI; 879 (*ptr)++; 880 break; 881 case ATOM_PORT_SYSIO: 882 ctx->ctx->io_mode = ATOM_IO_SYSIO; 883 (*ptr)++; 884 break; 885 } 886 } 887 888 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) 889 { 890 ctx->ctx->reg_block = U16(*ptr); 891 (*ptr) += 2; 892 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 893 } 894 895 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) 896 { 897 uint8_t attr = U8((*ptr)++), shift; 898 uint32_t saved, dst; 899 int dptr = *ptr; 900 attr &= 0x38; 901 attr |= atom_def_dst[attr >> 3] << 6; 902 SDEBUG(" dst: "); 903 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 904 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 905 SDEBUG(" shift: %d\n", shift); 906 dst <<= shift; 907 SDEBUG(" dst: "); 908 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 909 } 910 911 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) 912 { 913 uint8_t attr = U8((*ptr)++), shift; 914 uint32_t saved, dst; 915 int dptr = *ptr; 916 attr &= 0x38; 917 attr |= atom_def_dst[attr >> 3] << 6; 918 SDEBUG(" dst: "); 919 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 920 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 921 SDEBUG(" shift: %d\n", shift); 922 dst >>= shift; 923 SDEBUG(" dst: "); 924 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 925 } 926 927 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 928 { 929 uint8_t attr = U8((*ptr)++), shift; 930 uint32_t saved, dst; 931 int dptr = *ptr; 932 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 933 SDEBUG(" dst: "); 934 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 935 /* op needs to full dst value */ 936 dst = saved; 937 shift = atom_get_src(ctx, attr, ptr); 938 SDEBUG(" shift: %d\n", shift); 939 dst <<= shift; 940 dst &= atom_arg_mask[dst_align]; 941 dst >>= atom_arg_shift[dst_align]; 942 SDEBUG(" dst: "); 943 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 944 } 945 946 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) 947 { 948 uint8_t attr = U8((*ptr)++), shift; 949 uint32_t saved, dst; 950 int dptr = *ptr; 951 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 952 SDEBUG(" dst: "); 953 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 954 /* op needs to full dst value */ 955 dst = saved; 956 shift = atom_get_src(ctx, attr, ptr); 957 SDEBUG(" shift: %d\n", shift); 958 dst >>= shift; 959 dst &= atom_arg_mask[dst_align]; 960 dst >>= atom_arg_shift[dst_align]; 961 SDEBUG(" dst: "); 962 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 963 } 964 965 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) 966 { 967 uint8_t attr = U8((*ptr)++); 968 uint32_t dst, src, saved; 969 int dptr = *ptr; 970 SDEBUG(" dst: "); 971 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 972 SDEBUG(" src: "); 973 src = atom_get_src(ctx, attr, ptr); 974 dst -= src; 975 SDEBUG(" dst: "); 976 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 977 } 978 979 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) 980 { 981 uint8_t attr = U8((*ptr)++); 982 uint32_t src, val, target; 983 SDEBUG(" switch: "); 984 src = atom_get_src(ctx, attr, ptr); 985 while (U16(*ptr) != ATOM_CASE_END) 986 if (U8(*ptr) == ATOM_CASE_MAGIC) { 987 (*ptr)++; 988 SDEBUG(" case: "); 989 val = 990 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, 991 ptr); 992 target = U16(*ptr); 993 if (val == src) { 994 SDEBUG(" target: %04X\n", target); 995 *ptr = ctx->start + target; 996 return; 997 } 998 (*ptr) += 2; 999 } else { 1000 DRM_INFO( "Bad case.\n"); 1001 return; 1002 } 1003 (*ptr) += 2; 1004 } 1005 1006 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) 1007 { 1008 uint8_t attr = U8((*ptr)++); 1009 uint32_t dst, src; 1010 SDEBUG(" src1: "); 1011 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 1012 SDEBUG(" src2: "); 1013 src = atom_get_src(ctx, attr, ptr); 1014 ctx->ctx->cs_equal = ((dst & src) == 0); 1015 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); 1016 } 1017 1018 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) 1019 { 1020 uint8_t attr = U8((*ptr)++); 1021 uint32_t dst, src, saved; 1022 int dptr = *ptr; 1023 SDEBUG(" dst: "); 1024 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1025 SDEBUG(" src: "); 1026 src = atom_get_src(ctx, attr, ptr); 1027 dst ^= src; 1028 SDEBUG(" dst: "); 1029 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1030 } 1031 1032 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) 1033 { 1034 DRM_INFO( "unimplemented!\n"); 1035 } 1036 1037 static struct { 1038 void (*func) (atom_exec_context *, int *, int); 1039 int arg; 1040 } opcode_table[ATOM_OP_CNT] = { 1041 { 1042 NULL, 0}, { 1043 atom_op_move, ATOM_ARG_REG}, { 1044 atom_op_move, ATOM_ARG_PS}, { 1045 atom_op_move, ATOM_ARG_WS}, { 1046 atom_op_move, ATOM_ARG_FB}, { 1047 atom_op_move, ATOM_ARG_PLL}, { 1048 atom_op_move, ATOM_ARG_MC}, { 1049 atom_op_and, ATOM_ARG_REG}, { 1050 atom_op_and, ATOM_ARG_PS}, { 1051 atom_op_and, ATOM_ARG_WS}, { 1052 atom_op_and, ATOM_ARG_FB}, { 1053 atom_op_and, ATOM_ARG_PLL}, { 1054 atom_op_and, ATOM_ARG_MC}, { 1055 atom_op_or, ATOM_ARG_REG}, { 1056 atom_op_or, ATOM_ARG_PS}, { 1057 atom_op_or, ATOM_ARG_WS}, { 1058 atom_op_or, ATOM_ARG_FB}, { 1059 atom_op_or, ATOM_ARG_PLL}, { 1060 atom_op_or, ATOM_ARG_MC}, { 1061 atom_op_shift_left, ATOM_ARG_REG}, { 1062 atom_op_shift_left, ATOM_ARG_PS}, { 1063 atom_op_shift_left, ATOM_ARG_WS}, { 1064 atom_op_shift_left, ATOM_ARG_FB}, { 1065 atom_op_shift_left, ATOM_ARG_PLL}, { 1066 atom_op_shift_left, ATOM_ARG_MC}, { 1067 atom_op_shift_right, ATOM_ARG_REG}, { 1068 atom_op_shift_right, ATOM_ARG_PS}, { 1069 atom_op_shift_right, ATOM_ARG_WS}, { 1070 atom_op_shift_right, ATOM_ARG_FB}, { 1071 atom_op_shift_right, ATOM_ARG_PLL}, { 1072 atom_op_shift_right, ATOM_ARG_MC}, { 1073 atom_op_mul, ATOM_ARG_REG}, { 1074 atom_op_mul, ATOM_ARG_PS}, { 1075 atom_op_mul, ATOM_ARG_WS}, { 1076 atom_op_mul, ATOM_ARG_FB}, { 1077 atom_op_mul, ATOM_ARG_PLL}, { 1078 atom_op_mul, ATOM_ARG_MC}, { 1079 atom_op_div, ATOM_ARG_REG}, { 1080 atom_op_div, ATOM_ARG_PS}, { 1081 atom_op_div, ATOM_ARG_WS}, { 1082 atom_op_div, ATOM_ARG_FB}, { 1083 atom_op_div, ATOM_ARG_PLL}, { 1084 atom_op_div, ATOM_ARG_MC}, { 1085 atom_op_add, ATOM_ARG_REG}, { 1086 atom_op_add, ATOM_ARG_PS}, { 1087 atom_op_add, ATOM_ARG_WS}, { 1088 atom_op_add, ATOM_ARG_FB}, { 1089 atom_op_add, ATOM_ARG_PLL}, { 1090 atom_op_add, ATOM_ARG_MC}, { 1091 atom_op_sub, ATOM_ARG_REG}, { 1092 atom_op_sub, ATOM_ARG_PS}, { 1093 atom_op_sub, ATOM_ARG_WS}, { 1094 atom_op_sub, ATOM_ARG_FB}, { 1095 atom_op_sub, ATOM_ARG_PLL}, { 1096 atom_op_sub, ATOM_ARG_MC}, { 1097 atom_op_setport, ATOM_PORT_ATI}, { 1098 atom_op_setport, ATOM_PORT_PCI}, { 1099 atom_op_setport, ATOM_PORT_SYSIO}, { 1100 atom_op_setregblock, 0}, { 1101 atom_op_setfbbase, 0}, { 1102 atom_op_compare, ATOM_ARG_REG}, { 1103 atom_op_compare, ATOM_ARG_PS}, { 1104 atom_op_compare, ATOM_ARG_WS}, { 1105 atom_op_compare, ATOM_ARG_FB}, { 1106 atom_op_compare, ATOM_ARG_PLL}, { 1107 atom_op_compare, ATOM_ARG_MC}, { 1108 atom_op_switch, 0}, { 1109 atom_op_jump, ATOM_COND_ALWAYS}, { 1110 atom_op_jump, ATOM_COND_EQUAL}, { 1111 atom_op_jump, ATOM_COND_BELOW}, { 1112 atom_op_jump, ATOM_COND_ABOVE}, { 1113 atom_op_jump, ATOM_COND_BELOWOREQUAL}, { 1114 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { 1115 atom_op_jump, ATOM_COND_NOTEQUAL}, { 1116 atom_op_test, ATOM_ARG_REG}, { 1117 atom_op_test, ATOM_ARG_PS}, { 1118 atom_op_test, ATOM_ARG_WS}, { 1119 atom_op_test, ATOM_ARG_FB}, { 1120 atom_op_test, ATOM_ARG_PLL}, { 1121 atom_op_test, ATOM_ARG_MC}, { 1122 atom_op_delay, ATOM_UNIT_MILLISEC}, { 1123 atom_op_delay, ATOM_UNIT_MICROSEC}, { 1124 atom_op_calltable, 0}, { 1125 atom_op_repeat, 0}, { 1126 atom_op_clear, ATOM_ARG_REG}, { 1127 atom_op_clear, ATOM_ARG_PS}, { 1128 atom_op_clear, ATOM_ARG_WS}, { 1129 atom_op_clear, ATOM_ARG_FB}, { 1130 atom_op_clear, ATOM_ARG_PLL}, { 1131 atom_op_clear, ATOM_ARG_MC}, { 1132 atom_op_nop, 0}, { 1133 atom_op_eot, 0}, { 1134 atom_op_mask, ATOM_ARG_REG}, { 1135 atom_op_mask, ATOM_ARG_PS}, { 1136 atom_op_mask, ATOM_ARG_WS}, { 1137 atom_op_mask, ATOM_ARG_FB}, { 1138 atom_op_mask, ATOM_ARG_PLL}, { 1139 atom_op_mask, ATOM_ARG_MC}, { 1140 atom_op_postcard, 0}, { 1141 atom_op_beep, 0}, { 1142 atom_op_savereg, 0}, { 1143 atom_op_restorereg, 0}, { 1144 atom_op_setdatablock, 0}, { 1145 atom_op_xor, ATOM_ARG_REG}, { 1146 atom_op_xor, ATOM_ARG_PS}, { 1147 atom_op_xor, ATOM_ARG_WS}, { 1148 atom_op_xor, ATOM_ARG_FB}, { 1149 atom_op_xor, ATOM_ARG_PLL}, { 1150 atom_op_xor, ATOM_ARG_MC}, { 1151 atom_op_shl, ATOM_ARG_REG}, { 1152 atom_op_shl, ATOM_ARG_PS}, { 1153 atom_op_shl, ATOM_ARG_WS}, { 1154 atom_op_shl, ATOM_ARG_FB}, { 1155 atom_op_shl, ATOM_ARG_PLL}, { 1156 atom_op_shl, ATOM_ARG_MC}, { 1157 atom_op_shr, ATOM_ARG_REG}, { 1158 atom_op_shr, ATOM_ARG_PS}, { 1159 atom_op_shr, ATOM_ARG_WS}, { 1160 atom_op_shr, ATOM_ARG_FB}, { 1161 atom_op_shr, ATOM_ARG_PLL}, { 1162 atom_op_shr, ATOM_ARG_MC}, { 1163 atom_op_debug, 0},}; 1164 1165 static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) 1166 { 1167 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1168 int len, ws, ps, ptr; 1169 unsigned char op; 1170 atom_exec_context ectx; 1171 int ret = 0; 1172 1173 if (!base) 1174 return -EINVAL; 1175 1176 len = CU16(base + ATOM_CT_SIZE_PTR); 1177 ws = CU8(base + ATOM_CT_WS_PTR); 1178 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1179 ptr = base + ATOM_CT_CODE_PTR; 1180 1181 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1182 1183 ectx.ctx = ctx; 1184 ectx.ps_shift = ps / 4; 1185 ectx.start = base; 1186 ectx.ps = params; 1187 ectx.abort = false; 1188 ectx.last_jump = 0; 1189 if (ws) 1190 ectx.ws = kzalloc(4 * ws, GFP_KERNEL); 1191 else 1192 ectx.ws = NULL; 1193 1194 debug_depth++; 1195 while (1) { 1196 op = CU8(ptr++); 1197 if (op < ATOM_OP_NAMES_CNT) 1198 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); 1199 else 1200 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); 1201 if (ectx.abort) { 1202 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1203 base, len, ws, ps, ptr - 1); 1204 ret = -EINVAL; 1205 goto free; 1206 } 1207 1208 if (op < ATOM_OP_CNT && op > 0) 1209 opcode_table[op].func(&ectx, &ptr, 1210 opcode_table[op].arg); 1211 else 1212 break; 1213 1214 if (op == ATOM_OP_EOT) 1215 break; 1216 } 1217 debug_depth--; 1218 SDEBUG("<<\n"); 1219 1220 free: 1221 if (ws) 1222 kfree(ectx.ws); 1223 return ret; 1224 } 1225 1226 int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1227 { 1228 int r; 1229 1230 rw_enter_write(&ctx->rwlock); 1231 /* reset data block */ 1232 ctx->data_block = 0; 1233 /* reset reg block */ 1234 ctx->reg_block = 0; 1235 /* reset fb window */ 1236 ctx->fb_base = 0; 1237 /* reset io mode */ 1238 ctx->io_mode = ATOM_IO_MM; 1239 /* reset divmul */ 1240 ctx->divmul[0] = 0; 1241 ctx->divmul[1] = 0; 1242 r = atom_execute_table_locked(ctx, index, params); 1243 rw_exit_write(&ctx->rwlock); 1244 return r; 1245 } 1246 1247 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1248 1249 static void atom_index_iio(struct atom_context *ctx, int base) 1250 { 1251 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); 1252 while (CU8(base) == ATOM_IIO_START) { 1253 ctx->iio[CU8(base + 1)] = base + 2; 1254 base += 2; 1255 while (CU8(base) != ATOM_IIO_END) 1256 base += atom_iio_len[CU8(base)]; 1257 base += 3; 1258 } 1259 } 1260 1261 struct atom_context *atom_parse(struct card_info *card, void *bios) 1262 { 1263 int base; 1264 struct atom_context *ctx = 1265 kzalloc(sizeof(struct atom_context), GFP_KERNEL); 1266 #ifdef DRMDEBUG 1267 char *str; 1268 char name[512]; 1269 int i; 1270 #endif 1271 1272 if (!ctx) 1273 return NULL; 1274 1275 ctx->card = card; 1276 ctx->bios = bios; 1277 1278 if (CU16(0) != ATOM_BIOS_MAGIC) { 1279 DRM_INFO( "Invalid BIOS magic.\n"); 1280 kfree(ctx); 1281 return NULL; 1282 } 1283 if (strncmp 1284 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, 1285 strlen(ATOM_ATI_MAGIC))) { 1286 DRM_INFO( "Invalid ATI magic.\n"); 1287 kfree(ctx); 1288 return NULL; 1289 } 1290 1291 base = CU16(ATOM_ROM_TABLE_PTR); 1292 if (strncmp 1293 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, 1294 strlen(ATOM_ROM_MAGIC))) { 1295 DRM_INFO( "Invalid ATOM magic.\n"); 1296 kfree(ctx); 1297 return NULL; 1298 } 1299 1300 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); 1301 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); 1302 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); 1303 1304 #ifdef DRMDEBUG 1305 str = CSTR(CU16(base + ATOM_ROM_MSG_PTR)); 1306 while (*str && ((*str == '\n') || (*str == '\r'))) 1307 str++; 1308 /* name string isn't always 0 terminated */ 1309 for (i = 0; i < 511; i++) { 1310 name[i] = str[i]; 1311 if (name[i] < '.' || name[i] > 'z') { 1312 name[i] = 0; 1313 break; 1314 } 1315 } 1316 DRM_INFO( "ATOM BIOS: %s\n", name); 1317 #endif 1318 1319 return ctx; 1320 } 1321 1322 int atom_asic_init(struct atom_context *ctx) 1323 { 1324 struct radeon_device *rdev = ctx->card->dev->dev_private; 1325 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); 1326 uint32_t ps[16]; 1327 int ret; 1328 1329 memset(ps, 0, 64); 1330 1331 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); 1332 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); 1333 if (!ps[0] || !ps[1]) 1334 return 1; 1335 1336 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) 1337 return 1; 1338 ret = atom_execute_table(ctx, ATOM_CMD_INIT, ps); 1339 if (ret) 1340 return ret; 1341 1342 memset(ps, 0, 64); 1343 1344 if (rdev->family < CHIP_R600) { 1345 if (CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_SPDFANCNTL)) 1346 atom_execute_table(ctx, ATOM_CMD_SPDFANCNTL, ps); 1347 } 1348 return ret; 1349 } 1350 1351 void atom_destroy(struct atom_context *ctx) 1352 { 1353 if (ctx->iio) 1354 kfree(ctx->iio); 1355 kfree(ctx); 1356 } 1357 1358 bool atom_parse_data_header(struct atom_context *ctx, int index, 1359 uint16_t * size, uint8_t * frev, uint8_t * crev, 1360 uint16_t * data_start) 1361 { 1362 int offset = index * 2 + 4; 1363 int idx = CU16(ctx->data_table + offset); 1364 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); 1365 1366 if (!mdt[index]) 1367 return false; 1368 1369 if (size) 1370 *size = CU16(idx); 1371 if (frev) 1372 *frev = CU8(idx + 2); 1373 if (crev) 1374 *crev = CU8(idx + 3); 1375 *data_start = idx; 1376 return true; 1377 } 1378 1379 bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, 1380 uint8_t * crev) 1381 { 1382 int offset = index * 2 + 4; 1383 int idx = CU16(ctx->cmd_table + offset); 1384 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); 1385 1386 if (!mct[index]) 1387 return false; 1388 1389 if (frev) 1390 *frev = CU8(idx + 2); 1391 if (crev) 1392 *crev = CU8(idx + 3); 1393 return true; 1394 } 1395 1396 int atom_allocate_fb_scratch(struct atom_context *ctx) 1397 { 1398 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); 1399 uint16_t data_offset; 1400 int usage_bytes = 0; 1401 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; 1402 1403 if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 1404 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); 1405 1406 DRM_DEBUG("atom firmware requested %08x %dkb\n", 1407 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), 1408 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); 1409 1410 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; 1411 } 1412 ctx->scratch_size_bytes = 0; 1413 if (usage_bytes == 0) 1414 usage_bytes = 20 * 1024; 1415 /* allocate some scratch memory */ 1416 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 1417 if (!ctx->scratch) 1418 return -ENOMEM; 1419 ctx->scratch_size_bytes = usage_bytes; 1420 return 0; 1421 } 1422