1 /* $OpenBSD: atom.c,v 1.3 2014/02/09 11:03:31 jsg Exp $ */ 2 /* 3 * Copyright 2008 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Stanislaw Skowronek 24 */ 25 26 #define ATOM_DEBUG 27 28 #include "atom.h" 29 #include "atom-names.h" 30 #include "atom-bits.h" 31 #include "radeon.h" 32 33 #define ATOM_COND_ABOVE 0 34 #define ATOM_COND_ABOVEOREQUAL 1 35 #define ATOM_COND_ALWAYS 2 36 #define ATOM_COND_BELOW 3 37 #define ATOM_COND_BELOWOREQUAL 4 38 #define ATOM_COND_EQUAL 5 39 #define ATOM_COND_NOTEQUAL 6 40 41 #define ATOM_PORT_ATI 0 42 #define ATOM_PORT_PCI 1 43 #define ATOM_PORT_SYSIO 2 44 45 #define ATOM_UNIT_MICROSEC 0 46 #define ATOM_UNIT_MILLISEC 1 47 48 #define PLL_INDEX 2 49 #define PLL_DATA 3 50 51 typedef struct { 52 struct atom_context *ctx; 53 uint32_t *ps, *ws; 54 int ps_shift; 55 uint16_t start; 56 unsigned last_jump; 57 unsigned long last_jump_jiffies; 58 bool abort; 59 } atom_exec_context; 60 61 int atom_debug = 0; 62 static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); 63 int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 64 65 static uint32_t atom_arg_mask[8] = 66 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 67 0xFF000000 }; 68 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; 69 70 static int atom_dst_to_src[8][4] = { 71 /* translate destination alignment field to the source alignment encoding */ 72 {0, 0, 0, 0}, 73 {1, 2, 3, 0}, 74 {1, 2, 3, 0}, 75 {1, 2, 3, 0}, 76 {4, 5, 6, 7}, 77 {4, 5, 6, 7}, 78 {4, 5, 6, 7}, 79 {4, 5, 6, 7}, 80 }; 81 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; 82 83 extern int ticks; 84 85 static int debug_depth = 0; 86 #ifdef ATOM_DEBUG 87 static void debug_print_spaces(int n) 88 { 89 while (n--) 90 printf(" "); 91 } 92 93 #define DEBUG(...) do if (atom_debug) { printf(__FILE__ __VA_ARGS__); } while (0) 94 #define SDEBUG(...) do if (atom_debug) { printf(__FILE__); debug_print_spaces(debug_depth); printf(__VA_ARGS__); } while (0) 95 #else 96 #define DEBUG(...) do { } while (0) 97 #define SDEBUG(...) do { } while (0) 98 #endif 99 100 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, 101 uint32_t index, uint32_t data) 102 { 103 struct radeon_device *rdev = ctx->card->dev->dev_private; 104 uint32_t temp = 0xCDCDCDCD; 105 106 while (1) 107 switch (CU8(base)) { 108 case ATOM_IIO_NOP: 109 base++; 110 break; 111 case ATOM_IIO_READ: 112 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 113 base += 3; 114 break; 115 case ATOM_IIO_WRITE: 116 if (rdev->family == CHIP_RV515) 117 (void)ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 118 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 119 base += 3; 120 break; 121 case ATOM_IIO_CLEAR: 122 temp &= 123 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 124 CU8(base + 2)); 125 base += 3; 126 break; 127 case ATOM_IIO_SET: 128 temp |= 129 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 130 2); 131 base += 3; 132 break; 133 case ATOM_IIO_MOVE_INDEX: 134 temp &= 135 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 136 CU8(base + 3)); 137 temp |= 138 ((index >> CU8(base + 2)) & 139 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 140 3); 141 base += 4; 142 break; 143 case ATOM_IIO_MOVE_DATA: 144 temp &= 145 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 146 CU8(base + 3)); 147 temp |= 148 ((data >> CU8(base + 2)) & 149 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 150 3); 151 base += 4; 152 break; 153 case ATOM_IIO_MOVE_ATTR: 154 temp &= 155 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 156 CU8(base + 3)); 157 temp |= 158 ((ctx-> 159 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - 160 CU8 161 (base 162 + 163 1)))) 164 << CU8(base + 3); 165 base += 4; 166 break; 167 case ATOM_IIO_END: 168 return temp; 169 default: 170 DRM_INFO("Unknown IIO opcode.\n"); 171 return 0; 172 } 173 } 174 175 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, 176 int *ptr, uint32_t *saved, int print) 177 { 178 uint32_t idx, val = 0xCDCDCDCD, align, arg; 179 struct atom_context *gctx = ctx->ctx; 180 arg = attr & 7; 181 align = (attr >> 3) & 7; 182 switch (arg) { 183 case ATOM_ARG_REG: 184 idx = U16(*ptr); 185 (*ptr) += 2; 186 if (print) 187 DEBUG("REG[0x%04X]", idx); 188 idx += gctx->reg_block; 189 switch (gctx->io_mode) { 190 case ATOM_IO_MM: 191 val = gctx->card->reg_read(gctx->card, idx); 192 break; 193 case ATOM_IO_PCI: 194 DRM_INFO( 195 "PCI registers are not implemented.\n"); 196 return 0; 197 case ATOM_IO_SYSIO: 198 DRM_INFO( 199 "SYSIO registers are not implemented.\n"); 200 return 0; 201 default: 202 if (!(gctx->io_mode & 0x80)) { 203 DRM_INFO( "Bad IO mode.\n"); 204 return 0; 205 } 206 if (!gctx->iio[gctx->io_mode & 0x7F]) { 207 DRM_INFO( 208 "Undefined indirect IO read method %d.\n", 209 gctx->io_mode & 0x7F); 210 return 0; 211 } 212 val = 213 atom_iio_execute(gctx, 214 gctx->iio[gctx->io_mode & 0x7F], 215 idx, 0); 216 } 217 break; 218 case ATOM_ARG_PS: 219 idx = U8(*ptr); 220 (*ptr)++; 221 /* get_unaligned_le32 avoids unaligned accesses from atombios 222 * tables, noticed on a DEC Alpha. */ 223 #ifdef notyet 224 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 225 #else 226 val = le32_to_cpu(ctx->ps[idx]); 227 #endif 228 if (print) 229 DEBUG("PS[0x%02X,0x%04X]", idx, val); 230 break; 231 case ATOM_ARG_WS: 232 idx = U8(*ptr); 233 (*ptr)++; 234 if (print) 235 DEBUG("WS[0x%02X]", idx); 236 switch (idx) { 237 case ATOM_WS_QUOTIENT: 238 val = gctx->divmul[0]; 239 break; 240 case ATOM_WS_REMAINDER: 241 val = gctx->divmul[1]; 242 break; 243 case ATOM_WS_DATAPTR: 244 val = gctx->data_block; 245 break; 246 case ATOM_WS_SHIFT: 247 val = gctx->shift; 248 break; 249 case ATOM_WS_OR_MASK: 250 val = 1 << gctx->shift; 251 break; 252 case ATOM_WS_AND_MASK: 253 val = ~(1 << gctx->shift); 254 break; 255 case ATOM_WS_FB_WINDOW: 256 val = gctx->fb_base; 257 break; 258 case ATOM_WS_ATTRIBUTES: 259 val = gctx->io_attr; 260 break; 261 case ATOM_WS_REGPTR: 262 val = gctx->reg_block; 263 break; 264 default: 265 val = ctx->ws[idx]; 266 } 267 break; 268 case ATOM_ARG_ID: 269 idx = U16(*ptr); 270 (*ptr) += 2; 271 if (print) { 272 if (gctx->data_block) 273 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); 274 else 275 DEBUG("ID[0x%04X]", idx); 276 } 277 val = U32(idx + gctx->data_block); 278 break; 279 case ATOM_ARG_FB: 280 idx = U8(*ptr); 281 (*ptr)++; 282 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 283 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", 284 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 285 val = 0; 286 } else 287 val = gctx->scratch[(gctx->fb_base / 4) + idx]; 288 if (print) 289 DEBUG("FB[0x%02X]", idx); 290 break; 291 case ATOM_ARG_IMM: 292 switch (align) { 293 case ATOM_SRC_DWORD: 294 val = U32(*ptr); 295 (*ptr) += 4; 296 if (print) 297 DEBUG("IMM 0x%08X\n", val); 298 return val; 299 case ATOM_SRC_WORD0: 300 case ATOM_SRC_WORD8: 301 case ATOM_SRC_WORD16: 302 val = U16(*ptr); 303 (*ptr) += 2; 304 if (print) 305 DEBUG("IMM 0x%04X\n", val); 306 return val; 307 case ATOM_SRC_BYTE0: 308 case ATOM_SRC_BYTE8: 309 case ATOM_SRC_BYTE16: 310 case ATOM_SRC_BYTE24: 311 val = U8(*ptr); 312 (*ptr)++; 313 if (print) 314 DEBUG("IMM 0x%02X\n", val); 315 return val; 316 } 317 return 0; 318 case ATOM_ARG_PLL: 319 idx = U8(*ptr); 320 (*ptr)++; 321 if (print) 322 DEBUG("PLL[0x%02X]", idx); 323 val = gctx->card->pll_read(gctx->card, idx); 324 break; 325 case ATOM_ARG_MC: 326 idx = U8(*ptr); 327 (*ptr)++; 328 if (print) 329 DEBUG("MC[0x%02X]", idx); 330 val = gctx->card->mc_read(gctx->card, idx); 331 break; 332 } 333 if (saved) 334 *saved = val; 335 val &= atom_arg_mask[align]; 336 val >>= atom_arg_shift[align]; 337 if (print) 338 switch (align) { 339 case ATOM_SRC_DWORD: 340 DEBUG(".[31:0] -> 0x%08X\n", val); 341 break; 342 case ATOM_SRC_WORD0: 343 DEBUG(".[15:0] -> 0x%04X\n", val); 344 break; 345 case ATOM_SRC_WORD8: 346 DEBUG(".[23:8] -> 0x%04X\n", val); 347 break; 348 case ATOM_SRC_WORD16: 349 DEBUG(".[31:16] -> 0x%04X\n", val); 350 break; 351 case ATOM_SRC_BYTE0: 352 DEBUG(".[7:0] -> 0x%02X\n", val); 353 break; 354 case ATOM_SRC_BYTE8: 355 DEBUG(".[15:8] -> 0x%02X\n", val); 356 break; 357 case ATOM_SRC_BYTE16: 358 DEBUG(".[23:16] -> 0x%02X\n", val); 359 break; 360 case ATOM_SRC_BYTE24: 361 DEBUG(".[31:24] -> 0x%02X\n", val); 362 break; 363 } 364 return val; 365 } 366 367 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) 368 { 369 uint32_t align = (attr >> 3) & 7, arg = attr & 7; 370 switch (arg) { 371 case ATOM_ARG_REG: 372 case ATOM_ARG_ID: 373 (*ptr) += 2; 374 break; 375 case ATOM_ARG_PLL: 376 case ATOM_ARG_MC: 377 case ATOM_ARG_PS: 378 case ATOM_ARG_WS: 379 case ATOM_ARG_FB: 380 (*ptr)++; 381 break; 382 case ATOM_ARG_IMM: 383 switch (align) { 384 case ATOM_SRC_DWORD: 385 (*ptr) += 4; 386 return; 387 case ATOM_SRC_WORD0: 388 case ATOM_SRC_WORD8: 389 case ATOM_SRC_WORD16: 390 (*ptr) += 2; 391 return; 392 case ATOM_SRC_BYTE0: 393 case ATOM_SRC_BYTE8: 394 case ATOM_SRC_BYTE16: 395 case ATOM_SRC_BYTE24: 396 (*ptr)++; 397 return; 398 } 399 return; 400 } 401 } 402 403 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) 404 { 405 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 406 } 407 408 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) 409 { 410 uint32_t val = 0xCDCDCDCD; 411 412 switch (align) { 413 case ATOM_SRC_DWORD: 414 val = U32(*ptr); 415 (*ptr) += 4; 416 break; 417 case ATOM_SRC_WORD0: 418 case ATOM_SRC_WORD8: 419 case ATOM_SRC_WORD16: 420 val = U16(*ptr); 421 (*ptr) += 2; 422 break; 423 case ATOM_SRC_BYTE0: 424 case ATOM_SRC_BYTE8: 425 case ATOM_SRC_BYTE16: 426 case ATOM_SRC_BYTE24: 427 val = U8(*ptr); 428 (*ptr)++; 429 break; 430 } 431 return val; 432 } 433 434 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 435 int *ptr, uint32_t *saved, int print) 436 { 437 return atom_get_src_int(ctx, 438 arg | atom_dst_to_src[(attr >> 3) & 439 7][(attr >> 6) & 3] << 3, 440 ptr, saved, print); 441 } 442 443 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) 444 { 445 atom_skip_src_int(ctx, 446 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 447 3] << 3, ptr); 448 } 449 450 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, 451 int *ptr, uint32_t val, uint32_t saved) 452 { 453 uint32_t align = 454 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = 455 val, idx; 456 struct atom_context *gctx = ctx->ctx; 457 old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; 458 val <<= atom_arg_shift[align]; 459 val &= atom_arg_mask[align]; 460 saved &= ~atom_arg_mask[align]; 461 val |= saved; 462 switch (arg) { 463 case ATOM_ARG_REG: 464 idx = U16(*ptr); 465 (*ptr) += 2; 466 DEBUG("REG[0x%04X]", idx); 467 idx += gctx->reg_block; 468 switch (gctx->io_mode) { 469 case ATOM_IO_MM: 470 if (idx == 0) 471 gctx->card->reg_write(gctx->card, idx, 472 val << 2); 473 else 474 gctx->card->reg_write(gctx->card, idx, val); 475 break; 476 case ATOM_IO_PCI: 477 DRM_INFO( 478 "PCI registers are not implemented.\n"); 479 return; 480 case ATOM_IO_SYSIO: 481 DRM_INFO( 482 "SYSIO registers are not implemented.\n"); 483 return; 484 default: 485 if (!(gctx->io_mode & 0x80)) { 486 DRM_INFO( "Bad IO mode.\n"); 487 return; 488 } 489 if (!gctx->iio[gctx->io_mode & 0xFF]) { 490 DRM_INFO( 491 "Undefined indirect IO write method %d.\n", 492 gctx->io_mode & 0x7F); 493 return; 494 } 495 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], 496 idx, val); 497 } 498 break; 499 case ATOM_ARG_PS: 500 idx = U8(*ptr); 501 (*ptr)++; 502 DEBUG("PS[0x%02X]", idx); 503 ctx->ps[idx] = cpu_to_le32(val); 504 break; 505 case ATOM_ARG_WS: 506 idx = U8(*ptr); 507 (*ptr)++; 508 DEBUG("WS[0x%02X]", idx); 509 switch (idx) { 510 case ATOM_WS_QUOTIENT: 511 gctx->divmul[0] = val; 512 break; 513 case ATOM_WS_REMAINDER: 514 gctx->divmul[1] = val; 515 break; 516 case ATOM_WS_DATAPTR: 517 gctx->data_block = val; 518 break; 519 case ATOM_WS_SHIFT: 520 gctx->shift = val; 521 break; 522 case ATOM_WS_OR_MASK: 523 case ATOM_WS_AND_MASK: 524 break; 525 case ATOM_WS_FB_WINDOW: 526 gctx->fb_base = val; 527 break; 528 case ATOM_WS_ATTRIBUTES: 529 gctx->io_attr = val; 530 break; 531 case ATOM_WS_REGPTR: 532 gctx->reg_block = val; 533 break; 534 default: 535 ctx->ws[idx] = val; 536 } 537 break; 538 case ATOM_ARG_FB: 539 idx = U8(*ptr); 540 (*ptr)++; 541 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 542 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", 543 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 544 } else 545 gctx->scratch[(gctx->fb_base / 4) + idx] = val; 546 DEBUG("FB[0x%02X]", idx); 547 break; 548 case ATOM_ARG_PLL: 549 idx = U8(*ptr); 550 (*ptr)++; 551 DEBUG("PLL[0x%02X]", idx); 552 gctx->card->pll_write(gctx->card, idx, val); 553 break; 554 case ATOM_ARG_MC: 555 idx = U8(*ptr); 556 (*ptr)++; 557 DEBUG("MC[0x%02X]", idx); 558 gctx->card->mc_write(gctx->card, idx, val); 559 return; 560 } 561 switch (align) { 562 case ATOM_SRC_DWORD: 563 DEBUG(".[31:0] <- 0x%08X\n", old_val); 564 break; 565 case ATOM_SRC_WORD0: 566 DEBUG(".[15:0] <- 0x%04X\n", old_val); 567 break; 568 case ATOM_SRC_WORD8: 569 DEBUG(".[23:8] <- 0x%04X\n", old_val); 570 break; 571 case ATOM_SRC_WORD16: 572 DEBUG(".[31:16] <- 0x%04X\n", old_val); 573 break; 574 case ATOM_SRC_BYTE0: 575 DEBUG(".[7:0] <- 0x%02X\n", old_val); 576 break; 577 case ATOM_SRC_BYTE8: 578 DEBUG(".[15:8] <- 0x%02X\n", old_val); 579 break; 580 case ATOM_SRC_BYTE16: 581 DEBUG(".[23:16] <- 0x%02X\n", old_val); 582 break; 583 case ATOM_SRC_BYTE24: 584 DEBUG(".[31:24] <- 0x%02X\n", old_val); 585 break; 586 } 587 } 588 589 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) 590 { 591 uint8_t attr = U8((*ptr)++); 592 uint32_t dst, src, saved; 593 int dptr = *ptr; 594 SDEBUG(" dst: "); 595 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 596 SDEBUG(" src: "); 597 src = atom_get_src(ctx, attr, ptr); 598 dst += src; 599 SDEBUG(" dst: "); 600 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 601 } 602 603 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) 604 { 605 uint8_t attr = U8((*ptr)++); 606 uint32_t dst, src, saved; 607 int dptr = *ptr; 608 SDEBUG(" dst: "); 609 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 610 SDEBUG(" src: "); 611 src = atom_get_src(ctx, attr, ptr); 612 dst &= src; 613 SDEBUG(" dst: "); 614 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 615 } 616 617 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) 618 { 619 printf("ATOM BIOS beeped!\n"); 620 } 621 622 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) 623 { 624 int idx = U8((*ptr)++); 625 int r = 0; 626 627 if (idx < ATOM_TABLE_NAMES_CNT) 628 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); 629 else 630 SDEBUG(" table: %d\n", idx); 631 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 632 r = atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 633 if (r) { 634 ctx->abort = true; 635 } 636 } 637 638 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 639 { 640 uint8_t attr = U8((*ptr)++); 641 uint32_t saved; 642 int dptr = *ptr; 643 attr &= 0x38; 644 attr |= atom_def_dst[attr >> 3] << 6; 645 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 646 SDEBUG(" dst: "); 647 atom_put_dst(ctx, arg, attr, &dptr, 0, saved); 648 } 649 650 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 651 { 652 uint8_t attr = U8((*ptr)++); 653 uint32_t dst, src; 654 SDEBUG(" src1: "); 655 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 656 SDEBUG(" src2: "); 657 src = atom_get_src(ctx, attr, ptr); 658 ctx->ctx->cs_equal = (dst == src); 659 ctx->ctx->cs_above = (dst > src); 660 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", 661 ctx->ctx->cs_above ? "GT" : "LE"); 662 } 663 664 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 665 { 666 unsigned count = U8((*ptr)++); 667 SDEBUG(" count: %d\n", count); 668 if (arg == ATOM_UNIT_MICROSEC) 669 udelay(count); 670 else if (!drm_can_sleep()) 671 mdelay(count); 672 else 673 drm_msleep(count, "atomop"); 674 } 675 676 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 677 { 678 uint8_t attr = U8((*ptr)++); 679 uint32_t dst, src; 680 SDEBUG(" src1: "); 681 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 682 SDEBUG(" src2: "); 683 src = atom_get_src(ctx, attr, ptr); 684 if (src != 0) { 685 ctx->ctx->divmul[0] = dst / src; 686 ctx->ctx->divmul[1] = dst % src; 687 } else { 688 ctx->ctx->divmul[0] = 0; 689 ctx->ctx->divmul[1] = 0; 690 } 691 } 692 693 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) 694 { 695 /* functionally, a nop */ 696 } 697 698 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) 699 { 700 int execute = 0, target = U16(*ptr); 701 unsigned long cjiffies; 702 703 (*ptr) += 2; 704 switch (arg) { 705 case ATOM_COND_ABOVE: 706 execute = ctx->ctx->cs_above; 707 break; 708 case ATOM_COND_ABOVEOREQUAL: 709 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; 710 break; 711 case ATOM_COND_ALWAYS: 712 execute = 1; 713 break; 714 case ATOM_COND_BELOW: 715 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); 716 break; 717 case ATOM_COND_BELOWOREQUAL: 718 execute = !ctx->ctx->cs_above; 719 break; 720 case ATOM_COND_EQUAL: 721 execute = ctx->ctx->cs_equal; 722 break; 723 case ATOM_COND_NOTEQUAL: 724 execute = !ctx->ctx->cs_equal; 725 break; 726 } 727 if (arg != ATOM_COND_ALWAYS) 728 SDEBUG(" taken: %s\n", execute ? "yes" : "no"); 729 SDEBUG(" target: 0x%04X\n", target); 730 if (execute) { 731 if (ctx->last_jump == (ctx->start + target)) { 732 cjiffies = ticks; 733 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 734 cjiffies -= ctx->last_jump_jiffies; 735 if ((jiffies_to_msecs(cjiffies) > 5000)) { 736 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n"); 737 ctx->abort = true; 738 } 739 } else { 740 /* jiffies wrap around we will just wait a little longer */ 741 ctx->last_jump_jiffies = ticks; 742 } 743 } else { 744 ctx->last_jump = ctx->start + target; 745 ctx->last_jump_jiffies = ticks; 746 } 747 *ptr = ctx->start + target; 748 } 749 } 750 751 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) 752 { 753 uint8_t attr = U8((*ptr)++); 754 uint32_t dst, mask, src, saved; 755 int dptr = *ptr; 756 SDEBUG(" dst: "); 757 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 758 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); 759 SDEBUG(" mask: 0x%08x", mask); 760 SDEBUG(" src: "); 761 src = atom_get_src(ctx, attr, ptr); 762 dst &= mask; 763 dst |= src; 764 SDEBUG(" dst: "); 765 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 766 } 767 768 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) 769 { 770 uint8_t attr = U8((*ptr)++); 771 uint32_t src, saved; 772 int dptr = *ptr; 773 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) 774 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 775 else { 776 atom_skip_dst(ctx, arg, attr, ptr); 777 saved = 0xCDCDCDCD; 778 } 779 SDEBUG(" src: "); 780 src = atom_get_src(ctx, attr, ptr); 781 SDEBUG(" dst: "); 782 atom_put_dst(ctx, arg, attr, &dptr, src, saved); 783 } 784 785 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) 786 { 787 uint8_t attr = U8((*ptr)++); 788 uint32_t dst, src; 789 SDEBUG(" src1: "); 790 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 791 SDEBUG(" src2: "); 792 src = atom_get_src(ctx, attr, ptr); 793 ctx->ctx->divmul[0] = dst * src; 794 } 795 796 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) 797 { 798 /* nothing */ 799 } 800 801 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) 802 { 803 uint8_t attr = U8((*ptr)++); 804 uint32_t dst, src, saved; 805 int dptr = *ptr; 806 SDEBUG(" dst: "); 807 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 808 SDEBUG(" src: "); 809 src = atom_get_src(ctx, attr, ptr); 810 dst |= src; 811 SDEBUG(" dst: "); 812 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 813 } 814 815 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) 816 { 817 uint8_t val = U8((*ptr)++); 818 SDEBUG("POST card output: 0x%02X\n", val); 819 } 820 821 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) 822 { 823 DRM_INFO( "unimplemented!\n"); 824 } 825 826 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) 827 { 828 DRM_INFO( "unimplemented!\n"); 829 } 830 831 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) 832 { 833 DRM_INFO( "unimplemented!\n"); 834 } 835 836 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) 837 { 838 int idx = U8(*ptr); 839 (*ptr)++; 840 SDEBUG(" block: %d\n", idx); 841 if (!idx) 842 ctx->ctx->data_block = 0; 843 else if (idx == 255) 844 ctx->ctx->data_block = ctx->start; 845 else 846 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); 847 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); 848 } 849 850 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) 851 { 852 uint8_t attr = U8((*ptr)++); 853 SDEBUG(" fb_base: "); 854 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); 855 } 856 857 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) 858 { 859 int port; 860 switch (arg) { 861 case ATOM_PORT_ATI: 862 port = U16(*ptr); 863 if (port < ATOM_IO_NAMES_CNT) 864 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); 865 else 866 SDEBUG(" port: %d\n", port); 867 if (!port) 868 ctx->ctx->io_mode = ATOM_IO_MM; 869 else 870 ctx->ctx->io_mode = ATOM_IO_IIO | port; 871 (*ptr) += 2; 872 break; 873 case ATOM_PORT_PCI: 874 ctx->ctx->io_mode = ATOM_IO_PCI; 875 (*ptr)++; 876 break; 877 case ATOM_PORT_SYSIO: 878 ctx->ctx->io_mode = ATOM_IO_SYSIO; 879 (*ptr)++; 880 break; 881 } 882 } 883 884 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) 885 { 886 ctx->ctx->reg_block = U16(*ptr); 887 (*ptr) += 2; 888 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 889 } 890 891 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) 892 { 893 uint8_t attr = U8((*ptr)++), shift; 894 uint32_t saved, dst; 895 int dptr = *ptr; 896 attr &= 0x38; 897 attr |= atom_def_dst[attr >> 3] << 6; 898 SDEBUG(" dst: "); 899 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 900 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 901 SDEBUG(" shift: %d\n", shift); 902 dst <<= shift; 903 SDEBUG(" dst: "); 904 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 905 } 906 907 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) 908 { 909 uint8_t attr = U8((*ptr)++), shift; 910 uint32_t saved, dst; 911 int dptr = *ptr; 912 attr &= 0x38; 913 attr |= atom_def_dst[attr >> 3] << 6; 914 SDEBUG(" dst: "); 915 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 916 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 917 SDEBUG(" shift: %d\n", shift); 918 dst >>= shift; 919 SDEBUG(" dst: "); 920 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 921 } 922 923 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 924 { 925 uint8_t attr = U8((*ptr)++), shift; 926 uint32_t saved, dst; 927 int dptr = *ptr; 928 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 929 SDEBUG(" dst: "); 930 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 931 /* op needs to full dst value */ 932 dst = saved; 933 shift = atom_get_src(ctx, attr, ptr); 934 SDEBUG(" shift: %d\n", shift); 935 dst <<= shift; 936 dst &= atom_arg_mask[dst_align]; 937 dst >>= atom_arg_shift[dst_align]; 938 SDEBUG(" dst: "); 939 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 940 } 941 942 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) 943 { 944 uint8_t attr = U8((*ptr)++), shift; 945 uint32_t saved, dst; 946 int dptr = *ptr; 947 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 948 SDEBUG(" dst: "); 949 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 950 /* op needs to full dst value */ 951 dst = saved; 952 shift = atom_get_src(ctx, attr, ptr); 953 SDEBUG(" shift: %d\n", shift); 954 dst >>= shift; 955 dst &= atom_arg_mask[dst_align]; 956 dst >>= atom_arg_shift[dst_align]; 957 SDEBUG(" dst: "); 958 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 959 } 960 961 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) 962 { 963 uint8_t attr = U8((*ptr)++); 964 uint32_t dst, src, saved; 965 int dptr = *ptr; 966 SDEBUG(" dst: "); 967 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 968 SDEBUG(" src: "); 969 src = atom_get_src(ctx, attr, ptr); 970 dst -= src; 971 SDEBUG(" dst: "); 972 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 973 } 974 975 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) 976 { 977 uint8_t attr = U8((*ptr)++); 978 uint32_t src, val, target; 979 SDEBUG(" switch: "); 980 src = atom_get_src(ctx, attr, ptr); 981 while (U16(*ptr) != ATOM_CASE_END) 982 if (U8(*ptr) == ATOM_CASE_MAGIC) { 983 (*ptr)++; 984 SDEBUG(" case: "); 985 val = 986 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, 987 ptr); 988 target = U16(*ptr); 989 if (val == src) { 990 SDEBUG(" target: %04X\n", target); 991 *ptr = ctx->start + target; 992 return; 993 } 994 (*ptr) += 2; 995 } else { 996 DRM_INFO( "Bad case.\n"); 997 return; 998 } 999 (*ptr) += 2; 1000 } 1001 1002 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) 1003 { 1004 uint8_t attr = U8((*ptr)++); 1005 uint32_t dst, src; 1006 SDEBUG(" src1: "); 1007 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 1008 SDEBUG(" src2: "); 1009 src = atom_get_src(ctx, attr, ptr); 1010 ctx->ctx->cs_equal = ((dst & src) == 0); 1011 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); 1012 } 1013 1014 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) 1015 { 1016 uint8_t attr = U8((*ptr)++); 1017 uint32_t dst, src, saved; 1018 int dptr = *ptr; 1019 SDEBUG(" dst: "); 1020 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1021 SDEBUG(" src: "); 1022 src = atom_get_src(ctx, attr, ptr); 1023 dst ^= src; 1024 SDEBUG(" dst: "); 1025 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1026 } 1027 1028 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) 1029 { 1030 DRM_INFO( "unimplemented!\n"); 1031 } 1032 1033 static struct { 1034 void (*func) (atom_exec_context *, int *, int); 1035 int arg; 1036 } opcode_table[ATOM_OP_CNT] = { 1037 { 1038 NULL, 0}, { 1039 atom_op_move, ATOM_ARG_REG}, { 1040 atom_op_move, ATOM_ARG_PS}, { 1041 atom_op_move, ATOM_ARG_WS}, { 1042 atom_op_move, ATOM_ARG_FB}, { 1043 atom_op_move, ATOM_ARG_PLL}, { 1044 atom_op_move, ATOM_ARG_MC}, { 1045 atom_op_and, ATOM_ARG_REG}, { 1046 atom_op_and, ATOM_ARG_PS}, { 1047 atom_op_and, ATOM_ARG_WS}, { 1048 atom_op_and, ATOM_ARG_FB}, { 1049 atom_op_and, ATOM_ARG_PLL}, { 1050 atom_op_and, ATOM_ARG_MC}, { 1051 atom_op_or, ATOM_ARG_REG}, { 1052 atom_op_or, ATOM_ARG_PS}, { 1053 atom_op_or, ATOM_ARG_WS}, { 1054 atom_op_or, ATOM_ARG_FB}, { 1055 atom_op_or, ATOM_ARG_PLL}, { 1056 atom_op_or, ATOM_ARG_MC}, { 1057 atom_op_shift_left, ATOM_ARG_REG}, { 1058 atom_op_shift_left, ATOM_ARG_PS}, { 1059 atom_op_shift_left, ATOM_ARG_WS}, { 1060 atom_op_shift_left, ATOM_ARG_FB}, { 1061 atom_op_shift_left, ATOM_ARG_PLL}, { 1062 atom_op_shift_left, ATOM_ARG_MC}, { 1063 atom_op_shift_right, ATOM_ARG_REG}, { 1064 atom_op_shift_right, ATOM_ARG_PS}, { 1065 atom_op_shift_right, ATOM_ARG_WS}, { 1066 atom_op_shift_right, ATOM_ARG_FB}, { 1067 atom_op_shift_right, ATOM_ARG_PLL}, { 1068 atom_op_shift_right, ATOM_ARG_MC}, { 1069 atom_op_mul, ATOM_ARG_REG}, { 1070 atom_op_mul, ATOM_ARG_PS}, { 1071 atom_op_mul, ATOM_ARG_WS}, { 1072 atom_op_mul, ATOM_ARG_FB}, { 1073 atom_op_mul, ATOM_ARG_PLL}, { 1074 atom_op_mul, ATOM_ARG_MC}, { 1075 atom_op_div, ATOM_ARG_REG}, { 1076 atom_op_div, ATOM_ARG_PS}, { 1077 atom_op_div, ATOM_ARG_WS}, { 1078 atom_op_div, ATOM_ARG_FB}, { 1079 atom_op_div, ATOM_ARG_PLL}, { 1080 atom_op_div, ATOM_ARG_MC}, { 1081 atom_op_add, ATOM_ARG_REG}, { 1082 atom_op_add, ATOM_ARG_PS}, { 1083 atom_op_add, ATOM_ARG_WS}, { 1084 atom_op_add, ATOM_ARG_FB}, { 1085 atom_op_add, ATOM_ARG_PLL}, { 1086 atom_op_add, ATOM_ARG_MC}, { 1087 atom_op_sub, ATOM_ARG_REG}, { 1088 atom_op_sub, ATOM_ARG_PS}, { 1089 atom_op_sub, ATOM_ARG_WS}, { 1090 atom_op_sub, ATOM_ARG_FB}, { 1091 atom_op_sub, ATOM_ARG_PLL}, { 1092 atom_op_sub, ATOM_ARG_MC}, { 1093 atom_op_setport, ATOM_PORT_ATI}, { 1094 atom_op_setport, ATOM_PORT_PCI}, { 1095 atom_op_setport, ATOM_PORT_SYSIO}, { 1096 atom_op_setregblock, 0}, { 1097 atom_op_setfbbase, 0}, { 1098 atom_op_compare, ATOM_ARG_REG}, { 1099 atom_op_compare, ATOM_ARG_PS}, { 1100 atom_op_compare, ATOM_ARG_WS}, { 1101 atom_op_compare, ATOM_ARG_FB}, { 1102 atom_op_compare, ATOM_ARG_PLL}, { 1103 atom_op_compare, ATOM_ARG_MC}, { 1104 atom_op_switch, 0}, { 1105 atom_op_jump, ATOM_COND_ALWAYS}, { 1106 atom_op_jump, ATOM_COND_EQUAL}, { 1107 atom_op_jump, ATOM_COND_BELOW}, { 1108 atom_op_jump, ATOM_COND_ABOVE}, { 1109 atom_op_jump, ATOM_COND_BELOWOREQUAL}, { 1110 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { 1111 atom_op_jump, ATOM_COND_NOTEQUAL}, { 1112 atom_op_test, ATOM_ARG_REG}, { 1113 atom_op_test, ATOM_ARG_PS}, { 1114 atom_op_test, ATOM_ARG_WS}, { 1115 atom_op_test, ATOM_ARG_FB}, { 1116 atom_op_test, ATOM_ARG_PLL}, { 1117 atom_op_test, ATOM_ARG_MC}, { 1118 atom_op_delay, ATOM_UNIT_MILLISEC}, { 1119 atom_op_delay, ATOM_UNIT_MICROSEC}, { 1120 atom_op_calltable, 0}, { 1121 atom_op_repeat, 0}, { 1122 atom_op_clear, ATOM_ARG_REG}, { 1123 atom_op_clear, ATOM_ARG_PS}, { 1124 atom_op_clear, ATOM_ARG_WS}, { 1125 atom_op_clear, ATOM_ARG_FB}, { 1126 atom_op_clear, ATOM_ARG_PLL}, { 1127 atom_op_clear, ATOM_ARG_MC}, { 1128 atom_op_nop, 0}, { 1129 atom_op_eot, 0}, { 1130 atom_op_mask, ATOM_ARG_REG}, { 1131 atom_op_mask, ATOM_ARG_PS}, { 1132 atom_op_mask, ATOM_ARG_WS}, { 1133 atom_op_mask, ATOM_ARG_FB}, { 1134 atom_op_mask, ATOM_ARG_PLL}, { 1135 atom_op_mask, ATOM_ARG_MC}, { 1136 atom_op_postcard, 0}, { 1137 atom_op_beep, 0}, { 1138 atom_op_savereg, 0}, { 1139 atom_op_restorereg, 0}, { 1140 atom_op_setdatablock, 0}, { 1141 atom_op_xor, ATOM_ARG_REG}, { 1142 atom_op_xor, ATOM_ARG_PS}, { 1143 atom_op_xor, ATOM_ARG_WS}, { 1144 atom_op_xor, ATOM_ARG_FB}, { 1145 atom_op_xor, ATOM_ARG_PLL}, { 1146 atom_op_xor, ATOM_ARG_MC}, { 1147 atom_op_shl, ATOM_ARG_REG}, { 1148 atom_op_shl, ATOM_ARG_PS}, { 1149 atom_op_shl, ATOM_ARG_WS}, { 1150 atom_op_shl, ATOM_ARG_FB}, { 1151 atom_op_shl, ATOM_ARG_PLL}, { 1152 atom_op_shl, ATOM_ARG_MC}, { 1153 atom_op_shr, ATOM_ARG_REG}, { 1154 atom_op_shr, ATOM_ARG_PS}, { 1155 atom_op_shr, ATOM_ARG_WS}, { 1156 atom_op_shr, ATOM_ARG_FB}, { 1157 atom_op_shr, ATOM_ARG_PLL}, { 1158 atom_op_shr, ATOM_ARG_MC}, { 1159 atom_op_debug, 0},}; 1160 1161 static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) 1162 { 1163 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1164 int len, ws, ps, ptr; 1165 unsigned char op; 1166 atom_exec_context ectx; 1167 int ret = 0; 1168 1169 if (!base) 1170 return -EINVAL; 1171 1172 len = CU16(base + ATOM_CT_SIZE_PTR); 1173 ws = CU8(base + ATOM_CT_WS_PTR); 1174 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1175 ptr = base + ATOM_CT_CODE_PTR; 1176 1177 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1178 1179 ectx.ctx = ctx; 1180 ectx.ps_shift = ps / 4; 1181 ectx.start = base; 1182 ectx.ps = params; 1183 ectx.abort = false; 1184 ectx.last_jump = 0; 1185 if (ws) 1186 ectx.ws = kzalloc(4 * ws, GFP_KERNEL); 1187 else 1188 ectx.ws = NULL; 1189 1190 debug_depth++; 1191 while (1) { 1192 op = CU8(ptr++); 1193 if (op < ATOM_OP_NAMES_CNT) 1194 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); 1195 else 1196 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); 1197 if (ectx.abort) { 1198 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1199 base, len, ws, ps, ptr - 1); 1200 ret = -EINVAL; 1201 goto free; 1202 } 1203 1204 if (op < ATOM_OP_CNT && op > 0) 1205 opcode_table[op].func(&ectx, &ptr, 1206 opcode_table[op].arg); 1207 else 1208 break; 1209 1210 if (op == ATOM_OP_EOT) 1211 break; 1212 } 1213 debug_depth--; 1214 SDEBUG("<<\n"); 1215 1216 free: 1217 if (ws) 1218 kfree(ectx.ws); 1219 return ret; 1220 } 1221 1222 int atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1223 { 1224 int r; 1225 1226 rw_enter_write(&ctx->rwlock); 1227 /* reset data block */ 1228 ctx->data_block = 0; 1229 /* reset reg block */ 1230 ctx->reg_block = 0; 1231 /* reset fb window */ 1232 ctx->fb_base = 0; 1233 /* reset io mode */ 1234 ctx->io_mode = ATOM_IO_MM; 1235 /* reset divmul */ 1236 ctx->divmul[0] = 0; 1237 ctx->divmul[1] = 0; 1238 r = atom_execute_table_locked(ctx, index, params); 1239 rw_exit_write(&ctx->rwlock); 1240 return r; 1241 } 1242 1243 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1244 1245 static void atom_index_iio(struct atom_context *ctx, int base) 1246 { 1247 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); 1248 while (CU8(base) == ATOM_IIO_START) { 1249 ctx->iio[CU8(base + 1)] = base + 2; 1250 base += 2; 1251 while (CU8(base) != ATOM_IIO_END) 1252 base += atom_iio_len[CU8(base)]; 1253 base += 3; 1254 } 1255 } 1256 1257 struct atom_context *atom_parse(struct card_info *card, void *bios) 1258 { 1259 int base; 1260 struct atom_context *ctx = 1261 kzalloc(sizeof(struct atom_context), GFP_KERNEL); 1262 #ifdef DRMDEBUG 1263 char *str; 1264 char name[512]; 1265 int i; 1266 #endif 1267 1268 if (!ctx) 1269 return NULL; 1270 1271 ctx->card = card; 1272 ctx->bios = bios; 1273 1274 if (CU16(0) != ATOM_BIOS_MAGIC) { 1275 DRM_INFO( "Invalid BIOS magic.\n"); 1276 kfree(ctx); 1277 return NULL; 1278 } 1279 if (strncmp 1280 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, 1281 strlen(ATOM_ATI_MAGIC))) { 1282 DRM_INFO( "Invalid ATI magic.\n"); 1283 kfree(ctx); 1284 return NULL; 1285 } 1286 1287 base = CU16(ATOM_ROM_TABLE_PTR); 1288 if (strncmp 1289 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, 1290 strlen(ATOM_ROM_MAGIC))) { 1291 DRM_INFO( "Invalid ATOM magic.\n"); 1292 kfree(ctx); 1293 return NULL; 1294 } 1295 1296 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); 1297 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); 1298 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); 1299 1300 #ifdef DRMDEBUG 1301 str = CSTR(CU16(base + ATOM_ROM_MSG_PTR)); 1302 while (*str && ((*str == '\n') || (*str == '\r'))) 1303 str++; 1304 /* name string isn't always 0 terminated */ 1305 for (i = 0; i < 511; i++) { 1306 name[i] = str[i]; 1307 if (name[i] < '.' || name[i] > 'z') { 1308 name[i] = 0; 1309 break; 1310 } 1311 } 1312 DRM_INFO( "ATOM BIOS: %s\n", name); 1313 #endif 1314 1315 return ctx; 1316 } 1317 1318 int atom_asic_init(struct atom_context *ctx) 1319 { 1320 struct radeon_device *rdev = ctx->card->dev->dev_private; 1321 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); 1322 uint32_t ps[16]; 1323 int ret; 1324 1325 memset(ps, 0, 64); 1326 1327 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); 1328 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); 1329 if (!ps[0] || !ps[1]) 1330 return 1; 1331 1332 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) 1333 return 1; 1334 ret = atom_execute_table(ctx, ATOM_CMD_INIT, ps); 1335 if (ret) 1336 return ret; 1337 1338 memset(ps, 0, 64); 1339 1340 if (rdev->family < CHIP_R600) { 1341 if (CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_SPDFANCNTL)) 1342 atom_execute_table(ctx, ATOM_CMD_SPDFANCNTL, ps); 1343 } 1344 return ret; 1345 } 1346 1347 void atom_destroy(struct atom_context *ctx) 1348 { 1349 if (ctx->iio) 1350 kfree(ctx->iio); 1351 kfree(ctx); 1352 } 1353 1354 bool atom_parse_data_header(struct atom_context *ctx, int index, 1355 uint16_t * size, uint8_t * frev, uint8_t * crev, 1356 uint16_t * data_start) 1357 { 1358 int offset = index * 2 + 4; 1359 int idx = CU16(ctx->data_table + offset); 1360 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); 1361 1362 if (!mdt[index]) 1363 return false; 1364 1365 if (size) 1366 *size = CU16(idx); 1367 if (frev) 1368 *frev = CU8(idx + 2); 1369 if (crev) 1370 *crev = CU8(idx + 3); 1371 *data_start = idx; 1372 return true; 1373 } 1374 1375 bool atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, 1376 uint8_t * crev) 1377 { 1378 int offset = index * 2 + 4; 1379 int idx = CU16(ctx->cmd_table + offset); 1380 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); 1381 1382 if (!mct[index]) 1383 return false; 1384 1385 if (frev) 1386 *frev = CU8(idx + 2); 1387 if (crev) 1388 *crev = CU8(idx + 3); 1389 return true; 1390 } 1391 1392 int atom_allocate_fb_scratch(struct atom_context *ctx) 1393 { 1394 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); 1395 uint16_t data_offset; 1396 int usage_bytes = 0; 1397 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; 1398 1399 if (atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 1400 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); 1401 1402 DRM_DEBUG("atom firmware requested %08x %dkb\n", 1403 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), 1404 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); 1405 1406 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; 1407 } 1408 ctx->scratch_size_bytes = 0; 1409 if (usage_bytes == 0) 1410 usage_bytes = 20 * 1024; 1411 /* allocate some scratch memory */ 1412 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 1413 if (!ctx->scratch) 1414 return -ENOMEM; 1415 ctx->scratch_size_bytes = usage_bytes; 1416 return 0; 1417 } 1418