1 /* $OpenBSD: pci.h,v 1.11 2022/04/11 03:02:40 jsg Exp $ */ 2 /* 3 * Copyright (c) 2015 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _LINUX_PCI_H_ 19 #define _LINUX_PCI_H_ 20 21 #include <sys/types.h> 22 /* sparc64 cpu.h needs time.h and siginfo.h (indirect via param.h) */ 23 #include <sys/param.h> 24 #include <machine/cpu.h> 25 26 #include <dev/pci/pcireg.h> 27 #include <dev/pci/pcivar.h> 28 #include <dev/pci/pcidevs.h> 29 #include <uvm/uvm_extern.h> 30 31 #include <linux/io.h> 32 #include <linux/ioport.h> 33 #include <linux/kobject.h> 34 #include <linux/dma-mapping.h> /* pci-dma-compat.h -> dma-mapping.h */ 35 #include <linux/mod_devicetable.h> 36 37 struct pci_dev; 38 39 struct pci_bus { 40 pci_chipset_tag_t pc; 41 unsigned char number; 42 int domain_nr; 43 pcitag_t *bridgetag; 44 struct pci_dev *self; 45 }; 46 47 struct pci_acpi { 48 struct aml_node *node; 49 }; 50 51 struct pci_dev { 52 struct pci_bus _bus; 53 struct pci_bus *bus; 54 55 unsigned int devfn; 56 uint16_t vendor; 57 uint16_t device; 58 uint16_t subsystem_vendor; 59 uint16_t subsystem_device; 60 uint8_t revision; 61 uint32_t class; /* class:subclass:interface */ 62 63 pci_chipset_tag_t pc; 64 pcitag_t tag; 65 struct pci_softc *pci; 66 67 int irq; 68 int msi_enabled; 69 uint8_t no_64bit_msi; 70 71 struct pci_acpi dev; 72 }; 73 #define PCI_ANY_ID (uint16_t) (~0U) 74 75 #ifndef PCI_MEM_START 76 #define PCI_MEM_START 0 77 #endif 78 79 #ifndef PCI_MEM_END 80 #define PCI_MEM_END 0xffffffff 81 #endif 82 83 #ifndef PCI_MEM64_END 84 #define PCI_MEM64_END 0xffffffffffffffff 85 #endif 86 87 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 88 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 89 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 90 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 91 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 92 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 93 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 94 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 95 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 96 97 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_QY 98 99 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 100 #define PCI_SUBDEVICE_ID_QEMU 0x1100 101 102 #define PCI_DEVFN(slot, func) ((slot) << 3 | (func)) 103 #define PCI_SLOT(devfn) ((devfn) >> 3) 104 #define PCI_FUNC(devfn) ((devfn) & 0x7) 105 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 106 107 #define pci_dev_put(x) 108 109 #define PCI_EXP_DEVSTA 0x0a 110 #define PCI_EXP_DEVSTA_TRPND 0x0020 111 #define PCI_EXP_LNKCAP 0x0c 112 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 113 #define PCI_EXP_LNKCTL 0x10 114 #define PCI_EXP_LNKCTL_HAWD 0x0200 115 #define PCI_EXP_LNKCTL2 0x30 116 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 117 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 118 #define PCI_EXP_LNKCTL2_TLS PCI_PCIE_LCSR2_TLS 119 #define PCI_EXP_LNKCTL2_TLS_2_5GT PCI_PCIE_LCSR2_TLS_2_5 120 #define PCI_EXP_LNKCTL2_TLS_5_0GT PCI_PCIE_LCSR2_TLS_5 121 #define PCI_EXP_LNKCTL2_TLS_8_0GT PCI_PCIE_LCSR2_TLS_8 122 123 #define PCI_COMMAND PCI_COMMAND_STATUS_REG 124 #define PCI_COMMAND_MEMORY PCI_COMMAND_MEM_ENABLE 125 126 static inline int 127 pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val) 128 { 129 *val = pci_conf_read(pdev->pc, pdev->tag, reg); 130 return 0; 131 } 132 133 static inline int 134 pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val) 135 { 136 uint32_t v; 137 138 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 139 *val = (v >> ((reg & 0x2) * 8)); 140 return 0; 141 } 142 143 static inline int 144 pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val) 145 { 146 uint32_t v; 147 148 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 149 *val = (v >> ((reg & 0x3) * 8)); 150 return 0; 151 } 152 153 static inline int 154 pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val) 155 { 156 pci_conf_write(pdev->pc, pdev->tag, reg, val); 157 return 0; 158 } 159 160 static inline int 161 pci_write_config_word(struct pci_dev *pdev, int reg, u16 val) 162 { 163 uint32_t v; 164 165 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 166 v &= ~(0xffff << ((reg & 0x2) * 8)); 167 v |= (val << ((reg & 0x2) * 8)); 168 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v); 169 return 0; 170 } 171 172 static inline int 173 pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val) 174 { 175 uint32_t v; 176 177 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 178 v &= ~(0xff << ((reg & 0x3) * 8)); 179 v |= (val << ((reg & 0x3) * 8)); 180 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x3), v); 181 return 0; 182 } 183 184 static inline int 185 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 186 int reg, u16 *val) 187 { 188 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 189 PCI_SLOT(devfn), PCI_FUNC(devfn)); 190 uint32_t v; 191 192 v = pci_conf_read(bus->pc, tag, (reg & ~0x2)); 193 *val = (v >> ((reg & 0x2) * 8)); 194 return 0; 195 } 196 197 static inline int 198 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 199 int reg, u8 *val) 200 { 201 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 202 PCI_SLOT(devfn), PCI_FUNC(devfn)); 203 uint32_t v; 204 205 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 206 *val = (v >> ((reg & 0x3) * 8)); 207 return 0; 208 } 209 210 static inline int 211 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 212 int reg, u8 val) 213 { 214 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 215 PCI_SLOT(devfn), PCI_FUNC(devfn)); 216 uint32_t v; 217 218 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 219 v &= ~(0xff << ((reg & 0x3) * 8)); 220 v |= (val << ((reg & 0x3) * 8)); 221 pci_conf_write(bus->pc, tag, (reg & ~0x3), v); 222 return 0; 223 } 224 225 static inline int 226 pci_pcie_cap(struct pci_dev *pdev) 227 { 228 int pos; 229 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 230 &pos, NULL)) 231 return -EINVAL; 232 return pos; 233 } 234 235 bool pcie_aspm_enabled(struct pci_dev *); 236 237 static inline bool 238 pci_is_pcie(struct pci_dev *pdev) 239 { 240 return (pci_pcie_cap(pdev) > 0); 241 } 242 243 static inline bool 244 pci_is_root_bus(struct pci_bus *pbus) 245 { 246 return (pbus->bridgetag == NULL); 247 } 248 249 static inline struct pci_dev * 250 pci_upstream_bridge(struct pci_dev *pdev) 251 { 252 if (pci_is_root_bus(pdev->bus)) 253 return NULL; 254 return pdev->bus->self; 255 } 256 257 /* XXX check for ACPI _PR3 */ 258 static inline bool 259 pci_pr3_present(struct pci_dev *pdev) 260 { 261 return false; 262 } 263 264 static inline int 265 pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val) 266 { 267 int pos; 268 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 269 &pos, NULL)) { 270 *val = 0; 271 return -EINVAL; 272 } 273 *val = pci_conf_read(pdev->pc, pdev->tag, pos + off); 274 return 0; 275 } 276 277 static inline int 278 pcie_capability_read_word(struct pci_dev *pdev, int off, u16 *val) 279 { 280 int pos; 281 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 282 &pos, NULL)) { 283 *val = 0; 284 return -EINVAL; 285 } 286 pci_read_config_word(pdev, pos + off, val); 287 return 0; 288 } 289 290 static inline int 291 pcie_capability_write_word(struct pci_dev *pdev, int off, u16 val) 292 { 293 int pos; 294 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 295 &pos, NULL)) 296 return -EINVAL; 297 pci_write_config_word(pdev, pos + off, val); 298 return 0; 299 } 300 301 static inline int 302 pcie_get_readrq(struct pci_dev *pdev) 303 { 304 uint16_t val; 305 306 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val); 307 308 return 128 << ((val & PCI_PCIE_DCSR_MPS) >> 12); 309 } 310 311 static inline int 312 pcie_set_readrq(struct pci_dev *pdev, int rrq) 313 { 314 uint16_t val; 315 316 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val); 317 val &= ~PCI_PCIE_DCSR_MPS; 318 val |= (ffs(rrq) - 8) << 12; 319 return pcie_capability_write_word(pdev, PCI_PCIE_DCSR, val); 320 } 321 322 static inline void 323 pci_set_master(struct pci_dev *pdev) 324 { 325 } 326 327 static inline void 328 pci_clear_master(struct pci_dev *pdev) 329 { 330 } 331 332 static inline void 333 pci_save_state(struct pci_dev *pdev) 334 { 335 } 336 337 static inline void 338 pci_restore_state(struct pci_dev *pdev) 339 { 340 } 341 342 static inline int 343 pci_enable_msi(struct pci_dev *pdev) 344 { 345 return 0; 346 } 347 348 static inline void 349 pci_disable_msi(struct pci_dev *pdev) 350 { 351 } 352 353 typedef enum { 354 PCI_D0, 355 PCI_D1, 356 PCI_D2, 357 PCI_D3hot, 358 PCI_D3cold 359 } pci_power_t; 360 361 enum pci_bus_speed { 362 PCIE_SPEED_2_5GT, 363 PCIE_SPEED_5_0GT, 364 PCIE_SPEED_8_0GT, 365 PCIE_SPEED_16_0GT, 366 PCIE_SPEED_32_0GT, 367 PCIE_SPEED_64_0GT, 368 PCI_SPEED_UNKNOWN 369 }; 370 371 enum pcie_link_width { 372 PCIE_LNK_X1 = 1, 373 PCIE_LNK_X2 = 2, 374 PCIE_LNK_X4 = 4, 375 PCIE_LNK_X8 = 8, 376 PCIE_LNK_X12 = 12, 377 PCIE_LNK_X16 = 16, 378 PCIE_LNK_X32 = 32, 379 PCIE_LNK_WIDTH_UNKNOWN = 0xff 380 }; 381 382 typedef unsigned int pci_ers_result_t; 383 typedef unsigned int pci_channel_state_t; 384 385 #define PCI_ERS_RESULT_DISCONNECT 0 386 #define PCI_ERS_RESULT_RECOVERED 1 387 388 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *); 389 enum pcie_link_width pcie_get_width_cap(struct pci_dev *); 390 int pci_resize_resource(struct pci_dev *, int, int); 391 392 static inline void 393 pcie_bandwidth_available(struct pci_dev *pdev, struct pci_dev **ldev, 394 enum pci_bus_speed *speed, enum pcie_link_width *width) 395 { 396 struct pci_dev *bdev = pdev->bus->self; 397 if (bdev == NULL) 398 return; 399 400 if (speed) 401 *speed = pcie_get_speed_cap(bdev); 402 if (width) 403 *width = pcie_get_width_cap(bdev); 404 } 405 406 static inline int 407 pci_enable_device(struct pci_dev *pdev) 408 { 409 return 0; 410 } 411 412 static inline void 413 pci_disable_device(struct pci_dev *pdev) 414 { 415 } 416 417 static inline bool 418 pci_is_thunderbolt_attached(struct pci_dev *pdev) 419 { 420 return false; 421 } 422 423 static inline void 424 pci_set_drvdata(struct pci_dev *pdev, void *data) 425 { 426 } 427 428 static inline int 429 pci_domain_nr(struct pci_bus *pbus) 430 { 431 return pbus->domain_nr; 432 } 433 434 static inline int 435 pci_irq_vector(struct pci_dev *pdev, unsigned int num) 436 { 437 return pdev->irq; 438 } 439 440 static inline void 441 pci_free_irq_vectors(struct pci_dev *pdev) 442 { 443 } 444 445 static inline int 446 pci_set_power_state(struct pci_dev *dev, int state) 447 { 448 return 0; 449 } 450 451 static inline void 452 pci_unregister_driver(void *d) 453 { 454 } 455 456 #define PCI_CLASS_DISPLAY_VGA \ 457 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_VGA) 458 #define PCI_CLASS_DISPLAY_OTHER \ 459 ((PCI_CLASS_DISPLAY << 8) | PCI_SUBCLASS_DISPLAY_MISC) 460 461 #endif /* _LINUX_PCI_H_ */ 462