1 /* $OpenBSD: pci.h,v 1.4 2019/08/28 10:17:59 kettenis Exp $ */ 2 /* 3 * Copyright (c) 2015 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _LINUX_PCI_H 19 #define _LINUX_PCI_H 20 21 #include <sys/types.h> 22 #include <dev/pci/pcireg.h> 23 #include <dev/pci/pcivar.h> 24 /* sparc64 cpu.h needs time.h and siginfo.h (indirect via param.h) */ 25 #include <sys/param.h> 26 #include <machine/cpu.h> 27 #include <uvm/uvm_extern.h> 28 29 #include <linux/io.h> 30 #include <linux/ioport.h> 31 #include <linux/kobject.h> 32 33 struct pci_dev; 34 35 struct pci_bus { 36 pci_chipset_tag_t pc; 37 unsigned char number; 38 pcitag_t *bridgetag; 39 struct pci_dev *self; 40 }; 41 42 struct pci_acpi { 43 struct aml_node *node; 44 }; 45 46 struct pci_dev { 47 struct pci_bus _bus; 48 struct pci_bus *bus; 49 50 unsigned int devfn; 51 uint16_t vendor; 52 uint16_t device; 53 uint16_t subsystem_vendor; 54 uint16_t subsystem_device; 55 uint8_t revision; 56 57 pci_chipset_tag_t pc; 58 pcitag_t tag; 59 struct pci_softc *pci; 60 61 int irq; 62 int msi_enabled; 63 uint8_t no_64bit_msi; 64 65 struct pci_acpi dev; 66 }; 67 #define PCI_ANY_ID (uint16_t) (~0U) 68 69 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 70 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 71 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 72 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 73 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 74 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 75 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 76 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 77 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 78 79 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_QY 80 81 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 82 #define PCI_SUBDEVICE_ID_QEMU 0x1100 83 84 #define PCI_DEVFN(slot, func) ((slot) << 3 | (func)) 85 #define PCI_SLOT(devfn) ((devfn) >> 3) 86 #define PCI_FUNC(devfn) ((devfn) & 0x7) 87 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 88 89 #define pci_dev_put(x) 90 91 #define PCI_EXP_DEVSTA 0x0a 92 #define PCI_EXP_DEVSTA_TRPND 0x0020 93 #define PCI_EXP_LNKCAP 0x0c 94 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 95 #define PCI_EXP_LNKCTL 0x10 96 #define PCI_EXP_LNKCTL_HAWD 0x0200 97 #define PCI_EXP_LNKCTL2 0x30 98 99 #define PCI_COMMAND PCI_COMMAND_STATUS_REG 100 #define PCI_COMMAND_MEMORY PCI_COMMAND_MEM_ENABLE 101 102 static inline int 103 pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val) 104 { 105 *val = pci_conf_read(pdev->pc, pdev->tag, reg); 106 return 0; 107 } 108 109 static inline int 110 pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val) 111 { 112 uint32_t v; 113 114 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 115 *val = (v >> ((reg & 0x2) * 8)); 116 return 0; 117 } 118 119 static inline int 120 pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val) 121 { 122 uint32_t v; 123 124 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 125 *val = (v >> ((reg & 0x3) * 8)); 126 return 0; 127 } 128 129 static inline int 130 pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val) 131 { 132 pci_conf_write(pdev->pc, pdev->tag, reg, val); 133 return 0; 134 } 135 136 static inline int 137 pci_write_config_word(struct pci_dev *pdev, int reg, u16 val) 138 { 139 uint32_t v; 140 141 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 142 v &= ~(0xffff << ((reg & 0x2) * 8)); 143 v |= (val << ((reg & 0x2) * 8)); 144 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v); 145 return 0; 146 } 147 148 static inline int 149 pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val) 150 { 151 uint32_t v; 152 153 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 154 v &= ~(0xff << ((reg & 0x3) * 8)); 155 v |= (val << ((reg & 0x3) * 8)); 156 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x3), v); 157 return 0; 158 } 159 160 static inline int 161 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 162 int reg, u16 *val) 163 { 164 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 165 PCI_SLOT(devfn), PCI_FUNC(devfn)); 166 uint32_t v; 167 168 v = pci_conf_read(bus->pc, tag, (reg & ~0x2)); 169 *val = (v >> ((reg & 0x2) * 8)); 170 return 0; 171 } 172 173 static inline int 174 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 175 int reg, u8 *val) 176 { 177 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 178 PCI_SLOT(devfn), PCI_FUNC(devfn)); 179 uint32_t v; 180 181 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 182 *val = (v >> ((reg & 0x3) * 8)); 183 return 0; 184 } 185 186 static inline int 187 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 188 int reg, u8 val) 189 { 190 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 191 PCI_SLOT(devfn), PCI_FUNC(devfn)); 192 uint32_t v; 193 194 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 195 v &= ~(0xff << ((reg & 0x3) * 8)); 196 v |= (val << ((reg & 0x3) * 8)); 197 pci_conf_write(bus->pc, tag, (reg & ~0x3), v); 198 return 0; 199 } 200 201 static inline int 202 pci_pcie_cap(struct pci_dev *pdev) 203 { 204 int pos; 205 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 206 &pos, NULL)) 207 return -EINVAL; 208 return pos; 209 } 210 211 static inline bool 212 pci_is_root_bus(struct pci_bus *pbus) 213 { 214 return (pbus->bridgetag == NULL); 215 } 216 217 static inline int 218 pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val) 219 { 220 int pos; 221 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 222 &pos, NULL)) { 223 *val = 0; 224 return -EINVAL; 225 } 226 *val = pci_conf_read(pdev->pc, pdev->tag, pos + off); 227 return 0; 228 } 229 230 #define pci_set_master(x) 231 #define pci_clear_master(x) 232 233 #define pci_save_state(x) 234 #define pci_restore_state(x) 235 236 #define pci_enable_msi(x) 0 237 #define pci_disable_msi(x) 238 239 typedef enum { 240 PCI_D0, 241 PCI_D1, 242 PCI_D2, 243 PCI_D3hot, 244 PCI_D3cold 245 } pci_power_t; 246 247 enum pci_bus_speed { 248 PCIE_SPEED_2_5GT, 249 PCIE_SPEED_5_0GT, 250 PCIE_SPEED_8_0GT, 251 PCIE_SPEED_16_0GT, 252 PCI_SPEED_UNKNOWN 253 }; 254 255 enum pcie_link_width { 256 PCIE_LNK_X1 = 1, 257 PCIE_LNK_X2 = 2, 258 PCIE_LNK_X4 = 4, 259 PCIE_LNK_X8 = 8, 260 PCIE_LNK_X12 = 12, 261 PCIE_LNK_X16 = 16, 262 PCIE_LNK_X32 = 32, 263 PCIE_LNK_WIDTH_UNKNOWN = 0xff 264 }; 265 266 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *); 267 enum pcie_link_width pcie_get_width_cap(struct pci_dev *); 268 int pci_resize_resource(struct pci_dev *, int, int); 269 270 #define pci_save_state(x) 271 #define pci_enable_device(x) 0 272 #define pci_disable_device(x) 273 #define pci_is_thunderbolt_attached(x) false 274 #define pci_set_drvdata(x, y) 275 276 static inline int 277 pci_set_power_state(struct pci_dev *dev, int state) 278 { 279 return 0; 280 } 281 282 static inline struct pci_dev * 283 pci_get_class(pcireg_t class, struct pci_dev *pdev) 284 { 285 return NULL; 286 } 287 288 #define PCI_CLASS_DISPLAY_VGA \ 289 (PCI_CLASS_DISPLAY | PCI_SUBCLASS_DISPLAY_VGA) 290 #define PCI_CLASS_DISPLAY_OTHER \ 291 (PCI_CLASS_DISPLAY | PCI_SUBCLASS_DISPLAY_MISC) 292 293 #if defined(__amd64__) || defined(__arm64__) || defined(__i386__) 294 295 #define PCI_DMA_BIDIRECTIONAL 0 296 297 static inline dma_addr_t 298 pci_map_page(struct pci_dev *pdev, struct vm_page *page, unsigned long offset, size_t size, int direction) 299 { 300 return VM_PAGE_TO_PHYS(page); 301 } 302 303 static inline void 304 pci_unmap_page(struct pci_dev *pdev, dma_addr_t dma_address, size_t size, int direction) 305 { 306 } 307 308 static inline int 309 pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t dma_addr) 310 { 311 return 0; 312 } 313 314 #define pci_set_dma_mask(x, y) 0 315 #define pci_set_consistent_dma_mask(x, y) 0 316 317 #endif /* defined(__amd64__) || defined(__arm64__) || defined(__i386__) */ 318 319 #endif 320