1 /* $OpenBSD: pci.h,v 1.1 2019/04/14 10:14:53 jsg Exp $ */ 2 /* 3 * Copyright (c) 2015 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _LINUX_PCI_H 19 #define _LINUX_PCI_H 20 21 #include <sys/types.h> 22 #include <dev/pci/pcireg.h> 23 #include <dev/pci/pcivar.h> 24 /* sparc64 cpu.h needs time.h and siginfo.h (indirect via param.h) */ 25 #include <sys/param.h> 26 #include <machine/cpu.h> 27 #include <uvm/uvm_extern.h> 28 29 #include <linux/io.h> 30 #include <linux/ioport.h> 31 #include <linux/kobject.h> 32 33 struct pci_dev; 34 35 struct pci_bus { 36 pci_chipset_tag_t pc; 37 unsigned char number; 38 pcitag_t *bridgetag; 39 struct pci_dev *self; 40 }; 41 42 struct pci_dev { 43 struct pci_bus _bus; 44 struct pci_bus *bus; 45 46 unsigned int devfn; 47 uint16_t vendor; 48 uint16_t device; 49 uint16_t subsystem_vendor; 50 uint16_t subsystem_device; 51 uint8_t revision; 52 53 pci_chipset_tag_t pc; 54 pcitag_t tag; 55 struct pci_softc *pci; 56 57 int irq; 58 int msi_enabled; 59 uint8_t no_64bit_msi; 60 }; 61 #define PCI_ANY_ID (uint16_t) (~0U) 62 63 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 64 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 65 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 66 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 67 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 68 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 69 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 70 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 71 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 72 73 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_QY 74 75 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 76 #define PCI_SUBDEVICE_ID_QEMU 0x1100 77 78 #define PCI_DEVFN(slot, func) ((slot) << 3 | (func)) 79 #define PCI_SLOT(devfn) ((devfn) >> 3) 80 #define PCI_FUNC(devfn) ((devfn) & 0x7) 81 82 #define pci_dev_put(x) 83 84 #define PCI_EXP_DEVSTA 0x0a 85 #define PCI_EXP_DEVSTA_TRPND 0x0020 86 #define PCI_EXP_LNKCAP 0x0c 87 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 88 #define PCI_EXP_LNKCTL 0x10 89 #define PCI_EXP_LNKCTL_HAWD 0x0200 90 #define PCI_EXP_LNKCTL2 0x30 91 92 #define PCI_COMMAND PCI_COMMAND_STATUS_REG 93 #define PCI_COMMAND_MEMORY PCI_COMMAND_MEM_ENABLE 94 95 static inline int 96 pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val) 97 { 98 *val = pci_conf_read(pdev->pc, pdev->tag, reg); 99 return 0; 100 } 101 102 static inline int 103 pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val) 104 { 105 uint32_t v; 106 107 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 108 *val = (v >> ((reg & 0x2) * 8)); 109 return 0; 110 } 111 112 static inline int 113 pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val) 114 { 115 uint32_t v; 116 117 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 118 *val = (v >> ((reg & 0x3) * 8)); 119 return 0; 120 } 121 122 static inline int 123 pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val) 124 { 125 pci_conf_write(pdev->pc, pdev->tag, reg, val); 126 return 0; 127 } 128 129 static inline int 130 pci_write_config_word(struct pci_dev *pdev, int reg, u16 val) 131 { 132 uint32_t v; 133 134 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 135 v &= ~(0xffff << ((reg & 0x2) * 8)); 136 v |= (val << ((reg & 0x2) * 8)); 137 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v); 138 return 0; 139 } 140 141 static inline int 142 pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val) 143 { 144 uint32_t v; 145 146 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 147 v &= ~(0xff << ((reg & 0x3) * 8)); 148 v |= (val << ((reg & 0x3) * 8)); 149 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x3), v); 150 return 0; 151 } 152 153 static inline int 154 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 155 int reg, u16 *val) 156 { 157 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 158 PCI_SLOT(devfn), PCI_FUNC(devfn)); 159 uint32_t v; 160 161 v = pci_conf_read(bus->pc, tag, (reg & ~0x2)); 162 *val = (v >> ((reg & 0x2) * 8)); 163 return 0; 164 } 165 166 static inline int 167 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 168 int reg, u8 *val) 169 { 170 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 171 PCI_SLOT(devfn), PCI_FUNC(devfn)); 172 uint32_t v; 173 174 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 175 *val = (v >> ((reg & 0x3) * 8)); 176 return 0; 177 } 178 179 static inline int 180 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 181 int reg, u8 val) 182 { 183 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 184 PCI_SLOT(devfn), PCI_FUNC(devfn)); 185 uint32_t v; 186 187 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 188 v &= ~(0xff << ((reg & 0x3) * 8)); 189 v |= (val << ((reg & 0x3) * 8)); 190 pci_conf_write(bus->pc, tag, (reg & ~0x3), v); 191 return 0; 192 } 193 194 static inline int 195 pci_pcie_cap(struct pci_dev *pdev) 196 { 197 int pos; 198 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 199 &pos, NULL)) 200 return -EINVAL; 201 return pos; 202 } 203 204 static inline bool 205 pci_is_root_bus(struct pci_bus *pbus) 206 { 207 return (pbus->bridgetag == NULL); 208 } 209 210 static inline int 211 pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val) 212 { 213 int pos; 214 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 215 &pos, NULL)) { 216 *val = 0; 217 return -EINVAL; 218 } 219 *val = pci_conf_read(pdev->pc, pdev->tag, pos + off); 220 return 0; 221 } 222 223 #define pci_set_master(x) 224 #define pci_clear_master(x) 225 226 #define pci_save_state(x) 227 #define pci_restore_state(x) 228 229 #define pci_enable_msi(x) 0 230 #define pci_disable_msi(x) 231 232 typedef enum { 233 PCI_D0, 234 PCI_D1, 235 PCI_D2, 236 PCI_D3hot, 237 PCI_D3cold 238 } pci_power_t; 239 240 enum pci_bus_speed { 241 PCIE_SPEED_2_5GT, 242 PCIE_SPEED_5_0GT, 243 PCIE_SPEED_8_0GT, 244 PCIE_SPEED_16_0GT, 245 PCI_SPEED_UNKNOWN 246 }; 247 248 enum pcie_link_width { 249 PCIE_LNK_X1 = 1, 250 PCIE_LNK_X2 = 2, 251 PCIE_LNK_X4 = 4, 252 PCIE_LNK_X8 = 8, 253 PCIE_LNK_X12 = 12, 254 PCIE_LNK_X16 = 16, 255 PCIE_LNK_X32 = 32, 256 PCIE_LNK_WIDTH_UNKNOWN = 0xff 257 }; 258 259 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *); 260 enum pcie_link_width pcie_get_width_cap(struct pci_dev *); 261 int pci_resize_resource(struct pci_dev *, int, int); 262 263 #define pci_save_state(x) 264 #define pci_enable_device(x) 0 265 #define pci_disable_device(x) 266 #define pci_is_thunderbolt_attached(x) false 267 #define pci_set_drvdata(x, y) 268 269 static inline int 270 pci_set_power_state(struct pci_dev *dev, int state) 271 { 272 return 0; 273 } 274 275 #if defined(__amd64__) || defined(__i386__) 276 277 #define PCI_DMA_BIDIRECTIONAL 0 278 279 static inline dma_addr_t 280 pci_map_page(struct pci_dev *pdev, struct vm_page *page, unsigned long offset, size_t size, int direction) 281 { 282 return VM_PAGE_TO_PHYS(page); 283 } 284 285 static inline void 286 pci_unmap_page(struct pci_dev *pdev, dma_addr_t dma_address, size_t size, int direction) 287 { 288 } 289 290 static inline int 291 pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t dma_addr) 292 { 293 return 0; 294 } 295 296 #define pci_set_dma_mask(x, y) 0 297 #define pci_set_consistent_dma_mask(x, y) 0 298 299 #endif /* defined(__amd64__) || defined(__i386__) */ 300 301 #endif 302