1 /* $OpenBSD: pci.h,v 1.5 2020/06/08 04:48:15 jsg Exp $ */ 2 /* 3 * Copyright (c) 2015 Mark Kettenis 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _LINUX_PCI_H 19 #define _LINUX_PCI_H 20 21 #include <sys/types.h> 22 /* sparc64 cpu.h needs time.h and siginfo.h (indirect via param.h) */ 23 #include <sys/param.h> 24 #include <machine/cpu.h> 25 26 #include <dev/pci/pcireg.h> 27 #include <dev/pci/pcivar.h> 28 #include <dev/pci/pcidevs.h> 29 #include <uvm/uvm_extern.h> 30 31 #include <linux/io.h> 32 #include <linux/ioport.h> 33 #include <linux/kobject.h> 34 #include <linux/dma-mapping.h> /* pci-dma-compat.h -> dma-mapping.h */ 35 #include <linux/mod_devicetable.h> 36 37 struct pci_dev; 38 39 struct pci_bus { 40 pci_chipset_tag_t pc; 41 unsigned char number; 42 int domain_nr; 43 pcitag_t *bridgetag; 44 struct pci_dev *self; 45 }; 46 47 struct pci_acpi { 48 struct aml_node *node; 49 }; 50 51 struct pci_dev { 52 struct pci_bus _bus; 53 struct pci_bus *bus; 54 55 unsigned int devfn; 56 uint16_t vendor; 57 uint16_t device; 58 uint16_t subsystem_vendor; 59 uint16_t subsystem_device; 60 uint8_t revision; 61 62 pci_chipset_tag_t pc; 63 pcitag_t tag; 64 struct pci_softc *pci; 65 66 int irq; 67 int msi_enabled; 68 uint8_t no_64bit_msi; 69 70 struct pci_acpi dev; 71 }; 72 #define PCI_ANY_ID (uint16_t) (~0U) 73 74 #ifndef PCI_MEM_START 75 #define PCI_MEM_START 0 76 #endif 77 78 #ifndef PCI_MEM_END 79 #define PCI_MEM_END 0xffffffff 80 #endif 81 82 #ifndef PCI_MEM64_END 83 #define PCI_MEM64_END 0xffffffffffffffff 84 #endif 85 86 #define PCI_VENDOR_ID_APPLE PCI_VENDOR_APPLE 87 #define PCI_VENDOR_ID_ASUSTEK PCI_VENDOR_ASUSTEK 88 #define PCI_VENDOR_ID_ATI PCI_VENDOR_ATI 89 #define PCI_VENDOR_ID_DELL PCI_VENDOR_DELL 90 #define PCI_VENDOR_ID_HP PCI_VENDOR_HP 91 #define PCI_VENDOR_ID_IBM PCI_VENDOR_IBM 92 #define PCI_VENDOR_ID_INTEL PCI_VENDOR_INTEL 93 #define PCI_VENDOR_ID_SONY PCI_VENDOR_SONY 94 #define PCI_VENDOR_ID_VIA PCI_VENDOR_VIATECH 95 96 #define PCI_DEVICE_ID_ATI_RADEON_QY PCI_PRODUCT_ATI_RADEON_QY 97 98 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4 99 #define PCI_SUBDEVICE_ID_QEMU 0x1100 100 101 #define PCI_DEVFN(slot, func) ((slot) << 3 | (func)) 102 #define PCI_SLOT(devfn) ((devfn) >> 3) 103 #define PCI_FUNC(devfn) ((devfn) & 0x7) 104 #define PCI_BUS_NUM(devfn) (((devfn) >> 8) & 0xff) 105 106 #define pci_dev_put(x) 107 108 #define PCI_EXP_DEVSTA 0x0a 109 #define PCI_EXP_DEVSTA_TRPND 0x0020 110 #define PCI_EXP_LNKCAP 0x0c 111 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 112 #define PCI_EXP_LNKCTL 0x10 113 #define PCI_EXP_LNKCTL_HAWD 0x0200 114 #define PCI_EXP_LNKCTL2 0x30 115 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 116 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 117 #define PCI_EXP_LNKCTL2_TLS PCI_PCIE_LCSR2_TLS 118 #define PCI_EXP_LNKCTL2_TLS_2_5GT PCI_PCIE_LCSR2_TLS_2_5 119 #define PCI_EXP_LNKCTL2_TLS_5_0GT PCI_PCIE_LCSR2_TLS_5 120 #define PCI_EXP_LNKCTL2_TLS_8_0GT PCI_PCIE_LCSR2_TLS_8 121 122 #define PCI_COMMAND PCI_COMMAND_STATUS_REG 123 #define PCI_COMMAND_MEMORY PCI_COMMAND_MEM_ENABLE 124 125 static inline int 126 pci_read_config_dword(struct pci_dev *pdev, int reg, u32 *val) 127 { 128 *val = pci_conf_read(pdev->pc, pdev->tag, reg); 129 return 0; 130 } 131 132 static inline int 133 pci_read_config_word(struct pci_dev *pdev, int reg, u16 *val) 134 { 135 uint32_t v; 136 137 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 138 *val = (v >> ((reg & 0x2) * 8)); 139 return 0; 140 } 141 142 static inline int 143 pci_read_config_byte(struct pci_dev *pdev, int reg, u8 *val) 144 { 145 uint32_t v; 146 147 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 148 *val = (v >> ((reg & 0x3) * 8)); 149 return 0; 150 } 151 152 static inline int 153 pci_write_config_dword(struct pci_dev *pdev, int reg, u32 val) 154 { 155 pci_conf_write(pdev->pc, pdev->tag, reg, val); 156 return 0; 157 } 158 159 static inline int 160 pci_write_config_word(struct pci_dev *pdev, int reg, u16 val) 161 { 162 uint32_t v; 163 164 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x2)); 165 v &= ~(0xffff << ((reg & 0x2) * 8)); 166 v |= (val << ((reg & 0x2) * 8)); 167 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x2), v); 168 return 0; 169 } 170 171 static inline int 172 pci_write_config_byte(struct pci_dev *pdev, int reg, u8 val) 173 { 174 uint32_t v; 175 176 v = pci_conf_read(pdev->pc, pdev->tag, (reg & ~0x3)); 177 v &= ~(0xff << ((reg & 0x3) * 8)); 178 v |= (val << ((reg & 0x3) * 8)); 179 pci_conf_write(pdev->pc, pdev->tag, (reg & ~0x3), v); 180 return 0; 181 } 182 183 static inline int 184 pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, 185 int reg, u16 *val) 186 { 187 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 188 PCI_SLOT(devfn), PCI_FUNC(devfn)); 189 uint32_t v; 190 191 v = pci_conf_read(bus->pc, tag, (reg & ~0x2)); 192 *val = (v >> ((reg & 0x2) * 8)); 193 return 0; 194 } 195 196 static inline int 197 pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, 198 int reg, u8 *val) 199 { 200 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 201 PCI_SLOT(devfn), PCI_FUNC(devfn)); 202 uint32_t v; 203 204 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 205 *val = (v >> ((reg & 0x3) * 8)); 206 return 0; 207 } 208 209 static inline int 210 pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, 211 int reg, u8 val) 212 { 213 pcitag_t tag = pci_make_tag(bus->pc, bus->number, 214 PCI_SLOT(devfn), PCI_FUNC(devfn)); 215 uint32_t v; 216 217 v = pci_conf_read(bus->pc, tag, (reg & ~0x3)); 218 v &= ~(0xff << ((reg & 0x3) * 8)); 219 v |= (val << ((reg & 0x3) * 8)); 220 pci_conf_write(bus->pc, tag, (reg & ~0x3), v); 221 return 0; 222 } 223 224 static inline int 225 pci_pcie_cap(struct pci_dev *pdev) 226 { 227 int pos; 228 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 229 &pos, NULL)) 230 return -EINVAL; 231 return pos; 232 } 233 234 static inline bool 235 pci_is_pcie(struct pci_dev *pdev) 236 { 237 return (pci_pcie_cap(pdev) > 0); 238 } 239 240 static inline bool 241 pci_is_root_bus(struct pci_bus *pbus) 242 { 243 return (pbus->bridgetag == NULL); 244 } 245 246 static inline int 247 pcie_capability_read_dword(struct pci_dev *pdev, int off, u32 *val) 248 { 249 int pos; 250 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 251 &pos, NULL)) { 252 *val = 0; 253 return -EINVAL; 254 } 255 *val = pci_conf_read(pdev->pc, pdev->tag, pos + off); 256 return 0; 257 } 258 259 static inline int 260 pcie_capability_read_word(struct pci_dev *pdev, int off, u16 *val) 261 { 262 int pos; 263 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 264 &pos, NULL)) { 265 *val = 0; 266 return -EINVAL; 267 } 268 pci_read_config_word(pdev, pos + off, val); 269 return 0; 270 } 271 272 static inline int 273 pcie_capability_write_word(struct pci_dev *pdev, int off, u16 val) 274 { 275 int pos; 276 if (!pci_get_capability(pdev->pc, pdev->tag, PCI_CAP_PCIEXPRESS, 277 &pos, NULL)) 278 return -EINVAL; 279 pci_write_config_word(pdev, pos + off, val); 280 return 0; 281 } 282 283 static inline int 284 pcie_get_readrq(struct pci_dev *pdev) 285 { 286 uint16_t val; 287 288 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val); 289 290 return 128 << ((val & PCI_PCIE_DCSR_MPS) >> 12); 291 } 292 293 static inline int 294 pcie_set_readrq(struct pci_dev *pdev, int rrq) 295 { 296 uint16_t val; 297 298 pcie_capability_read_word(pdev, PCI_PCIE_DCSR, &val); 299 val &= ~PCI_PCIE_DCSR_MPS; 300 val |= (ffs(rrq) - 8) << 12; 301 return pcie_capability_write_word(pdev, PCI_PCIE_DCSR, val); 302 } 303 304 #define pci_set_master(x) 305 #define pci_clear_master(x) 306 307 #define pci_save_state(x) 308 #define pci_restore_state(x) 309 310 #define pci_enable_msi(x) 0 311 #define pci_disable_msi(x) 312 313 typedef enum { 314 PCI_D0, 315 PCI_D1, 316 PCI_D2, 317 PCI_D3hot, 318 PCI_D3cold 319 } pci_power_t; 320 321 enum pci_bus_speed { 322 PCIE_SPEED_2_5GT, 323 PCIE_SPEED_5_0GT, 324 PCIE_SPEED_8_0GT, 325 PCIE_SPEED_16_0GT, 326 PCI_SPEED_UNKNOWN 327 }; 328 329 enum pcie_link_width { 330 PCIE_LNK_X1 = 1, 331 PCIE_LNK_X2 = 2, 332 PCIE_LNK_X4 = 4, 333 PCIE_LNK_X8 = 8, 334 PCIE_LNK_X12 = 12, 335 PCIE_LNK_X16 = 16, 336 PCIE_LNK_X32 = 32, 337 PCIE_LNK_WIDTH_UNKNOWN = 0xff 338 }; 339 340 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *); 341 enum pcie_link_width pcie_get_width_cap(struct pci_dev *); 342 int pci_resize_resource(struct pci_dev *, int, int); 343 344 static inline void 345 pcie_bandwidth_available(struct pci_dev *pdev, struct pci_dev **ldev, 346 enum pci_bus_speed *speed, enum pcie_link_width *width) 347 { 348 struct pci_dev *bdev = pdev->bus->self; 349 if (bdev == NULL) 350 return; 351 352 if (speed) 353 *speed = pcie_get_speed_cap(bdev); 354 if (width) 355 *width = pcie_get_width_cap(bdev); 356 } 357 358 #define pci_save_state(x) 359 #define pci_enable_device(x) 0 360 #define pci_disable_device(x) 361 #define pci_is_thunderbolt_attached(x) false 362 #define pci_set_drvdata(x, y) 363 364 static inline int 365 pci_domain_nr(struct pci_bus *pbus) 366 { 367 return pbus->domain_nr; 368 } 369 370 static inline int 371 pci_irq_vector(struct pci_dev *pdev, unsigned int num) 372 { 373 return pdev->irq; 374 } 375 376 static inline void 377 pci_free_irq_vectors(struct pci_dev *pdev) 378 { 379 } 380 381 static inline int 382 pci_set_power_state(struct pci_dev *dev, int state) 383 { 384 return 0; 385 } 386 387 static inline struct pci_dev * 388 pci_get_class(pcireg_t class, struct pci_dev *pdev) 389 { 390 return NULL; 391 } 392 393 #define PCI_CLASS_DISPLAY_VGA \ 394 (PCI_CLASS_DISPLAY | PCI_SUBCLASS_DISPLAY_VGA) 395 #define PCI_CLASS_DISPLAY_OTHER \ 396 (PCI_CLASS_DISPLAY | PCI_SUBCLASS_DISPLAY_MISC) 397 398 #if defined(__amd64__) || defined(__arm64__) || defined(__i386__) 399 400 #define PCI_DMA_BIDIRECTIONAL 0 401 402 static inline dma_addr_t 403 pci_map_page(struct pci_dev *pdev, struct vm_page *page, unsigned long offset, size_t size, int direction) 404 { 405 return VM_PAGE_TO_PHYS(page); 406 } 407 408 static inline void 409 pci_unmap_page(struct pci_dev *pdev, dma_addr_t dma_address, size_t size, int direction) 410 { 411 } 412 413 static inline int 414 pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t dma_addr) 415 { 416 return 0; 417 } 418 419 #define pci_set_dma_mask(x, y) 0 420 #define pci_set_consistent_dma_mask(x, y) 0 421 422 #endif /* defined(__amd64__) || defined(__arm64__) || defined(__i386__) */ 423 424 #endif 425