xref: /openbsd-src/sys/dev/pci/drm/i915/pxp/intel_pxp_irq.h (revision f005ef32267c16bdb134f0e9fa4477dbe07c263a)
11bb76ff1Sjsg /* SPDX-License-Identifier: MIT */
21bb76ff1Sjsg /*
31bb76ff1Sjsg  * Copyright(c) 2020, Intel Corporation. All rights reserved.
41bb76ff1Sjsg  */
51bb76ff1Sjsg 
61bb76ff1Sjsg #ifndef __INTEL_PXP_IRQ_H__
71bb76ff1Sjsg #define __INTEL_PXP_IRQ_H__
81bb76ff1Sjsg 
91bb76ff1Sjsg #include <linux/types.h>
101bb76ff1Sjsg 
111bb76ff1Sjsg struct intel_pxp;
121bb76ff1Sjsg 
131bb76ff1Sjsg #define GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT BIT(1)
141bb76ff1Sjsg #define GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT BIT(2)
151bb76ff1Sjsg #define GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT BIT(3)
161bb76ff1Sjsg 
171bb76ff1Sjsg #define GEN12_PXP_INTERRUPTS \
181bb76ff1Sjsg 	(GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT | \
191bb76ff1Sjsg 	 GEN12_DISPLAY_APP_TERMINATED_PER_FW_REQ_INTERRUPT | \
201bb76ff1Sjsg 	 GEN12_DISPLAY_STATE_RESET_COMPLETE_INTERRUPT)
211bb76ff1Sjsg 
221bb76ff1Sjsg #ifdef CONFIG_DRM_I915_PXP
231bb76ff1Sjsg void intel_pxp_irq_enable(struct intel_pxp *pxp);
241bb76ff1Sjsg void intel_pxp_irq_disable(struct intel_pxp *pxp);
251bb76ff1Sjsg void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir);
261bb76ff1Sjsg #else
intel_pxp_irq_handler(struct intel_pxp * pxp,u16 iir)271bb76ff1Sjsg static inline void intel_pxp_irq_handler(struct intel_pxp *pxp, u16 iir)
281bb76ff1Sjsg {
291bb76ff1Sjsg }
30*f005ef32Sjsg 
intel_pxp_irq_enable(struct intel_pxp * pxp)31*f005ef32Sjsg static inline void intel_pxp_irq_enable(struct intel_pxp *pxp)
32*f005ef32Sjsg {
33*f005ef32Sjsg }
34*f005ef32Sjsg 
intel_pxp_irq_disable(struct intel_pxp * pxp)35*f005ef32Sjsg static inline void intel_pxp_irq_disable(struct intel_pxp *pxp)
36*f005ef32Sjsg {
37*f005ef32Sjsg }
381bb76ff1Sjsg #endif
391bb76ff1Sjsg 
401bb76ff1Sjsg #endif /* __INTEL_PXP_IRQ_H__ */
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