1*f005ef32Sjsg // SPDX-License-Identifier: MIT
2*f005ef32Sjsg /*
3*f005ef32Sjsg * Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
4*f005ef32Sjsg */
5*f005ef32Sjsg
6*f005ef32Sjsg #include "i915_drv.h"
7*f005ef32Sjsg
8*f005ef32Sjsg #include "gem/i915_gem_region.h"
9*f005ef32Sjsg #include "gt/intel_gt.h"
10*f005ef32Sjsg
11*f005ef32Sjsg #include "intel_pxp.h"
12*f005ef32Sjsg #include "intel_pxp_huc.h"
13*f005ef32Sjsg #include "intel_pxp_tee.h"
14*f005ef32Sjsg #include "intel_pxp_types.h"
15*f005ef32Sjsg #include "intel_pxp_cmd_interface_43.h"
16*f005ef32Sjsg
intel_pxp_huc_load_and_auth(struct intel_pxp * pxp)17*f005ef32Sjsg int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
18*f005ef32Sjsg {
19*f005ef32Sjsg struct intel_gt *gt;
20*f005ef32Sjsg struct intel_huc *huc;
21*f005ef32Sjsg struct pxp43_start_huc_auth_in huc_in = {0};
22*f005ef32Sjsg struct pxp43_huc_auth_out huc_out = {0};
23*f005ef32Sjsg dma_addr_t huc_phys_addr;
24*f005ef32Sjsg u8 client_id = 0;
25*f005ef32Sjsg u8 fence_id = 0;
26*f005ef32Sjsg int err;
27*f005ef32Sjsg
28*f005ef32Sjsg if (!pxp || !pxp->pxp_component)
29*f005ef32Sjsg return -ENODEV;
30*f005ef32Sjsg
31*f005ef32Sjsg gt = pxp->ctrl_gt;
32*f005ef32Sjsg huc = >->uc.huc;
33*f005ef32Sjsg
34*f005ef32Sjsg huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0);
35*f005ef32Sjsg
36*f005ef32Sjsg /* write the PXP message into the lmem (the sg list) */
37*f005ef32Sjsg huc_in.header.api_version = PXP_APIVER(4, 3);
38*f005ef32Sjsg huc_in.header.command_id = PXP43_CMDID_START_HUC_AUTH;
39*f005ef32Sjsg huc_in.header.status = 0;
40*f005ef32Sjsg huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
41*f005ef32Sjsg huc_in.huc_base_address = cpu_to_le64(huc_phys_addr);
42*f005ef32Sjsg
43*f005ef32Sjsg err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
44*f005ef32Sjsg &huc_in, sizeof(huc_in),
45*f005ef32Sjsg &huc_out, sizeof(huc_out));
46*f005ef32Sjsg if (err < 0) {
47*f005ef32Sjsg drm_err(>->i915->drm,
48*f005ef32Sjsg "Failed to send HuC load and auth command to GSC [%d]!\n",
49*f005ef32Sjsg err);
50*f005ef32Sjsg return err;
51*f005ef32Sjsg }
52*f005ef32Sjsg
53*f005ef32Sjsg /*
54*f005ef32Sjsg * HuC does sometimes survive suspend/resume (it depends on how "deep"
55*f005ef32Sjsg * a sleep state the device reaches) so we can end up here on resume
56*f005ef32Sjsg * with HuC already loaded, in which case the GSC will return
57*f005ef32Sjsg * PXP_STATUS_OP_NOT_PERMITTED. We can therefore consider the GuC
58*f005ef32Sjsg * correctly transferred in this scenario; if the same error is ever
59*f005ef32Sjsg * returned with HuC not loaded we'll still catch it when we check the
60*f005ef32Sjsg * authentication bit later.
61*f005ef32Sjsg */
62*f005ef32Sjsg if (huc_out.header.status != PXP_STATUS_SUCCESS &&
63*f005ef32Sjsg huc_out.header.status != PXP_STATUS_OP_NOT_PERMITTED) {
64*f005ef32Sjsg drm_err(>->i915->drm,
65*f005ef32Sjsg "HuC load failed with GSC error = 0x%x\n",
66*f005ef32Sjsg huc_out.header.status);
67*f005ef32Sjsg return -EPROTO;
68*f005ef32Sjsg }
69*f005ef32Sjsg
70*f005ef32Sjsg return 0;
71*f005ef32Sjsg }
72