1f005ef32Sjsg /* SPDX-License-Identifier: MIT */ 2f005ef32Sjsg /* 3f005ef32Sjsg * Copyright(c) 2022, Intel Corporation. All rights reserved. 4f005ef32Sjsg */ 5f005ef32Sjsg 6f005ef32Sjsg #ifndef __INTEL_PXP_GSCCS_H__ 7f005ef32Sjsg #define __INTEL_PXP_GSCCS_H__ 8f005ef32Sjsg 9f005ef32Sjsg #include <linux/types.h> 10f005ef32Sjsg 11*ab5e6dadSjsg #include "gt/uc/intel_gsc_uc_heci_cmd_submit.h" 12*ab5e6dadSjsg 13f005ef32Sjsg struct intel_pxp; 14f005ef32Sjsg 15f005ef32Sjsg #define GSC_PENDING_RETRY_MAXCOUNT 40 16f005ef32Sjsg #define GSC_PENDING_RETRY_PAUSE_MS 50 17*ab5e6dadSjsg #define GSCFW_MAX_ROUND_TRIP_LATENCY_MS (GSC_HECI_REPLY_LATENCY_MS + \ 18*ab5e6dadSjsg (GSC_PENDING_RETRY_MAXCOUNT * GSC_PENDING_RETRY_PAUSE_MS)) 19f005ef32Sjsg 20f005ef32Sjsg #ifdef CONFIG_DRM_I915_PXP 21f005ef32Sjsg void intel_pxp_gsccs_fini(struct intel_pxp *pxp); 22f005ef32Sjsg int intel_pxp_gsccs_init(struct intel_pxp *pxp); 23f005ef32Sjsg 24f005ef32Sjsg int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id); 25f005ef32Sjsg void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id); 26f005ef32Sjsg 27f005ef32Sjsg #else intel_pxp_gsccs_fini(struct intel_pxp * pxp)28f005ef32Sjsgstatic inline void intel_pxp_gsccs_fini(struct intel_pxp *pxp) 29f005ef32Sjsg { 30f005ef32Sjsg } 31f005ef32Sjsg intel_pxp_gsccs_init(struct intel_pxp * pxp)32f005ef32Sjsgstatic inline int intel_pxp_gsccs_init(struct intel_pxp *pxp) 33f005ef32Sjsg { 34f005ef32Sjsg return 0; 35f005ef32Sjsg } 36f005ef32Sjsg 37f005ef32Sjsg #endif 38f005ef32Sjsg 39f005ef32Sjsg bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp); 40f005ef32Sjsg 41f005ef32Sjsg #endif /*__INTEL_PXP_GSCCS_H__ */ 42