11bb76ff1Sjsg // SPDX-License-Identifier: MIT
21bb76ff1Sjsg /*
31bb76ff1Sjsg * Copyright © 2021 Intel Corporation
41bb76ff1Sjsg */
51bb76ff1Sjsg
61bb76ff1Sjsg #include <linux/debugfs.h>
71bb76ff1Sjsg #include <linux/string_helpers.h>
81bb76ff1Sjsg
91bb76ff1Sjsg #include <drm/drm_print.h>
101bb76ff1Sjsg
111bb76ff1Sjsg #include "gt/intel_gt_debugfs.h"
12*f005ef32Sjsg
131bb76ff1Sjsg #include "i915_drv.h"
14*f005ef32Sjsg
151bb76ff1Sjsg #include "intel_pxp.h"
161bb76ff1Sjsg #include "intel_pxp_debugfs.h"
17*f005ef32Sjsg #include "intel_pxp_gsccs.h"
181bb76ff1Sjsg #include "intel_pxp_irq.h"
19*f005ef32Sjsg #include "intel_pxp_types.h"
201bb76ff1Sjsg
pxp_info_show(struct seq_file * m,void * data)211bb76ff1Sjsg static int pxp_info_show(struct seq_file *m, void *data)
221bb76ff1Sjsg {
231bb76ff1Sjsg struct intel_pxp *pxp = m->private;
241bb76ff1Sjsg struct drm_printer p = drm_seq_file_printer(m);
251bb76ff1Sjsg
26*f005ef32Sjsg if (!intel_pxp_is_enabled(pxp)) {
271bb76ff1Sjsg drm_printf(&p, "pxp disabled\n");
281bb76ff1Sjsg return 0;
291bb76ff1Sjsg }
301bb76ff1Sjsg
311bb76ff1Sjsg drm_printf(&p, "active: %s\n", str_yes_no(intel_pxp_is_active(pxp)));
321bb76ff1Sjsg drm_printf(&p, "instance counter: %u\n", pxp->key_instance);
331bb76ff1Sjsg
341bb76ff1Sjsg return 0;
351bb76ff1Sjsg }
36*f005ef32Sjsg
37*f005ef32Sjsg DEFINE_SHOW_ATTRIBUTE(pxp_info);
381bb76ff1Sjsg
pxp_terminate_get(void * data,u64 * val)391bb76ff1Sjsg static int pxp_terminate_get(void *data, u64 *val)
401bb76ff1Sjsg {
411bb76ff1Sjsg /* nothing to read */
421bb76ff1Sjsg return -EPERM;
431bb76ff1Sjsg }
441bb76ff1Sjsg
pxp_terminate_set(void * data,u64 val)451bb76ff1Sjsg static int pxp_terminate_set(void *data, u64 val)
461bb76ff1Sjsg {
471bb76ff1Sjsg struct intel_pxp *pxp = data;
48*f005ef32Sjsg struct intel_gt *gt = pxp->ctrl_gt;
49*f005ef32Sjsg int timeout_ms;
501bb76ff1Sjsg
511bb76ff1Sjsg if (!intel_pxp_is_active(pxp))
521bb76ff1Sjsg return -ENODEV;
531bb76ff1Sjsg
541bb76ff1Sjsg /* simulate a termination interrupt */
551bb76ff1Sjsg spin_lock_irq(gt->irq_lock);
561bb76ff1Sjsg intel_pxp_irq_handler(pxp, GEN12_DISPLAY_PXP_STATE_TERMINATED_INTERRUPT);
571bb76ff1Sjsg spin_unlock_irq(gt->irq_lock);
581bb76ff1Sjsg
59*f005ef32Sjsg timeout_ms = intel_pxp_get_backend_timeout_ms(pxp);
60*f005ef32Sjsg
611bb76ff1Sjsg if (!wait_for_completion_timeout(&pxp->termination,
62*f005ef32Sjsg msecs_to_jiffies(timeout_ms)))
631bb76ff1Sjsg return -ETIMEDOUT;
641bb76ff1Sjsg
651bb76ff1Sjsg return 0;
661bb76ff1Sjsg }
671bb76ff1Sjsg
681bb76ff1Sjsg DEFINE_SIMPLE_ATTRIBUTE(pxp_terminate_fops, pxp_terminate_get, pxp_terminate_set, "%llx\n");
69*f005ef32Sjsg
intel_pxp_debugfs_register(struct intel_pxp * pxp)70*f005ef32Sjsg void intel_pxp_debugfs_register(struct intel_pxp *pxp)
711bb76ff1Sjsg {
72*f005ef32Sjsg struct drm_minor *minor;
73*f005ef32Sjsg struct dentry *pxproot;
741bb76ff1Sjsg
75*f005ef32Sjsg if (!intel_pxp_is_supported(pxp))
761bb76ff1Sjsg return;
771bb76ff1Sjsg
78*f005ef32Sjsg minor = pxp->ctrl_gt->i915->drm.primary;
79*f005ef32Sjsg if (!minor->debugfs_root)
801bb76ff1Sjsg return;
811bb76ff1Sjsg
82*f005ef32Sjsg pxproot = debugfs_create_dir("pxp", minor->debugfs_root);
83*f005ef32Sjsg if (IS_ERR(pxproot))
841bb76ff1Sjsg return;
851bb76ff1Sjsg
86*f005ef32Sjsg debugfs_create_file("info", 0444, pxproot,
87*f005ef32Sjsg pxp, &pxp_info_fops);
88*f005ef32Sjsg
89*f005ef32Sjsg debugfs_create_file("terminate_state", 0644, pxproot,
90*f005ef32Sjsg pxp, &pxp_terminate_fops);
911bb76ff1Sjsg }
92