1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <linux/pm_runtime.h> 25 #include <asm/iosf_mbi.h> 26 27 #include "gt/intel_lrc_reg.h" /* for shadow reg list */ 28 29 #include "i915_drv.h" 30 #include "i915_trace.h" 31 #include "i915_vgpu.h" 32 #include "intel_pm.h" 33 34 #define FORCEWAKE_ACK_TIMEOUT_MS 50 35 #define GT_FIFO_TIMEOUT_MS 10 36 37 #define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) 38 39 void 40 intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug) 41 { 42 mtx_init(&mmio_debug->lock, IPL_TTY); 43 mmio_debug->unclaimed_mmio_check = 1; 44 } 45 46 static void mmio_debug_suspend(struct intel_uncore_mmio_debug *mmio_debug) 47 { 48 lockdep_assert_held(&mmio_debug->lock); 49 50 /* Save and disable mmio debugging for the user bypass */ 51 if (!mmio_debug->suspend_count++) { 52 mmio_debug->saved_mmio_check = mmio_debug->unclaimed_mmio_check; 53 mmio_debug->unclaimed_mmio_check = 0; 54 } 55 } 56 57 static void mmio_debug_resume(struct intel_uncore_mmio_debug *mmio_debug) 58 { 59 lockdep_assert_held(&mmio_debug->lock); 60 61 if (!--mmio_debug->suspend_count) 62 mmio_debug->unclaimed_mmio_check = mmio_debug->saved_mmio_check; 63 } 64 65 static const char * const forcewake_domain_names[] = { 66 "render", 67 "blitter", 68 "media", 69 "vdbox0", 70 "vdbox1", 71 "vdbox2", 72 "vdbox3", 73 "vdbox4", 74 "vdbox5", 75 "vdbox6", 76 "vdbox7", 77 "vebox0", 78 "vebox1", 79 "vebox2", 80 "vebox3", 81 }; 82 83 const char * 84 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 85 { 86 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); 87 88 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 89 return forcewake_domain_names[id]; 90 91 WARN_ON(id); 92 93 return "unknown"; 94 } 95 96 #define fw_ack(d) readl((d)->reg_ack) 97 #define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) 98 #define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) 99 100 static inline void 101 fw_domain_reset(const struct intel_uncore_forcewake_domain *d) 102 { 103 /* 104 * We don't really know if the powerwell for the forcewake domain we are 105 * trying to reset here does exist at this point (engines could be fused 106 * off in ICL+), so no waiting for acks 107 */ 108 /* WaRsClearFWBitsAtReset:bdw,skl */ 109 fw_clear(d, 0xffff); 110 } 111 112 static inline void 113 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 114 { 115 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); 116 d->uncore->fw_domains_timer |= d->mask; 117 d->wake_count++; 118 #ifdef __linux__ 119 hrtimer_start_range_ns(&d->timer, 120 NSEC_PER_MSEC, 121 NSEC_PER_MSEC, 122 HRTIMER_MODE_REL); 123 #else 124 timeout_add_msec(&d->timer, 1); 125 #endif 126 } 127 128 static inline int 129 __wait_for_ack(const struct intel_uncore_forcewake_domain *d, 130 const u32 ack, 131 const u32 value) 132 { 133 return wait_for_atomic((fw_ack(d) & ack) == value, 134 FORCEWAKE_ACK_TIMEOUT_MS); 135 } 136 137 static inline int 138 wait_ack_clear(const struct intel_uncore_forcewake_domain *d, 139 const u32 ack) 140 { 141 return __wait_for_ack(d, ack, 0); 142 } 143 144 static inline int 145 wait_ack_set(const struct intel_uncore_forcewake_domain *d, 146 const u32 ack) 147 { 148 return __wait_for_ack(d, ack, ack); 149 } 150 151 static inline void 152 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) 153 { 154 if (wait_ack_clear(d, FORCEWAKE_KERNEL)) { 155 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n", 156 intel_uncore_forcewake_domain_to_str(d->id)); 157 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 158 } 159 } 160 161 enum ack_type { 162 ACK_CLEAR = 0, 163 ACK_SET 164 }; 165 166 static int 167 fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, 168 const enum ack_type type) 169 { 170 const u32 ack_bit = FORCEWAKE_KERNEL; 171 const u32 value = type == ACK_SET ? ack_bit : 0; 172 unsigned int pass; 173 bool ack_detected; 174 175 /* 176 * There is a possibility of driver's wake request colliding 177 * with hardware's own wake requests and that can cause 178 * hardware to not deliver the driver's ack message. 179 * 180 * Use a fallback bit toggle to kick the gpu state machine 181 * in the hope that the original ack will be delivered along with 182 * the fallback ack. 183 * 184 * This workaround is described in HSDES #1604254524 and it's known as: 185 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl 186 * although the name is a bit misleading. 187 */ 188 189 pass = 1; 190 do { 191 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); 192 193 fw_set(d, FORCEWAKE_KERNEL_FALLBACK); 194 /* Give gt some time to relax before the polling frenzy */ 195 udelay(10 * pass); 196 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); 197 198 ack_detected = (fw_ack(d) & ack_bit) == value; 199 200 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); 201 } while (!ack_detected && pass++ < 10); 202 203 DRM_DEBUG_DRIVER("%s had to use fallback to %s ack, 0x%x (passes %u)\n", 204 intel_uncore_forcewake_domain_to_str(d->id), 205 type == ACK_SET ? "set" : "clear", 206 fw_ack(d), 207 pass); 208 209 return ack_detected ? 0 : -ETIMEDOUT; 210 } 211 212 static inline void 213 fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) 214 { 215 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) 216 return; 217 218 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) 219 fw_domain_wait_ack_clear(d); 220 } 221 222 static inline void 223 fw_domain_get(const struct intel_uncore_forcewake_domain *d) 224 { 225 fw_set(d, FORCEWAKE_KERNEL); 226 } 227 228 static inline void 229 fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) 230 { 231 if (wait_ack_set(d, FORCEWAKE_KERNEL)) { 232 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n", 233 intel_uncore_forcewake_domain_to_str(d->id)); 234 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 235 } 236 } 237 238 static inline void 239 fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) 240 { 241 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) 242 return; 243 244 if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) 245 fw_domain_wait_ack_set(d); 246 } 247 248 static inline void 249 fw_domain_put(const struct intel_uncore_forcewake_domain *d) 250 { 251 fw_clear(d, FORCEWAKE_KERNEL); 252 } 253 254 static void 255 fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 256 { 257 struct intel_uncore_forcewake_domain *d; 258 unsigned int tmp; 259 260 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 261 262 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 263 fw_domain_wait_ack_clear(d); 264 fw_domain_get(d); 265 } 266 267 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 268 fw_domain_wait_ack_set(d); 269 270 uncore->fw_domains_active |= fw_domains; 271 } 272 273 static void 274 fw_domains_get_with_fallback(struct intel_uncore *uncore, 275 enum forcewake_domains fw_domains) 276 { 277 struct intel_uncore_forcewake_domain *d; 278 unsigned int tmp; 279 280 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 281 282 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 283 fw_domain_wait_ack_clear_fallback(d); 284 fw_domain_get(d); 285 } 286 287 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 288 fw_domain_wait_ack_set_fallback(d); 289 290 uncore->fw_domains_active |= fw_domains; 291 } 292 293 static void 294 fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 295 { 296 struct intel_uncore_forcewake_domain *d; 297 unsigned int tmp; 298 299 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 300 301 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 302 fw_domain_put(d); 303 304 uncore->fw_domains_active &= ~fw_domains; 305 } 306 307 static void 308 fw_domains_reset(struct intel_uncore *uncore, 309 enum forcewake_domains fw_domains) 310 { 311 struct intel_uncore_forcewake_domain *d; 312 unsigned int tmp; 313 314 if (!fw_domains) 315 return; 316 317 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 318 319 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 320 fw_domain_reset(d); 321 } 322 323 static inline u32 gt_thread_status(struct intel_uncore *uncore) 324 { 325 u32 val; 326 327 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); 328 val &= GEN6_GT_THREAD_STATUS_CORE_MASK; 329 330 return val; 331 } 332 333 static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) 334 { 335 /* 336 * w/a for a sporadic read returning 0 by waiting for the GT 337 * thread to wake up. 338 */ 339 drm_WARN_ONCE(&uncore->i915->drm, 340 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), 341 "GT thread status wait timed out\n"); 342 } 343 344 static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, 345 enum forcewake_domains fw_domains) 346 { 347 fw_domains_get(uncore, fw_domains); 348 349 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 350 __gen6_gt_wait_for_thread_c0(uncore); 351 } 352 353 static inline u32 fifo_free_entries(struct intel_uncore *uncore) 354 { 355 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); 356 357 return count & GT_FIFO_FREE_ENTRIES_MASK; 358 } 359 360 static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) 361 { 362 u32 n; 363 364 /* On VLV, FIFO will be shared by both SW and HW. 365 * So, we need to read the FREE_ENTRIES everytime */ 366 if (IS_VALLEYVIEW(uncore->i915)) 367 n = fifo_free_entries(uncore); 368 else 369 n = uncore->fifo_count; 370 371 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { 372 if (wait_for_atomic((n = fifo_free_entries(uncore)) > 373 GT_FIFO_NUM_RESERVED_ENTRIES, 374 GT_FIFO_TIMEOUT_MS)) { 375 drm_dbg(&uncore->i915->drm, 376 "GT_FIFO timeout, entries: %u\n", n); 377 return; 378 } 379 } 380 381 uncore->fifo_count = n - 1; 382 } 383 384 #ifdef __linux__ 385 386 static enum hrtimer_restart 387 intel_uncore_fw_release_timer(struct hrtimer *timer) 388 { 389 struct intel_uncore_forcewake_domain *domain = 390 container_of(timer, struct intel_uncore_forcewake_domain, timer); 391 struct intel_uncore *uncore = domain->uncore; 392 unsigned long irqflags; 393 394 assert_rpm_device_not_suspended(uncore->rpm); 395 396 if (xchg(&domain->active, false)) 397 return HRTIMER_RESTART; 398 399 spin_lock_irqsave(&uncore->lock, irqflags); 400 401 uncore->fw_domains_timer &= ~domain->mask; 402 403 GEM_BUG_ON(!domain->wake_count); 404 if (--domain->wake_count == 0) 405 uncore->funcs.force_wake_put(uncore, domain->mask); 406 407 spin_unlock_irqrestore(&uncore->lock, irqflags); 408 409 return HRTIMER_NORESTART; 410 } 411 412 #else 413 414 void 415 intel_uncore_fw_release_timer(void *arg) 416 { 417 struct intel_uncore_forcewake_domain *domain = arg; 418 struct intel_uncore *uncore = domain->uncore; 419 unsigned long irqflags; 420 421 assert_rpm_device_not_suspended(uncore->rpm); 422 423 if (xchg(&domain->active, false)) 424 return; 425 426 spin_lock_irqsave(&uncore->lock, irqflags); 427 428 uncore->fw_domains_timer &= ~domain->mask; 429 430 GEM_BUG_ON(!domain->wake_count); 431 if (--domain->wake_count == 0) 432 uncore->funcs.force_wake_put(uncore, domain->mask); 433 434 spin_unlock_irqrestore(&uncore->lock, irqflags); 435 } 436 437 #endif 438 439 /* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ 440 static unsigned int 441 intel_uncore_forcewake_reset(struct intel_uncore *uncore) 442 { 443 unsigned long irqflags; 444 struct intel_uncore_forcewake_domain *domain; 445 int retry_count = 100; 446 enum forcewake_domains fw, active_domains; 447 448 iosf_mbi_assert_punit_acquired(); 449 450 /* Hold uncore.lock across reset to prevent any register access 451 * with forcewake not set correctly. Wait until all pending 452 * timers are run before holding. 453 */ 454 while (1) { 455 unsigned int tmp; 456 457 active_domains = 0; 458 459 for_each_fw_domain(domain, uncore, tmp) { 460 smp_store_mb(domain->active, false); 461 if (hrtimer_cancel(&domain->timer) == 0) 462 continue; 463 464 intel_uncore_fw_release_timer(&domain->timer); 465 } 466 467 spin_lock_irqsave(&uncore->lock, irqflags); 468 469 for_each_fw_domain(domain, uncore, tmp) { 470 if (hrtimer_active(&domain->timer)) 471 active_domains |= domain->mask; 472 } 473 474 if (active_domains == 0) 475 break; 476 477 if (--retry_count == 0) { 478 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n"); 479 break; 480 } 481 482 spin_unlock_irqrestore(&uncore->lock, irqflags); 483 cond_resched(); 484 } 485 486 drm_WARN_ON(&uncore->i915->drm, active_domains); 487 488 fw = uncore->fw_domains_active; 489 if (fw) 490 uncore->funcs.force_wake_put(uncore, fw); 491 492 fw_domains_reset(uncore, uncore->fw_domains); 493 assert_forcewakes_inactive(uncore); 494 495 spin_unlock_irqrestore(&uncore->lock, irqflags); 496 497 return fw; /* track the lost user forcewake domains */ 498 } 499 500 static bool 501 fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) 502 { 503 u32 dbg; 504 505 dbg = __raw_uncore_read32(uncore, FPGA_DBG); 506 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) 507 return false; 508 509 /* 510 * Bugs in PCI programming (or failing hardware) can occasionally cause 511 * us to lose access to the MMIO BAR. When this happens, register 512 * reads will come back with 0xFFFFFFFF for every register and things 513 * go bad very quickly. Let's try to detect that special case and at 514 * least try to print a more informative message about what has 515 * happened. 516 * 517 * During normal operation the FPGA_DBG register has several unused 518 * bits that will always read back as 0's so we can use them as canaries 519 * to recognize when MMIO accesses are just busted. 520 */ 521 if (unlikely(dbg == ~0)) 522 drm_err(&uncore->i915->drm, 523 "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n"); 524 525 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 526 527 return true; 528 } 529 530 static bool 531 vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) 532 { 533 u32 cer; 534 535 cer = __raw_uncore_read32(uncore, CLAIM_ER); 536 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) 537 return false; 538 539 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); 540 541 return true; 542 } 543 544 static bool 545 gen6_check_for_fifo_debug(struct intel_uncore *uncore) 546 { 547 u32 fifodbg; 548 549 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); 550 551 if (unlikely(fifodbg)) { 552 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg); 553 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); 554 } 555 556 return fifodbg; 557 } 558 559 static bool 560 check_for_unclaimed_mmio(struct intel_uncore *uncore) 561 { 562 bool ret = false; 563 564 lockdep_assert_held(&uncore->debug->lock); 565 566 if (uncore->debug->suspend_count) 567 return false; 568 569 if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) 570 ret |= fpga_check_for_unclaimed_mmio(uncore); 571 572 if (intel_uncore_has_dbg_unclaimed(uncore)) 573 ret |= vlv_check_for_unclaimed_mmio(uncore); 574 575 if (intel_uncore_has_fifo(uncore)) 576 ret |= gen6_check_for_fifo_debug(uncore); 577 578 return ret; 579 } 580 581 static void forcewake_early_sanitize(struct intel_uncore *uncore, 582 unsigned int restore_forcewake) 583 { 584 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 585 586 /* WaDisableShadowRegForCpd:chv */ 587 if (IS_CHERRYVIEW(uncore->i915)) { 588 __raw_uncore_write32(uncore, GTFIFOCTL, 589 __raw_uncore_read32(uncore, GTFIFOCTL) | 590 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 591 GT_FIFO_CTL_RC6_POLICY_STALL); 592 } 593 594 iosf_mbi_punit_acquire(); 595 intel_uncore_forcewake_reset(uncore); 596 if (restore_forcewake) { 597 spin_lock_irq(&uncore->lock); 598 uncore->funcs.force_wake_get(uncore, restore_forcewake); 599 600 if (intel_uncore_has_fifo(uncore)) 601 uncore->fifo_count = fifo_free_entries(uncore); 602 spin_unlock_irq(&uncore->lock); 603 } 604 iosf_mbi_punit_release(); 605 } 606 607 void intel_uncore_suspend(struct intel_uncore *uncore) 608 { 609 if (!intel_uncore_has_forcewake(uncore)) 610 return; 611 612 iosf_mbi_punit_acquire(); 613 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 614 &uncore->pmic_bus_access_nb); 615 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); 616 iosf_mbi_punit_release(); 617 } 618 619 void intel_uncore_resume_early(struct intel_uncore *uncore) 620 { 621 unsigned int restore_forcewake; 622 623 if (intel_uncore_unclaimed_mmio(uncore)) 624 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n"); 625 626 if (!intel_uncore_has_forcewake(uncore)) 627 return; 628 629 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); 630 forcewake_early_sanitize(uncore, restore_forcewake); 631 632 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 633 } 634 635 void intel_uncore_runtime_resume(struct intel_uncore *uncore) 636 { 637 if (!intel_uncore_has_forcewake(uncore)) 638 return; 639 640 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 641 } 642 643 static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, 644 enum forcewake_domains fw_domains) 645 { 646 struct intel_uncore_forcewake_domain *domain; 647 unsigned int tmp; 648 649 fw_domains &= uncore->fw_domains; 650 651 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 652 if (domain->wake_count++) { 653 fw_domains &= ~domain->mask; 654 domain->active = true; 655 } 656 } 657 658 if (fw_domains) 659 uncore->funcs.force_wake_get(uncore, fw_domains); 660 } 661 662 /** 663 * intel_uncore_forcewake_get - grab forcewake domain references 664 * @uncore: the intel_uncore structure 665 * @fw_domains: forcewake domains to get reference on 666 * 667 * This function can be used get GT's forcewake domain references. 668 * Normal register access will handle the forcewake domains automatically. 669 * However if some sequence requires the GT to not power down a particular 670 * forcewake domains this function should be called at the beginning of the 671 * sequence. And subsequently the reference should be dropped by symmetric 672 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 673 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 674 */ 675 void intel_uncore_forcewake_get(struct intel_uncore *uncore, 676 enum forcewake_domains fw_domains) 677 { 678 unsigned long irqflags; 679 680 if (!uncore->funcs.force_wake_get) 681 return; 682 683 assert_rpm_wakelock_held(uncore->rpm); 684 685 spin_lock_irqsave(&uncore->lock, irqflags); 686 __intel_uncore_forcewake_get(uncore, fw_domains); 687 spin_unlock_irqrestore(&uncore->lock, irqflags); 688 } 689 690 /** 691 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace 692 * @uncore: the intel_uncore structure 693 * 694 * This function is a wrapper around intel_uncore_forcewake_get() to acquire 695 * the GT powerwell and in the process disable our debugging for the 696 * duration of userspace's bypass. 697 */ 698 void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) 699 { 700 spin_lock_irq(&uncore->lock); 701 if (!uncore->user_forcewake_count++) { 702 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); 703 spin_lock(&uncore->debug->lock); 704 mmio_debug_suspend(uncore->debug); 705 spin_unlock(&uncore->debug->lock); 706 } 707 spin_unlock_irq(&uncore->lock); 708 } 709 710 /** 711 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace 712 * @uncore: the intel_uncore structure 713 * 714 * This function complements intel_uncore_forcewake_user_get() and releases 715 * the GT powerwell taken on behalf of the userspace bypass. 716 */ 717 void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) 718 { 719 spin_lock_irq(&uncore->lock); 720 if (!--uncore->user_forcewake_count) { 721 spin_lock(&uncore->debug->lock); 722 mmio_debug_resume(uncore->debug); 723 724 if (check_for_unclaimed_mmio(uncore)) 725 drm_info(&uncore->i915->drm, 726 "Invalid mmio detected during user access\n"); 727 spin_unlock(&uncore->debug->lock); 728 729 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); 730 } 731 spin_unlock_irq(&uncore->lock); 732 } 733 734 /** 735 * intel_uncore_forcewake_get__locked - grab forcewake domain references 736 * @uncore: the intel_uncore structure 737 * @fw_domains: forcewake domains to get reference on 738 * 739 * See intel_uncore_forcewake_get(). This variant places the onus 740 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 741 */ 742 void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, 743 enum forcewake_domains fw_domains) 744 { 745 lockdep_assert_held(&uncore->lock); 746 747 if (!uncore->funcs.force_wake_get) 748 return; 749 750 __intel_uncore_forcewake_get(uncore, fw_domains); 751 } 752 753 static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, 754 enum forcewake_domains fw_domains, 755 bool delayed) 756 { 757 struct intel_uncore_forcewake_domain *domain; 758 unsigned int tmp; 759 760 fw_domains &= uncore->fw_domains; 761 762 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 763 GEM_BUG_ON(!domain->wake_count); 764 765 if (--domain->wake_count) { 766 domain->active = true; 767 continue; 768 } 769 770 if (delayed && 771 !(domain->uncore->fw_domains_timer & domain->mask)) 772 fw_domain_arm_timer(domain); 773 else 774 uncore->funcs.force_wake_put(uncore, domain->mask); 775 } 776 } 777 778 /** 779 * intel_uncore_forcewake_put - release a forcewake domain reference 780 * @uncore: the intel_uncore structure 781 * @fw_domains: forcewake domains to put references 782 * 783 * This function drops the device-level forcewakes for specified 784 * domains obtained by intel_uncore_forcewake_get(). 785 */ 786 void intel_uncore_forcewake_put(struct intel_uncore *uncore, 787 enum forcewake_domains fw_domains) 788 { 789 unsigned long irqflags; 790 791 if (!uncore->funcs.force_wake_put) 792 return; 793 794 spin_lock_irqsave(&uncore->lock, irqflags); 795 __intel_uncore_forcewake_put(uncore, fw_domains, false); 796 spin_unlock_irqrestore(&uncore->lock, irqflags); 797 } 798 799 void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, 800 enum forcewake_domains fw_domains) 801 { 802 unsigned long irqflags; 803 804 if (!uncore->funcs.force_wake_put) 805 return; 806 807 spin_lock_irqsave(&uncore->lock, irqflags); 808 __intel_uncore_forcewake_put(uncore, fw_domains, true); 809 spin_unlock_irqrestore(&uncore->lock, irqflags); 810 } 811 812 /** 813 * intel_uncore_forcewake_flush - flush the delayed release 814 * @uncore: the intel_uncore structure 815 * @fw_domains: forcewake domains to flush 816 */ 817 void intel_uncore_forcewake_flush(struct intel_uncore *uncore, 818 enum forcewake_domains fw_domains) 819 { 820 struct intel_uncore_forcewake_domain *domain; 821 unsigned int tmp; 822 823 if (!uncore->funcs.force_wake_put) 824 return; 825 826 fw_domains &= uncore->fw_domains; 827 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 828 WRITE_ONCE(domain->active, false); 829 if (hrtimer_cancel(&domain->timer)) 830 intel_uncore_fw_release_timer(&domain->timer); 831 } 832 } 833 834 /** 835 * intel_uncore_forcewake_put__locked - grab forcewake domain references 836 * @uncore: the intel_uncore structure 837 * @fw_domains: forcewake domains to get reference on 838 * 839 * See intel_uncore_forcewake_put(). This variant places the onus 840 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 841 */ 842 void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, 843 enum forcewake_domains fw_domains) 844 { 845 lockdep_assert_held(&uncore->lock); 846 847 if (!uncore->funcs.force_wake_put) 848 return; 849 850 __intel_uncore_forcewake_put(uncore, fw_domains, false); 851 } 852 853 void assert_forcewakes_inactive(struct intel_uncore *uncore) 854 { 855 if (!uncore->funcs.force_wake_get) 856 return; 857 858 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active, 859 "Expected all fw_domains to be inactive, but %08x are still on\n", 860 uncore->fw_domains_active); 861 } 862 863 void assert_forcewakes_active(struct intel_uncore *uncore, 864 enum forcewake_domains fw_domains) 865 { 866 struct intel_uncore_forcewake_domain *domain; 867 unsigned int tmp; 868 869 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 870 return; 871 872 if (!uncore->funcs.force_wake_get) 873 return; 874 875 spin_lock_irq(&uncore->lock); 876 877 assert_rpm_wakelock_held(uncore->rpm); 878 879 fw_domains &= uncore->fw_domains; 880 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active, 881 "Expected %08x fw_domains to be active, but %08x are off\n", 882 fw_domains, fw_domains & ~uncore->fw_domains_active); 883 884 /* 885 * Check that the caller has an explicit wakeref and we don't mistake 886 * it for the auto wakeref. 887 */ 888 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 889 unsigned int actual = READ_ONCE(domain->wake_count); 890 unsigned int expect = 1; 891 892 if (uncore->fw_domains_timer & domain->mask) 893 expect++; /* pending automatic release */ 894 895 if (drm_WARN(&uncore->i915->drm, actual < expect, 896 "Expected domain %d to be held awake by caller, count=%d\n", 897 domain->id, actual)) 898 break; 899 } 900 901 spin_unlock_irq(&uncore->lock); 902 } 903 904 /* We give fast paths for the really cool registers */ 905 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000) 906 907 #define __gen6_reg_read_fw_domains(uncore, offset) \ 908 ({ \ 909 enum forcewake_domains __fwd; \ 910 if (NEEDS_FORCE_WAKE(offset)) \ 911 __fwd = FORCEWAKE_RENDER; \ 912 else \ 913 __fwd = 0; \ 914 __fwd; \ 915 }) 916 917 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) 918 { 919 if (offset < entry->start) 920 return -1; 921 else if (offset > entry->end) 922 return 1; 923 else 924 return 0; 925 } 926 927 /* Copied and "macroized" from lib/bsearch.c */ 928 #define BSEARCH(key, base, num, cmp) ({ \ 929 unsigned int start__ = 0, end__ = (num); \ 930 typeof(base) result__ = NULL; \ 931 while (start__ < end__) { \ 932 unsigned int mid__ = start__ + (end__ - start__) / 2; \ 933 int ret__ = (cmp)((key), (base) + mid__); \ 934 if (ret__ < 0) { \ 935 end__ = mid__; \ 936 } else if (ret__ > 0) { \ 937 start__ = mid__ + 1; \ 938 } else { \ 939 result__ = (base) + mid__; \ 940 break; \ 941 } \ 942 } \ 943 result__; \ 944 }) 945 946 static enum forcewake_domains 947 find_fw_domain(struct intel_uncore *uncore, u32 offset) 948 { 949 const struct intel_forcewake_range *entry; 950 951 entry = BSEARCH(offset, 952 uncore->fw_domains_table, 953 uncore->fw_domains_table_entries, 954 fw_range_cmp); 955 956 if (!entry) 957 return 0; 958 959 /* 960 * The list of FW domains depends on the SKU in gen11+ so we 961 * can't determine it statically. We use FORCEWAKE_ALL and 962 * translate it here to the list of available domains. 963 */ 964 if (entry->domains == FORCEWAKE_ALL) 965 return uncore->fw_domains; 966 967 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains, 968 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", 969 entry->domains & ~uncore->fw_domains, offset); 970 971 return entry->domains; 972 } 973 974 #define GEN_FW_RANGE(s, e, d) \ 975 { .start = (s), .end = (e), .domains = (d) } 976 977 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 978 static const struct intel_forcewake_range __vlv_fw_ranges[] = { 979 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 980 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), 981 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), 982 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 983 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), 984 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), 985 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 986 }; 987 988 #define __fwtable_reg_read_fw_domains(uncore, offset) \ 989 ({ \ 990 enum forcewake_domains __fwd = 0; \ 991 if (NEEDS_FORCE_WAKE((offset))) \ 992 __fwd = find_fw_domain(uncore, offset); \ 993 __fwd; \ 994 }) 995 996 #define __gen11_fwtable_reg_read_fw_domains(uncore, offset) \ 997 find_fw_domain(uncore, offset) 998 999 #define __gen12_fwtable_reg_read_fw_domains(uncore, offset) \ 1000 find_fw_domain(uncore, offset) 1001 1002 /* *Must* be sorted by offset! See intel_shadow_table_check(). */ 1003 static const i915_reg_t gen8_shadowed_regs[] = { 1004 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 1005 GEN6_RPNSWREQ, /* 0xA008 */ 1006 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 1007 RING_TAIL(GEN6_BSD_RING_BASE), /* 0x12000 (base) */ 1008 RING_TAIL(VEBOX_RING_BASE), /* 0x1a000 (base) */ 1009 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 1010 /* TODO: Other registers are not yet used */ 1011 }; 1012 1013 static const i915_reg_t gen11_shadowed_regs[] = { 1014 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 1015 RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */ 1016 GEN6_RPNSWREQ, /* 0xA008 */ 1017 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 1018 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 1019 RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */ 1020 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ 1021 RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */ 1022 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ 1023 RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */ 1024 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ 1025 RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */ 1026 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ 1027 RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */ 1028 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ 1029 RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */ 1030 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ 1031 RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */ 1032 /* TODO: Other registers are not yet used */ 1033 }; 1034 1035 static const i915_reg_t gen12_shadowed_regs[] = { 1036 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 1037 RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */ 1038 GEN6_RPNSWREQ, /* 0xA008 */ 1039 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 1040 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 1041 RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */ 1042 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ 1043 RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */ 1044 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ 1045 RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */ 1046 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ 1047 RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */ 1048 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ 1049 RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */ 1050 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ 1051 RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */ 1052 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ 1053 RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */ 1054 /* TODO: Other registers are not yet used */ 1055 }; 1056 1057 static const i915_reg_t xehp_shadowed_regs[] = { 1058 RING_TAIL(RENDER_RING_BASE), /* 0x2000 (base) */ 1059 RING_EXECLIST_CONTROL(RENDER_RING_BASE), /* 0x2550 */ 1060 GEN6_RPNSWREQ, /* 0xA008 */ 1061 GEN6_RC_VIDEO_FREQ, /* 0xA00C */ 1062 RING_TAIL(BLT_RING_BASE), /* 0x22000 (base) */ 1063 RING_EXECLIST_CONTROL(BLT_RING_BASE), /* 0x22550 */ 1064 RING_TAIL(GEN11_BSD_RING_BASE), /* 0x1C0000 (base) */ 1065 RING_EXECLIST_CONTROL(GEN11_BSD_RING_BASE), /* 0x1C0550 */ 1066 RING_TAIL(GEN11_BSD2_RING_BASE), /* 0x1C4000 (base) */ 1067 RING_EXECLIST_CONTROL(GEN11_BSD2_RING_BASE), /* 0x1C4550 */ 1068 RING_TAIL(GEN11_VEBOX_RING_BASE), /* 0x1C8000 (base) */ 1069 RING_EXECLIST_CONTROL(GEN11_VEBOX_RING_BASE), /* 0x1C8550 */ 1070 RING_TAIL(GEN11_BSD3_RING_BASE), /* 0x1D0000 (base) */ 1071 RING_EXECLIST_CONTROL(GEN11_BSD3_RING_BASE), /* 0x1D0550 */ 1072 RING_TAIL(GEN11_BSD4_RING_BASE), /* 0x1D4000 (base) */ 1073 RING_EXECLIST_CONTROL(GEN11_BSD4_RING_BASE), /* 0x1D4550 */ 1074 RING_TAIL(GEN11_VEBOX2_RING_BASE), /* 0x1D8000 (base) */ 1075 RING_EXECLIST_CONTROL(GEN11_VEBOX2_RING_BASE), /* 0x1D8550 */ 1076 RING_TAIL(XEHP_BSD5_RING_BASE), /* 0x1E0000 (base) */ 1077 RING_EXECLIST_CONTROL(XEHP_BSD5_RING_BASE), /* 0x1E0550 */ 1078 RING_TAIL(XEHP_BSD6_RING_BASE), /* 0x1E4000 (base) */ 1079 RING_EXECLIST_CONTROL(XEHP_BSD6_RING_BASE), /* 0x1E4550 */ 1080 RING_TAIL(XEHP_VEBOX3_RING_BASE), /* 0x1E8000 (base) */ 1081 RING_EXECLIST_CONTROL(XEHP_VEBOX3_RING_BASE), /* 0x1E8550 */ 1082 RING_TAIL(XEHP_BSD7_RING_BASE), /* 0x1F0000 (base) */ 1083 RING_EXECLIST_CONTROL(XEHP_BSD7_RING_BASE), /* 0x1F0550 */ 1084 RING_TAIL(XEHP_BSD8_RING_BASE), /* 0x1F4000 (base) */ 1085 RING_EXECLIST_CONTROL(XEHP_BSD8_RING_BASE), /* 0x1F4550 */ 1086 RING_TAIL(XEHP_VEBOX4_RING_BASE), /* 0x1F8000 (base) */ 1087 RING_EXECLIST_CONTROL(XEHP_VEBOX4_RING_BASE), /* 0x1F8550 */ 1088 /* TODO: Other registers are not yet used */ 1089 }; 1090 1091 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg) 1092 { 1093 u32 offset = i915_mmio_reg_offset(*reg); 1094 1095 if (key < offset) 1096 return -1; 1097 else if (key > offset) 1098 return 1; 1099 else 1100 return 0; 1101 } 1102 1103 #define __is_X_shadowed(x) \ 1104 static bool is_##x##_shadowed(u32 offset) \ 1105 { \ 1106 const i915_reg_t *regs = x##_shadowed_regs; \ 1107 return BSEARCH(offset, regs, ARRAY_SIZE(x##_shadowed_regs), \ 1108 mmio_reg_cmp); \ 1109 } 1110 1111 __is_X_shadowed(gen8) 1112 __is_X_shadowed(gen11) 1113 __is_X_shadowed(gen12) 1114 __is_X_shadowed(xehp) 1115 1116 static enum forcewake_domains 1117 gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 1118 { 1119 return FORCEWAKE_RENDER; 1120 } 1121 1122 #define __gen8_reg_write_fw_domains(uncore, offset) \ 1123 ({ \ 1124 enum forcewake_domains __fwd; \ 1125 if (NEEDS_FORCE_WAKE(offset) && !is_gen8_shadowed(offset)) \ 1126 __fwd = FORCEWAKE_RENDER; \ 1127 else \ 1128 __fwd = 0; \ 1129 __fwd; \ 1130 }) 1131 1132 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 1133 static const struct intel_forcewake_range __chv_fw_ranges[] = { 1134 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1135 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1136 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1137 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1138 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1139 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1140 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), 1141 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1142 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1143 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1144 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), 1145 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1146 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1147 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), 1148 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), 1149 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), 1150 }; 1151 1152 #define __fwtable_reg_write_fw_domains(uncore, offset) \ 1153 ({ \ 1154 enum forcewake_domains __fwd = 0; \ 1155 if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \ 1156 __fwd = find_fw_domain(uncore, offset); \ 1157 __fwd; \ 1158 }) 1159 1160 #define __gen11_fwtable_reg_write_fw_domains(uncore, offset) \ 1161 ({ \ 1162 enum forcewake_domains __fwd = 0; \ 1163 const u32 __offset = (offset); \ 1164 if (!is_gen11_shadowed(__offset)) \ 1165 __fwd = find_fw_domain(uncore, __offset); \ 1166 __fwd; \ 1167 }) 1168 1169 #define __gen12_fwtable_reg_write_fw_domains(uncore, offset) \ 1170 ({ \ 1171 enum forcewake_domains __fwd = 0; \ 1172 const u32 __offset = (offset); \ 1173 if (!is_gen12_shadowed(__offset)) \ 1174 __fwd = find_fw_domain(uncore, __offset); \ 1175 __fwd; \ 1176 }) 1177 1178 #define __xehp_fwtable_reg_write_fw_domains(uncore, offset) \ 1179 ({ \ 1180 enum forcewake_domains __fwd = 0; \ 1181 const u32 __offset = (offset); \ 1182 if (!is_xehp_shadowed(__offset)) \ 1183 __fwd = find_fw_domain(uncore, __offset); \ 1184 __fwd; \ 1185 }) 1186 1187 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 1188 static const struct intel_forcewake_range __gen9_fw_ranges[] = { 1189 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), 1190 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ 1191 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1192 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1193 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1194 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1195 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1196 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT), 1197 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), 1198 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1199 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1200 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1201 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1202 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), 1203 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT), 1204 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1205 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), 1206 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1207 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1208 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1209 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT), 1210 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1211 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT), 1212 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), 1213 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), 1214 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1215 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT), 1216 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), 1217 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT), 1218 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), 1219 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT), 1220 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1221 }; 1222 1223 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */ 1224 static const struct intel_forcewake_range __gen11_fw_ranges[] = { 1225 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */ 1226 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1227 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1228 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1229 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1230 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1231 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1232 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1233 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1234 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1235 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1236 GEN_FW_RANGE(0x8800, 0x8bff, 0), 1237 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1238 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT), 1239 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1240 GEN_FW_RANGE(0x9560, 0x95ff, 0), 1241 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT), 1242 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1243 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT), 1244 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), 1245 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT), 1246 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), 1247 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT), 1248 GEN_FW_RANGE(0x24000, 0x2407f, 0), 1249 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT), 1250 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER), 1251 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT), 1252 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER), 1253 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT), 1254 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1255 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), 1256 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1257 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0), 1258 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), 1259 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) 1260 }; 1261 1262 /* 1263 * *Must* be sorted by offset ranges! See intel_fw_table_check(). 1264 * 1265 * Note that the spec lists several reserved/unused ranges that don't 1266 * actually contain any registers. In the table below we'll combine those 1267 * reserved ranges with either the preceding or following range to keep the 1268 * table small and lookups fast. 1269 */ 1270 static const struct intel_forcewake_range __gen12_fw_ranges[] = { 1271 GEN_FW_RANGE(0x0, 0x1fff, 0), /* 1272 0x0 - 0xaff: reserved 1273 0xb00 - 0x1fff: always on */ 1274 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1275 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT), 1276 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), 1277 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT), 1278 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1279 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* 1280 0x4000 - 0x48ff: gt 1281 0x4900 - 0x51ff: reserved */ 1282 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* 1283 0x5200 - 0x53ff: render 1284 0x5400 - 0x54ff: reserved 1285 0x5500 - 0x7fff: render */ 1286 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1287 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1288 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* 1289 0x8160 - 0x817f: reserved 1290 0x8180 - 0x81ff: always on */ 1291 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), 1292 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1293 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* 1294 0x8500 - 0x87ff: gt 1295 0x8800 - 0x8fff: reserved 1296 0x9000 - 0x947f: gt 1297 0x9480 - 0x94cf: reserved */ 1298 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1299 GEN_FW_RANGE(0x9560, 0x97ff, 0), /* 1300 0x9560 - 0x95ff: always on 1301 0x9600 - 0x97ff: reserved */ 1302 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1303 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), 1304 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* 1305 0xb400 - 0xbf7f: gt 1306 0xb480 - 0xbfff: reserved 1307 0xc000 - 0xcfff: gt */ 1308 GEN_FW_RANGE(0xd000, 0xd7ff, 0), 1309 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), 1310 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT), 1311 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* 1312 0xdc00 - 0xddff: render 1313 0xde00 - 0xde7f: reserved 1314 0xde80 - 0xe8ff: render 1315 0xe900 - 0xefff: reserved */ 1316 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* 1317 0xf000 - 0xffff: gt 1318 0x10000 - 0x147ff: reserved */ 1319 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* 1320 0x14800 - 0x14fff: render 1321 0x15000 - 0x16dff: reserved 1322 0x16e00 - 0x1bfff: render 1323 0x1c000 - 0x1ffff: reserved */ 1324 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), 1325 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), 1326 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1327 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1328 0x24000 - 0x2407f: always on 1329 0x24080 - 0x2417f: reserved */ 1330 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* 1331 0x24180 - 0x241ff: gt 1332 0x24200 - 0x249ff: reserved */ 1333 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* 1334 0x24a00 - 0x24a7f: render 1335 0x24a80 - 0x251ff: reserved */ 1336 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* 1337 0x25200 - 0x252ff: gt 1338 0x25300 - 0x255ff: reserved */ 1339 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), 1340 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* 1341 0x25680 - 0x256ff: VD2 1342 0x25700 - 0x259ff: reserved */ 1343 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), 1344 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* 1345 0x25a80 - 0x25aff: VD2 1346 0x25b00 - 0x2ffff: reserved */ 1347 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1348 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1349 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1350 0x1c0000 - 0x1c2bff: VD0 1351 0x1c2c00 - 0x1c2cff: reserved 1352 0x1c2d00 - 0x1c2dff: VD0 1353 0x1c2e00 - 0x1c3eff: reserved 1354 0x1c3f00 - 0x1c3fff: VD0 */ 1355 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1356 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1357 0x1c8000 - 0x1ca0ff: VE0 1358 0x1ca100 - 0x1cbeff: reserved 1359 0x1cbf00 - 0x1cbfff: VE0 */ 1360 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* 1361 0x1cc000 - 0x1ccfff: VD0 1362 0x1cd000 - 0x1cffff: reserved */ 1363 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* 1364 0x1d0000 - 0x1d2bff: VD2 1365 0x1d2c00 - 0x1d2cff: reserved 1366 0x1d2d00 - 0x1d2dff: VD2 1367 0x1d2e00 - 0x1d3eff: reserved 1368 0x1d3f00 - 0x1d3fff: VD2 */ 1369 }; 1370 1371 /* 1372 * Graphics IP version 12.55 brings a slight change to the 0xd800 range, 1373 * switching it from the GT domain to the render domain. 1374 * 1375 * *Must* be sorted by offset ranges! See intel_fw_table_check(). 1376 */ 1377 #define XEHP_FWRANGES(FW_RANGE_D800) \ 1378 GEN_FW_RANGE(0x0, 0x1fff, 0), /* \ 1379 0x0 - 0xaff: reserved \ 1380 0xb00 - 0x1fff: always on */ \ 1381 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), \ 1382 GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), \ 1383 GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* \ 1384 0x4b00 - 0x4fff: reserved \ 1385 0x5000 - 0x51ff: always on */ \ 1386 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), \ 1387 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), \ 1388 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), \ 1389 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* \ 1390 0x8160 - 0x817f: reserved \ 1391 0x8180 - 0x81ff: always on */ \ 1392 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), \ 1393 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), \ 1394 GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* \ 1395 0x8500 - 0x87ff: gt \ 1396 0x8800 - 0x8c7f: reserved \ 1397 0x8c80 - 0x8cff: gt (DG2 only) */ \ 1398 GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* \ 1399 0x8d00 - 0x8dff: render (DG2 only) \ 1400 0x8e00 - 0x8fff: reserved */ \ 1401 GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* \ 1402 0x9000 - 0x947f: gt \ 1403 0x9480 - 0x94cf: reserved */ \ 1404 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), \ 1405 GEN_FW_RANGE(0x9560, 0x967f, 0), /* \ 1406 0x9560 - 0x95ff: always on \ 1407 0x9600 - 0x967f: reserved */ \ 1408 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* \ 1409 0x9680 - 0x96ff: render (DG2 only) \ 1410 0x9700 - 0x97ff: reserved */ \ 1411 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* \ 1412 0x9800 - 0xb4ff: gt \ 1413 0xb500 - 0xbfff: reserved \ 1414 0xc000 - 0xcfff: gt */ \ 1415 GEN_FW_RANGE(0xd000, 0xd7ff, 0), \ 1416 GEN_FW_RANGE(0xd800, 0xd87f, FW_RANGE_D800), \ 1417 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), \ 1418 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), \ 1419 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* \ 1420 0xdd00 - 0xddff: gt \ 1421 0xde00 - 0xde7f: reserved */ \ 1422 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* \ 1423 0xde80 - 0xdfff: render \ 1424 0xe000 - 0xe0ff: reserved \ 1425 0xe100 - 0xe8ff: render */ \ 1426 GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* \ 1427 0xe900 - 0xe9ff: gt \ 1428 0xea00 - 0xefff: reserved \ 1429 0xf000 - 0xffff: gt */ \ 1430 GEN_FW_RANGE(0x10000, 0x12fff, 0), /* \ 1431 0x10000 - 0x11fff: reserved \ 1432 0x12000 - 0x127ff: always on \ 1433 0x12800 - 0x12fff: reserved */ \ 1434 GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), /* DG2 only */ \ 1435 GEN_FW_RANGE(0x13200, 0x13fff, FORCEWAKE_MEDIA_VDBOX2), /* \ 1436 0x13200 - 0x133ff: VD2 (DG2 only) \ 1437 0x13400 - 0x13fff: reserved */ \ 1438 GEN_FW_RANGE(0x14000, 0x141ff, FORCEWAKE_MEDIA_VDBOX0), /* XEHPSDV only */ \ 1439 GEN_FW_RANGE(0x14200, 0x143ff, FORCEWAKE_MEDIA_VDBOX2), /* XEHPSDV only */ \ 1440 GEN_FW_RANGE(0x14400, 0x145ff, FORCEWAKE_MEDIA_VDBOX4), /* XEHPSDV only */ \ 1441 GEN_FW_RANGE(0x14600, 0x147ff, FORCEWAKE_MEDIA_VDBOX6), /* XEHPSDV only */ \ 1442 GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), \ 1443 GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* \ 1444 0x15000 - 0x15fff: gt (DG2 only) \ 1445 0x16000 - 0x16dff: reserved */ \ 1446 GEN_FW_RANGE(0x16e00, 0x1ffff, FORCEWAKE_RENDER), \ 1447 GEN_FW_RANGE(0x20000, 0x21fff, FORCEWAKE_MEDIA_VDBOX0), /* \ 1448 0x20000 - 0x20fff: VD0 (XEHPSDV only) \ 1449 0x21000 - 0x21fff: reserved */ \ 1450 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), \ 1451 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* \ 1452 0x24000 - 0x2407f: always on \ 1453 0x24080 - 0x2417f: reserved */ \ 1454 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* \ 1455 0x24180 - 0x241ff: gt \ 1456 0x24200 - 0x249ff: reserved */ \ 1457 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* \ 1458 0x24a00 - 0x24a7f: render \ 1459 0x24a80 - 0x251ff: reserved */ \ 1460 GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* \ 1461 0x25200 - 0x252ff: gt \ 1462 0x25300 - 0x25fff: reserved */ \ 1463 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* \ 1464 0x26000 - 0x27fff: render \ 1465 0x28000 - 0x29fff: reserved \ 1466 0x2a000 - 0x2ffff: undocumented */ \ 1467 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), \ 1468 GEN_FW_RANGE(0x40000, 0x1bffff, 0), \ 1469 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* \ 1470 0x1c0000 - 0x1c2bff: VD0 \ 1471 0x1c2c00 - 0x1c2cff: reserved \ 1472 0x1c2d00 - 0x1c2dff: VD0 \ 1473 0x1c2e00 - 0x1c3eff: VD0 (DG2 only) \ 1474 0x1c3f00 - 0x1c3fff: VD0 */ \ 1475 GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* \ 1476 0x1c4000 - 0x1c6bff: VD1 \ 1477 0x1c6c00 - 0x1c6cff: reserved \ 1478 0x1c6d00 - 0x1c6dff: VD1 \ 1479 0x1c6e00 - 0x1c7fff: reserved */ \ 1480 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* \ 1481 0x1c8000 - 0x1ca0ff: VE0 \ 1482 0x1ca100 - 0x1cbfff: reserved */ \ 1483 GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), \ 1484 GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), \ 1485 GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), \ 1486 GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), \ 1487 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* \ 1488 0x1d0000 - 0x1d2bff: VD2 \ 1489 0x1d2c00 - 0x1d2cff: reserved \ 1490 0x1d2d00 - 0x1d2dff: VD2 \ 1491 0x1d2e00 - 0x1d3dff: VD2 (DG2 only) \ 1492 0x1d3e00 - 0x1d3eff: reserved \ 1493 0x1d3f00 - 0x1d3fff: VD2 */ \ 1494 GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* \ 1495 0x1d4000 - 0x1d6bff: VD3 \ 1496 0x1d6c00 - 0x1d6cff: reserved \ 1497 0x1d6d00 - 0x1d6dff: VD3 \ 1498 0x1d6e00 - 0x1d7fff: reserved */ \ 1499 GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* \ 1500 0x1d8000 - 0x1da0ff: VE1 \ 1501 0x1da100 - 0x1dffff: reserved */ \ 1502 GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* \ 1503 0x1e0000 - 0x1e2bff: VD4 \ 1504 0x1e2c00 - 0x1e2cff: reserved \ 1505 0x1e2d00 - 0x1e2dff: VD4 \ 1506 0x1e2e00 - 0x1e3eff: reserved \ 1507 0x1e3f00 - 0x1e3fff: VD4 */ \ 1508 GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* \ 1509 0x1e4000 - 0x1e6bff: VD5 \ 1510 0x1e6c00 - 0x1e6cff: reserved \ 1511 0x1e6d00 - 0x1e6dff: VD5 \ 1512 0x1e6e00 - 0x1e7fff: reserved */ \ 1513 GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* \ 1514 0x1e8000 - 0x1ea0ff: VE2 \ 1515 0x1ea100 - 0x1effff: reserved */ \ 1516 GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* \ 1517 0x1f0000 - 0x1f2bff: VD6 \ 1518 0x1f2c00 - 0x1f2cff: reserved \ 1519 0x1f2d00 - 0x1f2dff: VD6 \ 1520 0x1f2e00 - 0x1f3eff: reserved \ 1521 0x1f3f00 - 0x1f3fff: VD6 */ \ 1522 GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* \ 1523 0x1f4000 - 0x1f6bff: VD7 \ 1524 0x1f6c00 - 0x1f6cff: reserved \ 1525 0x1f6d00 - 0x1f6dff: VD7 \ 1526 0x1f6e00 - 0x1f7fff: reserved */ \ 1527 GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3), 1528 1529 static const struct intel_forcewake_range __xehp_fw_ranges[] = { 1530 XEHP_FWRANGES(FORCEWAKE_GT) 1531 }; 1532 1533 static const struct intel_forcewake_range __dg2_fw_ranges[] = { 1534 XEHP_FWRANGES(FORCEWAKE_RENDER) 1535 }; 1536 1537 static void 1538 ilk_dummy_write(struct intel_uncore *uncore) 1539 { 1540 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 1541 * the chip from rc6 before touching it for real. MI_MODE is masked, 1542 * hence harmless to write 0 into. */ 1543 __raw_uncore_write32(uncore, MI_MODE, 0); 1544 } 1545 1546 static void 1547 __unclaimed_reg_debug(struct intel_uncore *uncore, 1548 const i915_reg_t reg, 1549 const bool read, 1550 const bool before) 1551 { 1552 if (drm_WARN(&uncore->i915->drm, 1553 check_for_unclaimed_mmio(uncore) && !before, 1554 "Unclaimed %s register 0x%x\n", 1555 read ? "read from" : "write to", 1556 i915_mmio_reg_offset(reg))) 1557 /* Only report the first N failures */ 1558 uncore->i915->params.mmio_debug--; 1559 } 1560 1561 static inline void 1562 unclaimed_reg_debug(struct intel_uncore *uncore, 1563 const i915_reg_t reg, 1564 const bool read, 1565 const bool before) 1566 { 1567 if (likely(!uncore->i915->params.mmio_debug)) 1568 return; 1569 1570 /* interrupts are disabled and re-enabled around uncore->lock usage */ 1571 lockdep_assert_held(&uncore->lock); 1572 1573 if (before) 1574 spin_lock(&uncore->debug->lock); 1575 1576 __unclaimed_reg_debug(uncore, reg, read, before); 1577 1578 if (!before) 1579 spin_unlock(&uncore->debug->lock); 1580 } 1581 1582 #define __vgpu_read(x) \ 1583 static u##x \ 1584 vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1585 u##x val = __raw_uncore_read##x(uncore, reg); \ 1586 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1587 return val; \ 1588 } 1589 __vgpu_read(8) 1590 __vgpu_read(16) 1591 __vgpu_read(32) 1592 __vgpu_read(64) 1593 1594 #define GEN2_READ_HEADER(x) \ 1595 u##x val = 0; \ 1596 assert_rpm_wakelock_held(uncore->rpm); 1597 1598 #define GEN2_READ_FOOTER \ 1599 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1600 return val 1601 1602 #define __gen2_read(x) \ 1603 static u##x \ 1604 gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1605 GEN2_READ_HEADER(x); \ 1606 val = __raw_uncore_read##x(uncore, reg); \ 1607 GEN2_READ_FOOTER; \ 1608 } 1609 1610 #define __gen5_read(x) \ 1611 static u##x \ 1612 gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1613 GEN2_READ_HEADER(x); \ 1614 ilk_dummy_write(uncore); \ 1615 val = __raw_uncore_read##x(uncore, reg); \ 1616 GEN2_READ_FOOTER; \ 1617 } 1618 1619 __gen5_read(8) 1620 __gen5_read(16) 1621 __gen5_read(32) 1622 __gen5_read(64) 1623 __gen2_read(8) 1624 __gen2_read(16) 1625 __gen2_read(32) 1626 __gen2_read(64) 1627 1628 #undef __gen5_read 1629 #undef __gen2_read 1630 1631 #undef GEN2_READ_FOOTER 1632 #undef GEN2_READ_HEADER 1633 1634 #define GEN6_READ_HEADER(x) \ 1635 u32 offset = i915_mmio_reg_offset(reg); \ 1636 unsigned long irqflags; \ 1637 u##x val = 0; \ 1638 assert_rpm_wakelock_held(uncore->rpm); \ 1639 spin_lock_irqsave(&uncore->lock, irqflags); \ 1640 unclaimed_reg_debug(uncore, reg, true, true) 1641 1642 #define GEN6_READ_FOOTER \ 1643 unclaimed_reg_debug(uncore, reg, true, false); \ 1644 spin_unlock_irqrestore(&uncore->lock, irqflags); \ 1645 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1646 return val 1647 1648 static noinline void ___force_wake_auto(struct intel_uncore *uncore, 1649 enum forcewake_domains fw_domains) 1650 { 1651 struct intel_uncore_forcewake_domain *domain; 1652 unsigned int tmp; 1653 1654 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 1655 1656 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) 1657 fw_domain_arm_timer(domain); 1658 1659 uncore->funcs.force_wake_get(uncore, fw_domains); 1660 } 1661 1662 static inline void __force_wake_auto(struct intel_uncore *uncore, 1663 enum forcewake_domains fw_domains) 1664 { 1665 GEM_BUG_ON(!fw_domains); 1666 1667 /* Turn on all requested but inactive supported forcewake domains. */ 1668 fw_domains &= uncore->fw_domains; 1669 fw_domains &= ~uncore->fw_domains_active; 1670 1671 if (fw_domains) 1672 ___force_wake_auto(uncore, fw_domains); 1673 } 1674 1675 #define __gen_read(func, x) \ 1676 static u##x \ 1677 func##_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1678 enum forcewake_domains fw_engine; \ 1679 GEN6_READ_HEADER(x); \ 1680 fw_engine = __##func##_reg_read_fw_domains(uncore, offset); \ 1681 if (fw_engine) \ 1682 __force_wake_auto(uncore, fw_engine); \ 1683 val = __raw_uncore_read##x(uncore, reg); \ 1684 GEN6_READ_FOOTER; \ 1685 } 1686 1687 #define __gen_reg_read_funcs(func) \ 1688 static enum forcewake_domains \ 1689 func##_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ 1690 return __##func##_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ 1691 } \ 1692 \ 1693 __gen_read(func, 8) \ 1694 __gen_read(func, 16) \ 1695 __gen_read(func, 32) \ 1696 __gen_read(func, 64) 1697 1698 __gen_reg_read_funcs(gen12_fwtable); 1699 __gen_reg_read_funcs(gen11_fwtable); 1700 __gen_reg_read_funcs(fwtable); 1701 __gen_reg_read_funcs(gen6); 1702 1703 #undef __gen_reg_read_funcs 1704 #undef GEN6_READ_FOOTER 1705 #undef GEN6_READ_HEADER 1706 1707 #define GEN2_WRITE_HEADER \ 1708 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1709 assert_rpm_wakelock_held(uncore->rpm); \ 1710 1711 #define GEN2_WRITE_FOOTER 1712 1713 #define __gen2_write(x) \ 1714 static void \ 1715 gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1716 GEN2_WRITE_HEADER; \ 1717 __raw_uncore_write##x(uncore, reg, val); \ 1718 GEN2_WRITE_FOOTER; \ 1719 } 1720 1721 #define __gen5_write(x) \ 1722 static void \ 1723 gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1724 GEN2_WRITE_HEADER; \ 1725 ilk_dummy_write(uncore); \ 1726 __raw_uncore_write##x(uncore, reg, val); \ 1727 GEN2_WRITE_FOOTER; \ 1728 } 1729 1730 __gen5_write(8) 1731 __gen5_write(16) 1732 __gen5_write(32) 1733 __gen2_write(8) 1734 __gen2_write(16) 1735 __gen2_write(32) 1736 1737 #undef __gen5_write 1738 #undef __gen2_write 1739 1740 #undef GEN2_WRITE_FOOTER 1741 #undef GEN2_WRITE_HEADER 1742 1743 #define GEN6_WRITE_HEADER \ 1744 u32 offset = i915_mmio_reg_offset(reg); \ 1745 unsigned long irqflags; \ 1746 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1747 assert_rpm_wakelock_held(uncore->rpm); \ 1748 spin_lock_irqsave(&uncore->lock, irqflags); \ 1749 unclaimed_reg_debug(uncore, reg, false, true) 1750 1751 #define GEN6_WRITE_FOOTER \ 1752 unclaimed_reg_debug(uncore, reg, false, false); \ 1753 spin_unlock_irqrestore(&uncore->lock, irqflags) 1754 1755 #define __gen6_write(x) \ 1756 static void \ 1757 gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1758 GEN6_WRITE_HEADER; \ 1759 if (NEEDS_FORCE_WAKE(offset)) \ 1760 __gen6_gt_wait_for_fifo(uncore); \ 1761 __raw_uncore_write##x(uncore, reg, val); \ 1762 GEN6_WRITE_FOOTER; \ 1763 } 1764 __gen6_write(8) 1765 __gen6_write(16) 1766 __gen6_write(32) 1767 1768 #define __gen_write(func, x) \ 1769 static void \ 1770 func##_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1771 enum forcewake_domains fw_engine; \ 1772 GEN6_WRITE_HEADER; \ 1773 fw_engine = __##func##_reg_write_fw_domains(uncore, offset); \ 1774 if (fw_engine) \ 1775 __force_wake_auto(uncore, fw_engine); \ 1776 __raw_uncore_write##x(uncore, reg, val); \ 1777 GEN6_WRITE_FOOTER; \ 1778 } 1779 1780 #define __gen_reg_write_funcs(func) \ 1781 static enum forcewake_domains \ 1782 func##_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { \ 1783 return __##func##_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); \ 1784 } \ 1785 \ 1786 __gen_write(func, 8) \ 1787 __gen_write(func, 16) \ 1788 __gen_write(func, 32) 1789 1790 __gen_reg_write_funcs(xehp_fwtable); 1791 __gen_reg_write_funcs(gen12_fwtable); 1792 __gen_reg_write_funcs(gen11_fwtable); 1793 __gen_reg_write_funcs(fwtable); 1794 __gen_reg_write_funcs(gen8); 1795 1796 #undef __gen_reg_write_funcs 1797 #undef GEN6_WRITE_FOOTER 1798 #undef GEN6_WRITE_HEADER 1799 1800 #define __vgpu_write(x) \ 1801 static void \ 1802 vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1803 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1804 __raw_uncore_write##x(uncore, reg, val); \ 1805 } 1806 __vgpu_write(8) 1807 __vgpu_write(16) 1808 __vgpu_write(32) 1809 1810 #define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \ 1811 do { \ 1812 (uncore)->funcs.mmio_writeb = x##_write8; \ 1813 (uncore)->funcs.mmio_writew = x##_write16; \ 1814 (uncore)->funcs.mmio_writel = x##_write32; \ 1815 } while (0) 1816 1817 #define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \ 1818 do { \ 1819 (uncore)->funcs.mmio_readb = x##_read8; \ 1820 (uncore)->funcs.mmio_readw = x##_read16; \ 1821 (uncore)->funcs.mmio_readl = x##_read32; \ 1822 (uncore)->funcs.mmio_readq = x##_read64; \ 1823 } while (0) 1824 1825 #define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ 1826 do { \ 1827 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \ 1828 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ 1829 } while (0) 1830 1831 #define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ 1832 do { \ 1833 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \ 1834 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ 1835 } while (0) 1836 1837 static int __fw_domain_init(struct intel_uncore *uncore, 1838 enum forcewake_domain_id domain_id, 1839 i915_reg_t reg_set, 1840 i915_reg_t reg_ack) 1841 { 1842 struct intel_uncore_forcewake_domain *d; 1843 1844 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 1845 GEM_BUG_ON(uncore->fw_domain[domain_id]); 1846 1847 if (i915_inject_probe_failure(uncore->i915)) 1848 return -ENOMEM; 1849 1850 d = kzalloc(sizeof(*d), GFP_KERNEL); 1851 if (!d) 1852 return -ENOMEM; 1853 1854 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); 1855 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack)); 1856 1857 d->uncore = uncore; 1858 d->wake_count = 0; 1859 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set); 1860 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack); 1861 1862 d->id = domain_id; 1863 1864 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); 1865 BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT)); 1866 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); 1867 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); 1868 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); 1869 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); 1870 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); 1871 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4)); 1872 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5)); 1873 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6)); 1874 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7)); 1875 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); 1876 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); 1877 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2)); 1878 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3)); 1879 1880 d->mask = BIT(domain_id); 1881 1882 #ifdef __linux__ 1883 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1884 d->timer.function = intel_uncore_fw_release_timer; 1885 #else 1886 timeout_set(&d->timer, intel_uncore_fw_release_timer, d); 1887 #endif 1888 1889 uncore->fw_domains |= BIT(domain_id); 1890 1891 fw_domain_reset(d); 1892 1893 uncore->fw_domain[domain_id] = d; 1894 1895 return 0; 1896 } 1897 1898 static void fw_domain_fini(struct intel_uncore *uncore, 1899 enum forcewake_domain_id domain_id) 1900 { 1901 struct intel_uncore_forcewake_domain *d; 1902 1903 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 1904 1905 d = fetch_and_zero(&uncore->fw_domain[domain_id]); 1906 if (!d) 1907 return; 1908 1909 uncore->fw_domains &= ~BIT(domain_id); 1910 drm_WARN_ON(&uncore->i915->drm, d->wake_count); 1911 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer)); 1912 kfree(d); 1913 } 1914 1915 static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) 1916 { 1917 struct intel_uncore_forcewake_domain *d; 1918 int tmp; 1919 1920 for_each_fw_domain(d, uncore, tmp) 1921 fw_domain_fini(uncore, d->id); 1922 } 1923 1924 static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) 1925 { 1926 struct drm_i915_private *i915 = uncore->i915; 1927 int ret = 0; 1928 1929 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 1930 1931 #define fw_domain_init(uncore__, id__, set__, ack__) \ 1932 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) 1933 1934 if (GRAPHICS_VER(i915) >= 11) { 1935 /* we'll prune the domains of missing engines later */ 1936 intel_engine_mask_t emask = INTEL_INFO(i915)->platform_engine_mask; 1937 int i; 1938 1939 uncore->funcs.force_wake_get = fw_domains_get_with_fallback; 1940 uncore->funcs.force_wake_put = fw_domains_put; 1941 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1942 FORCEWAKE_RENDER_GEN9, 1943 FORCEWAKE_ACK_RENDER_GEN9); 1944 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 1945 FORCEWAKE_GT_GEN9, 1946 FORCEWAKE_ACK_GT_GEN9); 1947 1948 for (i = 0; i < I915_MAX_VCS; i++) { 1949 if (!__HAS_ENGINE(emask, _VCS(i))) 1950 continue; 1951 1952 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, 1953 FORCEWAKE_MEDIA_VDBOX_GEN11(i), 1954 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); 1955 } 1956 for (i = 0; i < I915_MAX_VECS; i++) { 1957 if (!__HAS_ENGINE(emask, _VECS(i))) 1958 continue; 1959 1960 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, 1961 FORCEWAKE_MEDIA_VEBOX_GEN11(i), 1962 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); 1963 } 1964 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 1965 uncore->funcs.force_wake_get = fw_domains_get_with_fallback; 1966 uncore->funcs.force_wake_put = fw_domains_put; 1967 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1968 FORCEWAKE_RENDER_GEN9, 1969 FORCEWAKE_ACK_RENDER_GEN9); 1970 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 1971 FORCEWAKE_GT_GEN9, 1972 FORCEWAKE_ACK_GT_GEN9); 1973 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 1974 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 1975 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 1976 uncore->funcs.force_wake_get = fw_domains_get; 1977 uncore->funcs.force_wake_put = fw_domains_put; 1978 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1979 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 1980 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 1981 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 1982 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 1983 uncore->funcs.force_wake_get = 1984 fw_domains_get_with_thread_status; 1985 uncore->funcs.force_wake_put = fw_domains_put; 1986 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 1987 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 1988 } else if (IS_IVYBRIDGE(i915)) { 1989 u32 ecobus; 1990 1991 /* IVB configs may use multi-threaded forcewake */ 1992 1993 /* A small trick here - if the bios hasn't configured 1994 * MT forcewake, and if the device is in RC6, then 1995 * force_wake_mt_get will not wake the device and the 1996 * ECOBUS read will return zero. Which will be 1997 * (correctly) interpreted by the test below as MT 1998 * forcewake being disabled. 1999 */ 2000 uncore->funcs.force_wake_get = 2001 fw_domains_get_with_thread_status; 2002 uncore->funcs.force_wake_put = fw_domains_put; 2003 2004 /* We need to init first for ECOBUS access and then 2005 * determine later if we want to reinit, in case of MT access is 2006 * not working. In this stage we don't know which flavour this 2007 * ivb is, so it is better to reset also the gen6 fw registers 2008 * before the ecobus check. 2009 */ 2010 2011 __raw_uncore_write32(uncore, FORCEWAKE, 0); 2012 __raw_posting_read(uncore, ECOBUS); 2013 2014 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2015 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 2016 if (ret) 2017 goto out; 2018 2019 spin_lock_irq(&uncore->lock); 2020 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); 2021 ecobus = __raw_uncore_read32(uncore, ECOBUS); 2022 fw_domains_put(uncore, FORCEWAKE_RENDER); 2023 spin_unlock_irq(&uncore->lock); 2024 2025 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 2026 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n"); 2027 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n"); 2028 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER); 2029 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2030 FORCEWAKE, FORCEWAKE_ACK); 2031 } 2032 } else if (GRAPHICS_VER(i915) == 6) { 2033 uncore->funcs.force_wake_get = 2034 fw_domains_get_with_thread_status; 2035 uncore->funcs.force_wake_put = fw_domains_put; 2036 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2037 FORCEWAKE, FORCEWAKE_ACK); 2038 } 2039 2040 #undef fw_domain_init 2041 2042 /* All future platforms are expected to require complex power gating */ 2043 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0); 2044 2045 out: 2046 if (ret) 2047 intel_uncore_fw_domains_fini(uncore); 2048 2049 return ret; 2050 } 2051 2052 #define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ 2053 { \ 2054 (uncore)->fw_domains_table = \ 2055 (struct intel_forcewake_range *)(d); \ 2056 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ 2057 } 2058 2059 static int i915_pmic_bus_access_notifier(struct notifier_block *nb, 2060 unsigned long action, void *data) 2061 { 2062 struct intel_uncore *uncore = container_of(nb, 2063 struct intel_uncore, pmic_bus_access_nb); 2064 2065 switch (action) { 2066 case MBI_PMIC_BUS_ACCESS_BEGIN: 2067 /* 2068 * forcewake all now to make sure that we don't need to do a 2069 * forcewake later which on systems where this notifier gets 2070 * called requires the punit to access to the shared pmic i2c 2071 * bus, which will be busy after this notification, leading to: 2072 * "render: timed out waiting for forcewake ack request." 2073 * errors. 2074 * 2075 * The notifier is unregistered during intel_runtime_suspend(), 2076 * so it's ok to access the HW here without holding a RPM 2077 * wake reference -> disable wakeref asserts for the time of 2078 * the access. 2079 */ 2080 disable_rpm_wakeref_asserts(uncore->rpm); 2081 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 2082 enable_rpm_wakeref_asserts(uncore->rpm); 2083 break; 2084 case MBI_PMIC_BUS_ACCESS_END: 2085 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 2086 break; 2087 } 2088 2089 return NOTIFY_OK; 2090 } 2091 2092 static int uncore_mmio_setup(struct intel_uncore *uncore) 2093 { 2094 struct drm_i915_private *i915 = uncore->i915; 2095 struct pci_dev *pdev = i915->drm.pdev; 2096 int mmio_bar; 2097 int mmio_size; 2098 2099 mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0; 2100 /* 2101 * Before gen4, the registers and the GTT are behind different BARs. 2102 * However, from gen4 onwards, the registers and the GTT are shared 2103 * in the same BAR, so we want to restrict this ioremap from 2104 * clobbering the GTT which we want ioremap_wc instead. Fortunately, 2105 * the register BAR remains the same size for all the earlier 2106 * generations up to Ironlake. 2107 * For dgfx chips register range is expanded to 4MB. 2108 */ 2109 if (GRAPHICS_VER(i915) < 5) 2110 mmio_size = 512 * 1024; 2111 else if (IS_DGFX(i915)) 2112 mmio_size = 4 * 1024 * 1024; 2113 else 2114 mmio_size = 2 * 1024 * 1024; 2115 #ifdef __linux__ 2116 uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size); 2117 if (uncore->regs == NULL) { 2118 drm_err(&i915->drm, "failed to map registers\n"); 2119 return -EIO; 2120 } 2121 #endif 2122 2123 return 0; 2124 } 2125 2126 static void uncore_mmio_cleanup(struct intel_uncore *uncore) 2127 { 2128 #ifdef __linux__ 2129 struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev); 2130 2131 pci_iounmap(pdev, uncore->regs); 2132 #endif 2133 } 2134 2135 void intel_uncore_init_early(struct intel_uncore *uncore, 2136 struct drm_i915_private *i915) 2137 { 2138 mtx_init(&uncore->lock, IPL_TTY); 2139 uncore->i915 = i915; 2140 uncore->rpm = &i915->runtime_pm; 2141 uncore->debug = &i915->mmio_debug; 2142 } 2143 2144 static void uncore_raw_init(struct intel_uncore *uncore) 2145 { 2146 GEM_BUG_ON(intel_uncore_has_forcewake(uncore)); 2147 2148 if (intel_vgpu_active(uncore->i915)) { 2149 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu); 2150 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu); 2151 } else if (GRAPHICS_VER(uncore->i915) == 5) { 2152 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5); 2153 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5); 2154 } else { 2155 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2); 2156 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2); 2157 } 2158 } 2159 2160 static int uncore_forcewake_init(struct intel_uncore *uncore) 2161 { 2162 struct drm_i915_private *i915 = uncore->i915; 2163 int ret; 2164 2165 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 2166 2167 ret = intel_uncore_fw_domains_init(uncore); 2168 if (ret) 2169 return ret; 2170 forcewake_early_sanitize(uncore, 0); 2171 2172 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 2173 ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges); 2174 ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable); 2175 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); 2176 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) { 2177 ASSIGN_FW_DOMAINS_TABLE(uncore, __xehp_fw_ranges); 2178 ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fwtable); 2179 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); 2180 } else if (GRAPHICS_VER(i915) >= 12) { 2181 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); 2182 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable); 2183 ASSIGN_READ_MMIO_VFUNCS(uncore, gen12_fwtable); 2184 } else if (GRAPHICS_VER(i915) == 11) { 2185 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); 2186 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen11_fwtable); 2187 ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable); 2188 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 2189 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); 2190 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2191 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 2192 } else if (IS_CHERRYVIEW(i915)) { 2193 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); 2194 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2195 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 2196 } else if (GRAPHICS_VER(i915) == 8) { 2197 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8); 2198 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); 2199 } else if (IS_VALLEYVIEW(i915)) { 2200 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); 2201 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2202 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 2203 } else if (IS_GRAPHICS_VER(i915, 6, 7)) { 2204 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2205 ASSIGN_READ_MMIO_VFUNCS(uncore, gen6); 2206 } 2207 2208 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; 2209 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 2210 2211 return 0; 2212 } 2213 2214 int intel_uncore_init_mmio(struct intel_uncore *uncore) 2215 { 2216 struct drm_i915_private *i915 = uncore->i915; 2217 int ret; 2218 2219 ret = uncore_mmio_setup(uncore); 2220 if (ret) 2221 return ret; 2222 2223 /* 2224 * The boot firmware initializes local memory and assesses its health. 2225 * If memory training fails, the punit will have been instructed to 2226 * keep the GT powered down; we won't be able to communicate with it 2227 * and we should not continue with driver initialization. 2228 */ 2229 if (IS_DGFX(i915) && 2230 !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) { 2231 drm_err(&i915->drm, "LMEM not initialized by firmware\n"); 2232 return -ENODEV; 2233 } 2234 2235 if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915)) 2236 uncore->flags |= UNCORE_HAS_FORCEWAKE; 2237 2238 if (!intel_uncore_has_forcewake(uncore)) { 2239 uncore_raw_init(uncore); 2240 } else { 2241 ret = uncore_forcewake_init(uncore); 2242 if (ret) 2243 goto out_mmio_cleanup; 2244 } 2245 2246 /* make sure fw funcs are set if and only if we have fw*/ 2247 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_get); 2248 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.force_wake_put); 2249 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); 2250 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); 2251 2252 if (HAS_FPGA_DBG_UNCLAIMED(i915)) 2253 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; 2254 2255 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 2256 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; 2257 2258 if (IS_GRAPHICS_VER(i915, 6, 7)) 2259 uncore->flags |= UNCORE_HAS_FIFO; 2260 2261 /* clear out unclaimed reg detection bit */ 2262 if (intel_uncore_unclaimed_mmio(uncore)) 2263 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n"); 2264 2265 return 0; 2266 2267 out_mmio_cleanup: 2268 uncore_mmio_cleanup(uncore); 2269 2270 return ret; 2271 } 2272 2273 /* 2274 * We might have detected that some engines are fused off after we initialized 2275 * the forcewake domains. Prune them, to make sure they only reference existing 2276 * engines. 2277 */ 2278 void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, 2279 struct intel_gt *gt) 2280 { 2281 enum forcewake_domains fw_domains = uncore->fw_domains; 2282 enum forcewake_domain_id domain_id; 2283 int i; 2284 2285 if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11) 2286 return; 2287 2288 for (i = 0; i < I915_MAX_VCS; i++) { 2289 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; 2290 2291 if (HAS_ENGINE(gt, _VCS(i))) 2292 continue; 2293 2294 /* 2295 * Starting with XeHP, the power well for an even-numbered 2296 * VDBOX is also used for shared units within the 2297 * media slice such as SFC. So even if the engine 2298 * itself is fused off, we still need to initialize 2299 * the forcewake domain if any of the other engines 2300 * in the same media slice are present. 2301 */ 2302 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50) && i % 2 == 0) { 2303 if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1))) 2304 continue; 2305 2306 if (HAS_ENGINE(gt, _VECS(i / 2))) 2307 continue; 2308 } 2309 2310 if (fw_domains & BIT(domain_id)) 2311 fw_domain_fini(uncore, domain_id); 2312 } 2313 2314 for (i = 0; i < I915_MAX_VECS; i++) { 2315 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; 2316 2317 if (HAS_ENGINE(gt, _VECS(i))) 2318 continue; 2319 2320 if (fw_domains & BIT(domain_id)) 2321 fw_domain_fini(uncore, domain_id); 2322 } 2323 } 2324 2325 void intel_uncore_fini_mmio(struct intel_uncore *uncore) 2326 { 2327 if (intel_uncore_has_forcewake(uncore)) { 2328 iosf_mbi_punit_acquire(); 2329 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 2330 &uncore->pmic_bus_access_nb); 2331 intel_uncore_forcewake_reset(uncore); 2332 intel_uncore_fw_domains_fini(uncore); 2333 iosf_mbi_punit_release(); 2334 } 2335 2336 uncore_mmio_cleanup(uncore); 2337 } 2338 2339 static const struct reg_whitelist { 2340 i915_reg_t offset_ldw; 2341 i915_reg_t offset_udw; 2342 u8 min_graphics_ver; 2343 u8 max_graphics_ver; 2344 u8 size; 2345 } reg_read_whitelist[] = { { 2346 .offset_ldw = RING_TIMESTAMP(RENDER_RING_BASE), 2347 .offset_udw = RING_TIMESTAMP_UDW(RENDER_RING_BASE), 2348 .min_graphics_ver = 4, 2349 .max_graphics_ver = 12, 2350 .size = 8 2351 } }; 2352 2353 int i915_reg_read_ioctl(struct drm_device *dev, 2354 void *data, struct drm_file *file) 2355 { 2356 struct drm_i915_private *i915 = to_i915(dev); 2357 struct intel_uncore *uncore = &i915->uncore; 2358 struct drm_i915_reg_read *reg = data; 2359 struct reg_whitelist const *entry; 2360 intel_wakeref_t wakeref; 2361 unsigned int flags; 2362 int remain; 2363 int ret = 0; 2364 2365 entry = reg_read_whitelist; 2366 remain = ARRAY_SIZE(reg_read_whitelist); 2367 while (remain) { 2368 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); 2369 2370 GEM_BUG_ON(!is_power_of_2(entry->size)); 2371 GEM_BUG_ON(entry->size > 8); 2372 GEM_BUG_ON(entry_offset & (entry->size - 1)); 2373 2374 if (IS_GRAPHICS_VER(i915, entry->min_graphics_ver, entry->max_graphics_ver) && 2375 entry_offset == (reg->offset & -entry->size)) 2376 break; 2377 entry++; 2378 remain--; 2379 } 2380 2381 if (!remain) 2382 return -EINVAL; 2383 2384 flags = reg->offset & (entry->size - 1); 2385 2386 with_intel_runtime_pm(&i915->runtime_pm, wakeref) { 2387 if (entry->size == 8 && flags == I915_REG_READ_8B_WA) 2388 reg->val = intel_uncore_read64_2x32(uncore, 2389 entry->offset_ldw, 2390 entry->offset_udw); 2391 else if (entry->size == 8 && flags == 0) 2392 reg->val = intel_uncore_read64(uncore, 2393 entry->offset_ldw); 2394 else if (entry->size == 4 && flags == 0) 2395 reg->val = intel_uncore_read(uncore, entry->offset_ldw); 2396 else if (entry->size == 2 && flags == 0) 2397 reg->val = intel_uncore_read16(uncore, 2398 entry->offset_ldw); 2399 else if (entry->size == 1 && flags == 0) 2400 reg->val = intel_uncore_read8(uncore, 2401 entry->offset_ldw); 2402 else 2403 ret = -EINVAL; 2404 } 2405 2406 return ret; 2407 } 2408 2409 /** 2410 * __intel_wait_for_register_fw - wait until register matches expected state 2411 * @uncore: the struct intel_uncore 2412 * @reg: the register to read 2413 * @mask: mask to apply to register value 2414 * @value: expected value 2415 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2416 * @slow_timeout_ms: slow timeout in millisecond 2417 * @out_value: optional placeholder to hold registry value 2418 * 2419 * This routine waits until the target register @reg contains the expected 2420 * @value after applying the @mask, i.e. it waits until :: 2421 * 2422 * (intel_uncore_read_fw(uncore, reg) & mask) == value 2423 * 2424 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. 2425 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us 2426 * must be not larger than 20,0000 microseconds. 2427 * 2428 * Note that this routine assumes the caller holds forcewake asserted, it is 2429 * not suitable for very long waits. See intel_wait_for_register() if you 2430 * wish to wait without holding forcewake for the duration (i.e. you expect 2431 * the wait to be slow). 2432 * 2433 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2434 */ 2435 int __intel_wait_for_register_fw(struct intel_uncore *uncore, 2436 i915_reg_t reg, 2437 u32 mask, 2438 u32 value, 2439 unsigned int fast_timeout_us, 2440 unsigned int slow_timeout_ms, 2441 u32 *out_value) 2442 { 2443 u32 reg_value = 0; 2444 #define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) 2445 int ret; 2446 2447 /* Catch any overuse of this function */ 2448 might_sleep_if(slow_timeout_ms); 2449 GEM_BUG_ON(fast_timeout_us > 20000); 2450 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms); 2451 2452 ret = -ETIMEDOUT; 2453 if (fast_timeout_us && fast_timeout_us <= 20000) 2454 ret = _wait_for_atomic(done, fast_timeout_us, 0); 2455 if (ret && slow_timeout_ms) 2456 ret = wait_for(done, slow_timeout_ms); 2457 2458 if (out_value) 2459 *out_value = reg_value; 2460 2461 return ret; 2462 #undef done 2463 } 2464 2465 /** 2466 * __intel_wait_for_register - wait until register matches expected state 2467 * @uncore: the struct intel_uncore 2468 * @reg: the register to read 2469 * @mask: mask to apply to register value 2470 * @value: expected value 2471 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2472 * @slow_timeout_ms: slow timeout in millisecond 2473 * @out_value: optional placeholder to hold registry value 2474 * 2475 * This routine waits until the target register @reg contains the expected 2476 * @value after applying the @mask, i.e. it waits until :: 2477 * 2478 * (intel_uncore_read(uncore, reg) & mask) == value 2479 * 2480 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 2481 * 2482 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2483 */ 2484 int __intel_wait_for_register(struct intel_uncore *uncore, 2485 i915_reg_t reg, 2486 u32 mask, 2487 u32 value, 2488 unsigned int fast_timeout_us, 2489 unsigned int slow_timeout_ms, 2490 u32 *out_value) 2491 { 2492 unsigned fw = 2493 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 2494 u32 reg_value; 2495 int ret; 2496 2497 might_sleep_if(slow_timeout_ms); 2498 2499 spin_lock_irq(&uncore->lock); 2500 intel_uncore_forcewake_get__locked(uncore, fw); 2501 2502 ret = __intel_wait_for_register_fw(uncore, 2503 reg, mask, value, 2504 fast_timeout_us, 0, ®_value); 2505 2506 intel_uncore_forcewake_put__locked(uncore, fw); 2507 spin_unlock_irq(&uncore->lock); 2508 2509 if (ret && slow_timeout_ms) 2510 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, 2511 reg), 2512 (reg_value & mask) == value, 2513 slow_timeout_ms * 1000, 10, 1000); 2514 2515 /* just trace the final value */ 2516 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); 2517 2518 if (out_value) 2519 *out_value = reg_value; 2520 2521 return ret; 2522 } 2523 2524 bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) 2525 { 2526 bool ret; 2527 2528 spin_lock_irq(&uncore->debug->lock); 2529 ret = check_for_unclaimed_mmio(uncore); 2530 spin_unlock_irq(&uncore->debug->lock); 2531 2532 return ret; 2533 } 2534 2535 bool 2536 intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) 2537 { 2538 bool ret = false; 2539 2540 spin_lock_irq(&uncore->debug->lock); 2541 2542 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) 2543 goto out; 2544 2545 if (unlikely(check_for_unclaimed_mmio(uncore))) { 2546 if (!uncore->i915->params.mmio_debug) { 2547 drm_dbg(&uncore->i915->drm, 2548 "Unclaimed register detected, " 2549 "enabling oneshot unclaimed register reporting. " 2550 "Please use i915.mmio_debug=N for more information.\n"); 2551 uncore->i915->params.mmio_debug++; 2552 } 2553 uncore->debug->unclaimed_mmio_check--; 2554 ret = true; 2555 } 2556 2557 out: 2558 spin_unlock_irq(&uncore->debug->lock); 2559 2560 return ret; 2561 } 2562 2563 /** 2564 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access 2565 * a register 2566 * @uncore: pointer to struct intel_uncore 2567 * @reg: register in question 2568 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE 2569 * 2570 * Returns a set of forcewake domains required to be taken with for example 2571 * intel_uncore_forcewake_get for the specified register to be accessible in the 2572 * specified mode (read, write or read/write) with raw mmio accessors. 2573 * 2574 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the 2575 * callers to do FIFO management on their own or risk losing writes. 2576 */ 2577 enum forcewake_domains 2578 intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, 2579 i915_reg_t reg, unsigned int op) 2580 { 2581 enum forcewake_domains fw_domains = 0; 2582 2583 drm_WARN_ON(&uncore->i915->drm, !op); 2584 2585 if (!intel_uncore_has_forcewake(uncore)) 2586 return 0; 2587 2588 if (op & FW_REG_READ) 2589 fw_domains = uncore->funcs.read_fw_domains(uncore, reg); 2590 2591 if (op & FW_REG_WRITE) 2592 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); 2593 2594 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains); 2595 2596 return fw_domains; 2597 } 2598 2599 u32 intel_uncore_read_with_mcr_steering_fw(struct intel_uncore *uncore, 2600 i915_reg_t reg, 2601 int slice, int subslice) 2602 { 2603 u32 mcr_mask, mcr_ss, mcr, old_mcr, val; 2604 2605 lockdep_assert_held(&uncore->lock); 2606 2607 if (GRAPHICS_VER(uncore->i915) >= 11) { 2608 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; 2609 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); 2610 } else { 2611 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK; 2612 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); 2613 } 2614 2615 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR); 2616 2617 mcr &= ~mcr_mask; 2618 mcr |= mcr_ss; 2619 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 2620 2621 val = intel_uncore_read_fw(uncore, reg); 2622 2623 mcr &= ~mcr_mask; 2624 mcr |= old_mcr & mcr_mask; 2625 2626 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr); 2627 2628 return val; 2629 } 2630 2631 u32 intel_uncore_read_with_mcr_steering(struct intel_uncore *uncore, 2632 i915_reg_t reg, int slice, int subslice) 2633 { 2634 enum forcewake_domains fw_domains; 2635 u32 val; 2636 2637 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, 2638 FW_REG_READ); 2639 fw_domains |= intel_uncore_forcewake_for_reg(uncore, 2640 GEN8_MCR_SELECTOR, 2641 FW_REG_READ | FW_REG_WRITE); 2642 2643 spin_lock_irq(&uncore->lock); 2644 intel_uncore_forcewake_get__locked(uncore, fw_domains); 2645 2646 val = intel_uncore_read_with_mcr_steering_fw(uncore, reg, slice, subslice); 2647 2648 intel_uncore_forcewake_put__locked(uncore, fw_domains); 2649 spin_unlock_irq(&uncore->lock); 2650 2651 return val; 2652 } 2653 2654 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2655 #include "selftests/mock_uncore.c" 2656 #include "selftests/intel_uncore.c" 2657 #endif 2658