1 /* $OpenBSD: i915_irq.c,v 1.13 2014/07/12 18:48:52 tedu Exp $ */ 2 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 3 */ 4 /* 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 31 32 #include <dev/pci/drm/drmP.h> 33 #include <dev/pci/drm/i915_drm.h> 34 #include "i915_drv.h" 35 #include "intel_drv.h" 36 37 #define IRQ_NONE 0 38 #define IRQ_HANDLED 1 39 40 /* For display hotplug interrupt */ 41 static void 42 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 43 { 44 if ((dev_priv->irq_mask & mask) != 0) { 45 dev_priv->irq_mask &= ~mask; 46 I915_WRITE(DEIMR, dev_priv->irq_mask); 47 POSTING_READ(DEIMR); 48 } 49 } 50 51 static inline void 52 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 53 { 54 if ((dev_priv->irq_mask & mask) != mask) { 55 dev_priv->irq_mask |= mask; 56 I915_WRITE(DEIMR, dev_priv->irq_mask); 57 POSTING_READ(DEIMR); 58 } 59 } 60 61 void 62 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 63 { 64 if ((dev_priv->pipestat[pipe] & mask) != mask) { 65 u32 reg = PIPESTAT(pipe); 66 67 dev_priv->pipestat[pipe] |= mask; 68 /* Enable the interrupt, clear any pending status */ 69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 70 POSTING_READ(reg); 71 } 72 } 73 74 void 75 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 76 { 77 if ((dev_priv->pipestat[pipe] & mask) != 0) { 78 u32 reg = PIPESTAT(pipe); 79 80 dev_priv->pipestat[pipe] &= ~mask; 81 I915_WRITE(reg, dev_priv->pipestat[pipe]); 82 POSTING_READ(reg); 83 } 84 } 85 86 /** 87 * intel_enable_asle - enable ASLE interrupt for OpRegion 88 */ 89 void intel_enable_asle(struct drm_device *dev) 90 { 91 drm_i915_private_t *dev_priv = dev->dev_private; 92 93 /* FIXME: opregion/asle for VLV */ 94 if (IS_VALLEYVIEW(dev)) 95 return; 96 97 mtx_enter(&dev_priv->irq_lock); 98 99 if (HAS_PCH_SPLIT(dev)) 100 ironlake_enable_display_irq(dev_priv, DE_GSE); 101 else { 102 i915_enable_pipestat(dev_priv, 1, 103 PIPE_LEGACY_BLC_EVENT_ENABLE); 104 if (INTEL_INFO(dev)->gen >= 4) 105 i915_enable_pipestat(dev_priv, 0, 106 PIPE_LEGACY_BLC_EVENT_ENABLE); 107 } 108 109 mtx_leave(&dev_priv->irq_lock); 110 } 111 112 /** 113 * i915_pipe_enabled - check if a pipe is enabled 114 * @dev: DRM device 115 * @pipe: pipe to check 116 * 117 * Reading certain registers when the pipe is disabled can hang the chip. 118 * Use this routine to make sure the PLL is running and the pipe is active 119 * before reading such registers if unsure. 120 */ 121 static int 122 i915_pipe_enabled(struct drm_device *dev, int pipe) 123 { 124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 126 pipe); 127 128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE; 129 } 130 131 /* Called from drm generic code, passed a 'crtc', which 132 * we use as a pipe index 133 */ 134 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 135 { 136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 137 unsigned long high_frame; 138 unsigned long low_frame; 139 u32 high1, high2, low; 140 141 if (!i915_pipe_enabled(dev, pipe)) { 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 143 "pipe %c\n", pipe_name(pipe)); 144 return 0; 145 } 146 147 high_frame = PIPEFRAME(pipe); 148 low_frame = PIPEFRAMEPIXEL(pipe); 149 150 /* 151 * High & low register fields aren't synchronized, so make sure 152 * we get a low value that's stable across two reads of the high 153 * register. 154 */ 155 do { 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; 158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 159 } while (high1 != high2); 160 161 high1 >>= PIPE_FRAME_HIGH_SHIFT; 162 low >>= PIPE_FRAME_LOW_SHIFT; 163 return (high1 << 8) | low; 164 } 165 166 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 167 { 168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 169 int reg = PIPE_FRMCOUNT_GM45(pipe); 170 171 if (!i915_pipe_enabled(dev, pipe)) { 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 173 "pipe %c\n", pipe_name(pipe)); 174 return 0; 175 } 176 177 return I915_READ(reg); 178 } 179 180 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 181 int *vpos, int *hpos) 182 { 183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 184 u32 vbl = 0, position = 0; 185 int vbl_start, vbl_end, htotal, vtotal; 186 bool in_vbl = true; 187 int ret = 0; 188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 189 pipe); 190 191 if (!i915_pipe_enabled(dev, pipe)) { 192 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 193 "pipe %c\n", pipe_name(pipe)); 194 return 0; 195 } 196 197 /* Get vtotal. */ 198 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff); 199 200 if (INTEL_INFO(dev)->gen >= 4) { 201 /* No obvious pixelcount register. Only query vertical 202 * scanout position from Display scan line register. 203 */ 204 position = I915_READ(PIPEDSL(pipe)); 205 206 /* Decode into vertical scanout position. Don't have 207 * horizontal scanout position. 208 */ 209 *vpos = position & 0x1fff; 210 *hpos = 0; 211 } else { 212 /* Have access to pixelcount since start of frame. 213 * We can split this into vertical and horizontal 214 * scanout position. 215 */ 216 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 217 218 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff); 219 *vpos = position / htotal; 220 *hpos = position - (*vpos * htotal); 221 } 222 223 /* Query vblank area. */ 224 vbl = I915_READ(VBLANK(cpu_transcoder)); 225 226 /* Test position against vblank region. */ 227 vbl_start = vbl & 0x1fff; 228 vbl_end = (vbl >> 16) & 0x1fff; 229 230 if ((*vpos < vbl_start) || (*vpos > vbl_end)) 231 in_vbl = false; 232 233 /* Inside "upper part" of vblank area? Apply corrective offset: */ 234 if (in_vbl && (*vpos >= vbl_start)) 235 *vpos = *vpos - vtotal; 236 237 /* Readouts valid? */ 238 if (vbl > 0) 239 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 240 241 /* In vblank? */ 242 if (in_vbl) 243 ret |= DRM_SCANOUTPOS_INVBL; 244 245 return ret; 246 } 247 248 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 249 int *max_error, 250 struct timeval *vblank_time, 251 unsigned flags) 252 { 253 struct drm_crtc *crtc; 254 255 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { 256 DRM_ERROR("Invalid crtc %d\n", pipe); 257 return -EINVAL; 258 } 259 260 /* Get drm_crtc to timestamp: */ 261 crtc = intel_get_crtc_for_pipe(dev, pipe); 262 if (crtc == NULL) { 263 DRM_ERROR("Invalid crtc %d\n", pipe); 264 return -EINVAL; 265 } 266 267 if (!crtc->enabled) { 268 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 269 return -EBUSY; 270 } 271 272 /* Helper routine in DRM core does all the work: */ 273 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 274 vblank_time, flags, 275 crtc); 276 } 277 278 /* 279 * Handle hotplug events outside the interrupt handler proper. 280 */ 281 static void i915_hotplug_work_func(void *arg1, void *arg2) 282 { 283 drm_i915_private_t *dev_priv = (drm_i915_private_t *)arg1; 284 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 285 struct drm_mode_config *mode_config = &dev->mode_config; 286 struct intel_encoder *encoder; 287 288 rw_enter_write(&mode_config->rwl); 289 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 290 291 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 292 if (encoder->hot_plug) 293 encoder->hot_plug(encoder); 294 295 rw_exit_write(&mode_config->rwl); 296 297 /* Just fire off a uevent and let userspace tell us what to do */ 298 drm_helper_hpd_irq_event(dev); 299 } 300 301 /* defined intel_pm.c */ 302 extern struct mutex mchdev_lock; 303 304 static void ironlake_handle_rps_change(struct drm_device *dev) 305 { 306 drm_i915_private_t *dev_priv = dev->dev_private; 307 u32 busy_up, busy_down, max_avg, min_avg; 308 u8 new_delay; 309 310 mtx_enter(&mchdev_lock); 311 312 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 313 314 new_delay = dev_priv->ips.cur_delay; 315 316 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 317 busy_up = I915_READ(RCPREVBSYTUPAVG); 318 busy_down = I915_READ(RCPREVBSYTDNAVG); 319 max_avg = I915_READ(RCBMAXAVG); 320 min_avg = I915_READ(RCBMINAVG); 321 322 /* Handle RCS change request from hw */ 323 if (busy_up > max_avg) { 324 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) 325 new_delay = dev_priv->ips.cur_delay - 1; 326 if (new_delay < dev_priv->ips.max_delay) 327 new_delay = dev_priv->ips.max_delay; 328 } else if (busy_down < min_avg) { 329 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) 330 new_delay = dev_priv->ips.cur_delay + 1; 331 if (new_delay > dev_priv->ips.min_delay) 332 new_delay = dev_priv->ips.min_delay; 333 } 334 335 if (ironlake_set_drps(dev, new_delay)) 336 dev_priv->ips.cur_delay = new_delay; 337 338 mtx_leave(&mchdev_lock); 339 340 return; 341 } 342 343 static void notify_ring(struct drm_device *dev, 344 struct intel_ring_buffer *ring) 345 { 346 struct drm_i915_private *dev_priv = dev->dev_private; 347 348 if (ring->obj == NULL) 349 return; 350 351 // trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false)); 352 353 wakeup(ring); 354 if (i915_enable_hangcheck) { 355 dev_priv->hangcheck_count = 0; 356 timeout_add_msec(&dev_priv->hangcheck_timer, 357 DRM_I915_HANGCHECK_PERIOD); 358 } 359 } 360 361 static void gen6_pm_rps_work(void *arg1, void *arg2) 362 { 363 drm_i915_private_t *dev_priv = arg1; 364 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 365 u32 pm_iir, pm_imr; 366 u8 new_delay; 367 368 mtx_enter(&dev_priv->rps.lock); 369 pm_iir = dev_priv->rps.pm_iir; 370 dev_priv->rps.pm_iir = 0; 371 pm_imr = I915_READ(GEN6_PMIMR); 372 I915_WRITE(GEN6_PMIMR, 0); 373 mtx_leave(&dev_priv->rps.lock); 374 375 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0) 376 return; 377 378 rw_enter_write(&dev_priv->rps.hw_lock); 379 380 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) 381 new_delay = dev_priv->rps.cur_delay + 1; 382 else 383 new_delay = dev_priv->rps.cur_delay - 1; 384 385 /* sysfs frequency interfaces may have snuck in while servicing the 386 * interrupt 387 */ 388 if (!(new_delay > dev_priv->rps.max_delay || 389 new_delay < dev_priv->rps.min_delay)) { 390 gen6_set_rps(dev, new_delay); 391 } 392 393 rw_exit_write(&dev_priv->rps.hw_lock); 394 } 395 396 /** 397 * ivybridge_parity_work - Workqueue called when a parity error interrupt 398 * occurred. 399 * @work: workqueue struct 400 * 401 * Doesn't actually do anything except notify userspace. As a consequence of 402 * this event, userspace should try to remap the bad rows since statistically 403 * it is likely the same row is more likely to go bad again. 404 */ 405 static void ivybridge_parity_work(void *arg1, void *arg2) 406 { 407 drm_i915_private_t *dev_priv = arg1; 408 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 409 u32 error_status, row, bank, subbank; 410 // char *parity_event[5]; 411 uint32_t misccpctl; 412 413 /* We must turn off DOP level clock gating to access the L3 registers. 414 * In order to prevent a get/put style interface, acquire struct mutex 415 * any time we access those registers. 416 */ 417 DRM_LOCK(); 418 419 misccpctl = I915_READ(GEN7_MISCCPCTL); 420 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 421 POSTING_READ(GEN7_MISCCPCTL); 422 423 error_status = I915_READ(GEN7_L3CDERRST1); 424 row = GEN7_PARITY_ERROR_ROW(error_status); 425 bank = GEN7_PARITY_ERROR_BANK(error_status); 426 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 427 428 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID | 429 GEN7_L3CDERRST1_ENABLE); 430 POSTING_READ(GEN7_L3CDERRST1); 431 432 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 433 434 mtx_enter(&dev_priv->irq_lock); 435 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 436 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 437 mtx_leave(&dev_priv->irq_lock); 438 439 DRM_UNLOCK(); 440 441 #if 0 442 parity_event[0] = "L3_PARITY_ERROR=1"; 443 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); 444 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); 445 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); 446 parity_event[4] = NULL; 447 #endif 448 449 #ifdef notyet 450 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj, 451 KOBJ_CHANGE, parity_event); 452 #endif 453 454 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n", 455 row, bank, subbank); 456 457 #if 0 458 free(parity_event[3], M_DRM, 0); 459 free(parity_event[2], M_DRM, 0); 460 free(parity_event[1], M_DRM, 0); 461 #endif 462 } 463 464 static void ivybridge_handle_parity_error(struct drm_device *dev) 465 { 466 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 467 468 if (!HAS_L3_GPU_CACHE(dev)) 469 return; 470 471 mtx_enter(&dev_priv->irq_lock); 472 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 473 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 474 mtx_leave(&dev_priv->irq_lock); 475 476 task_add(systq, &dev_priv->l3_parity.error_task); 477 } 478 479 static void snb_gt_irq_handler(struct drm_device *dev, 480 struct drm_i915_private *dev_priv, 481 u32 gt_iir) 482 { 483 484 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | 485 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) 486 notify_ring(dev, &dev_priv->ring[RCS]); 487 if (gt_iir & GEN6_BSD_USER_INTERRUPT) 488 notify_ring(dev, &dev_priv->ring[VCS]); 489 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) 490 notify_ring(dev, &dev_priv->ring[BCS]); 491 492 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | 493 GT_GEN6_BSD_CS_ERROR_INTERRUPT | 494 GT_RENDER_CS_ERROR_INTERRUPT)) { 495 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); 496 i915_handle_error(dev, false); 497 } 498 499 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT) 500 ivybridge_handle_parity_error(dev); 501 } 502 503 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, 504 u32 pm_iir) 505 { 506 /* 507 * IIR bits should never already be set because IMR should 508 * prevent an interrupt from being shown in IIR. The warning 509 * displays a case where we've unsafely cleared 510 * dev_priv->rps.pm_iir. Although missing an interrupt of the same 511 * type is not a problem, it displays a problem in the logic. 512 * 513 * The mask bit in IMR is cleared by dev_priv->rps.work. 514 */ 515 516 mtx_enter(&dev_priv->rps.lock); 517 dev_priv->rps.pm_iir |= pm_iir; 518 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); 519 POSTING_READ(GEN6_PMIMR); 520 mtx_leave(&dev_priv->rps.lock); 521 522 task_add(systq, &dev_priv->rps.task); 523 } 524 525 static int valleyview_intr(void *arg) 526 { 527 drm_i915_private_t *dev_priv = arg; 528 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 529 u32 iir, gt_iir, pm_iir; 530 int ret = IRQ_NONE; 531 int pipe; 532 u32 pipe_stats[I915_MAX_PIPES]; 533 bool blc_event; 534 535 // atomic_inc(&dev_priv->irq_received); 536 537 while (true) { 538 iir = I915_READ(VLV_IIR); 539 gt_iir = I915_READ(GTIIR); 540 pm_iir = I915_READ(GEN6_PMIIR); 541 542 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 543 goto out; 544 545 ret = IRQ_HANDLED; 546 547 snb_gt_irq_handler(dev, dev_priv, gt_iir); 548 549 mtx_enter(&dev_priv->irq_lock); 550 for_each_pipe(pipe) { 551 int reg = PIPESTAT(pipe); 552 pipe_stats[pipe] = I915_READ(reg); 553 554 /* 555 * Clear the PIPE*STAT regs before the IIR 556 */ 557 if (pipe_stats[pipe] & 0x8000ffff) { 558 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 559 DRM_DEBUG_DRIVER("pipe %c underrun\n", 560 pipe_name(pipe)); 561 I915_WRITE(reg, pipe_stats[pipe]); 562 } 563 } 564 mtx_leave(&dev_priv->irq_lock); 565 566 for_each_pipe(pipe) { 567 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) 568 drm_handle_vblank(dev, pipe); 569 570 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { 571 intel_prepare_page_flip(dev, pipe); 572 intel_finish_page_flip(dev, pipe); 573 } 574 } 575 576 /* Consume port. Then clear IIR or we'll miss events */ 577 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 578 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 579 580 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 581 hotplug_status); 582 if (hotplug_status & dev_priv->hotplug_supported_mask) 583 task_add(systq, &dev_priv->hotplug_task); 584 585 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 586 I915_READ(PORT_HOTPLUG_STAT); 587 } 588 589 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 590 blc_event = true; 591 592 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) 593 gen6_queue_rps_work(dev_priv, pm_iir); 594 595 I915_WRITE(GTIIR, gt_iir); 596 I915_WRITE(GEN6_PMIIR, pm_iir); 597 I915_WRITE(VLV_IIR, iir); 598 } 599 600 out: 601 return ret; 602 } 603 604 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 605 { 606 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 607 int pipe; 608 609 if (pch_iir & SDE_HOTPLUG_MASK) 610 task_add(systq, &dev_priv->hotplug_task); 611 612 if (pch_iir & SDE_AUDIO_POWER_MASK) 613 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 614 (pch_iir & SDE_AUDIO_POWER_MASK) >> 615 SDE_AUDIO_POWER_SHIFT); 616 617 if (pch_iir & SDE_GMBUS) 618 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 619 620 if (pch_iir & SDE_AUDIO_HDCP_MASK) 621 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 622 623 if (pch_iir & SDE_AUDIO_TRANS_MASK) 624 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 625 626 if (pch_iir & SDE_POISON) 627 DRM_ERROR("PCH poison interrupt\n"); 628 629 if (pch_iir & SDE_FDI_MASK) 630 for_each_pipe(pipe) 631 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 632 pipe_name(pipe), 633 I915_READ(FDI_RX_IIR(pipe))); 634 635 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 636 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 637 638 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 639 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 640 641 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 642 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); 643 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 644 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 645 } 646 647 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 648 { 649 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 650 int pipe; 651 652 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 653 task_add(systq, &dev_priv->hotplug_task); 654 655 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) 656 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 657 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 658 SDE_AUDIO_POWER_SHIFT_CPT); 659 660 if (pch_iir & SDE_AUX_MASK_CPT) 661 DRM_DEBUG_DRIVER("AUX channel interrupt\n"); 662 663 if (pch_iir & SDE_GMBUS_CPT) 664 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 665 666 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 667 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 668 669 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 670 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 671 672 if (pch_iir & SDE_FDI_MASK_CPT) 673 for_each_pipe(pipe) 674 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 675 pipe_name(pipe), 676 I915_READ(FDI_RX_IIR(pipe))); 677 } 678 679 static int ivybridge_intr(void *arg) 680 { 681 drm_i915_private_t *dev_priv = arg; 682 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 683 u32 de_iir, gt_iir, de_ier, pm_iir; 684 int ret = IRQ_NONE; 685 int i; 686 687 // atomic_inc(&dev_priv->irq_received); 688 689 /* disable master interrupt before clearing iir */ 690 de_ier = I915_READ(DEIER); 691 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 692 693 gt_iir = I915_READ(GTIIR); 694 if (gt_iir) { 695 snb_gt_irq_handler(dev, dev_priv, gt_iir); 696 I915_WRITE(GTIIR, gt_iir); 697 ret = IRQ_HANDLED; 698 } 699 700 de_iir = I915_READ(DEIIR); 701 if (de_iir) { 702 if (de_iir & DE_GSE_IVB) 703 intel_opregion_gse_intr(dev); 704 705 for (i = 0; i < 3; i++) { 706 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) 707 drm_handle_vblank(dev, i); 708 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { 709 intel_prepare_page_flip(dev, i); 710 intel_finish_page_flip_plane(dev, i); 711 } 712 } 713 714 /* check event from PCH */ 715 if (de_iir & DE_PCH_EVENT_IVB) { 716 u32 pch_iir = I915_READ(SDEIIR); 717 718 cpt_irq_handler(dev, pch_iir); 719 720 /* clear PCH hotplug event before clear CPU irq */ 721 I915_WRITE(SDEIIR, pch_iir); 722 } 723 724 I915_WRITE(DEIIR, de_iir); 725 ret = IRQ_HANDLED; 726 } 727 728 pm_iir = I915_READ(GEN6_PMIIR); 729 if (pm_iir) { 730 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) 731 gen6_queue_rps_work(dev_priv, pm_iir); 732 I915_WRITE(GEN6_PMIIR, pm_iir); 733 ret = IRQ_HANDLED; 734 } 735 736 I915_WRITE(DEIER, de_ier); 737 POSTING_READ(DEIER); 738 739 return ret; 740 } 741 742 static void ilk_gt_irq_handler(struct drm_device *dev, 743 struct drm_i915_private *dev_priv, 744 u32 gt_iir) 745 { 746 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 747 notify_ring(dev, &dev_priv->ring[RCS]); 748 if (gt_iir & GT_BSD_USER_INTERRUPT) 749 notify_ring(dev, &dev_priv->ring[VCS]); 750 } 751 752 static int ironlake_intr(void *arg) 753 { 754 drm_i915_private_t *dev_priv = arg; 755 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 756 int ret = IRQ_NONE; 757 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 758 759 // atomic_inc(&dev_priv->irq_received); 760 761 /* disable master interrupt before clearing iir */ 762 de_ier = I915_READ(DEIER); 763 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 764 POSTING_READ(DEIER); 765 766 de_iir = I915_READ(DEIIR); 767 gt_iir = I915_READ(GTIIR); 768 pch_iir = I915_READ(SDEIIR); 769 pm_iir = I915_READ(GEN6_PMIIR); 770 771 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && 772 (!IS_GEN6(dev) || pm_iir == 0)) 773 goto done; 774 775 ret = IRQ_HANDLED; 776 777 if (IS_GEN5(dev)) 778 ilk_gt_irq_handler(dev, dev_priv, gt_iir); 779 else 780 snb_gt_irq_handler(dev, dev_priv, gt_iir); 781 782 if (de_iir & DE_GSE) 783 intel_opregion_gse_intr(dev); 784 785 if (de_iir & DE_PIPEA_VBLANK) 786 drm_handle_vblank(dev, 0); 787 788 if (de_iir & DE_PIPEB_VBLANK) 789 drm_handle_vblank(dev, 1); 790 791 if (de_iir & DE_PLANEA_FLIP_DONE) { 792 intel_prepare_page_flip(dev, 0); 793 intel_finish_page_flip_plane(dev, 0); 794 } 795 796 if (de_iir & DE_PLANEB_FLIP_DONE) { 797 intel_prepare_page_flip(dev, 1); 798 intel_finish_page_flip_plane(dev, 1); 799 } 800 801 /* check event from PCH */ 802 if (de_iir & DE_PCH_EVENT) { 803 if (HAS_PCH_CPT(dev)) 804 cpt_irq_handler(dev, pch_iir); 805 else 806 ibx_irq_handler(dev, pch_iir); 807 } 808 809 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 810 ironlake_handle_rps_change(dev); 811 812 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) 813 gen6_queue_rps_work(dev_priv, pm_iir); 814 815 /* should clear PCH hotplug event before clear CPU irq */ 816 I915_WRITE(SDEIIR, pch_iir); 817 I915_WRITE(GTIIR, gt_iir); 818 I915_WRITE(DEIIR, de_iir); 819 I915_WRITE(GEN6_PMIIR, pm_iir); 820 821 done: 822 I915_WRITE(DEIER, de_ier); 823 POSTING_READ(DEIER); 824 825 return ret; 826 } 827 828 /** 829 * i915_error_work_func - do process context error handling work 830 * @work: work struct 831 * 832 * Fire an error uevent so userspace can see that a hang or error 833 * was detected. 834 */ 835 static void i915_error_work_func(void *arg1, void *arg2) 836 { 837 drm_i915_private_t *dev_priv = arg1; 838 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 839 #if 0 840 char *error_event[] = { "ERROR=1", NULL }; 841 char *reset_event[] = { "RESET=1", NULL }; 842 char *reset_done_event[] = { "ERROR=0", NULL }; 843 844 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); 845 #endif 846 847 if (atomic_read(&dev_priv->mm.wedged)) { 848 DRM_DEBUG_DRIVER("resetting chip\n"); 849 // kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); 850 if (!i915_reset(dev)) { 851 atomic_set(&dev_priv->mm.wedged, 0); 852 // kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); 853 } 854 mtx_enter(&dev_priv->error_completion_lock); 855 dev_priv->error_completion++; 856 wakeup(&dev_priv->error_completion); 857 mtx_leave(&dev_priv->error_completion_lock); 858 } 859 } 860 861 /* NB: please notice the memset */ 862 static void i915_get_extra_instdone(struct drm_device *dev, 863 uint32_t *instdone) 864 { 865 struct drm_i915_private *dev_priv = dev->dev_private; 866 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 867 868 switch(INTEL_INFO(dev)->gen) { 869 case 2: 870 case 3: 871 instdone[0] = I915_READ(INSTDONE); 872 break; 873 case 4: 874 case 5: 875 case 6: 876 instdone[0] = I915_READ(INSTDONE_I965); 877 instdone[1] = I915_READ(INSTDONE1); 878 break; 879 default: 880 WARN_ONCE(1, "Unsupported platform\n"); 881 case 7: 882 instdone[0] = I915_READ(GEN7_INSTDONE_1); 883 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 884 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 885 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 886 break; 887 } 888 } 889 890 #ifdef CONFIG_DEBUG_FS 891 static struct drm_i915_error_object * 892 i915_error_object_create(struct drm_i915_private *dev_priv, 893 struct drm_i915_gem_object *src) 894 { 895 struct drm_i915_error_object *dst; 896 int i, count; 897 u32 reloc_offset; 898 899 if (src == NULL || src->pages == NULL) 900 return NULL; 901 902 count = src->base.size / PAGE_SIZE; 903 904 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC); 905 if (dst == NULL) 906 return NULL; 907 908 reloc_offset = src->gtt_offset; 909 for (i = 0; i < count; i++) { 910 unsigned long flags; 911 void *d; 912 913 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 914 if (d == NULL) 915 goto unwind; 916 917 local_irq_save(flags); 918 if (reloc_offset < dev_priv->mm.gtt_mappable_end && 919 src->has_global_gtt_mapping) { 920 void __iomem *s; 921 922 /* Simply ignore tiling or any overlapping fence. 923 * It's part of the error state, and this hopefully 924 * captures what the GPU read. 925 */ 926 927 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 928 reloc_offset); 929 memcpy_fromio(d, s, PAGE_SIZE); 930 io_mapping_unmap_atomic(s); 931 } else { 932 struct page *page; 933 void *s; 934 935 page = i915_gem_object_get_page(src, i); 936 937 drm_clflush_pages(&page, 1); 938 939 s = kmap_atomic(page); 940 memcpy(d, s, PAGE_SIZE); 941 kunmap_atomic(s); 942 943 drm_clflush_pages(&page, 1); 944 } 945 local_irq_restore(flags); 946 947 dst->pages[i] = d; 948 949 reloc_offset += PAGE_SIZE; 950 } 951 dst->page_count = count; 952 dst->gtt_offset = src->gtt_offset; 953 954 return dst; 955 956 unwind: 957 while (i--) 958 kfree(dst->pages[i]); 959 kfree(dst); 960 return NULL; 961 } 962 963 static void 964 i915_error_object_free(struct drm_i915_error_object *obj) 965 { 966 int page; 967 968 if (obj == NULL) 969 return; 970 971 for (page = 0; page < obj->page_count; page++) 972 kfree(obj->pages[page]); 973 974 kfree(obj); 975 } 976 977 void 978 i915_error_state_free(struct kref *error_ref) 979 { 980 struct drm_i915_error_state *error = container_of(error_ref, 981 typeof(*error), ref); 982 int i; 983 984 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 985 i915_error_object_free(error->ring[i].batchbuffer); 986 i915_error_object_free(error->ring[i].ringbuffer); 987 kfree(error->ring[i].requests); 988 } 989 990 kfree(error->active_bo); 991 kfree(error->overlay); 992 kfree(error); 993 } 994 static void capture_bo(struct drm_i915_error_buffer *err, 995 struct drm_i915_gem_object *obj) 996 { 997 err->size = obj->base.size; 998 err->name = obj->base.name; 999 err->rseqno = obj->last_read_seqno; 1000 err->wseqno = obj->last_write_seqno; 1001 err->gtt_offset = obj->gtt_offset; 1002 err->read_domains = obj->base.read_domains; 1003 err->write_domain = obj->base.write_domain; 1004 err->fence_reg = obj->fence_reg; 1005 err->pinned = 0; 1006 if (obj->pin_count > 0) 1007 err->pinned = 1; 1008 if (obj->user_pin_count > 0) 1009 err->pinned = -1; 1010 err->tiling = obj->tiling_mode; 1011 err->dirty = obj->dirty; 1012 err->purgeable = obj->madv != I915_MADV_WILLNEED; 1013 err->ring = obj->ring ? obj->ring->id : -1; 1014 err->cache_level = obj->cache_level; 1015 } 1016 1017 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 1018 int count, struct list_head *head) 1019 { 1020 struct drm_i915_gem_object *obj; 1021 int i = 0; 1022 1023 list_for_each_entry(obj, head, mm_list) { 1024 capture_bo(err++, obj); 1025 if (++i == count) 1026 break; 1027 } 1028 1029 return i; 1030 } 1031 1032 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 1033 int count, struct list_head *head) 1034 { 1035 struct drm_i915_gem_object *obj; 1036 int i = 0; 1037 1038 list_for_each_entry(obj, head, gtt_list) { 1039 if (obj->pin_count == 0) 1040 continue; 1041 1042 capture_bo(err++, obj); 1043 if (++i == count) 1044 break; 1045 } 1046 1047 return i; 1048 } 1049 1050 static void i915_gem_record_fences(struct drm_device *dev, 1051 struct drm_i915_error_state *error) 1052 { 1053 struct drm_i915_private *dev_priv = dev->dev_private; 1054 int i; 1055 1056 /* Fences */ 1057 switch (INTEL_INFO(dev)->gen) { 1058 case 7: 1059 case 6: 1060 for (i = 0; i < 16; i++) 1061 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 1062 break; 1063 case 5: 1064 case 4: 1065 for (i = 0; i < 16; i++) 1066 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); 1067 break; 1068 case 3: 1069 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 1070 for (i = 0; i < 8; i++) 1071 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); 1072 case 2: 1073 for (i = 0; i < 8; i++) 1074 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 1075 break; 1076 1077 } 1078 } 1079 1080 static struct drm_i915_error_object * 1081 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 1082 struct intel_ring_buffer *ring) 1083 { 1084 struct drm_i915_gem_object *obj; 1085 u32 seqno; 1086 1087 if (!ring->get_seqno) 1088 return NULL; 1089 1090 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) { 1091 u32 acthd = I915_READ(ACTHD); 1092 1093 if (WARN_ON(ring->id != RCS)) 1094 return NULL; 1095 1096 obj = ring->private; 1097 if (acthd >= obj->gtt_offset && 1098 acthd < obj->gtt_offset + obj->base.size) 1099 return i915_error_object_create(dev_priv, obj); 1100 } 1101 1102 seqno = ring->get_seqno(ring, false); 1103 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 1104 if (obj->ring != ring) 1105 continue; 1106 1107 if (i915_seqno_passed(seqno, obj->last_read_seqno)) 1108 continue; 1109 1110 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 1111 continue; 1112 1113 /* We need to copy these to an anonymous buffer as the simplest 1114 * method to avoid being overwritten by userspace. 1115 */ 1116 return i915_error_object_create(dev_priv, obj); 1117 } 1118 1119 return NULL; 1120 } 1121 1122 static void i915_record_ring_state(struct drm_device *dev, 1123 struct drm_i915_error_state *error, 1124 struct intel_ring_buffer *ring) 1125 { 1126 struct drm_i915_private *dev_priv = dev->dev_private; 1127 1128 if (INTEL_INFO(dev)->gen >= 6) { 1129 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50); 1130 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); 1131 error->semaphore_mboxes[ring->id][0] 1132 = I915_READ(RING_SYNC_0(ring->mmio_base)); 1133 error->semaphore_mboxes[ring->id][1] 1134 = I915_READ(RING_SYNC_1(ring->mmio_base)); 1135 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0]; 1136 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1]; 1137 } 1138 1139 if (INTEL_INFO(dev)->gen >= 4) { 1140 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 1141 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 1142 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 1143 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 1144 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 1145 if (ring->id == RCS) 1146 error->bbaddr = I915_READ64(BB_ADDR); 1147 } else { 1148 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX); 1149 error->ipeir[ring->id] = I915_READ(IPEIR); 1150 error->ipehr[ring->id] = I915_READ(IPEHR); 1151 error->instdone[ring->id] = I915_READ(INSTDONE); 1152 } 1153 1154 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue); 1155 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); 1156 error->seqno[ring->id] = ring->get_seqno(ring, false); 1157 error->acthd[ring->id] = intel_ring_get_active_head(ring); 1158 error->head[ring->id] = I915_READ_HEAD(ring); 1159 error->tail[ring->id] = I915_READ_TAIL(ring); 1160 error->ctl[ring->id] = I915_READ_CTL(ring); 1161 1162 error->cpu_ring_head[ring->id] = ring->head; 1163 error->cpu_ring_tail[ring->id] = ring->tail; 1164 } 1165 1166 static void i915_gem_record_rings(struct drm_device *dev, 1167 struct drm_i915_error_state *error) 1168 { 1169 struct drm_i915_private *dev_priv = dev->dev_private; 1170 struct intel_ring_buffer *ring; 1171 struct drm_i915_gem_request *request; 1172 int i, count; 1173 1174 for_each_ring(ring, dev_priv, i) { 1175 i915_record_ring_state(dev, error, ring); 1176 1177 error->ring[i].batchbuffer = 1178 i915_error_first_batchbuffer(dev_priv, ring); 1179 1180 error->ring[i].ringbuffer = 1181 i915_error_object_create(dev_priv, ring->obj); 1182 1183 count = 0; 1184 list_for_each_entry(request, &ring->request_list, list) 1185 count++; 1186 1187 error->ring[i].num_requests = count; 1188 error->ring[i].requests = 1189 kmalloc(count*sizeof(struct drm_i915_error_request), 1190 GFP_ATOMIC); 1191 if (error->ring[i].requests == NULL) { 1192 error->ring[i].num_requests = 0; 1193 continue; 1194 } 1195 1196 count = 0; 1197 list_for_each_entry(request, &ring->request_list, list) { 1198 struct drm_i915_error_request *erq; 1199 1200 erq = &error->ring[i].requests[count++]; 1201 erq->seqno = request->seqno; 1202 erq->jiffies = request->emitted_jiffies; 1203 erq->tail = request->tail; 1204 } 1205 } 1206 } 1207 1208 /** 1209 * i915_capture_error_state - capture an error record for later analysis 1210 * @dev: drm device 1211 * 1212 * Should be called when an error is detected (either a hang or an error 1213 * interrupt) to capture error state from the time of the error. Fills 1214 * out a structure which becomes available in debugfs for user level tools 1215 * to pick up. 1216 */ 1217 static void i915_capture_error_state(struct drm_device *dev) 1218 { 1219 struct drm_i915_private *dev_priv = dev->dev_private; 1220 struct drm_i915_gem_object *obj; 1221 struct drm_i915_error_state *error; 1222 unsigned long flags; 1223 int i, pipe; 1224 1225 spin_lock_irqsave(&dev_priv->error_lock, flags); 1226 error = dev_priv->first_error; 1227 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1228 if (error) 1229 return; 1230 1231 /* Account for pipe specific data like PIPE*STAT */ 1232 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1233 if (!error) { 1234 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1235 return; 1236 } 1237 1238 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", 1239 dev->primary->index); 1240 1241 kref_init(&error->ref); 1242 error->eir = I915_READ(EIR); 1243 error->pgtbl_er = I915_READ(PGTBL_ER); 1244 error->ccid = I915_READ(CCID); 1245 1246 if (HAS_PCH_SPLIT(dev)) 1247 error->ier = I915_READ(DEIER) | I915_READ(GTIER); 1248 else if (IS_VALLEYVIEW(dev)) 1249 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER); 1250 else if (IS_GEN2(dev)) 1251 error->ier = I915_READ16(IER); 1252 else 1253 error->ier = I915_READ(IER); 1254 1255 if (INTEL_INFO(dev)->gen >= 6) 1256 error->derrmr = I915_READ(DERRMR); 1257 1258 if (IS_VALLEYVIEW(dev)) 1259 error->forcewake = I915_READ(FORCEWAKE_VLV); 1260 else if (INTEL_INFO(dev)->gen >= 7) 1261 error->forcewake = I915_READ(FORCEWAKE_MT); 1262 else if (INTEL_INFO(dev)->gen == 6) 1263 error->forcewake = I915_READ(FORCEWAKE); 1264 1265 for_each_pipe(pipe) 1266 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 1267 1268 if (INTEL_INFO(dev)->gen >= 6) { 1269 error->error = I915_READ(ERROR_GEN6); 1270 error->done_reg = I915_READ(DONE_REG); 1271 } 1272 1273 if (INTEL_INFO(dev)->gen == 7) 1274 error->err_int = I915_READ(GEN7_ERR_INT); 1275 1276 i915_get_extra_instdone(dev, error->extra_instdone); 1277 1278 i915_gem_record_fences(dev, error); 1279 i915_gem_record_rings(dev, error); 1280 1281 /* Record buffers on the active and pinned lists. */ 1282 error->active_bo = NULL; 1283 error->pinned_bo = NULL; 1284 1285 i = 0; 1286 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 1287 i++; 1288 error->active_bo_count = i; 1289 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) 1290 if (obj->pin_count) 1291 i++; 1292 error->pinned_bo_count = i - error->active_bo_count; 1293 1294 error->active_bo = NULL; 1295 error->pinned_bo = NULL; 1296 if (i) { 1297 error->active_bo = kmalloc(sizeof(*error->active_bo)*i, 1298 GFP_ATOMIC); 1299 if (error->active_bo) 1300 error->pinned_bo = 1301 error->active_bo + error->active_bo_count; 1302 } 1303 1304 if (error->active_bo) 1305 error->active_bo_count = 1306 capture_active_bo(error->active_bo, 1307 error->active_bo_count, 1308 &dev_priv->mm.active_list); 1309 1310 if (error->pinned_bo) 1311 error->pinned_bo_count = 1312 capture_pinned_bo(error->pinned_bo, 1313 error->pinned_bo_count, 1314 &dev_priv->mm.bound_list); 1315 1316 do_gettimeofday(&error->time); 1317 1318 error->overlay = intel_overlay_capture_error_state(dev); 1319 error->display = intel_display_capture_error_state(dev); 1320 1321 spin_lock_irqsave(&dev_priv->error_lock, flags); 1322 if (dev_priv->first_error == NULL) { 1323 dev_priv->first_error = error; 1324 error = NULL; 1325 } 1326 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1327 1328 if (error) 1329 i915_error_state_free(&error->ref); 1330 } 1331 1332 void i915_destroy_error_state(struct drm_device *dev) 1333 { 1334 struct drm_i915_private *dev_priv = dev->dev_private; 1335 struct drm_i915_error_state *error; 1336 unsigned long flags; 1337 1338 spin_lock_irqsave(&dev_priv->error_lock, flags); 1339 error = dev_priv->first_error; 1340 dev_priv->first_error = NULL; 1341 spin_unlock_irqrestore(&dev_priv->error_lock, flags); 1342 1343 if (error) 1344 kref_put(&error->ref, i915_error_state_free); 1345 } 1346 #else 1347 #define i915_capture_error_state(x) 1348 #endif 1349 1350 static void i915_report_and_clear_eir(struct drm_device *dev) 1351 { 1352 struct drm_i915_private *dev_priv = dev->dev_private; 1353 uint32_t instdone[I915_NUM_INSTDONE_REG]; 1354 u32 eir = I915_READ(EIR); 1355 int pipe, i; 1356 1357 if (!eir) 1358 return; 1359 1360 printf("render error detected, EIR: 0x%08x\n", eir); 1361 1362 i915_get_extra_instdone(dev, instdone); 1363 1364 if (IS_G4X(dev)) { 1365 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 1366 u32 ipeir = I915_READ(IPEIR_I965); 1367 1368 printf(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 1369 printf(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 1370 for (i = 0; i < ARRAY_SIZE(instdone); i++) 1371 printf(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 1372 printf(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 1373 printf(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 1374 I915_WRITE(IPEIR_I965, ipeir); 1375 POSTING_READ(IPEIR_I965); 1376 } 1377 if (eir & GM45_ERROR_PAGE_TABLE) { 1378 u32 pgtbl_err = I915_READ(PGTBL_ER); 1379 printf("page table error\n"); 1380 printf(" PGTBL_ER: 0x%08x\n", pgtbl_err); 1381 I915_WRITE(PGTBL_ER, pgtbl_err); 1382 POSTING_READ(PGTBL_ER); 1383 } 1384 } 1385 1386 if (!IS_GEN2(dev)) { 1387 if (eir & I915_ERROR_PAGE_TABLE) { 1388 u32 pgtbl_err = I915_READ(PGTBL_ER); 1389 printf("page table error\n"); 1390 printf(" PGTBL_ER: 0x%08x\n", pgtbl_err); 1391 I915_WRITE(PGTBL_ER, pgtbl_err); 1392 POSTING_READ(PGTBL_ER); 1393 } 1394 } 1395 1396 if (eir & I915_ERROR_MEMORY_REFRESH) { 1397 printf("memory refresh error:\n"); 1398 for_each_pipe(pipe) 1399 printf("pipe %c stat: 0x%08x\n", 1400 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 1401 /* pipestat has already been acked */ 1402 } 1403 if (eir & I915_ERROR_INSTRUCTION) { 1404 printf("instruction error\n"); 1405 printf(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); 1406 for (i = 0; i < ARRAY_SIZE(instdone); i++) 1407 printf(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 1408 if (INTEL_INFO(dev)->gen < 4) { 1409 u32 ipeir = I915_READ(IPEIR); 1410 1411 printf(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); 1412 printf(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); 1413 printf(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); 1414 I915_WRITE(IPEIR, ipeir); 1415 POSTING_READ(IPEIR); 1416 } else { 1417 u32 ipeir = I915_READ(IPEIR_I965); 1418 1419 printf(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 1420 printf(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 1421 printf(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 1422 printf(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 1423 I915_WRITE(IPEIR_I965, ipeir); 1424 POSTING_READ(IPEIR_I965); 1425 } 1426 } 1427 1428 I915_WRITE(EIR, eir); 1429 POSTING_READ(EIR); 1430 eir = I915_READ(EIR); 1431 if (eir) { 1432 /* 1433 * some errors might have become stuck, 1434 * mask them. 1435 */ 1436 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 1437 I915_WRITE(EMR, I915_READ(EMR) | eir); 1438 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 1439 } 1440 } 1441 1442 /** 1443 * i915_handle_error - handle an error interrupt 1444 * @dev: drm device 1445 * 1446 * Do some basic checking of regsiter state at error interrupt time and 1447 * dump it to the syslog. Also call i915_capture_error_state() to make 1448 * sure we get a record and make it available in debugfs. Fire a uevent 1449 * so userspace knows something bad happened (should trigger collection 1450 * of a ring dump etc.). 1451 */ 1452 void i915_handle_error(struct drm_device *dev, bool wedged) 1453 { 1454 struct drm_i915_private *dev_priv = dev->dev_private; 1455 struct intel_ring_buffer *ring; 1456 int i; 1457 1458 i915_capture_error_state(dev); 1459 i915_report_and_clear_eir(dev); 1460 1461 if (wedged) { 1462 // INIT_COMPLETION(dev_priv->error_completion); 1463 atomic_set(&dev_priv->mm.wedged, 1); 1464 1465 /* 1466 * Wakeup waiting processes so they don't hang 1467 */ 1468 for_each_ring(ring, dev_priv, i) 1469 wakeup(ring); 1470 } 1471 1472 task_add(systq, &dev_priv->error_task); 1473 } 1474 1475 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 1476 { 1477 drm_i915_private_t *dev_priv = dev->dev_private; 1478 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1480 struct drm_i915_gem_object *obj; 1481 struct intel_unpin_work *work; 1482 bool stall_detected; 1483 1484 /* Ignore early vblank irqs */ 1485 if (intel_crtc == NULL) 1486 return; 1487 1488 mtx_enter(&dev->event_lock); 1489 work = intel_crtc->unpin_work; 1490 1491 if (work == NULL || 1492 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || 1493 !work->enable_stall_check) { 1494 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 1495 mtx_leave(&dev->event_lock); 1496 return; 1497 } 1498 1499 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 1500 obj = work->pending_flip_obj; 1501 if (INTEL_INFO(dev)->gen >= 4) { 1502 int dspsurf = DSPSURF(intel_crtc->plane); 1503 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == 1504 obj->gtt_offset; 1505 } else { 1506 int dspaddr = DSPADDR(intel_crtc->plane); 1507 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 1508 crtc->y * crtc->fb->pitches[0] + 1509 crtc->x * crtc->fb->bits_per_pixel/8); 1510 } 1511 1512 mtx_leave(&dev->event_lock); 1513 1514 if (stall_detected) { 1515 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 1516 intel_prepare_page_flip(dev, intel_crtc->plane); 1517 } 1518 } 1519 1520 /* Called from drm generic code, passed 'crtc' which 1521 * we use as a pipe index 1522 */ 1523 static int i915_enable_vblank(struct drm_device *dev, int pipe) 1524 { 1525 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1526 1527 if (!i915_pipe_enabled(dev, pipe)) 1528 return -EINVAL; 1529 1530 mtx_enter(&dev_priv->irq_lock); 1531 if (INTEL_INFO(dev)->gen >= 4) 1532 i915_enable_pipestat(dev_priv, pipe, 1533 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1534 else 1535 i915_enable_pipestat(dev_priv, pipe, 1536 PIPE_VBLANK_INTERRUPT_ENABLE); 1537 1538 /* maintain vblank delivery even in deep C-states */ 1539 if (dev_priv->info->gen == 3) 1540 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); 1541 mtx_leave(&dev_priv->irq_lock); 1542 1543 return 0; 1544 } 1545 1546 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 1547 { 1548 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1549 1550 if (!i915_pipe_enabled(dev, pipe)) 1551 return -EINVAL; 1552 1553 mtx_enter(&dev_priv->irq_lock); 1554 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1555 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1556 mtx_leave(&dev_priv->irq_lock); 1557 1558 return 0; 1559 } 1560 1561 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1562 { 1563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1564 1565 if (!i915_pipe_enabled(dev, pipe)) 1566 return -EINVAL; 1567 1568 mtx_enter(&dev_priv->irq_lock); 1569 ironlake_enable_display_irq(dev_priv, 1570 DE_PIPEA_VBLANK_IVB << (5 * pipe)); 1571 mtx_leave(&dev_priv->irq_lock); 1572 1573 return 0; 1574 } 1575 1576 static int valleyview_enable_vblank(struct drm_device *dev, int pipe) 1577 { 1578 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1579 u32 imr; 1580 1581 if (!i915_pipe_enabled(dev, pipe)) 1582 return -EINVAL; 1583 1584 mtx_enter(&dev_priv->irq_lock); 1585 imr = I915_READ(VLV_IMR); 1586 if (pipe == 0) 1587 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 1588 else 1589 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1590 I915_WRITE(VLV_IMR, imr); 1591 i915_enable_pipestat(dev_priv, pipe, 1592 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1593 mtx_leave(&dev_priv->irq_lock); 1594 1595 return 0; 1596 } 1597 1598 /* Called from drm generic code, passed 'crtc' which 1599 * we use as a pipe index 1600 */ 1601 static void i915_disable_vblank(struct drm_device *dev, int pipe) 1602 { 1603 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1604 1605 mtx_enter(&dev_priv->irq_lock); 1606 if (dev_priv->info->gen == 3) 1607 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); 1608 1609 i915_disable_pipestat(dev_priv, pipe, 1610 PIPE_VBLANK_INTERRUPT_ENABLE | 1611 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1612 mtx_leave(&dev_priv->irq_lock); 1613 } 1614 1615 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 1616 { 1617 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1618 1619 mtx_enter(&dev_priv->irq_lock); 1620 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1621 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1622 mtx_leave(&dev_priv->irq_lock); 1623 } 1624 1625 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1626 { 1627 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1628 1629 mtx_enter(&dev_priv->irq_lock); 1630 ironlake_disable_display_irq(dev_priv, 1631 DE_PIPEA_VBLANK_IVB << (pipe * 5)); 1632 mtx_leave(&dev_priv->irq_lock); 1633 } 1634 1635 static void valleyview_disable_vblank(struct drm_device *dev, int pipe) 1636 { 1637 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1638 u32 imr; 1639 1640 mtx_enter(&dev_priv->irq_lock); 1641 i915_disable_pipestat(dev_priv, pipe, 1642 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1643 imr = I915_READ(VLV_IMR); 1644 if (pipe == 0) 1645 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 1646 else 1647 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1648 I915_WRITE(VLV_IMR, imr); 1649 mtx_leave(&dev_priv->irq_lock); 1650 } 1651 1652 static u32 1653 ring_last_seqno(struct intel_ring_buffer *ring) 1654 { 1655 return list_entry(ring->request_list.prev, 1656 struct drm_i915_gem_request, list)->seqno; 1657 } 1658 1659 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) 1660 { 1661 if (list_empty(&ring->request_list) || 1662 i915_seqno_passed(ring->get_seqno(ring, false), 1663 ring_last_seqno(ring))) { 1664 /* Issue a wake-up to catch stuck h/w. */ 1665 #ifdef notyet 1666 if (wakeup(ring) > 0) { 1667 DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 1668 ring->name); 1669 *err = true; 1670 } 1671 #else 1672 wakeup(ring); 1673 #endif 1674 return true; 1675 } 1676 return false; 1677 } 1678 1679 static bool kick_ring(struct intel_ring_buffer *ring) 1680 { 1681 struct drm_device *dev = ring->dev; 1682 struct drm_i915_private *dev_priv = dev->dev_private; 1683 u32 tmp = I915_READ_CTL(ring); 1684 if (tmp & RING_WAIT) { 1685 DRM_ERROR("Kicking stuck wait on %s\n", 1686 ring->name); 1687 I915_WRITE_CTL(ring, tmp); 1688 return true; 1689 } 1690 return false; 1691 } 1692 1693 static bool i915_hangcheck_hung(struct drm_device *dev) 1694 { 1695 drm_i915_private_t *dev_priv = dev->dev_private; 1696 1697 if (dev_priv->hangcheck_count++ > 1) { 1698 bool hung = true; 1699 1700 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 1701 i915_handle_error(dev, true); 1702 1703 if (!IS_GEN2(dev)) { 1704 struct intel_ring_buffer *ring; 1705 int i; 1706 1707 /* Is the chip hanging on a WAIT_FOR_EVENT? 1708 * If so we can simply poke the RB_WAIT bit 1709 * and break the hang. This should work on 1710 * all but the second generation chipsets. 1711 */ 1712 for_each_ring(ring, dev_priv, i) 1713 hung &= !kick_ring(ring); 1714 } 1715 1716 return hung; 1717 } 1718 1719 return false; 1720 } 1721 1722 /** 1723 * This is called when the chip hasn't reported back with completed 1724 * batchbuffers in a long time. The first time this is called we simply record 1725 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1726 * again, we assume the chip is wedged and try to fix it. 1727 */ 1728 void i915_hangcheck_elapsed(void *arg) 1729 { 1730 drm_i915_private_t *dev_priv = arg; 1731 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 1732 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG]; 1733 struct intel_ring_buffer *ring; 1734 bool err = false, idle; 1735 int i; 1736 1737 if (!i915_enable_hangcheck) 1738 return; 1739 1740 memset(acthd, 0, sizeof(acthd)); 1741 idle = true; 1742 for_each_ring(ring, dev_priv, i) { 1743 idle &= i915_hangcheck_ring_idle(ring, &err); 1744 acthd[i] = intel_ring_get_active_head(ring); 1745 } 1746 1747 /* If all work is done then ACTHD clearly hasn't advanced. */ 1748 if (idle) { 1749 if (err) { 1750 if (i915_hangcheck_hung(dev)) 1751 return; 1752 1753 goto repeat; 1754 } 1755 1756 dev_priv->hangcheck_count = 0; 1757 return; 1758 } 1759 1760 i915_get_extra_instdone(dev, instdone); 1761 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 && 1762 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) { 1763 if (i915_hangcheck_hung(dev)) 1764 return; 1765 } else { 1766 dev_priv->hangcheck_count = 0; 1767 1768 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd)); 1769 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone)); 1770 } 1771 1772 repeat: 1773 /* Reset timer case chip hangs without another request being added */ 1774 timeout_add_msec(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD); 1775 } 1776 1777 /* drm_dma.h hooks 1778 */ 1779 static void ironlake_irq_preinstall(struct drm_device *dev) 1780 { 1781 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1782 1783 // atomic_set(&dev_priv->irq_received, 0); 1784 1785 I915_WRITE(HWSTAM, 0xeffe); 1786 1787 /* XXX hotplug from PCH */ 1788 1789 I915_WRITE(DEIMR, 0xffffffff); 1790 I915_WRITE(DEIER, 0x0); 1791 POSTING_READ(DEIER); 1792 1793 /* and GT */ 1794 I915_WRITE(GTIMR, 0xffffffff); 1795 I915_WRITE(GTIER, 0x0); 1796 POSTING_READ(GTIER); 1797 1798 /* south display irq */ 1799 I915_WRITE(SDEIMR, 0xffffffff); 1800 I915_WRITE(SDEIER, 0x0); 1801 POSTING_READ(SDEIER); 1802 } 1803 1804 static void valleyview_irq_preinstall(struct drm_device *dev) 1805 { 1806 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1807 int pipe; 1808 1809 // atomic_set(&dev_priv->irq_received, 0); 1810 1811 /* VLV magic */ 1812 I915_WRITE(VLV_IMR, 0); 1813 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); 1814 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); 1815 I915_WRITE(RING_IMR(BLT_RING_BASE), 0); 1816 1817 /* and GT */ 1818 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1819 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1820 I915_WRITE(GTIMR, 0xffffffff); 1821 I915_WRITE(GTIER, 0x0); 1822 POSTING_READ(GTIER); 1823 1824 I915_WRITE(DPINVGTT, 0xff); 1825 1826 I915_WRITE(PORT_HOTPLUG_EN, 0); 1827 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1828 for_each_pipe(pipe) 1829 I915_WRITE(PIPESTAT(pipe), 0xffff); 1830 I915_WRITE(VLV_IIR, 0xffffffff); 1831 I915_WRITE(VLV_IMR, 0xffffffff); 1832 I915_WRITE(VLV_IER, 0x0); 1833 POSTING_READ(VLV_IER); 1834 } 1835 1836 /* 1837 * Enable digital hotplug on the PCH, and configure the DP short pulse 1838 * duration to 2ms (which is the minimum in the Display Port spec) 1839 * 1840 * This register is the same on all known PCH chips. 1841 */ 1842 1843 static void ironlake_enable_pch_hotplug(struct drm_device *dev) 1844 { 1845 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1846 u32 hotplug; 1847 1848 hotplug = I915_READ(PCH_PORT_HOTPLUG); 1849 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 1850 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 1851 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 1852 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 1853 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 1854 } 1855 1856 static int ironlake_irq_postinstall(struct drm_device *dev) 1857 { 1858 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1859 /* enable kind of interrupts always enabled */ 1860 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1861 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1862 u32 render_irqs; 1863 u32 hotplug_mask; 1864 1865 dev_priv->irq_mask = ~display_mask; 1866 1867 /* should always can generate irq */ 1868 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1869 I915_WRITE(DEIMR, dev_priv->irq_mask); 1870 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); 1871 POSTING_READ(DEIER); 1872 1873 dev_priv->gt_irq_mask = ~0; 1874 1875 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1876 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1877 1878 if (IS_GEN6(dev)) 1879 render_irqs = 1880 GT_USER_INTERRUPT | 1881 GEN6_BSD_USER_INTERRUPT | 1882 GEN6_BLITTER_USER_INTERRUPT; 1883 else 1884 render_irqs = 1885 GT_USER_INTERRUPT | 1886 GT_PIPE_NOTIFY | 1887 GT_BSD_USER_INTERRUPT; 1888 I915_WRITE(GTIER, render_irqs); 1889 POSTING_READ(GTIER); 1890 1891 if (HAS_PCH_CPT(dev)) { 1892 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1893 SDE_PORTB_HOTPLUG_CPT | 1894 SDE_PORTC_HOTPLUG_CPT | 1895 SDE_PORTD_HOTPLUG_CPT); 1896 } else { 1897 hotplug_mask = (SDE_CRT_HOTPLUG | 1898 SDE_PORTB_HOTPLUG | 1899 SDE_PORTC_HOTPLUG | 1900 SDE_PORTD_HOTPLUG | 1901 SDE_AUX_MASK); 1902 } 1903 1904 dev_priv->pch_irq_mask = ~hotplug_mask; 1905 1906 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1907 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1908 I915_WRITE(SDEIER, hotplug_mask); 1909 POSTING_READ(SDEIER); 1910 1911 ironlake_enable_pch_hotplug(dev); 1912 1913 if (IS_IRONLAKE_M(dev)) { 1914 /* Clear & enable PCU event interrupts */ 1915 I915_WRITE(DEIIR, DE_PCU_EVENT); 1916 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); 1917 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 1918 } 1919 1920 return 0; 1921 } 1922 1923 static int ivybridge_irq_postinstall(struct drm_device *dev) 1924 { 1925 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1926 /* enable kind of interrupts always enabled */ 1927 u32 display_mask = 1928 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | 1929 DE_PLANEC_FLIP_DONE_IVB | 1930 DE_PLANEB_FLIP_DONE_IVB | 1931 DE_PLANEA_FLIP_DONE_IVB; 1932 u32 render_irqs; 1933 u32 hotplug_mask; 1934 1935 dev_priv->irq_mask = ~display_mask; 1936 1937 /* should always can generate irq */ 1938 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1939 I915_WRITE(DEIMR, dev_priv->irq_mask); 1940 I915_WRITE(DEIER, 1941 display_mask | 1942 DE_PIPEC_VBLANK_IVB | 1943 DE_PIPEB_VBLANK_IVB | 1944 DE_PIPEA_VBLANK_IVB); 1945 POSTING_READ(DEIER); 1946 1947 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 1948 1949 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1950 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1951 1952 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | 1953 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT; 1954 I915_WRITE(GTIER, render_irqs); 1955 POSTING_READ(GTIER); 1956 1957 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1958 SDE_PORTB_HOTPLUG_CPT | 1959 SDE_PORTC_HOTPLUG_CPT | 1960 SDE_PORTD_HOTPLUG_CPT); 1961 dev_priv->pch_irq_mask = ~hotplug_mask; 1962 1963 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1964 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1965 I915_WRITE(SDEIER, hotplug_mask); 1966 POSTING_READ(SDEIER); 1967 1968 ironlake_enable_pch_hotplug(dev); 1969 1970 return 0; 1971 } 1972 1973 static int valleyview_irq_postinstall(struct drm_device *dev) 1974 { 1975 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1976 u32 enable_mask; 1977 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1978 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV; 1979 u32 render_irqs; 1980 u16 msid; 1981 1982 enable_mask = I915_DISPLAY_PORT_INTERRUPT; 1983 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 1984 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 1985 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 1986 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1987 1988 /* 1989 *Leave vblank interrupts masked initially. enable/disable will 1990 * toggle them based on usage. 1991 */ 1992 dev_priv->irq_mask = (~enable_mask) | 1993 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 1994 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 1995 1996 dev_priv->pipestat[0] = 0; 1997 dev_priv->pipestat[1] = 0; 1998 1999 /* Hack for broken MSIs on VLV */ 2000 pci_conf_write(dev_priv->pc, dev_priv->tag, 0x94, 0xfee00000); 2001 msid = pci_conf_read(dev_priv->pc, dev_priv->tag, 0x98); 2002 msid &= 0xff; /* mask out delivery bits */ 2003 msid |= (1<<14); 2004 pci_conf_write(dev_priv->pc, dev_priv->tag, 0x98, msid); 2005 2006 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 2007 I915_WRITE(VLV_IER, enable_mask); 2008 I915_WRITE(VLV_IIR, 0xffffffff); 2009 I915_WRITE(PIPESTAT(0), 0xffff); 2010 I915_WRITE(PIPESTAT(1), 0xffff); 2011 POSTING_READ(VLV_IER); 2012 2013 i915_enable_pipestat(dev_priv, 0, pipestat_enable); 2014 i915_enable_pipestat(dev_priv, 1, pipestat_enable); 2015 2016 I915_WRITE(VLV_IIR, 0xffffffff); 2017 I915_WRITE(VLV_IIR, 0xffffffff); 2018 2019 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2020 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 2021 2022 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT | 2023 GEN6_BLITTER_USER_INTERRUPT; 2024 I915_WRITE(GTIER, render_irqs); 2025 POSTING_READ(GTIER); 2026 2027 /* ack & enable invalid PTE error interrupts */ 2028 #if 0 /* FIXME: add support to irq handler for checking these bits */ 2029 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); 2030 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); 2031 #endif 2032 2033 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 2034 /* Note HDMI and DP share bits */ 2035 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2036 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2037 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2038 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2039 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2040 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2041 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) 2042 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2043 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) 2044 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2045 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2046 hotplug_en |= CRT_HOTPLUG_INT_EN; 2047 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2048 } 2049 2050 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2051 2052 return 0; 2053 } 2054 2055 static void valleyview_irq_uninstall(struct drm_device *dev) 2056 { 2057 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2058 int pipe; 2059 2060 if (!dev_priv) 2061 return; 2062 2063 for_each_pipe(pipe) 2064 I915_WRITE(PIPESTAT(pipe), 0xffff); 2065 2066 I915_WRITE(HWSTAM, 0xffffffff); 2067 I915_WRITE(PORT_HOTPLUG_EN, 0); 2068 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2069 for_each_pipe(pipe) 2070 I915_WRITE(PIPESTAT(pipe), 0xffff); 2071 I915_WRITE(VLV_IIR, 0xffffffff); 2072 I915_WRITE(VLV_IMR, 0xffffffff); 2073 I915_WRITE(VLV_IER, 0x0); 2074 POSTING_READ(VLV_IER); 2075 } 2076 2077 static void ironlake_irq_uninstall(struct drm_device *dev) 2078 { 2079 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2080 2081 if (!dev_priv) 2082 return; 2083 2084 I915_WRITE(HWSTAM, 0xffffffff); 2085 2086 I915_WRITE(DEIMR, 0xffffffff); 2087 I915_WRITE(DEIER, 0x0); 2088 I915_WRITE(DEIIR, I915_READ(DEIIR)); 2089 2090 I915_WRITE(GTIMR, 0xffffffff); 2091 I915_WRITE(GTIER, 0x0); 2092 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2093 2094 I915_WRITE(SDEIMR, 0xffffffff); 2095 I915_WRITE(SDEIER, 0x0); 2096 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2097 } 2098 2099 static void i8xx_irq_preinstall(struct drm_device * dev) 2100 { 2101 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2102 int pipe; 2103 2104 // atomic_set(&dev_priv->irq_received, 0); 2105 2106 for_each_pipe(pipe) 2107 I915_WRITE(PIPESTAT(pipe), 0); 2108 I915_WRITE16(IMR, 0xffff); 2109 I915_WRITE16(IER, 0x0); 2110 POSTING_READ16(IER); 2111 } 2112 2113 static int i8xx_irq_postinstall(struct drm_device *dev) 2114 { 2115 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2116 2117 dev_priv->pipestat[0] = 0; 2118 dev_priv->pipestat[1] = 0; 2119 2120 I915_WRITE16(EMR, 2121 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2122 2123 /* Unmask the interrupts that we always want on. */ 2124 dev_priv->irq_mask = 2125 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2126 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2127 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2128 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2129 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2130 I915_WRITE16(IMR, dev_priv->irq_mask); 2131 2132 I915_WRITE16(IER, 2133 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2134 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2135 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 2136 I915_USER_INTERRUPT); 2137 POSTING_READ16(IER); 2138 2139 return 0; 2140 } 2141 2142 static int i8xx_intr(void *arg) 2143 { 2144 drm_i915_private_t *dev_priv = arg; 2145 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 2146 u16 iir, new_iir; 2147 u32 pipe_stats[2]; 2148 int irq_received; 2149 int pipe; 2150 u16 flip_mask = 2151 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2152 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2153 2154 // atomic_inc(&dev_priv->irq_received); 2155 2156 iir = I915_READ16(IIR); 2157 if (iir == 0) 2158 return IRQ_NONE; 2159 2160 while (iir & ~flip_mask) { 2161 /* Can't rely on pipestat interrupt bit in iir as it might 2162 * have been cleared after the pipestat interrupt was received. 2163 * It doesn't set the bit in iir again, but it still produces 2164 * interrupts (for non-MSI). 2165 */ 2166 mtx_enter(&dev_priv->irq_lock); 2167 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2168 i915_handle_error(dev, false); 2169 2170 for_each_pipe(pipe) { 2171 int reg = PIPESTAT(pipe); 2172 pipe_stats[pipe] = I915_READ(reg); 2173 2174 /* 2175 * Clear the PIPE*STAT regs before the IIR 2176 */ 2177 if (pipe_stats[pipe] & 0x8000ffff) { 2178 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2179 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2180 pipe_name(pipe)); 2181 I915_WRITE(reg, pipe_stats[pipe]); 2182 irq_received = 1; 2183 } 2184 } 2185 mtx_leave(&dev_priv->irq_lock); 2186 2187 I915_WRITE16(IIR, iir & ~flip_mask); 2188 new_iir = I915_READ16(IIR); /* Flush posted writes */ 2189 2190 // i915_update_dri1_breadcrumb(dev); 2191 2192 if (iir & I915_USER_INTERRUPT) 2193 notify_ring(dev, &dev_priv->ring[RCS]); 2194 2195 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && 2196 drm_handle_vblank(dev, 0)) { 2197 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 2198 intel_prepare_page_flip(dev, 0); 2199 intel_finish_page_flip(dev, 0); 2200 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT; 2201 } 2202 } 2203 2204 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && 2205 drm_handle_vblank(dev, 1)) { 2206 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 2207 intel_prepare_page_flip(dev, 1); 2208 intel_finish_page_flip(dev, 1); 2209 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2210 } 2211 } 2212 2213 iir = new_iir; 2214 } 2215 2216 return IRQ_HANDLED; 2217 } 2218 2219 static void i8xx_irq_uninstall(struct drm_device * dev) 2220 { 2221 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2222 int pipe; 2223 2224 for_each_pipe(pipe) { 2225 /* Clear enable bits; then clear status bits */ 2226 I915_WRITE(PIPESTAT(pipe), 0); 2227 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 2228 } 2229 I915_WRITE16(IMR, 0xffff); 2230 I915_WRITE16(IER, 0x0); 2231 I915_WRITE16(IIR, I915_READ16(IIR)); 2232 } 2233 2234 static void i915_irq_preinstall(struct drm_device * dev) 2235 { 2236 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2237 int pipe; 2238 2239 // atomic_set(&dev_priv->irq_received, 0); 2240 2241 if (I915_HAS_HOTPLUG(dev)) { 2242 I915_WRITE(PORT_HOTPLUG_EN, 0); 2243 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2244 } 2245 2246 I915_WRITE16(HWSTAM, 0xeffe); 2247 for_each_pipe(pipe) 2248 I915_WRITE(PIPESTAT(pipe), 0); 2249 I915_WRITE(IMR, 0xffffffff); 2250 I915_WRITE(IER, 0x0); 2251 POSTING_READ(IER); 2252 } 2253 2254 static int i915_irq_postinstall(struct drm_device *dev) 2255 { 2256 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2257 u32 enable_mask; 2258 2259 dev_priv->pipestat[0] = 0; 2260 dev_priv->pipestat[1] = 0; 2261 2262 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 2263 2264 /* Unmask the interrupts that we always want on. */ 2265 dev_priv->irq_mask = 2266 ~(I915_ASLE_INTERRUPT | 2267 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2268 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2269 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2270 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2271 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2272 2273 enable_mask = 2274 I915_ASLE_INTERRUPT | 2275 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2276 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2277 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 2278 I915_USER_INTERRUPT; 2279 2280 if (I915_HAS_HOTPLUG(dev)) { 2281 /* Enable in IER... */ 2282 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 2283 /* and unmask in IMR */ 2284 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 2285 } 2286 2287 I915_WRITE(IMR, dev_priv->irq_mask); 2288 I915_WRITE(IER, enable_mask); 2289 POSTING_READ(IER); 2290 2291 if (I915_HAS_HOTPLUG(dev)) { 2292 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 2293 2294 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2295 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2296 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2297 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2298 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2299 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2300 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) 2301 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2302 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) 2303 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2304 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2305 hotplug_en |= CRT_HOTPLUG_INT_EN; 2306 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2307 } 2308 2309 /* Ignore TV since it's buggy */ 2310 2311 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2312 } 2313 2314 intel_opregion_enable_asle(dev); 2315 2316 return 0; 2317 } 2318 2319 static int i915_intr(void *arg) 2320 { 2321 drm_i915_private_t *dev_priv = arg; 2322 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 2323 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 2324 u32 flip_mask = 2325 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2326 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 2327 u32 flip[2] = { 2328 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT, 2329 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT 2330 }; 2331 int pipe, ret = IRQ_NONE; 2332 2333 // atomic_inc(&dev_priv->irq_received); 2334 2335 iir = I915_READ(IIR); 2336 do { 2337 bool irq_received = (iir & ~flip_mask) != 0; 2338 bool blc_event = false; 2339 2340 /* Can't rely on pipestat interrupt bit in iir as it might 2341 * have been cleared after the pipestat interrupt was received. 2342 * It doesn't set the bit in iir again, but it still produces 2343 * interrupts (for non-MSI). 2344 */ 2345 mtx_enter(&dev_priv->irq_lock); 2346 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2347 i915_handle_error(dev, false); 2348 2349 for_each_pipe(pipe) { 2350 int reg = PIPESTAT(pipe); 2351 pipe_stats[pipe] = I915_READ(reg); 2352 2353 /* Clear the PIPE*STAT regs before the IIR */ 2354 if (pipe_stats[pipe] & 0x8000ffff) { 2355 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2356 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2357 pipe_name(pipe)); 2358 I915_WRITE(reg, pipe_stats[pipe]); 2359 irq_received = true; 2360 } 2361 } 2362 mtx_leave(&dev_priv->irq_lock); 2363 2364 if (!irq_received) 2365 break; 2366 2367 /* Consume port. Then clear IIR or we'll miss events */ 2368 if ((I915_HAS_HOTPLUG(dev)) && 2369 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 2370 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 2371 2372 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2373 hotplug_status); 2374 if (hotplug_status & dev_priv->hotplug_supported_mask) 2375 task_add(systq, &dev_priv->hotplug_task); 2376 2377 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 2378 POSTING_READ(PORT_HOTPLUG_STAT); 2379 } 2380 2381 I915_WRITE(IIR, iir & ~flip_mask); 2382 new_iir = I915_READ(IIR); /* Flush posted writes */ 2383 2384 if (iir & I915_USER_INTERRUPT) 2385 notify_ring(dev, &dev_priv->ring[RCS]); 2386 2387 for_each_pipe(pipe) { 2388 int plane = pipe; 2389 if (IS_MOBILE(dev)) 2390 plane = !plane; 2391 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 2392 drm_handle_vblank(dev, pipe)) { 2393 if (iir & flip[plane]) { 2394 intel_prepare_page_flip(dev, plane); 2395 intel_finish_page_flip(dev, pipe); 2396 flip_mask &= ~flip[plane]; 2397 } 2398 } 2399 2400 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 2401 blc_event = true; 2402 } 2403 2404 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 2405 intel_opregion_asle_intr(dev); 2406 2407 /* With MSI, interrupts are only generated when iir 2408 * transitions from zero to nonzero. If another bit got 2409 * set while we were handling the existing iir bits, then 2410 * we would never get another interrupt. 2411 * 2412 * This is fine on non-MSI as well, as if we hit this path 2413 * we avoid exiting the interrupt handler only to generate 2414 * another one. 2415 * 2416 * Note that for MSI this could cause a stray interrupt report 2417 * if an interrupt landed in the time between writing IIR and 2418 * the posting read. This should be rare enough to never 2419 * trigger the 99% of 100,000 interrupts test for disabling 2420 * stray interrupts. 2421 */ 2422 ret = IRQ_HANDLED; 2423 iir = new_iir; 2424 } while (iir & ~flip_mask); 2425 2426 // i915_update_dri1_breadcrumb(dev); 2427 2428 return ret; 2429 } 2430 2431 static void i915_irq_uninstall(struct drm_device * dev) 2432 { 2433 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2434 int pipe; 2435 2436 if (I915_HAS_HOTPLUG(dev)) { 2437 I915_WRITE(PORT_HOTPLUG_EN, 0); 2438 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2439 } 2440 2441 I915_WRITE16(HWSTAM, 0xffff); 2442 for_each_pipe(pipe) { 2443 /* Clear enable bits; then clear status bits */ 2444 I915_WRITE(PIPESTAT(pipe), 0); 2445 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 2446 } 2447 I915_WRITE(IMR, 0xffffffff); 2448 I915_WRITE(IER, 0x0); 2449 2450 I915_WRITE(IIR, I915_READ(IIR)); 2451 } 2452 2453 static void i965_irq_preinstall(struct drm_device * dev) 2454 { 2455 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2456 int pipe; 2457 2458 // atomic_set(&dev_priv->irq_received, 0); 2459 2460 I915_WRITE(PORT_HOTPLUG_EN, 0); 2461 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2462 2463 I915_WRITE(HWSTAM, 0xeffe); 2464 for_each_pipe(pipe) 2465 I915_WRITE(PIPESTAT(pipe), 0); 2466 I915_WRITE(IMR, 0xffffffff); 2467 I915_WRITE(IER, 0x0); 2468 POSTING_READ(IER); 2469 } 2470 2471 static int i965_irq_postinstall(struct drm_device *dev) 2472 { 2473 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2474 u32 hotplug_en; 2475 u32 enable_mask; 2476 u32 error_mask; 2477 2478 /* Unmask the interrupts that we always want on. */ 2479 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | 2480 I915_DISPLAY_PORT_INTERRUPT | 2481 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2482 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2483 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 2484 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 2485 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2486 2487 enable_mask = ~dev_priv->irq_mask; 2488 enable_mask |= I915_USER_INTERRUPT; 2489 2490 if (IS_G4X(dev)) 2491 enable_mask |= I915_BSD_USER_INTERRUPT; 2492 2493 dev_priv->pipestat[0] = 0; 2494 dev_priv->pipestat[1] = 0; 2495 2496 /* 2497 * Enable some error detection, note the instruction error mask 2498 * bit is reserved, so we leave it masked. 2499 */ 2500 if (IS_G4X(dev)) { 2501 error_mask = ~(GM45_ERROR_PAGE_TABLE | 2502 GM45_ERROR_MEM_PRIV | 2503 GM45_ERROR_CP_PRIV | 2504 I915_ERROR_MEMORY_REFRESH); 2505 } else { 2506 error_mask = ~(I915_ERROR_PAGE_TABLE | 2507 I915_ERROR_MEMORY_REFRESH); 2508 } 2509 I915_WRITE(EMR, error_mask); 2510 2511 I915_WRITE(IMR, dev_priv->irq_mask); 2512 I915_WRITE(IER, enable_mask); 2513 POSTING_READ(IER); 2514 2515 /* Note HDMI and DP share hotplug bits */ 2516 hotplug_en = 0; 2517 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 2518 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 2519 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 2520 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 2521 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 2522 hotplug_en |= HDMID_HOTPLUG_INT_EN; 2523 if (IS_G4X(dev)) { 2524 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X) 2525 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2526 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X) 2527 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2528 } else { 2529 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965) 2530 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 2531 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965) 2532 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 2533 } 2534 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 2535 hotplug_en |= CRT_HOTPLUG_INT_EN; 2536 2537 /* Programming the CRT detection parameters tends 2538 to generate a spurious hotplug event about three 2539 seconds later. So just do it once. 2540 */ 2541 if (IS_G4X(dev)) 2542 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 2543 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 2544 } 2545 2546 /* Ignore TV since it's buggy */ 2547 2548 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 2549 2550 intel_opregion_enable_asle(dev); 2551 2552 return 0; 2553 } 2554 2555 static int i965_intr(void *arg) 2556 { 2557 drm_i915_private_t *dev_priv = arg; 2558 struct drm_device *dev = (struct drm_device *)dev_priv->drmdev; 2559 u32 iir, new_iir; 2560 u32 pipe_stats[I915_MAX_PIPES]; 2561 int irq_received; 2562 int ret = IRQ_NONE, pipe; 2563 2564 // atomic_inc(&dev_priv->irq_received); 2565 2566 iir = I915_READ(IIR); 2567 2568 for (;;) { 2569 bool blc_event = false; 2570 2571 irq_received = iir != 0; 2572 2573 /* Can't rely on pipestat interrupt bit in iir as it might 2574 * have been cleared after the pipestat interrupt was received. 2575 * It doesn't set the bit in iir again, but it still produces 2576 * interrupts (for non-MSI). 2577 */ 2578 mtx_enter(&dev_priv->irq_lock); 2579 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 2580 i915_handle_error(dev, false); 2581 2582 for_each_pipe(pipe) { 2583 int reg = PIPESTAT(pipe); 2584 pipe_stats[pipe] = I915_READ(reg); 2585 2586 /* 2587 * Clear the PIPE*STAT regs before the IIR 2588 */ 2589 if (pipe_stats[pipe] & 0x8000ffff) { 2590 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 2591 DRM_DEBUG_DRIVER("pipe %c underrun\n", 2592 pipe_name(pipe)); 2593 I915_WRITE(reg, pipe_stats[pipe]); 2594 irq_received = 1; 2595 } 2596 } 2597 mtx_leave(&dev_priv->irq_lock); 2598 2599 if (!irq_received) 2600 break; 2601 2602 ret = IRQ_HANDLED; 2603 2604 /* Consume port. Then clear IIR or we'll miss events */ 2605 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 2606 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 2607 2608 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 2609 hotplug_status); 2610 if (hotplug_status & dev_priv->hotplug_supported_mask) 2611 task_add(systq, &dev_priv->hotplug_task); 2612 2613 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 2614 I915_READ(PORT_HOTPLUG_STAT); 2615 } 2616 2617 I915_WRITE(IIR, iir); 2618 new_iir = I915_READ(IIR); /* Flush posted writes */ 2619 2620 if (iir & I915_USER_INTERRUPT) 2621 notify_ring(dev, &dev_priv->ring[RCS]); 2622 if (iir & I915_BSD_USER_INTERRUPT) 2623 notify_ring(dev, &dev_priv->ring[VCS]); 2624 2625 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) 2626 intel_prepare_page_flip(dev, 0); 2627 2628 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) 2629 intel_prepare_page_flip(dev, 1); 2630 2631 for_each_pipe(pipe) { 2632 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 2633 drm_handle_vblank(dev, pipe)) { 2634 i915_pageflip_stall_check(dev, pipe); 2635 intel_finish_page_flip(dev, pipe); 2636 } 2637 2638 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 2639 blc_event = true; 2640 } 2641 2642 2643 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 2644 intel_opregion_asle_intr(dev); 2645 2646 /* With MSI, interrupts are only generated when iir 2647 * transitions from zero to nonzero. If another bit got 2648 * set while we were handling the existing iir bits, then 2649 * we would never get another interrupt. 2650 * 2651 * This is fine on non-MSI as well, as if we hit this path 2652 * we avoid exiting the interrupt handler only to generate 2653 * another one. 2654 * 2655 * Note that for MSI this could cause a stray interrupt report 2656 * if an interrupt landed in the time between writing IIR and 2657 * the posting read. This should be rare enough to never 2658 * trigger the 99% of 100,000 interrupts test for disabling 2659 * stray interrupts. 2660 */ 2661 iir = new_iir; 2662 } 2663 2664 // i915_update_dri1_breadcrumb(dev); 2665 2666 return ret; 2667 } 2668 2669 static void i965_irq_uninstall(struct drm_device * dev) 2670 { 2671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2672 int pipe; 2673 2674 if (!dev_priv) 2675 return; 2676 2677 I915_WRITE(PORT_HOTPLUG_EN, 0); 2678 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2679 2680 I915_WRITE(HWSTAM, 0xffffffff); 2681 for_each_pipe(pipe) 2682 I915_WRITE(PIPESTAT(pipe), 0); 2683 I915_WRITE(IMR, 0xffffffff); 2684 I915_WRITE(IER, 0x0); 2685 2686 for_each_pipe(pipe) 2687 I915_WRITE(PIPESTAT(pipe), 2688 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 2689 I915_WRITE(IIR, I915_READ(IIR)); 2690 } 2691 2692 void intel_irq_init(struct drm_device *dev) 2693 { 2694 struct drm_i915_private *dev_priv = dev->dev_private; 2695 2696 task_set(&dev_priv->hotplug_task, i915_hotplug_work_func, 2697 dev_priv, NULL); 2698 task_set(&dev_priv->error_task, i915_error_work_func, 2699 dev_priv, NULL); 2700 task_set(&dev_priv->rps.task, gen6_pm_rps_work, 2701 dev_priv, NULL); 2702 task_set(&dev_priv->l3_parity.error_task, ivybridge_parity_work, 2703 dev_priv, NULL); 2704 2705 dev->driver->get_vblank_counter = i915_get_vblank_counter; 2706 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 2707 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 2708 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 2709 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 2710 } 2711 2712 if (drm_core_check_feature(dev, DRIVER_MODESET)) 2713 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 2714 else 2715 dev->driver->get_vblank_timestamp = NULL; 2716 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 2717 2718 if (IS_VALLEYVIEW(dev)) { 2719 dev->driver->irq_handler = valleyview_intr; 2720 dev->driver->irq_preinstall = valleyview_irq_preinstall; 2721 dev->driver->irq_postinstall = valleyview_irq_postinstall; 2722 dev->driver->irq_uninstall = valleyview_irq_uninstall; 2723 dev->driver->enable_vblank = valleyview_enable_vblank; 2724 dev->driver->disable_vblank = valleyview_disable_vblank; 2725 } else if (IS_IVYBRIDGE(dev)) { 2726 /* Share pre & uninstall handlers with ILK/SNB */ 2727 dev->driver->irq_handler = ivybridge_intr; 2728 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2729 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2730 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2731 dev->driver->enable_vblank = ivybridge_enable_vblank; 2732 dev->driver->disable_vblank = ivybridge_disable_vblank; 2733 } else if (IS_HASWELL(dev)) { 2734 /* Share interrupts handling with IVB */ 2735 dev->driver->irq_handler = ivybridge_intr; 2736 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2737 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 2738 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2739 dev->driver->enable_vblank = ivybridge_enable_vblank; 2740 dev->driver->disable_vblank = ivybridge_disable_vblank; 2741 } else if (HAS_PCH_SPLIT(dev)) { 2742 dev->driver->irq_handler = ironlake_intr; 2743 dev->driver->irq_preinstall = ironlake_irq_preinstall; 2744 dev->driver->irq_postinstall = ironlake_irq_postinstall; 2745 dev->driver->irq_uninstall = ironlake_irq_uninstall; 2746 dev->driver->enable_vblank = ironlake_enable_vblank; 2747 dev->driver->disable_vblank = ironlake_disable_vblank; 2748 } else { 2749 if (INTEL_INFO(dev)->gen == 2) { 2750 dev->driver->irq_preinstall = i8xx_irq_preinstall; 2751 dev->driver->irq_postinstall = i8xx_irq_postinstall; 2752 dev->driver->irq_handler = i8xx_intr; 2753 dev->driver->irq_uninstall = i8xx_irq_uninstall; 2754 } else if (INTEL_INFO(dev)->gen == 3) { 2755 dev->driver->irq_preinstall = i915_irq_preinstall; 2756 dev->driver->irq_postinstall = i915_irq_postinstall; 2757 dev->driver->irq_uninstall = i915_irq_uninstall; 2758 dev->driver->irq_handler = i915_intr; 2759 } else { 2760 dev->driver->irq_preinstall = i965_irq_preinstall; 2761 dev->driver->irq_postinstall = i965_irq_postinstall; 2762 dev->driver->irq_uninstall = i965_irq_uninstall; 2763 dev->driver->irq_handler = i965_intr; 2764 } 2765 dev->driver->enable_vblank = i915_enable_vblank; 2766 dev->driver->disable_vblank = i915_disable_vblank; 2767 } 2768 } 2769