1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_atomic.h" 40 #include "display/intel_csr.h" 41 #include "display/intel_overlay.h" 42 43 #include "gem/i915_gem_context.h" 44 #include "gem/i915_gem_lmem.h" 45 #include "gt/intel_gt_pm.h" 46 47 #include "i915_drv.h" 48 #include "i915_gpu_error.h" 49 #include "i915_memcpy.h" 50 #include "i915_scatterlist.h" 51 52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 54 55 static void __sg_set_buf(struct scatterlist *sg, 56 void *addr, unsigned int len, loff_t it) 57 { 58 STUB(); 59 #ifdef notyet 60 sg->page_link = (unsigned long)virt_to_page(addr); 61 sg->offset = offset_in_page(addr); 62 sg->length = len; 63 sg->dma_address = it; 64 #endif 65 } 66 67 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 68 { 69 STUB(); 70 return false; 71 #ifdef notyet 72 if (!len) 73 return false; 74 75 if (e->bytes + len + 1 <= e->size) 76 return true; 77 78 if (e->bytes) { 79 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 80 e->iter += e->bytes; 81 e->buf = NULL; 82 e->bytes = 0; 83 } 84 85 if (e->cur == e->end) { 86 struct scatterlist *sgl; 87 88 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 89 if (!sgl) { 90 e->err = -ENOMEM; 91 return false; 92 } 93 94 if (e->cur) { 95 e->cur->offset = 0; 96 e->cur->length = 0; 97 e->cur->page_link = 98 (unsigned long)sgl | SG_CHAIN; 99 } else { 100 e->sgl = sgl; 101 } 102 103 e->cur = sgl; 104 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 105 } 106 107 e->size = roundup2(len + 1, SZ_64K); 108 e->buf = kmalloc(e->size, ALLOW_FAIL); 109 if (!e->buf) { 110 e->size = PAGE_ALIGN(len + 1); 111 e->buf = kmalloc(e->size, GFP_KERNEL); 112 } 113 if (!e->buf) { 114 e->err = -ENOMEM; 115 return false; 116 } 117 118 return true; 119 #endif 120 } 121 122 __printf(2, 0) 123 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 124 const char *fmt, va_list args) 125 { 126 va_list ap; 127 int len; 128 129 if (e->err) 130 return; 131 132 va_copy(ap, args); 133 len = vsnprintf(NULL, 0, fmt, ap); 134 va_end(ap); 135 if (len <= 0) { 136 e->err = len; 137 return; 138 } 139 140 if (!__i915_error_grow(e, len)) 141 return; 142 143 GEM_BUG_ON(e->bytes >= e->size); 144 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 145 if (len < 0) { 146 e->err = len; 147 return; 148 } 149 e->bytes += len; 150 } 151 152 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 153 { 154 unsigned len; 155 156 if (e->err || !str) 157 return; 158 159 len = strlen(str); 160 if (!__i915_error_grow(e, len)) 161 return; 162 163 GEM_BUG_ON(e->bytes + len > e->size); 164 memcpy(e->buf + e->bytes, str, len); 165 e->bytes += len; 166 } 167 168 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 169 #define err_puts(e, s) i915_error_puts(e, s) 170 171 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 172 { 173 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 174 } 175 176 static inline struct drm_printer 177 i915_error_printer(struct drm_i915_error_state_buf *e) 178 { 179 struct drm_printer p = { 180 .printfn = __i915_printfn_error, 181 .arg = e, 182 }; 183 return p; 184 } 185 186 /* single threaded page allocator with a reserved stash for emergencies */ 187 static void pool_fini(struct pagevec *pv) 188 { 189 STUB(); 190 #ifdef notyet 191 pagevec_release(pv); 192 #endif 193 } 194 195 static int pool_refill(struct pagevec *pv, gfp_t gfp) 196 { 197 while (pagevec_space(pv)) { 198 struct vm_page *p; 199 200 p = alloc_page(gfp); 201 if (!p) 202 return -ENOMEM; 203 204 pagevec_add(pv, p); 205 } 206 207 return 0; 208 } 209 210 static int intel_pool_init(struct pagevec *pv, gfp_t gfp) 211 { 212 int err; 213 214 pagevec_init(pv); 215 216 err = pool_refill(pv, gfp); 217 if (err) 218 pool_fini(pv); 219 220 return err; 221 } 222 223 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 224 { 225 STUB(); 226 return NULL; 227 #ifdef notyet 228 struct vm_page *p; 229 230 p = alloc_page(gfp); 231 if (!p && pagevec_count(pv)) 232 p = pv->pages[--pv->nr]; 233 234 return p ? page_address(p) : NULL; 235 #endif 236 } 237 238 static void pool_free(struct pagevec *pv, void *addr) 239 { 240 STUB(); 241 #ifdef notyet 242 struct vm_page *p = virt_to_page(addr); 243 244 if (pagevec_space(pv)) 245 pagevec_add(pv, p); 246 else 247 __free_page(p); 248 #endif 249 } 250 251 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 252 253 struct i915_vma_compress { 254 struct pagevec pool; 255 struct z_stream_s zstream; 256 void *tmp; 257 }; 258 259 static bool compress_init(struct i915_vma_compress *c) 260 { 261 struct z_stream_s *zstream = &c->zstream; 262 263 if (intel_pool_init(&c->pool, ALLOW_FAIL)) 264 return false; 265 266 zstream->workspace = 267 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 268 ALLOW_FAIL); 269 if (!zstream->workspace) { 270 pool_fini(&c->pool); 271 return false; 272 } 273 274 c->tmp = NULL; 275 if (i915_has_memcpy_from_wc()) 276 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 277 278 return true; 279 } 280 281 static bool compress_start(struct i915_vma_compress *c) 282 { 283 struct z_stream_s *zstream = &c->zstream; 284 void *workspace = zstream->workspace; 285 286 memset(zstream, 0, sizeof(*zstream)); 287 zstream->workspace = workspace; 288 289 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 290 } 291 292 static void *compress_next_page(struct i915_vma_compress *c, 293 struct i915_vma_coredump *dst) 294 { 295 void *page; 296 297 if (dst->page_count >= dst->num_pages) 298 return ERR_PTR(-ENOSPC); 299 300 page = pool_alloc(&c->pool, ALLOW_FAIL); 301 if (!page) 302 return ERR_PTR(-ENOMEM); 303 304 return dst->pages[dst->page_count++] = page; 305 } 306 307 static int compress_page(struct i915_vma_compress *c, 308 void *src, 309 struct i915_vma_coredump *dst, 310 bool wc) 311 { 312 struct z_stream_s *zstream = &c->zstream; 313 314 zstream->next_in = src; 315 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 316 zstream->next_in = c->tmp; 317 zstream->avail_in = PAGE_SIZE; 318 319 do { 320 if (zstream->avail_out == 0) { 321 zstream->next_out = compress_next_page(c, dst); 322 if (IS_ERR(zstream->next_out)) 323 return PTR_ERR(zstream->next_out); 324 325 zstream->avail_out = PAGE_SIZE; 326 } 327 328 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 329 return -EIO; 330 } while (zstream->avail_in); 331 332 /* Fallback to uncompressed if we increase size? */ 333 if (0 && zstream->total_out > zstream->total_in) 334 return -E2BIG; 335 336 return 0; 337 } 338 339 static int compress_flush(struct i915_vma_compress *c, 340 struct i915_vma_coredump *dst) 341 { 342 struct z_stream_s *zstream = &c->zstream; 343 344 do { 345 switch (zlib_deflate(zstream, Z_FINISH)) { 346 case Z_OK: /* more space requested */ 347 zstream->next_out = compress_next_page(c, dst); 348 if (IS_ERR(zstream->next_out)) 349 return PTR_ERR(zstream->next_out); 350 351 zstream->avail_out = PAGE_SIZE; 352 break; 353 354 case Z_STREAM_END: 355 goto end; 356 357 default: /* any error */ 358 return -EIO; 359 } 360 } while (1); 361 362 end: 363 memset(zstream->next_out, 0, zstream->avail_out); 364 dst->unused = zstream->avail_out; 365 return 0; 366 } 367 368 static void compress_finish(struct i915_vma_compress *c) 369 { 370 zlib_deflateEnd(&c->zstream); 371 } 372 373 static void compress_fini(struct i915_vma_compress *c) 374 { 375 kfree(c->zstream.workspace); 376 if (c->tmp) 377 pool_free(&c->pool, c->tmp); 378 pool_fini(&c->pool); 379 } 380 381 static void err_compression_marker(struct drm_i915_error_state_buf *m) 382 { 383 err_puts(m, ":"); 384 } 385 386 #else 387 388 struct i915_vma_compress { 389 struct pagevec pool; 390 }; 391 392 static bool compress_init(struct i915_vma_compress *c) 393 { 394 return intel_pool_init(&c->pool, ALLOW_FAIL) == 0; 395 } 396 397 static bool compress_start(struct i915_vma_compress *c) 398 { 399 return true; 400 } 401 402 static int compress_page(struct i915_vma_compress *c, 403 void *src, 404 struct i915_vma_coredump *dst, 405 bool wc) 406 { 407 void *ptr; 408 409 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 410 if (!ptr) 411 return -ENOMEM; 412 413 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 414 memcpy(ptr, src, PAGE_SIZE); 415 dst->pages[dst->page_count++] = ptr; 416 417 return 0; 418 } 419 420 static int compress_flush(struct i915_vma_compress *c, 421 struct i915_vma_coredump *dst) 422 { 423 return 0; 424 } 425 426 static void compress_finish(struct i915_vma_compress *c) 427 { 428 } 429 430 static void compress_fini(struct i915_vma_compress *c) 431 { 432 pool_fini(&c->pool); 433 } 434 435 static void err_compression_marker(struct drm_i915_error_state_buf *m) 436 { 437 err_puts(m, "~"); 438 } 439 440 #endif 441 442 static void error_print_instdone(struct drm_i915_error_state_buf *m, 443 const struct intel_engine_coredump *ee) 444 { 445 const struct sseu_dev_info *sseu = &RUNTIME_INFO(m->i915)->sseu; 446 int slice; 447 int subslice; 448 449 err_printf(m, " INSTDONE: 0x%08x\n", 450 ee->instdone.instdone); 451 452 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3) 453 return; 454 455 err_printf(m, " SC_INSTDONE: 0x%08x\n", 456 ee->instdone.slice_common); 457 458 if (INTEL_GEN(m->i915) <= 6) 459 return; 460 461 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 462 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 463 slice, subslice, 464 ee->instdone.sampler[slice][subslice]); 465 466 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 467 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 468 slice, subslice, 469 ee->instdone.row[slice][subslice]); 470 471 if (INTEL_GEN(m->i915) < 12) 472 return; 473 474 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 475 ee->instdone.slice_common_extra[0]); 476 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 477 ee->instdone.slice_common_extra[1]); 478 } 479 480 static void error_print_request(struct drm_i915_error_state_buf *m, 481 const char *prefix, 482 const struct i915_request_coredump *erq) 483 { 484 if (!erq->seqno) 485 return; 486 487 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, start %08x, head %08x, tail %08x\n", 488 prefix, erq->pid, erq->context, erq->seqno, 489 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 490 &erq->flags) ? "!" : "", 491 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 492 &erq->flags) ? "+" : "", 493 erq->sched_attr.priority, 494 erq->start, erq->head, erq->tail); 495 } 496 497 static void error_print_context(struct drm_i915_error_state_buf *m, 498 const char *header, 499 const struct i915_gem_context_coredump *ctx) 500 { 501 const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; 502 503 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 504 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 505 ctx->guilty, ctx->active, 506 ctx->total_runtime * period, 507 mul_u32_u32(ctx->avg_runtime, period)); 508 } 509 510 static struct i915_vma_coredump * 511 __find_vma(struct i915_vma_coredump *vma, const char *name) 512 { 513 while (vma) { 514 if (strcmp(vma->name, name) == 0) 515 return vma; 516 vma = vma->next; 517 } 518 519 return NULL; 520 } 521 522 static struct i915_vma_coredump * 523 find_batch(const struct intel_engine_coredump *ee) 524 { 525 return __find_vma(ee->vma, "batch"); 526 } 527 528 static void error_print_engine(struct drm_i915_error_state_buf *m, 529 const struct intel_engine_coredump *ee) 530 { 531 struct i915_vma_coredump *batch; 532 int n; 533 534 err_printf(m, "%s command stream:\n", ee->engine->name); 535 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 536 err_printf(m, " START: 0x%08x\n", ee->start); 537 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 538 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 539 ee->tail, ee->rq_post, ee->rq_tail); 540 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 541 err_printf(m, " MODE: 0x%08x\n", ee->mode); 542 err_printf(m, " HWS: 0x%08x\n", ee->hws); 543 err_printf(m, " ACTHD: 0x%08x %08x\n", 544 (u32)(ee->acthd>>32), (u32)ee->acthd); 545 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 546 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 547 err_printf(m, " ESR: 0x%08x\n", ee->esr); 548 549 error_print_instdone(m, ee); 550 551 batch = find_batch(ee); 552 if (batch) { 553 u64 start = batch->gtt_offset; 554 u64 end = start + batch->gtt_size; 555 556 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 557 upper_32_bits(start), lower_32_bits(start), 558 upper_32_bits(end), lower_32_bits(end)); 559 } 560 if (INTEL_GEN(m->i915) >= 4) { 561 err_printf(m, " BBADDR: 0x%08x_%08x\n", 562 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 563 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 564 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 565 } 566 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 567 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 568 lower_32_bits(ee->faddr)); 569 if (INTEL_GEN(m->i915) >= 6) { 570 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 571 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 572 } 573 if (HAS_PPGTT(m->i915)) { 574 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 575 576 if (INTEL_GEN(m->i915) >= 8) { 577 int i; 578 for (i = 0; i < 4; i++) 579 err_printf(m, " PDP%d: 0x%016llx\n", 580 i, ee->vm_info.pdp[i]); 581 } else { 582 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 583 ee->vm_info.pp_dir_base); 584 } 585 } 586 err_printf(m, " engine reset count: %u\n", ee->reset_count); 587 588 for (n = 0; n < ee->num_ports; n++) { 589 err_printf(m, " ELSP[%d]:", n); 590 error_print_request(m, " ", &ee->execlist[n]); 591 } 592 593 error_print_context(m, " Active context: ", &ee->context); 594 } 595 596 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 597 { 598 va_list args; 599 600 va_start(args, f); 601 i915_error_vprintf(e, f, args); 602 va_end(args); 603 } 604 605 static void print_error_vma(struct drm_i915_error_state_buf *m, 606 const struct intel_engine_cs *engine, 607 const struct i915_vma_coredump *vma) 608 { 609 STUB(); 610 #ifdef notyet 611 char out[ASCII85_BUFSZ]; 612 int page; 613 614 if (!vma) 615 return; 616 617 err_printf(m, "%s --- %s = 0x%08x %08x\n", 618 engine ? engine->name : "global", vma->name, 619 upper_32_bits(vma->gtt_offset), 620 lower_32_bits(vma->gtt_offset)); 621 622 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 623 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 624 625 err_compression_marker(m); 626 for (page = 0; page < vma->page_count; page++) { 627 int i, len; 628 629 len = PAGE_SIZE; 630 if (page == vma->page_count - 1) 631 len -= vma->unused; 632 len = ascii85_encode_len(len); 633 634 for (i = 0; i < len; i++) 635 err_puts(m, ascii85_encode(vma->pages[page][i], out)); 636 } 637 err_puts(m, "\n"); 638 #endif 639 } 640 641 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 642 const struct intel_device_info *info, 643 const struct intel_runtime_info *runtime, 644 const struct intel_driver_caps *caps) 645 { 646 struct drm_printer p = i915_error_printer(m); 647 648 intel_device_info_print_static(info, &p); 649 intel_device_info_print_runtime(runtime, &p); 650 intel_device_info_print_topology(&runtime->sseu, &p); 651 intel_driver_caps_print(caps, &p); 652 } 653 654 static void err_print_params(struct drm_i915_error_state_buf *m, 655 const struct i915_params *params) 656 { 657 struct drm_printer p = i915_error_printer(m); 658 659 i915_params_dump(params, &p); 660 } 661 662 static void err_print_pciid(struct drm_i915_error_state_buf *m, 663 struct drm_i915_private *i915) 664 { 665 struct pci_dev *pdev = i915->drm.pdev; 666 667 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 668 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 669 err_printf(m, "PCI Subsystem: %04x:%04x\n", 670 pdev->subsystem_vendor, 671 pdev->subsystem_device); 672 } 673 674 static void err_print_uc(struct drm_i915_error_state_buf *m, 675 const struct intel_uc_coredump *error_uc) 676 { 677 struct drm_printer p = i915_error_printer(m); 678 679 intel_uc_fw_dump(&error_uc->guc_fw, &p); 680 intel_uc_fw_dump(&error_uc->huc_fw, &p); 681 print_error_vma(m, NULL, error_uc->guc_log); 682 } 683 684 static void err_free_sgl(struct scatterlist *sgl) 685 { 686 STUB(); 687 #ifdef notyet 688 while (sgl) { 689 struct scatterlist *sg; 690 691 for (sg = sgl; !sg_is_chain(sg); sg++) { 692 kfree(sg_virt(sg)); 693 if (sg_is_last(sg)) 694 break; 695 } 696 697 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 698 free_page((unsigned long)sgl); 699 sgl = sg; 700 } 701 #endif 702 } 703 704 static void err_print_gt(struct drm_i915_error_state_buf *m, 705 struct intel_gt_coredump *gt) 706 { 707 const struct intel_engine_coredump *ee; 708 int i; 709 710 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 711 err_printf(m, "EIR: 0x%08x\n", gt->eir); 712 err_printf(m, "IER: 0x%08x\n", gt->ier); 713 for (i = 0; i < gt->ngtier; i++) 714 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 715 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 716 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 717 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 718 719 for (i = 0; i < gt->nfence; i++) 720 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 721 722 if (IS_GEN_RANGE(m->i915, 6, 11)) { 723 err_printf(m, "ERROR: 0x%08x\n", gt->error); 724 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 725 } 726 727 if (INTEL_GEN(m->i915) >= 8) 728 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 729 gt->fault_data1, gt->fault_data0); 730 731 if (IS_GEN(m->i915, 7)) 732 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 733 734 if (IS_GEN_RANGE(m->i915, 8, 11)) 735 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 736 737 if (IS_GEN(m->i915, 12)) 738 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 739 740 if (INTEL_GEN(m->i915) >= 12) { 741 int i; 742 743 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) 744 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 745 gt->sfc_done[i]); 746 747 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 748 } 749 750 for (ee = gt->engine; ee; ee = ee->next) { 751 const struct i915_vma_coredump *vma; 752 753 error_print_engine(m, ee); 754 for (vma = ee->vma; vma; vma = vma->next) 755 print_error_vma(m, ee->engine, vma); 756 } 757 758 if (gt->uc) 759 err_print_uc(m, gt->uc); 760 } 761 762 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 763 struct i915_gpu_coredump *error) 764 { 765 const struct intel_engine_coredump *ee; 766 struct timespec64 ts; 767 768 if (*error->error_msg) 769 err_printf(m, "%s\n", error->error_msg); 770 #ifdef __linux__ 771 err_printf(m, "Kernel: %s %s\n", 772 init_utsname()->release, 773 init_utsname()->machine); 774 #else 775 extern char machine[]; 776 err_printf(m, "Kernel: %s %s\n", 777 osrelease, 778 machine); 779 #endif 780 err_printf(m, "Driver: %s\n", DRIVER_DATE); 781 ts = ktime_to_timespec64(error->time); 782 err_printf(m, "Time: %lld s %ld us\n", 783 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 784 ts = ktime_to_timespec64(error->boottime); 785 err_printf(m, "Boottime: %lld s %ld us\n", 786 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 787 ts = ktime_to_timespec64(error->uptime); 788 err_printf(m, "Uptime: %lld s %ld us\n", 789 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 790 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 791 error->capture, jiffies_to_msecs(jiffies - error->capture)); 792 793 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 794 err_printf(m, "Active process (on ring %s): %s [%d]\n", 795 ee->engine->name, 796 ee->context.comm, 797 ee->context.pid); 798 799 err_printf(m, "Reset count: %u\n", error->reset_count); 800 err_printf(m, "Suspend count: %u\n", error->suspend_count); 801 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 802 err_printf(m, "Subplatform: 0x%x\n", 803 intel_subplatform(&error->runtime_info, 804 error->device_info.platform)); 805 err_print_pciid(m, m->i915); 806 807 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 808 809 if (HAS_CSR(m->i915)) { 810 struct intel_csr *csr = &m->i915->csr; 811 812 err_printf(m, "DMC loaded: %s\n", 813 yesno(csr->dmc_payload != NULL)); 814 err_printf(m, "DMC fw version: %d.%d\n", 815 CSR_VERSION_MAJOR(csr->version), 816 CSR_VERSION_MINOR(csr->version)); 817 } 818 819 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 820 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 821 822 if (error->gt) 823 err_print_gt(m, error->gt); 824 825 if (error->overlay) 826 intel_overlay_print_error_state(m, error->overlay); 827 828 if (error->display) 829 intel_display_print_error_state(m, error->display); 830 831 err_print_capabilities(m, &error->device_info, &error->runtime_info, 832 &error->driver_caps); 833 err_print_params(m, &error->params); 834 } 835 836 static int err_print_to_sgl(struct i915_gpu_coredump *error) 837 { 838 struct drm_i915_error_state_buf m; 839 840 if (IS_ERR(error)) 841 return PTR_ERR(error); 842 843 if (READ_ONCE(error->sgl)) 844 return 0; 845 846 memset(&m, 0, sizeof(m)); 847 m.i915 = error->i915; 848 849 __err_print_to_sgl(&m, error); 850 851 if (m.buf) { 852 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 853 m.bytes = 0; 854 m.buf = NULL; 855 } 856 if (m.cur) { 857 GEM_BUG_ON(m.end < m.cur); 858 sg_mark_end(m.cur - 1); 859 } 860 GEM_BUG_ON(m.sgl && !m.cur); 861 862 if (m.err) { 863 err_free_sgl(m.sgl); 864 return m.err; 865 } 866 867 if (cmpxchg(&error->sgl, NULL, m.sgl)) 868 err_free_sgl(m.sgl); 869 870 return 0; 871 } 872 873 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 874 char *buf, loff_t off, size_t rem) 875 { 876 STUB(); 877 return -ENOSYS; 878 #ifdef notyet 879 struct scatterlist *sg; 880 size_t count; 881 loff_t pos; 882 int err; 883 884 if (!error || !rem) 885 return 0; 886 887 err = err_print_to_sgl(error); 888 if (err) 889 return err; 890 891 sg = READ_ONCE(error->fit); 892 if (!sg || off < sg->dma_address) 893 sg = error->sgl; 894 if (!sg) 895 return 0; 896 897 pos = sg->dma_address; 898 count = 0; 899 do { 900 size_t len, start; 901 902 if (sg_is_chain(sg)) { 903 sg = sg_chain_ptr(sg); 904 GEM_BUG_ON(sg_is_chain(sg)); 905 } 906 907 len = sg->length; 908 if (pos + len <= off) { 909 pos += len; 910 continue; 911 } 912 913 start = sg->offset; 914 if (pos < off) { 915 GEM_BUG_ON(off - pos > len); 916 len -= off - pos; 917 start += off - pos; 918 pos = off; 919 } 920 921 len = min(len, rem); 922 GEM_BUG_ON(!len || len > sg->length); 923 924 memcpy(buf, page_address(sg_page(sg)) + start, len); 925 926 count += len; 927 pos += len; 928 929 buf += len; 930 rem -= len; 931 if (!rem) { 932 WRITE_ONCE(error->fit, sg); 933 break; 934 } 935 } while (!sg_is_last(sg++)); 936 937 return count; 938 #endif 939 } 940 941 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 942 { 943 while (vma) { 944 struct i915_vma_coredump *next = vma->next; 945 int page; 946 947 for (page = 0; page < vma->page_count; page++) 948 free_page((unsigned long)vma->pages[page]); 949 950 kfree(vma); 951 vma = next; 952 } 953 } 954 955 static void cleanup_params(struct i915_gpu_coredump *error) 956 { 957 i915_params_free(&error->params); 958 } 959 960 static void cleanup_uc(struct intel_uc_coredump *uc) 961 { 962 kfree(uc->guc_fw.path); 963 kfree(uc->huc_fw.path); 964 i915_vma_coredump_free(uc->guc_log); 965 966 kfree(uc); 967 } 968 969 static void cleanup_gt(struct intel_gt_coredump *gt) 970 { 971 while (gt->engine) { 972 struct intel_engine_coredump *ee = gt->engine; 973 974 gt->engine = ee->next; 975 976 i915_vma_coredump_free(ee->vma); 977 kfree(ee); 978 } 979 980 if (gt->uc) 981 cleanup_uc(gt->uc); 982 983 kfree(gt); 984 } 985 986 void __i915_gpu_coredump_free(struct kref *error_ref) 987 { 988 struct i915_gpu_coredump *error = 989 container_of(error_ref, typeof(*error), ref); 990 991 while (error->gt) { 992 struct intel_gt_coredump *gt = error->gt; 993 994 error->gt = gt->next; 995 cleanup_gt(gt); 996 } 997 998 kfree(error->overlay); 999 kfree(error->display); 1000 1001 cleanup_params(error); 1002 1003 err_free_sgl(error->sgl); 1004 kfree(error); 1005 } 1006 1007 static struct i915_vma_coredump * 1008 i915_vma_coredump_create(const struct intel_gt *gt, 1009 const struct i915_vma *vma, 1010 const char *name, 1011 struct i915_vma_compress *compress) 1012 { 1013 STUB(); 1014 return NULL; 1015 #ifdef notyet 1016 struct i915_ggtt *ggtt = gt->ggtt; 1017 const u64 slot = ggtt->error_capture.start; 1018 struct i915_vma_coredump *dst; 1019 unsigned long num_pages; 1020 struct sgt_iter iter; 1021 int ret; 1022 1023 might_sleep(); 1024 1025 if (!vma || !vma->pages || !compress) 1026 return NULL; 1027 1028 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 1029 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 1030 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); 1031 if (!dst) 1032 return NULL; 1033 1034 if (!compress_start(compress)) { 1035 kfree(dst); 1036 return NULL; 1037 } 1038 1039 strlcpy(dst->name, name, sizeof(dst->name)); 1040 dst->next = NULL; 1041 1042 dst->gtt_offset = vma->node.start; 1043 dst->gtt_size = vma->node.size; 1044 dst->gtt_page_sizes = vma->page_sizes.gtt; 1045 dst->num_pages = num_pages; 1046 dst->page_count = 0; 1047 dst->unused = 0; 1048 1049 ret = -EINVAL; 1050 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1051 void __iomem *s; 1052 dma_addr_t dma; 1053 1054 for_each_sgt_daddr(dma, iter, vma->pages) { 1055 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1056 I915_CACHE_NONE, 0); 1057 mb(); 1058 1059 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1060 ret = compress_page(compress, 1061 (void __force *)s, dst, 1062 true); 1063 io_mapping_unmap(s); 1064 if (ret) 1065 break; 1066 } 1067 } else if (i915_gem_object_is_lmem(vma->obj)) { 1068 struct intel_memory_region *mem = vma->obj->mm.region; 1069 dma_addr_t dma; 1070 1071 for_each_sgt_daddr(dma, iter, vma->pages) { 1072 void __iomem *s; 1073 1074 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE); 1075 ret = compress_page(compress, 1076 (void __force *)s, dst, 1077 true); 1078 io_mapping_unmap(s); 1079 if (ret) 1080 break; 1081 } 1082 } else { 1083 struct vm_page *page; 1084 1085 for_each_sgt_page(page, iter, vma->pages) { 1086 void *s; 1087 1088 drm_clflush_pages(&page, 1); 1089 1090 s = kmap(page); 1091 ret = compress_page(compress, s, dst, false); 1092 kunmap(page); 1093 1094 drm_clflush_pages(&page, 1); 1095 1096 if (ret) 1097 break; 1098 } 1099 } 1100 1101 if (ret || compress_flush(compress, dst)) { 1102 while (dst->page_count--) 1103 pool_free(&compress->pool, dst->pages[dst->page_count]); 1104 kfree(dst); 1105 dst = NULL; 1106 } 1107 compress_finish(compress); 1108 1109 return dst; 1110 #endif 1111 } 1112 1113 static void gt_record_fences(struct intel_gt_coredump *gt) 1114 { 1115 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1116 struct intel_uncore *uncore = gt->_gt->uncore; 1117 int i; 1118 1119 if (INTEL_GEN(uncore->i915) >= 6) { 1120 for (i = 0; i < ggtt->num_fences; i++) 1121 gt->fence[i] = 1122 intel_uncore_read64(uncore, 1123 FENCE_REG_GEN6_LO(i)); 1124 } else if (INTEL_GEN(uncore->i915) >= 4) { 1125 for (i = 0; i < ggtt->num_fences; i++) 1126 gt->fence[i] = 1127 intel_uncore_read64(uncore, 1128 FENCE_REG_965_LO(i)); 1129 } else { 1130 for (i = 0; i < ggtt->num_fences; i++) 1131 gt->fence[i] = 1132 intel_uncore_read(uncore, FENCE_REG(i)); 1133 } 1134 gt->nfence = i; 1135 } 1136 1137 static void engine_record_registers(struct intel_engine_coredump *ee) 1138 { 1139 const struct intel_engine_cs *engine = ee->engine; 1140 struct drm_i915_private *i915 = engine->i915; 1141 1142 if (INTEL_GEN(i915) >= 6) { 1143 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1144 1145 if (INTEL_GEN(i915) >= 12) 1146 ee->fault_reg = intel_uncore_read(engine->uncore, 1147 GEN12_RING_FAULT_REG); 1148 else if (INTEL_GEN(i915) >= 8) 1149 ee->fault_reg = intel_uncore_read(engine->uncore, 1150 GEN8_RING_FAULT_REG); 1151 else 1152 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1153 } 1154 1155 if (INTEL_GEN(i915) >= 4) { 1156 ee->esr = ENGINE_READ(engine, RING_ESR); 1157 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1158 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1159 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1160 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1161 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1162 ee->ccid = ENGINE_READ(engine, CCID); 1163 if (INTEL_GEN(i915) >= 8) { 1164 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1165 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1166 } 1167 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1168 } else { 1169 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1170 ee->ipeir = ENGINE_READ(engine, IPEIR); 1171 ee->ipehr = ENGINE_READ(engine, IPEHR); 1172 } 1173 1174 intel_engine_get_instdone(engine, &ee->instdone); 1175 1176 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1177 ee->acthd = intel_engine_get_active_head(engine); 1178 ee->start = ENGINE_READ(engine, RING_START); 1179 ee->head = ENGINE_READ(engine, RING_HEAD); 1180 ee->tail = ENGINE_READ(engine, RING_TAIL); 1181 ee->ctl = ENGINE_READ(engine, RING_CTL); 1182 if (INTEL_GEN(i915) > 2) 1183 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1184 1185 if (!HWS_NEEDS_PHYSICAL(i915)) { 1186 i915_reg_t mmio; 1187 1188 if (IS_GEN(i915, 7)) { 1189 switch (engine->id) { 1190 default: 1191 MISSING_CASE(engine->id); 1192 /* fall through */ 1193 case RCS0: 1194 mmio = RENDER_HWS_PGA_GEN7; 1195 break; 1196 case BCS0: 1197 mmio = BLT_HWS_PGA_GEN7; 1198 break; 1199 case VCS0: 1200 mmio = BSD_HWS_PGA_GEN7; 1201 break; 1202 case VECS0: 1203 mmio = VEBOX_HWS_PGA_GEN7; 1204 break; 1205 } 1206 } else if (IS_GEN(engine->i915, 6)) { 1207 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1208 } else { 1209 /* XXX: gen8 returns to sanity */ 1210 mmio = RING_HWS_PGA(engine->mmio_base); 1211 } 1212 1213 ee->hws = intel_uncore_read(engine->uncore, mmio); 1214 } 1215 1216 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1217 1218 if (HAS_PPGTT(i915)) { 1219 int i; 1220 1221 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1222 1223 if (IS_GEN(i915, 6)) { 1224 ee->vm_info.pp_dir_base = 1225 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1226 } else if (IS_GEN(i915, 7)) { 1227 ee->vm_info.pp_dir_base = 1228 ENGINE_READ(engine, RING_PP_DIR_BASE); 1229 } else if (INTEL_GEN(i915) >= 8) { 1230 u32 base = engine->mmio_base; 1231 1232 for (i = 0; i < 4; i++) { 1233 ee->vm_info.pdp[i] = 1234 intel_uncore_read(engine->uncore, 1235 GEN8_RING_PDP_UDW(base, i)); 1236 ee->vm_info.pdp[i] <<= 32; 1237 ee->vm_info.pdp[i] |= 1238 intel_uncore_read(engine->uncore, 1239 GEN8_RING_PDP_LDW(base, i)); 1240 } 1241 } 1242 } 1243 } 1244 1245 static void record_request(const struct i915_request *request, 1246 struct i915_request_coredump *erq) 1247 { 1248 erq->flags = request->fence.flags; 1249 erq->context = request->fence.context; 1250 erq->seqno = request->fence.seqno; 1251 erq->sched_attr = request->sched.attr; 1252 erq->start = i915_ggtt_offset(request->ring->vma); 1253 erq->head = request->head; 1254 erq->tail = request->tail; 1255 1256 erq->pid = 0; 1257 rcu_read_lock(); 1258 if (!intel_context_is_closed(request->context)) { 1259 const struct i915_gem_context *ctx; 1260 1261 ctx = rcu_dereference(request->context->gem_context); 1262 if (ctx) 1263 #ifdef __linux__ 1264 erq->pid = pid_nr(ctx->pid); 1265 #else 1266 erq->pid = ctx->pid; 1267 #endif 1268 } 1269 rcu_read_unlock(); 1270 } 1271 1272 static void engine_record_execlists(struct intel_engine_coredump *ee) 1273 { 1274 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1275 struct i915_request * const *port = el->active; 1276 unsigned int n = 0; 1277 1278 while (*port) 1279 record_request(*port++, &ee->execlist[n++]); 1280 1281 ee->num_ports = n; 1282 } 1283 1284 static bool record_context(struct i915_gem_context_coredump *e, 1285 const struct i915_request *rq) 1286 { 1287 struct i915_gem_context *ctx; 1288 struct task_struct *task; 1289 bool simulated; 1290 1291 rcu_read_lock(); 1292 ctx = rcu_dereference(rq->context->gem_context); 1293 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1294 ctx = NULL; 1295 rcu_read_unlock(); 1296 if (!ctx) 1297 return true; 1298 1299 #ifdef __linux__ 1300 rcu_read_lock(); 1301 task = pid_task(ctx->pid, PIDTYPE_PID); 1302 if (task) { 1303 strcpy(e->comm, task->comm); 1304 e->pid = task->pid; 1305 } 1306 rcu_read_unlock(); 1307 #endif 1308 1309 e->sched_attr = ctx->sched; 1310 e->guilty = atomic_read(&ctx->guilty_count); 1311 e->active = atomic_read(&ctx->active_count); 1312 1313 e->total_runtime = rq->context->runtime.total; 1314 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1315 1316 simulated = i915_gem_context_no_error_capture(ctx); 1317 1318 i915_gem_context_put(ctx); 1319 return simulated; 1320 } 1321 1322 struct intel_engine_capture_vma { 1323 struct intel_engine_capture_vma *next; 1324 struct i915_vma *vma; 1325 char name[16]; 1326 }; 1327 1328 static struct intel_engine_capture_vma * 1329 capture_vma(struct intel_engine_capture_vma *next, 1330 struct i915_vma *vma, 1331 const char *name, 1332 gfp_t gfp) 1333 { 1334 struct intel_engine_capture_vma *c; 1335 1336 if (!vma) 1337 return next; 1338 1339 c = kmalloc(sizeof(*c), gfp); 1340 if (!c) 1341 return next; 1342 1343 if (!i915_active_acquire_if_busy(&vma->active)) { 1344 kfree(c); 1345 return next; 1346 } 1347 1348 strlcpy(c->name, name, sizeof(c->name)); 1349 c->vma = i915_vma_get(vma); 1350 1351 c->next = next; 1352 return c; 1353 } 1354 1355 static struct intel_engine_capture_vma * 1356 capture_user(struct intel_engine_capture_vma *capture, 1357 const struct i915_request *rq, 1358 gfp_t gfp) 1359 { 1360 struct i915_capture_list *c; 1361 1362 for (c = rq->capture_list; c; c = c->next) 1363 capture = capture_vma(capture, c->vma, "user", gfp); 1364 1365 return capture; 1366 } 1367 1368 static struct i915_vma_coredump * 1369 capture_object(const struct intel_gt *gt, 1370 struct drm_i915_gem_object *obj, 1371 const char *name, 1372 struct i915_vma_compress *compress) 1373 { 1374 if (obj && i915_gem_object_has_pages(obj)) { 1375 struct i915_vma fake = { 1376 .node = { .start = U64_MAX, .size = obj->base.size }, 1377 .size = obj->base.size, 1378 .pages = obj->mm.pages, 1379 .obj = obj, 1380 }; 1381 1382 return i915_vma_coredump_create(gt, &fake, name, compress); 1383 } else { 1384 return NULL; 1385 } 1386 } 1387 1388 static void add_vma(struct intel_engine_coredump *ee, 1389 struct i915_vma_coredump *vma) 1390 { 1391 if (vma) { 1392 vma->next = ee->vma; 1393 ee->vma = vma; 1394 } 1395 } 1396 1397 struct intel_engine_coredump * 1398 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1399 { 1400 struct intel_engine_coredump *ee; 1401 1402 ee = kzalloc(sizeof(*ee), gfp); 1403 if (!ee) 1404 return NULL; 1405 1406 ee->engine = engine; 1407 1408 engine_record_registers(ee); 1409 engine_record_execlists(ee); 1410 1411 return ee; 1412 } 1413 1414 struct intel_engine_capture_vma * 1415 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1416 struct i915_request *rq, 1417 gfp_t gfp) 1418 { 1419 struct intel_engine_capture_vma *vma = NULL; 1420 1421 ee->simulated |= record_context(&ee->context, rq); 1422 if (ee->simulated) 1423 return NULL; 1424 1425 /* 1426 * We need to copy these to an anonymous buffer 1427 * as the simplest method to avoid being overwritten 1428 * by userspace. 1429 */ 1430 vma = capture_vma(vma, rq->batch, "batch", gfp); 1431 vma = capture_user(vma, rq, gfp); 1432 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1433 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1434 1435 ee->rq_head = rq->head; 1436 ee->rq_post = rq->postfix; 1437 ee->rq_tail = rq->tail; 1438 1439 return vma; 1440 } 1441 1442 void 1443 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1444 struct intel_engine_capture_vma *capture, 1445 struct i915_vma_compress *compress) 1446 { 1447 const struct intel_engine_cs *engine = ee->engine; 1448 1449 while (capture) { 1450 struct intel_engine_capture_vma *this = capture; 1451 struct i915_vma *vma = this->vma; 1452 1453 add_vma(ee, 1454 i915_vma_coredump_create(engine->gt, 1455 vma, this->name, 1456 compress)); 1457 1458 i915_active_release(&vma->active); 1459 i915_vma_put(vma); 1460 1461 capture = this->next; 1462 kfree(this); 1463 } 1464 1465 add_vma(ee, 1466 i915_vma_coredump_create(engine->gt, 1467 engine->status_page.vma, 1468 "HW Status", 1469 compress)); 1470 1471 add_vma(ee, 1472 i915_vma_coredump_create(engine->gt, 1473 engine->wa_ctx.vma, 1474 "WA context", 1475 compress)); 1476 1477 add_vma(ee, 1478 capture_object(engine->gt, 1479 engine->default_state, 1480 "NULL context", 1481 compress)); 1482 } 1483 1484 static struct intel_engine_coredump * 1485 capture_engine(struct intel_engine_cs *engine, 1486 struct i915_vma_compress *compress) 1487 { 1488 struct intel_engine_capture_vma *capture = NULL; 1489 struct intel_engine_coredump *ee; 1490 struct i915_request *rq; 1491 unsigned long flags; 1492 1493 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); 1494 if (!ee) 1495 return NULL; 1496 1497 spin_lock_irqsave(&engine->active.lock, flags); 1498 rq = intel_engine_find_active_request(engine); 1499 if (rq) 1500 capture = intel_engine_coredump_add_request(ee, rq, 1501 ATOMIC_MAYFAIL); 1502 spin_unlock_irqrestore(&engine->active.lock, flags); 1503 if (!capture) { 1504 kfree(ee); 1505 return NULL; 1506 } 1507 1508 intel_engine_coredump_add_vma(ee, capture, compress); 1509 1510 return ee; 1511 } 1512 1513 static void 1514 gt_record_engines(struct intel_gt_coredump *gt, 1515 struct i915_vma_compress *compress) 1516 { 1517 struct intel_engine_cs *engine; 1518 enum intel_engine_id id; 1519 1520 for_each_engine(engine, gt->_gt, id) { 1521 struct intel_engine_coredump *ee; 1522 1523 /* Refill our page pool before entering atomic section */ 1524 pool_refill(&compress->pool, ALLOW_FAIL); 1525 1526 ee = capture_engine(engine, compress); 1527 if (!ee) 1528 continue; 1529 1530 gt->simulated |= ee->simulated; 1531 if (ee->simulated) { 1532 kfree(ee); 1533 continue; 1534 } 1535 1536 ee->next = gt->engine; 1537 gt->engine = ee; 1538 } 1539 } 1540 1541 static struct intel_uc_coredump * 1542 gt_record_uc(struct intel_gt_coredump *gt, 1543 struct i915_vma_compress *compress) 1544 { 1545 const struct intel_uc *uc = >->_gt->uc; 1546 struct intel_uc_coredump *error_uc; 1547 1548 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1549 if (!error_uc) 1550 return NULL; 1551 1552 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1553 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1554 1555 /* Non-default firmware paths will be specified by the modparam. 1556 * As modparams are generally accesible from the userspace make 1557 * explicit copies of the firmware paths. 1558 */ 1559 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1560 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1561 error_uc->guc_log = 1562 i915_vma_coredump_create(gt->_gt, 1563 uc->guc.log.vma, "GuC log buffer", 1564 compress); 1565 1566 return error_uc; 1567 } 1568 1569 static void gt_capture_prepare(struct intel_gt_coredump *gt) 1570 { 1571 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1572 1573 mutex_lock(&ggtt->error_mutex); 1574 } 1575 1576 static void gt_capture_finish(struct intel_gt_coredump *gt) 1577 { 1578 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1579 1580 if (drm_mm_node_allocated(&ggtt->error_capture)) 1581 ggtt->vm.clear_range(&ggtt->vm, 1582 ggtt->error_capture.start, 1583 PAGE_SIZE); 1584 1585 mutex_unlock(&ggtt->error_mutex); 1586 } 1587 1588 /* Capture all registers which don't fit into another category. */ 1589 static void gt_record_regs(struct intel_gt_coredump *gt) 1590 { 1591 struct intel_uncore *uncore = gt->_gt->uncore; 1592 struct drm_i915_private *i915 = uncore->i915; 1593 int i; 1594 1595 /* 1596 * General organization 1597 * 1. Registers specific to a single generation 1598 * 2. Registers which belong to multiple generations 1599 * 3. Feature specific registers. 1600 * 4. Everything else 1601 * Please try to follow the order. 1602 */ 1603 1604 /* 1: Registers specific to a single generation */ 1605 if (IS_VALLEYVIEW(i915)) { 1606 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1607 gt->ier = intel_uncore_read(uncore, VLV_IER); 1608 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1609 } 1610 1611 if (IS_GEN(i915, 7)) 1612 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1613 1614 if (INTEL_GEN(i915) >= 12) { 1615 gt->fault_data0 = intel_uncore_read(uncore, 1616 GEN12_FAULT_TLB_DATA0); 1617 gt->fault_data1 = intel_uncore_read(uncore, 1618 GEN12_FAULT_TLB_DATA1); 1619 } else if (INTEL_GEN(i915) >= 8) { 1620 gt->fault_data0 = intel_uncore_read(uncore, 1621 GEN8_FAULT_TLB_DATA0); 1622 gt->fault_data1 = intel_uncore_read(uncore, 1623 GEN8_FAULT_TLB_DATA1); 1624 } 1625 1626 if (IS_GEN(i915, 6)) { 1627 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1628 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1629 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1630 } 1631 1632 /* 2: Registers which belong to multiple generations */ 1633 if (INTEL_GEN(i915) >= 7) 1634 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1635 1636 if (INTEL_GEN(i915) >= 6) { 1637 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1638 if (INTEL_GEN(i915) < 12) { 1639 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1640 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1641 } 1642 } 1643 1644 /* 3: Feature specific registers */ 1645 if (IS_GEN_RANGE(i915, 6, 7)) { 1646 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1647 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1648 } 1649 1650 if (IS_GEN_RANGE(i915, 8, 11)) 1651 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1652 1653 if (IS_GEN(i915, 12)) 1654 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1655 1656 if (INTEL_GEN(i915) >= 12) { 1657 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1658 gt->sfc_done[i] = 1659 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1660 } 1661 1662 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1663 } 1664 1665 /* 4: Everything else */ 1666 if (INTEL_GEN(i915) >= 11) { 1667 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1668 gt->gtier[0] = 1669 intel_uncore_read(uncore, 1670 GEN11_RENDER_COPY_INTR_ENABLE); 1671 gt->gtier[1] = 1672 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1673 gt->gtier[2] = 1674 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1675 gt->gtier[3] = 1676 intel_uncore_read(uncore, 1677 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1678 gt->gtier[4] = 1679 intel_uncore_read(uncore, 1680 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1681 gt->gtier[5] = 1682 intel_uncore_read(uncore, 1683 GEN11_GUNIT_CSME_INTR_ENABLE); 1684 gt->ngtier = 6; 1685 } else if (INTEL_GEN(i915) >= 8) { 1686 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1687 for (i = 0; i < 4; i++) 1688 gt->gtier[i] = 1689 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1690 gt->ngtier = 4; 1691 } else if (HAS_PCH_SPLIT(i915)) { 1692 gt->ier = intel_uncore_read(uncore, DEIER); 1693 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1694 gt->ngtier = 1; 1695 } else if (IS_GEN(i915, 2)) { 1696 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1697 } else if (!IS_VALLEYVIEW(i915)) { 1698 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1699 } 1700 gt->eir = intel_uncore_read(uncore, EIR); 1701 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1702 } 1703 1704 /* 1705 * Generate a semi-unique error code. The code is not meant to have meaning, The 1706 * code's only purpose is to try to prevent false duplicated bug reports by 1707 * grossly estimating a GPU error state. 1708 * 1709 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1710 * the hang if we could strip the GTT offset information from it. 1711 * 1712 * It's only a small step better than a random number in its current form. 1713 */ 1714 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1715 { 1716 /* 1717 * IPEHR would be an ideal way to detect errors, as it's the gross 1718 * measure of "the command that hung." However, has some very common 1719 * synchronization commands which almost always appear in the case 1720 * strictly a client bug. Use instdone to differentiate those some. 1721 */ 1722 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1723 } 1724 1725 static const char *error_msg(struct i915_gpu_coredump *error) 1726 { 1727 struct intel_engine_coredump *first = NULL; 1728 struct intel_gt_coredump *gt; 1729 intel_engine_mask_t engines; 1730 int len; 1731 1732 engines = 0; 1733 for (gt = error->gt; gt; gt = gt->next) { 1734 struct intel_engine_coredump *cs; 1735 1736 if (gt->engine && !first) 1737 first = gt->engine; 1738 1739 for (cs = gt->engine; cs; cs = cs->next) 1740 engines |= cs->engine->mask; 1741 } 1742 1743 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1744 "GPU HANG: ecode %d:%x:%08x", 1745 INTEL_GEN(error->i915), engines, 1746 generate_ecode(first)); 1747 if (first && first->context.pid) { 1748 /* Just show the first executing process, more is confusing */ 1749 len += scnprintf(error->error_msg + len, 1750 sizeof(error->error_msg) - len, 1751 ", in %s [%d]", 1752 first->context.comm, first->context.pid); 1753 } 1754 1755 return error->error_msg; 1756 } 1757 1758 static void capture_gen(struct i915_gpu_coredump *error) 1759 { 1760 struct drm_i915_private *i915 = error->i915; 1761 1762 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1763 error->suspended = i915->runtime_pm.suspended; 1764 1765 error->iommu = -1; 1766 #ifdef CONFIG_INTEL_IOMMU 1767 error->iommu = intel_iommu_gfx_mapped; 1768 #endif 1769 error->reset_count = i915_reset_count(&i915->gpu_error); 1770 error->suspend_count = i915->suspend_count; 1771 1772 i915_params_copy(&error->params, &i915_modparams); 1773 memcpy(&error->device_info, 1774 INTEL_INFO(i915), 1775 sizeof(error->device_info)); 1776 memcpy(&error->runtime_info, 1777 RUNTIME_INFO(i915), 1778 sizeof(error->runtime_info)); 1779 error->driver_caps = i915->caps; 1780 } 1781 1782 struct i915_gpu_coredump * 1783 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1784 { 1785 struct i915_gpu_coredump *error; 1786 1787 if (!i915_modparams.error_capture) 1788 return NULL; 1789 1790 error = kzalloc(sizeof(*error), gfp); 1791 if (!error) 1792 return NULL; 1793 1794 kref_init(&error->ref); 1795 error->i915 = i915; 1796 1797 error->time = ktime_get_real(); 1798 error->boottime = ktime_get_boottime(); 1799 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); 1800 error->capture = jiffies; 1801 1802 capture_gen(error); 1803 1804 return error; 1805 } 1806 1807 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1808 1809 struct intel_gt_coredump * 1810 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1811 { 1812 struct intel_gt_coredump *gc; 1813 1814 gc = kzalloc(sizeof(*gc), gfp); 1815 if (!gc) 1816 return NULL; 1817 1818 gc->_gt = gt; 1819 gc->awake = intel_gt_pm_is_awake(gt); 1820 1821 gt_record_regs(gc); 1822 gt_record_fences(gc); 1823 1824 return gc; 1825 } 1826 1827 struct i915_vma_compress * 1828 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1829 { 1830 struct i915_vma_compress *compress; 1831 1832 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1833 if (!compress) 1834 return NULL; 1835 1836 if (!compress_init(compress)) { 1837 kfree(compress); 1838 return NULL; 1839 } 1840 1841 gt_capture_prepare(gt); 1842 1843 return compress; 1844 } 1845 1846 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1847 struct i915_vma_compress *compress) 1848 { 1849 if (!compress) 1850 return; 1851 1852 gt_capture_finish(gt); 1853 1854 compress_fini(compress); 1855 kfree(compress); 1856 } 1857 1858 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) 1859 { 1860 struct i915_gpu_coredump *error; 1861 1862 /* Check if GPU capture has been disabled */ 1863 error = READ_ONCE(i915->gpu_error.first_error); 1864 if (IS_ERR(error)) 1865 return error; 1866 1867 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1868 if (!error) 1869 return ERR_PTR(-ENOMEM); 1870 1871 error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL); 1872 if (error->gt) { 1873 struct i915_vma_compress *compress; 1874 1875 compress = i915_vma_capture_prepare(error->gt); 1876 if (!compress) { 1877 kfree(error->gt); 1878 kfree(error); 1879 return ERR_PTR(-ENOMEM); 1880 } 1881 1882 gt_record_engines(error->gt, compress); 1883 1884 if (INTEL_INFO(i915)->has_gt_uc) 1885 error->gt->uc = gt_record_uc(error->gt, compress); 1886 1887 i915_vma_capture_finish(error->gt, compress); 1888 1889 error->simulated |= error->gt->simulated; 1890 } 1891 1892 error->overlay = intel_overlay_capture_error_state(i915); 1893 error->display = intel_display_capture_error_state(i915); 1894 1895 return error; 1896 } 1897 1898 void i915_error_state_store(struct i915_gpu_coredump *error) 1899 { 1900 struct drm_i915_private *i915; 1901 static bool warned; 1902 1903 if (IS_ERR_OR_NULL(error)) 1904 return; 1905 1906 i915 = error->i915; 1907 dev_info(i915->drm.dev, "%s\n", error_msg(error)); 1908 1909 if (error->simulated || 1910 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1911 return; 1912 1913 i915_gpu_coredump_get(error); 1914 1915 if (!xchg(&warned, true) && 1916 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1917 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1918 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1919 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1920 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1921 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1922 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1923 i915->drm.primary->index); 1924 } 1925 } 1926 1927 /** 1928 * i915_capture_error_state - capture an error record for later analysis 1929 * @i915: i915 device 1930 * 1931 * Should be called when an error is detected (either a hang or an error 1932 * interrupt) to capture error state from the time of the error. Fills 1933 * out a structure which becomes available in debugfs for user level tools 1934 * to pick up. 1935 */ 1936 void i915_capture_error_state(struct drm_i915_private *i915) 1937 { 1938 struct i915_gpu_coredump *error; 1939 1940 error = i915_gpu_coredump(i915); 1941 if (IS_ERR(error)) { 1942 cmpxchg(&i915->gpu_error.first_error, NULL, error); 1943 return; 1944 } 1945 1946 i915_error_state_store(error); 1947 i915_gpu_coredump_put(error); 1948 } 1949 1950 struct i915_gpu_coredump * 1951 i915_first_error_state(struct drm_i915_private *i915) 1952 { 1953 struct i915_gpu_coredump *error; 1954 1955 spin_lock_irq(&i915->gpu_error.lock); 1956 error = i915->gpu_error.first_error; 1957 if (!IS_ERR_OR_NULL(error)) 1958 i915_gpu_coredump_get(error); 1959 spin_unlock_irq(&i915->gpu_error.lock); 1960 1961 return error; 1962 } 1963 1964 void i915_reset_error_state(struct drm_i915_private *i915) 1965 { 1966 struct i915_gpu_coredump *error; 1967 1968 spin_lock_irq(&i915->gpu_error.lock); 1969 error = i915->gpu_error.first_error; 1970 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1971 i915->gpu_error.first_error = NULL; 1972 spin_unlock_irq(&i915->gpu_error.lock); 1973 1974 if (!IS_ERR_OR_NULL(error)) 1975 i915_gpu_coredump_put(error); 1976 } 1977 1978 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1979 { 1980 spin_lock_irq(&i915->gpu_error.lock); 1981 if (!i915->gpu_error.first_error) 1982 i915->gpu_error.first_error = ERR_PTR(err); 1983 spin_unlock_irq(&i915->gpu_error.lock); 1984 } 1985