1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_dmc.h" 40 #include "display/intel_overlay.h" 41 42 #include "gem/i915_gem_context.h" 43 #include "gem/i915_gem_lmem.h" 44 #include "gt/intel_gt.h" 45 #include "gt/intel_gt_pm.h" 46 47 #include "i915_drv.h" 48 #include "i915_gpu_error.h" 49 #include "i915_memcpy.h" 50 #include "i915_scatterlist.h" 51 52 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 53 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 54 55 static void __sg_set_buf(struct scatterlist *sg, 56 void *addr, unsigned int len, loff_t it) 57 { 58 STUB(); 59 #ifdef notyet 60 sg->page_link = (unsigned long)virt_to_page(addr); 61 sg->offset = offset_in_page(addr); 62 sg->length = len; 63 sg->dma_address = it; 64 #endif 65 } 66 67 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 68 { 69 STUB(); 70 return false; 71 #ifdef notyet 72 if (!len) 73 return false; 74 75 if (e->bytes + len + 1 <= e->size) 76 return true; 77 78 if (e->bytes) { 79 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 80 e->iter += e->bytes; 81 e->buf = NULL; 82 e->bytes = 0; 83 } 84 85 if (e->cur == e->end) { 86 struct scatterlist *sgl; 87 88 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 89 if (!sgl) { 90 e->err = -ENOMEM; 91 return false; 92 } 93 94 if (e->cur) { 95 e->cur->offset = 0; 96 e->cur->length = 0; 97 e->cur->page_link = 98 (unsigned long)sgl | SG_CHAIN; 99 } else { 100 e->sgl = sgl; 101 } 102 103 e->cur = sgl; 104 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 105 } 106 107 e->size = roundup2(len + 1, SZ_64K); 108 e->buf = kmalloc(e->size, ALLOW_FAIL); 109 if (!e->buf) { 110 e->size = PAGE_ALIGN(len + 1); 111 e->buf = kmalloc(e->size, GFP_KERNEL); 112 } 113 if (!e->buf) { 114 e->err = -ENOMEM; 115 return false; 116 } 117 118 return true; 119 #endif 120 } 121 122 __printf(2, 0) 123 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 124 const char *fmt, va_list args) 125 { 126 va_list ap; 127 int len; 128 129 if (e->err) 130 return; 131 132 va_copy(ap, args); 133 len = vsnprintf(NULL, 0, fmt, ap); 134 va_end(ap); 135 if (len <= 0) { 136 e->err = len; 137 return; 138 } 139 140 if (!__i915_error_grow(e, len)) 141 return; 142 143 GEM_BUG_ON(e->bytes >= e->size); 144 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 145 if (len < 0) { 146 e->err = len; 147 return; 148 } 149 e->bytes += len; 150 } 151 152 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 153 { 154 unsigned len; 155 156 if (e->err || !str) 157 return; 158 159 len = strlen(str); 160 if (!__i915_error_grow(e, len)) 161 return; 162 163 GEM_BUG_ON(e->bytes + len > e->size); 164 memcpy(e->buf + e->bytes, str, len); 165 e->bytes += len; 166 } 167 168 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 169 #define err_puts(e, s) i915_error_puts(e, s) 170 171 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 172 { 173 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 174 } 175 176 static inline struct drm_printer 177 i915_error_printer(struct drm_i915_error_state_buf *e) 178 { 179 struct drm_printer p = { 180 .printfn = __i915_printfn_error, 181 .arg = e, 182 }; 183 return p; 184 } 185 186 /* single threaded page allocator with a reserved stash for emergencies */ 187 static void pool_fini(struct pagevec *pv) 188 { 189 STUB(); 190 #ifdef notyet 191 pagevec_release(pv); 192 #endif 193 } 194 195 static int pool_refill(struct pagevec *pv, gfp_t gfp) 196 { 197 while (pagevec_space(pv)) { 198 struct vm_page *p; 199 200 p = alloc_page(gfp); 201 if (!p) 202 return -ENOMEM; 203 204 pagevec_add(pv, p); 205 } 206 207 return 0; 208 } 209 210 static int intel_pool_init(struct pagevec *pv, gfp_t gfp) 211 { 212 int err; 213 214 pagevec_init(pv); 215 216 err = pool_refill(pv, gfp); 217 if (err) 218 pool_fini(pv); 219 220 return err; 221 } 222 223 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 224 { 225 STUB(); 226 return NULL; 227 #ifdef notyet 228 struct vm_page *p; 229 230 p = alloc_page(gfp); 231 if (!p && pagevec_count(pv)) 232 p = pv->pages[--pv->nr]; 233 234 return p ? page_address(p) : NULL; 235 #endif 236 } 237 238 static void pool_free(struct pagevec *pv, void *addr) 239 { 240 STUB(); 241 #ifdef notyet 242 struct vm_page *p = virt_to_page(addr); 243 244 if (pagevec_space(pv)) 245 pagevec_add(pv, p); 246 else 247 __free_page(p); 248 #endif 249 } 250 251 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 252 253 struct i915_vma_compress { 254 struct pagevec pool; 255 struct z_stream_s zstream; 256 void *tmp; 257 }; 258 259 static bool compress_init(struct i915_vma_compress *c) 260 { 261 struct z_stream_s *zstream = &c->zstream; 262 263 if (intel_pool_init(&c->pool, ALLOW_FAIL)) 264 return false; 265 266 zstream->workspace = 267 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 268 ALLOW_FAIL); 269 if (!zstream->workspace) { 270 pool_fini(&c->pool); 271 return false; 272 } 273 274 c->tmp = NULL; 275 if (i915_has_memcpy_from_wc()) 276 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 277 278 return true; 279 } 280 281 static bool compress_start(struct i915_vma_compress *c) 282 { 283 struct z_stream_s *zstream = &c->zstream; 284 void *workspace = zstream->workspace; 285 286 memset(zstream, 0, sizeof(*zstream)); 287 zstream->workspace = workspace; 288 289 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 290 } 291 292 static void *compress_next_page(struct i915_vma_compress *c, 293 struct i915_vma_coredump *dst) 294 { 295 void *page; 296 297 if (dst->page_count >= dst->num_pages) 298 return ERR_PTR(-ENOSPC); 299 300 page = pool_alloc(&c->pool, ALLOW_FAIL); 301 if (!page) 302 return ERR_PTR(-ENOMEM); 303 304 return dst->pages[dst->page_count++] = page; 305 } 306 307 static int compress_page(struct i915_vma_compress *c, 308 void *src, 309 struct i915_vma_coredump *dst, 310 bool wc) 311 { 312 struct z_stream_s *zstream = &c->zstream; 313 314 zstream->next_in = src; 315 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 316 zstream->next_in = c->tmp; 317 zstream->avail_in = PAGE_SIZE; 318 319 do { 320 if (zstream->avail_out == 0) { 321 zstream->next_out = compress_next_page(c, dst); 322 if (IS_ERR(zstream->next_out)) 323 return PTR_ERR(zstream->next_out); 324 325 zstream->avail_out = PAGE_SIZE; 326 } 327 328 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 329 return -EIO; 330 331 cond_resched(); 332 } while (zstream->avail_in); 333 334 /* Fallback to uncompressed if we increase size? */ 335 if (0 && zstream->total_out > zstream->total_in) 336 return -E2BIG; 337 338 return 0; 339 } 340 341 static int compress_flush(struct i915_vma_compress *c, 342 struct i915_vma_coredump *dst) 343 { 344 struct z_stream_s *zstream = &c->zstream; 345 346 do { 347 switch (zlib_deflate(zstream, Z_FINISH)) { 348 case Z_OK: /* more space requested */ 349 zstream->next_out = compress_next_page(c, dst); 350 if (IS_ERR(zstream->next_out)) 351 return PTR_ERR(zstream->next_out); 352 353 zstream->avail_out = PAGE_SIZE; 354 break; 355 356 case Z_STREAM_END: 357 goto end; 358 359 default: /* any error */ 360 return -EIO; 361 } 362 } while (1); 363 364 end: 365 memset(zstream->next_out, 0, zstream->avail_out); 366 dst->unused = zstream->avail_out; 367 return 0; 368 } 369 370 static void compress_finish(struct i915_vma_compress *c) 371 { 372 zlib_deflateEnd(&c->zstream); 373 } 374 375 static void compress_fini(struct i915_vma_compress *c) 376 { 377 kfree(c->zstream.workspace); 378 if (c->tmp) 379 pool_free(&c->pool, c->tmp); 380 pool_fini(&c->pool); 381 } 382 383 static void err_compression_marker(struct drm_i915_error_state_buf *m) 384 { 385 err_puts(m, ":"); 386 } 387 388 #else 389 390 struct i915_vma_compress { 391 struct pagevec pool; 392 }; 393 394 static bool compress_init(struct i915_vma_compress *c) 395 { 396 return intel_pool_init(&c->pool, ALLOW_FAIL) == 0; 397 } 398 399 static bool compress_start(struct i915_vma_compress *c) 400 { 401 return true; 402 } 403 404 static int compress_page(struct i915_vma_compress *c, 405 void *src, 406 struct i915_vma_coredump *dst, 407 bool wc) 408 { 409 void *ptr; 410 411 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 412 if (!ptr) 413 return -ENOMEM; 414 415 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 416 memcpy(ptr, src, PAGE_SIZE); 417 dst->pages[dst->page_count++] = ptr; 418 cond_resched(); 419 420 return 0; 421 } 422 423 static int compress_flush(struct i915_vma_compress *c, 424 struct i915_vma_coredump *dst) 425 { 426 return 0; 427 } 428 429 static void compress_finish(struct i915_vma_compress *c) 430 { 431 } 432 433 static void compress_fini(struct i915_vma_compress *c) 434 { 435 pool_fini(&c->pool); 436 } 437 438 static void err_compression_marker(struct drm_i915_error_state_buf *m) 439 { 440 err_puts(m, "~"); 441 } 442 443 #endif 444 445 static void error_print_instdone(struct drm_i915_error_state_buf *m, 446 const struct intel_engine_coredump *ee) 447 { 448 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 449 int slice; 450 int subslice; 451 452 err_printf(m, " INSTDONE: 0x%08x\n", 453 ee->instdone.instdone); 454 455 if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3) 456 return; 457 458 err_printf(m, " SC_INSTDONE: 0x%08x\n", 459 ee->instdone.slice_common); 460 461 if (GRAPHICS_VER(m->i915) <= 6) 462 return; 463 464 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 465 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 466 slice, subslice, 467 ee->instdone.sampler[slice][subslice]); 468 469 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 470 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 471 slice, subslice, 472 ee->instdone.row[slice][subslice]); 473 474 if (GRAPHICS_VER(m->i915) < 12) 475 return; 476 477 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 478 ee->instdone.slice_common_extra[0]); 479 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 480 ee->instdone.slice_common_extra[1]); 481 } 482 483 static void error_print_request(struct drm_i915_error_state_buf *m, 484 const char *prefix, 485 const struct i915_request_coredump *erq) 486 { 487 if (!erq->seqno) 488 return; 489 490 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 491 prefix, erq->pid, erq->context, erq->seqno, 492 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 493 &erq->flags) ? "!" : "", 494 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 495 &erq->flags) ? "+" : "", 496 erq->sched_attr.priority, 497 erq->head, erq->tail); 498 } 499 500 static void error_print_context(struct drm_i915_error_state_buf *m, 501 const char *header, 502 const struct i915_gem_context_coredump *ctx) 503 { 504 const u32 period = m->i915->gt.clock_period_ns; 505 506 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 507 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 508 ctx->guilty, ctx->active, 509 ctx->total_runtime * period, 510 mul_u32_u32(ctx->avg_runtime, period)); 511 } 512 513 static struct i915_vma_coredump * 514 __find_vma(struct i915_vma_coredump *vma, const char *name) 515 { 516 while (vma) { 517 if (strcmp(vma->name, name) == 0) 518 return vma; 519 vma = vma->next; 520 } 521 522 return NULL; 523 } 524 525 static struct i915_vma_coredump * 526 find_batch(const struct intel_engine_coredump *ee) 527 { 528 return __find_vma(ee->vma, "batch"); 529 } 530 531 static void error_print_engine(struct drm_i915_error_state_buf *m, 532 const struct intel_engine_coredump *ee) 533 { 534 struct i915_vma_coredump *batch; 535 int n; 536 537 err_printf(m, "%s command stream:\n", ee->engine->name); 538 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 539 err_printf(m, " START: 0x%08x\n", ee->start); 540 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 541 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 542 ee->tail, ee->rq_post, ee->rq_tail); 543 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 544 err_printf(m, " MODE: 0x%08x\n", ee->mode); 545 err_printf(m, " HWS: 0x%08x\n", ee->hws); 546 err_printf(m, " ACTHD: 0x%08x %08x\n", 547 (u32)(ee->acthd>>32), (u32)ee->acthd); 548 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 549 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 550 err_printf(m, " ESR: 0x%08x\n", ee->esr); 551 552 error_print_instdone(m, ee); 553 554 batch = find_batch(ee); 555 if (batch) { 556 u64 start = batch->gtt_offset; 557 u64 end = start + batch->gtt_size; 558 559 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 560 upper_32_bits(start), lower_32_bits(start), 561 upper_32_bits(end), lower_32_bits(end)); 562 } 563 if (GRAPHICS_VER(m->i915) >= 4) { 564 err_printf(m, " BBADDR: 0x%08x_%08x\n", 565 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 566 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 567 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 568 } 569 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 570 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 571 lower_32_bits(ee->faddr)); 572 if (GRAPHICS_VER(m->i915) >= 6) { 573 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 574 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 575 } 576 if (HAS_PPGTT(m->i915)) { 577 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 578 579 if (GRAPHICS_VER(m->i915) >= 8) { 580 int i; 581 for (i = 0; i < 4; i++) 582 err_printf(m, " PDP%d: 0x%016llx\n", 583 i, ee->vm_info.pdp[i]); 584 } else { 585 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 586 ee->vm_info.pp_dir_base); 587 } 588 } 589 err_printf(m, " hung: %u\n", ee->hung); 590 err_printf(m, " engine reset count: %u\n", ee->reset_count); 591 592 for (n = 0; n < ee->num_ports; n++) { 593 err_printf(m, " ELSP[%d]:", n); 594 error_print_request(m, " ", &ee->execlist[n]); 595 } 596 597 error_print_context(m, " Active context: ", &ee->context); 598 } 599 600 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 601 { 602 va_list args; 603 604 va_start(args, f); 605 i915_error_vprintf(e, f, args); 606 va_end(args); 607 } 608 609 static void print_error_vma(struct drm_i915_error_state_buf *m, 610 const struct intel_engine_cs *engine, 611 const struct i915_vma_coredump *vma) 612 { 613 STUB(); 614 #ifdef notyet 615 char out[ASCII85_BUFSZ]; 616 int page; 617 618 if (!vma) 619 return; 620 621 err_printf(m, "%s --- %s = 0x%08x %08x\n", 622 engine ? engine->name : "global", vma->name, 623 upper_32_bits(vma->gtt_offset), 624 lower_32_bits(vma->gtt_offset)); 625 626 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 627 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 628 629 err_compression_marker(m); 630 for (page = 0; page < vma->page_count; page++) { 631 int i, len; 632 633 len = PAGE_SIZE; 634 if (page == vma->page_count - 1) 635 len -= vma->unused; 636 len = ascii85_encode_len(len); 637 638 for (i = 0; i < len; i++) 639 err_puts(m, ascii85_encode(vma->pages[page][i], out)); 640 } 641 err_puts(m, "\n"); 642 #endif 643 } 644 645 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 646 struct i915_gpu_coredump *error) 647 { 648 struct drm_printer p = i915_error_printer(m); 649 650 intel_device_info_print_static(&error->device_info, &p); 651 intel_device_info_print_runtime(&error->runtime_info, &p); 652 intel_driver_caps_print(&error->driver_caps, &p); 653 } 654 655 static void err_print_params(struct drm_i915_error_state_buf *m, 656 const struct i915_params *params) 657 { 658 struct drm_printer p = i915_error_printer(m); 659 660 i915_params_dump(params, &p); 661 } 662 663 static void err_print_pciid(struct drm_i915_error_state_buf *m, 664 struct drm_i915_private *i915) 665 { 666 struct pci_dev *pdev = i915->drm.pdev; 667 668 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 669 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 670 err_printf(m, "PCI Subsystem: %04x:%04x\n", 671 pdev->subsystem_vendor, 672 pdev->subsystem_device); 673 } 674 675 static void err_print_uc(struct drm_i915_error_state_buf *m, 676 const struct intel_uc_coredump *error_uc) 677 { 678 struct drm_printer p = i915_error_printer(m); 679 680 intel_uc_fw_dump(&error_uc->guc_fw, &p); 681 intel_uc_fw_dump(&error_uc->huc_fw, &p); 682 print_error_vma(m, NULL, error_uc->guc_log); 683 } 684 685 static void err_free_sgl(struct scatterlist *sgl) 686 { 687 STUB(); 688 #ifdef notyet 689 while (sgl) { 690 struct scatterlist *sg; 691 692 for (sg = sgl; !sg_is_chain(sg); sg++) { 693 kfree(sg_virt(sg)); 694 if (sg_is_last(sg)) 695 break; 696 } 697 698 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 699 free_page((unsigned long)sgl); 700 sgl = sg; 701 } 702 #endif 703 } 704 705 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 706 struct intel_gt_coredump *gt) 707 { 708 struct drm_printer p = i915_error_printer(m); 709 710 intel_gt_info_print(>->info, &p); 711 intel_sseu_print_topology(>->info.sseu, &p); 712 } 713 714 static void err_print_gt(struct drm_i915_error_state_buf *m, 715 struct intel_gt_coredump *gt) 716 { 717 const struct intel_engine_coredump *ee; 718 int i; 719 720 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 721 err_printf(m, "EIR: 0x%08x\n", gt->eir); 722 err_printf(m, "IER: 0x%08x\n", gt->ier); 723 for (i = 0; i < gt->ngtier; i++) 724 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 725 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 726 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 727 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 728 729 for (i = 0; i < gt->nfence; i++) 730 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 731 732 if (IS_GRAPHICS_VER(m->i915, 6, 11)) { 733 err_printf(m, "ERROR: 0x%08x\n", gt->error); 734 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 735 } 736 737 if (GRAPHICS_VER(m->i915) >= 8) 738 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 739 gt->fault_data1, gt->fault_data0); 740 741 if (GRAPHICS_VER(m->i915) == 7) 742 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 743 744 if (IS_GRAPHICS_VER(m->i915, 8, 11)) 745 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 746 747 if (GRAPHICS_VER(m->i915) == 12) 748 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 749 750 if (GRAPHICS_VER(m->i915) >= 12) { 751 int i; 752 753 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 754 /* 755 * SFC_DONE resides in the VD forcewake domain, so it 756 * only exists if the corresponding VCS engine is 757 * present. 758 */ 759 if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) 760 continue; 761 762 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 763 gt->sfc_done[i]); 764 } 765 766 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 767 } 768 769 for (ee = gt->engine; ee; ee = ee->next) { 770 const struct i915_vma_coredump *vma; 771 772 error_print_engine(m, ee); 773 for (vma = ee->vma; vma; vma = vma->next) 774 print_error_vma(m, ee->engine, vma); 775 } 776 777 if (gt->uc) 778 err_print_uc(m, gt->uc); 779 780 err_print_gt_info(m, gt); 781 } 782 783 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 784 struct i915_gpu_coredump *error) 785 { 786 const struct intel_engine_coredump *ee; 787 struct timespec64 ts; 788 789 if (*error->error_msg) 790 err_printf(m, "%s\n", error->error_msg); 791 #ifdef __linux__ 792 err_printf(m, "Kernel: %s %s\n", 793 init_utsname()->release, 794 init_utsname()->machine); 795 #else 796 extern char machine[]; 797 err_printf(m, "Kernel: %s %s\n", 798 osrelease, 799 machine); 800 #endif 801 err_printf(m, "Driver: %s\n", DRIVER_DATE); 802 ts = ktime_to_timespec64(error->time); 803 err_printf(m, "Time: %lld s %ld us\n", 804 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 805 ts = ktime_to_timespec64(error->boottime); 806 err_printf(m, "Boottime: %lld s %ld us\n", 807 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 808 ts = ktime_to_timespec64(error->uptime); 809 err_printf(m, "Uptime: %lld s %ld us\n", 810 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 811 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 812 error->capture, jiffies_to_msecs(jiffies - error->capture)); 813 814 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 815 err_printf(m, "Active process (on ring %s): %s [%d]\n", 816 ee->engine->name, 817 ee->context.comm, 818 ee->context.pid); 819 820 err_printf(m, "Reset count: %u\n", error->reset_count); 821 err_printf(m, "Suspend count: %u\n", error->suspend_count); 822 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 823 err_printf(m, "Subplatform: 0x%x\n", 824 intel_subplatform(&error->runtime_info, 825 error->device_info.platform)); 826 err_print_pciid(m, m->i915); 827 828 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 829 830 if (HAS_DMC(m->i915)) { 831 struct intel_dmc *dmc = &m->i915->dmc; 832 833 err_printf(m, "DMC loaded: %s\n", 834 yesno(intel_dmc_has_payload(m->i915) != 0)); 835 err_printf(m, "DMC fw version: %d.%d\n", 836 DMC_VERSION_MAJOR(dmc->version), 837 DMC_VERSION_MINOR(dmc->version)); 838 } 839 840 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 841 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 842 843 if (error->gt) 844 err_print_gt(m, error->gt); 845 846 if (error->overlay) 847 intel_overlay_print_error_state(m, error->overlay); 848 849 err_print_capabilities(m, error); 850 err_print_params(m, &error->params); 851 } 852 853 static int err_print_to_sgl(struct i915_gpu_coredump *error) 854 { 855 struct drm_i915_error_state_buf m; 856 857 if (IS_ERR(error)) 858 return PTR_ERR(error); 859 860 if (READ_ONCE(error->sgl)) 861 return 0; 862 863 memset(&m, 0, sizeof(m)); 864 m.i915 = error->i915; 865 866 __err_print_to_sgl(&m, error); 867 868 if (m.buf) { 869 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 870 m.bytes = 0; 871 m.buf = NULL; 872 } 873 if (m.cur) { 874 GEM_BUG_ON(m.end < m.cur); 875 sg_mark_end(m.cur - 1); 876 } 877 GEM_BUG_ON(m.sgl && !m.cur); 878 879 if (m.err) { 880 err_free_sgl(m.sgl); 881 return m.err; 882 } 883 884 if (cmpxchg(&error->sgl, NULL, m.sgl)) 885 err_free_sgl(m.sgl); 886 887 return 0; 888 } 889 890 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 891 char *buf, loff_t off, size_t rem) 892 { 893 STUB(); 894 return -ENOSYS; 895 #ifdef notyet 896 struct scatterlist *sg; 897 size_t count; 898 loff_t pos; 899 int err; 900 901 if (!error || !rem) 902 return 0; 903 904 err = err_print_to_sgl(error); 905 if (err) 906 return err; 907 908 sg = READ_ONCE(error->fit); 909 if (!sg || off < sg->dma_address) 910 sg = error->sgl; 911 if (!sg) 912 return 0; 913 914 pos = sg->dma_address; 915 count = 0; 916 do { 917 size_t len, start; 918 919 if (sg_is_chain(sg)) { 920 sg = sg_chain_ptr(sg); 921 GEM_BUG_ON(sg_is_chain(sg)); 922 } 923 924 len = sg->length; 925 if (pos + len <= off) { 926 pos += len; 927 continue; 928 } 929 930 start = sg->offset; 931 if (pos < off) { 932 GEM_BUG_ON(off - pos > len); 933 len -= off - pos; 934 start += off - pos; 935 pos = off; 936 } 937 938 len = min(len, rem); 939 GEM_BUG_ON(!len || len > sg->length); 940 941 memcpy(buf, page_address(sg_page(sg)) + start, len); 942 943 count += len; 944 pos += len; 945 946 buf += len; 947 rem -= len; 948 if (!rem) { 949 WRITE_ONCE(error->fit, sg); 950 break; 951 } 952 } while (!sg_is_last(sg++)); 953 954 return count; 955 #endif 956 } 957 958 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 959 { 960 while (vma) { 961 struct i915_vma_coredump *next = vma->next; 962 int page; 963 964 for (page = 0; page < vma->page_count; page++) 965 free_page((unsigned long)vma->pages[page]); 966 967 kfree(vma); 968 vma = next; 969 } 970 } 971 972 static void cleanup_params(struct i915_gpu_coredump *error) 973 { 974 i915_params_free(&error->params); 975 } 976 977 static void cleanup_uc(struct intel_uc_coredump *uc) 978 { 979 kfree(uc->guc_fw.path); 980 kfree(uc->huc_fw.path); 981 i915_vma_coredump_free(uc->guc_log); 982 983 kfree(uc); 984 } 985 986 static void cleanup_gt(struct intel_gt_coredump *gt) 987 { 988 while (gt->engine) { 989 struct intel_engine_coredump *ee = gt->engine; 990 991 gt->engine = ee->next; 992 993 i915_vma_coredump_free(ee->vma); 994 kfree(ee); 995 } 996 997 if (gt->uc) 998 cleanup_uc(gt->uc); 999 1000 kfree(gt); 1001 } 1002 1003 void __i915_gpu_coredump_free(struct kref *error_ref) 1004 { 1005 struct i915_gpu_coredump *error = 1006 container_of(error_ref, typeof(*error), ref); 1007 1008 while (error->gt) { 1009 struct intel_gt_coredump *gt = error->gt; 1010 1011 error->gt = gt->next; 1012 cleanup_gt(gt); 1013 } 1014 1015 kfree(error->overlay); 1016 1017 cleanup_params(error); 1018 1019 err_free_sgl(error->sgl); 1020 kfree(error); 1021 } 1022 1023 static struct i915_vma_coredump * 1024 i915_vma_coredump_create(const struct intel_gt *gt, 1025 const struct i915_vma *vma, 1026 const char *name, 1027 struct i915_vma_compress *compress) 1028 { 1029 STUB(); 1030 return NULL; 1031 #ifdef notyet 1032 struct i915_ggtt *ggtt = gt->ggtt; 1033 const u64 slot = ggtt->error_capture.start; 1034 struct i915_vma_coredump *dst; 1035 unsigned long num_pages; 1036 struct sgt_iter iter; 1037 int ret; 1038 1039 might_sleep(); 1040 1041 if (!vma || !vma->pages || !compress) 1042 return NULL; 1043 1044 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 1045 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 1046 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); 1047 if (!dst) 1048 return NULL; 1049 1050 if (!compress_start(compress)) { 1051 kfree(dst); 1052 return NULL; 1053 } 1054 1055 strlcpy(dst->name, name, sizeof(dst->name)); 1056 dst->next = NULL; 1057 1058 dst->gtt_offset = vma->node.start; 1059 dst->gtt_size = vma->node.size; 1060 dst->gtt_page_sizes = vma->page_sizes.gtt; 1061 dst->num_pages = num_pages; 1062 dst->page_count = 0; 1063 dst->unused = 0; 1064 1065 ret = -EINVAL; 1066 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1067 void __iomem *s; 1068 dma_addr_t dma; 1069 1070 for_each_sgt_daddr(dma, iter, vma->pages) { 1071 mutex_lock(&ggtt->error_mutex); 1072 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1073 I915_CACHE_NONE, 0); 1074 mb(); 1075 1076 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1077 ret = compress_page(compress, 1078 (void __force *)s, dst, 1079 true); 1080 io_mapping_unmap(s); 1081 1082 mb(); 1083 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE); 1084 mutex_unlock(&ggtt->error_mutex); 1085 if (ret) 1086 break; 1087 } 1088 } else if (__i915_gem_object_is_lmem(vma->obj)) { 1089 struct intel_memory_region *mem = vma->obj->mm.region; 1090 dma_addr_t dma; 1091 1092 for_each_sgt_daddr(dma, iter, vma->pages) { 1093 void __iomem *s; 1094 1095 s = io_mapping_map_wc(&mem->iomap, 1096 dma - mem->region.start, 1097 PAGE_SIZE); 1098 ret = compress_page(compress, 1099 (void __force *)s, dst, 1100 true); 1101 io_mapping_unmap(s); 1102 if (ret) 1103 break; 1104 } 1105 } else { 1106 struct vm_page *page; 1107 1108 for_each_sgt_page(page, iter, vma->pages) { 1109 void *s; 1110 1111 drm_clflush_pages(&page, 1); 1112 1113 s = kmap(page); 1114 ret = compress_page(compress, s, dst, false); 1115 kunmap(page); 1116 1117 drm_clflush_pages(&page, 1); 1118 1119 if (ret) 1120 break; 1121 } 1122 } 1123 1124 if (ret || compress_flush(compress, dst)) { 1125 while (dst->page_count--) 1126 pool_free(&compress->pool, dst->pages[dst->page_count]); 1127 kfree(dst); 1128 dst = NULL; 1129 } 1130 compress_finish(compress); 1131 1132 return dst; 1133 #endif 1134 } 1135 1136 static void gt_record_fences(struct intel_gt_coredump *gt) 1137 { 1138 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1139 struct intel_uncore *uncore = gt->_gt->uncore; 1140 int i; 1141 1142 if (GRAPHICS_VER(uncore->i915) >= 6) { 1143 for (i = 0; i < ggtt->num_fences; i++) 1144 gt->fence[i] = 1145 intel_uncore_read64(uncore, 1146 FENCE_REG_GEN6_LO(i)); 1147 } else if (GRAPHICS_VER(uncore->i915) >= 4) { 1148 for (i = 0; i < ggtt->num_fences; i++) 1149 gt->fence[i] = 1150 intel_uncore_read64(uncore, 1151 FENCE_REG_965_LO(i)); 1152 } else { 1153 for (i = 0; i < ggtt->num_fences; i++) 1154 gt->fence[i] = 1155 intel_uncore_read(uncore, FENCE_REG(i)); 1156 } 1157 gt->nfence = i; 1158 } 1159 1160 static void engine_record_registers(struct intel_engine_coredump *ee) 1161 { 1162 const struct intel_engine_cs *engine = ee->engine; 1163 struct drm_i915_private *i915 = engine->i915; 1164 1165 if (GRAPHICS_VER(i915) >= 6) { 1166 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1167 1168 if (GRAPHICS_VER(i915) >= 12) 1169 ee->fault_reg = intel_uncore_read(engine->uncore, 1170 GEN12_RING_FAULT_REG); 1171 else if (GRAPHICS_VER(i915) >= 8) 1172 ee->fault_reg = intel_uncore_read(engine->uncore, 1173 GEN8_RING_FAULT_REG); 1174 else 1175 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1176 } 1177 1178 if (GRAPHICS_VER(i915) >= 4) { 1179 ee->esr = ENGINE_READ(engine, RING_ESR); 1180 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1181 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1182 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1183 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1184 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1185 ee->ccid = ENGINE_READ(engine, CCID); 1186 if (GRAPHICS_VER(i915) >= 8) { 1187 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1188 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1189 } 1190 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1191 } else { 1192 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1193 ee->ipeir = ENGINE_READ(engine, IPEIR); 1194 ee->ipehr = ENGINE_READ(engine, IPEHR); 1195 } 1196 1197 intel_engine_get_instdone(engine, &ee->instdone); 1198 1199 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1200 ee->acthd = intel_engine_get_active_head(engine); 1201 ee->start = ENGINE_READ(engine, RING_START); 1202 ee->head = ENGINE_READ(engine, RING_HEAD); 1203 ee->tail = ENGINE_READ(engine, RING_TAIL); 1204 ee->ctl = ENGINE_READ(engine, RING_CTL); 1205 if (GRAPHICS_VER(i915) > 2) 1206 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1207 1208 if (!HWS_NEEDS_PHYSICAL(i915)) { 1209 i915_reg_t mmio; 1210 1211 if (GRAPHICS_VER(i915) == 7) { 1212 switch (engine->id) { 1213 default: 1214 MISSING_CASE(engine->id); 1215 fallthrough; 1216 case RCS0: 1217 mmio = RENDER_HWS_PGA_GEN7; 1218 break; 1219 case BCS0: 1220 mmio = BLT_HWS_PGA_GEN7; 1221 break; 1222 case VCS0: 1223 mmio = BSD_HWS_PGA_GEN7; 1224 break; 1225 case VECS0: 1226 mmio = VEBOX_HWS_PGA_GEN7; 1227 break; 1228 } 1229 } else if (GRAPHICS_VER(engine->i915) == 6) { 1230 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1231 } else { 1232 /* XXX: gen8 returns to sanity */ 1233 mmio = RING_HWS_PGA(engine->mmio_base); 1234 } 1235 1236 ee->hws = intel_uncore_read(engine->uncore, mmio); 1237 } 1238 1239 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1240 1241 if (HAS_PPGTT(i915)) { 1242 int i; 1243 1244 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1245 1246 if (GRAPHICS_VER(i915) == 6) { 1247 ee->vm_info.pp_dir_base = 1248 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1249 } else if (GRAPHICS_VER(i915) == 7) { 1250 ee->vm_info.pp_dir_base = 1251 ENGINE_READ(engine, RING_PP_DIR_BASE); 1252 } else if (GRAPHICS_VER(i915) >= 8) { 1253 u32 base = engine->mmio_base; 1254 1255 for (i = 0; i < 4; i++) { 1256 ee->vm_info.pdp[i] = 1257 intel_uncore_read(engine->uncore, 1258 GEN8_RING_PDP_UDW(base, i)); 1259 ee->vm_info.pdp[i] <<= 32; 1260 ee->vm_info.pdp[i] |= 1261 intel_uncore_read(engine->uncore, 1262 GEN8_RING_PDP_LDW(base, i)); 1263 } 1264 } 1265 } 1266 } 1267 1268 static void record_request(const struct i915_request *request, 1269 struct i915_request_coredump *erq) 1270 { 1271 erq->flags = request->fence.flags; 1272 erq->context = request->fence.context; 1273 erq->seqno = request->fence.seqno; 1274 erq->sched_attr = request->sched.attr; 1275 erq->head = request->head; 1276 erq->tail = request->tail; 1277 1278 erq->pid = 0; 1279 rcu_read_lock(); 1280 if (!intel_context_is_closed(request->context)) { 1281 const struct i915_gem_context *ctx; 1282 1283 ctx = rcu_dereference(request->context->gem_context); 1284 if (ctx) 1285 #ifdef __linux__ 1286 erq->pid = pid_nr(ctx->pid); 1287 #else 1288 erq->pid = ctx->pid; 1289 #endif 1290 } 1291 rcu_read_unlock(); 1292 } 1293 1294 static void engine_record_execlists(struct intel_engine_coredump *ee) 1295 { 1296 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1297 struct i915_request * const *port = el->active; 1298 unsigned int n = 0; 1299 1300 while (*port) 1301 record_request(*port++, &ee->execlist[n++]); 1302 1303 ee->num_ports = n; 1304 } 1305 1306 static bool record_context(struct i915_gem_context_coredump *e, 1307 const struct i915_request *rq) 1308 { 1309 struct i915_gem_context *ctx; 1310 struct task_struct *task; 1311 bool simulated; 1312 1313 rcu_read_lock(); 1314 ctx = rcu_dereference(rq->context->gem_context); 1315 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1316 ctx = NULL; 1317 rcu_read_unlock(); 1318 if (!ctx) 1319 return true; 1320 1321 #ifdef __linux__ 1322 rcu_read_lock(); 1323 task = pid_task(ctx->pid, PIDTYPE_PID); 1324 if (task) { 1325 strcpy(e->comm, task->comm); 1326 e->pid = task->pid; 1327 } 1328 rcu_read_unlock(); 1329 #endif 1330 1331 e->sched_attr = ctx->sched; 1332 e->guilty = atomic_read(&ctx->guilty_count); 1333 e->active = atomic_read(&ctx->active_count); 1334 1335 e->total_runtime = rq->context->runtime.total; 1336 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1337 1338 simulated = i915_gem_context_no_error_capture(ctx); 1339 1340 i915_gem_context_put(ctx); 1341 return simulated; 1342 } 1343 1344 struct intel_engine_capture_vma { 1345 struct intel_engine_capture_vma *next; 1346 struct i915_vma *vma; 1347 char name[16]; 1348 }; 1349 1350 static struct intel_engine_capture_vma * 1351 capture_vma(struct intel_engine_capture_vma *next, 1352 struct i915_vma *vma, 1353 const char *name, 1354 gfp_t gfp) 1355 { 1356 struct intel_engine_capture_vma *c; 1357 1358 if (!vma) 1359 return next; 1360 1361 c = kmalloc(sizeof(*c), gfp); 1362 if (!c) 1363 return next; 1364 1365 if (!i915_active_acquire_if_busy(&vma->active)) { 1366 kfree(c); 1367 return next; 1368 } 1369 1370 strlcpy(c->name, name, sizeof(c->name)); 1371 c->vma = vma; /* reference held while active */ 1372 1373 c->next = next; 1374 return c; 1375 } 1376 1377 static struct intel_engine_capture_vma * 1378 capture_user(struct intel_engine_capture_vma *capture, 1379 const struct i915_request *rq, 1380 gfp_t gfp) 1381 { 1382 struct i915_capture_list *c; 1383 1384 for (c = rq->capture_list; c; c = c->next) 1385 capture = capture_vma(capture, c->vma, "user", gfp); 1386 1387 return capture; 1388 } 1389 1390 static void add_vma(struct intel_engine_coredump *ee, 1391 struct i915_vma_coredump *vma) 1392 { 1393 if (vma) { 1394 vma->next = ee->vma; 1395 ee->vma = vma; 1396 } 1397 } 1398 1399 struct intel_engine_coredump * 1400 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1401 { 1402 struct intel_engine_coredump *ee; 1403 1404 ee = kzalloc(sizeof(*ee), gfp); 1405 if (!ee) 1406 return NULL; 1407 1408 ee->engine = engine; 1409 1410 engine_record_registers(ee); 1411 engine_record_execlists(ee); 1412 1413 return ee; 1414 } 1415 1416 struct intel_engine_capture_vma * 1417 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1418 struct i915_request *rq, 1419 gfp_t gfp) 1420 { 1421 struct intel_engine_capture_vma *vma = NULL; 1422 1423 ee->simulated |= record_context(&ee->context, rq); 1424 if (ee->simulated) 1425 return NULL; 1426 1427 /* 1428 * We need to copy these to an anonymous buffer 1429 * as the simplest method to avoid being overwritten 1430 * by userspace. 1431 */ 1432 vma = capture_vma(vma, rq->batch, "batch", gfp); 1433 vma = capture_user(vma, rq, gfp); 1434 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1435 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1436 1437 ee->rq_head = rq->head; 1438 ee->rq_post = rq->postfix; 1439 ee->rq_tail = rq->tail; 1440 1441 return vma; 1442 } 1443 1444 void 1445 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1446 struct intel_engine_capture_vma *capture, 1447 struct i915_vma_compress *compress) 1448 { 1449 const struct intel_engine_cs *engine = ee->engine; 1450 1451 while (capture) { 1452 struct intel_engine_capture_vma *this = capture; 1453 struct i915_vma *vma = this->vma; 1454 1455 add_vma(ee, 1456 i915_vma_coredump_create(engine->gt, 1457 vma, this->name, 1458 compress)); 1459 1460 i915_active_release(&vma->active); 1461 1462 capture = this->next; 1463 kfree(this); 1464 } 1465 1466 add_vma(ee, 1467 i915_vma_coredump_create(engine->gt, 1468 engine->status_page.vma, 1469 "HW Status", 1470 compress)); 1471 1472 add_vma(ee, 1473 i915_vma_coredump_create(engine->gt, 1474 engine->wa_ctx.vma, 1475 "WA context", 1476 compress)); 1477 } 1478 1479 static struct intel_engine_coredump * 1480 capture_engine(struct intel_engine_cs *engine, 1481 struct i915_vma_compress *compress) 1482 { 1483 struct intel_engine_capture_vma *capture = NULL; 1484 struct intel_engine_coredump *ee; 1485 struct intel_context *ce; 1486 struct i915_request *rq = NULL; 1487 unsigned long flags; 1488 1489 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); 1490 if (!ee) 1491 return NULL; 1492 1493 ce = intel_engine_get_hung_context(engine); 1494 if (ce) { 1495 intel_engine_clear_hung_context(engine); 1496 rq = intel_context_find_active_request(ce); 1497 if (!rq || !i915_request_started(rq)) 1498 goto no_request_capture; 1499 } else { 1500 /* 1501 * Getting here with GuC enabled means it is a forced error capture 1502 * with no actual hang. So, no need to attempt the execlist search. 1503 */ 1504 if (!intel_uc_uses_guc_submission(&engine->gt->uc)) { 1505 spin_lock_irqsave(&engine->sched_engine->lock, flags); 1506 rq = intel_engine_execlist_find_hung_request(engine); 1507 spin_unlock_irqrestore(&engine->sched_engine->lock, 1508 flags); 1509 } 1510 } 1511 if (rq) 1512 capture = intel_engine_coredump_add_request(ee, rq, 1513 ATOMIC_MAYFAIL); 1514 if (!capture) { 1515 no_request_capture: 1516 kfree(ee); 1517 return NULL; 1518 } 1519 1520 intel_engine_coredump_add_vma(ee, capture, compress); 1521 1522 return ee; 1523 } 1524 1525 static void 1526 gt_record_engines(struct intel_gt_coredump *gt, 1527 intel_engine_mask_t engine_mask, 1528 struct i915_vma_compress *compress) 1529 { 1530 struct intel_engine_cs *engine; 1531 enum intel_engine_id id; 1532 1533 for_each_engine(engine, gt->_gt, id) { 1534 struct intel_engine_coredump *ee; 1535 1536 /* Refill our page pool before entering atomic section */ 1537 pool_refill(&compress->pool, ALLOW_FAIL); 1538 1539 ee = capture_engine(engine, compress); 1540 if (!ee) 1541 continue; 1542 1543 ee->hung = engine->mask & engine_mask; 1544 1545 gt->simulated |= ee->simulated; 1546 if (ee->simulated) { 1547 kfree(ee); 1548 continue; 1549 } 1550 1551 ee->next = gt->engine; 1552 gt->engine = ee; 1553 } 1554 } 1555 1556 static struct intel_uc_coredump * 1557 gt_record_uc(struct intel_gt_coredump *gt, 1558 struct i915_vma_compress *compress) 1559 { 1560 const struct intel_uc *uc = >->_gt->uc; 1561 struct intel_uc_coredump *error_uc; 1562 1563 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1564 if (!error_uc) 1565 return NULL; 1566 1567 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1568 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1569 1570 /* Non-default firmware paths will be specified by the modparam. 1571 * As modparams are generally accesible from the userspace make 1572 * explicit copies of the firmware paths. 1573 */ 1574 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1575 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1576 error_uc->guc_log = 1577 i915_vma_coredump_create(gt->_gt, 1578 uc->guc.log.vma, "GuC log buffer", 1579 compress); 1580 1581 return error_uc; 1582 } 1583 1584 /* Capture all registers which don't fit into another category. */ 1585 static void gt_record_regs(struct intel_gt_coredump *gt) 1586 { 1587 struct intel_uncore *uncore = gt->_gt->uncore; 1588 struct drm_i915_private *i915 = uncore->i915; 1589 int i; 1590 1591 /* 1592 * General organization 1593 * 1. Registers specific to a single generation 1594 * 2. Registers which belong to multiple generations 1595 * 3. Feature specific registers. 1596 * 4. Everything else 1597 * Please try to follow the order. 1598 */ 1599 1600 /* 1: Registers specific to a single generation */ 1601 if (IS_VALLEYVIEW(i915)) { 1602 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1603 gt->ier = intel_uncore_read(uncore, VLV_IER); 1604 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1605 } 1606 1607 if (GRAPHICS_VER(i915) == 7) 1608 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1609 1610 if (GRAPHICS_VER(i915) >= 12) { 1611 gt->fault_data0 = intel_uncore_read(uncore, 1612 GEN12_FAULT_TLB_DATA0); 1613 gt->fault_data1 = intel_uncore_read(uncore, 1614 GEN12_FAULT_TLB_DATA1); 1615 } else if (GRAPHICS_VER(i915) >= 8) { 1616 gt->fault_data0 = intel_uncore_read(uncore, 1617 GEN8_FAULT_TLB_DATA0); 1618 gt->fault_data1 = intel_uncore_read(uncore, 1619 GEN8_FAULT_TLB_DATA1); 1620 } 1621 1622 if (GRAPHICS_VER(i915) == 6) { 1623 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1624 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1625 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1626 } 1627 1628 /* 2: Registers which belong to multiple generations */ 1629 if (GRAPHICS_VER(i915) >= 7) 1630 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1631 1632 if (GRAPHICS_VER(i915) >= 6) { 1633 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1634 if (GRAPHICS_VER(i915) < 12) { 1635 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1636 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1637 } 1638 } 1639 1640 /* 3: Feature specific registers */ 1641 if (IS_GRAPHICS_VER(i915, 6, 7)) { 1642 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1643 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1644 } 1645 1646 if (IS_GRAPHICS_VER(i915, 8, 11)) 1647 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1648 1649 if (GRAPHICS_VER(i915) == 12) 1650 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1651 1652 if (GRAPHICS_VER(i915) >= 12) { 1653 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1654 /* 1655 * SFC_DONE resides in the VD forcewake domain, so it 1656 * only exists if the corresponding VCS engine is 1657 * present. 1658 */ 1659 if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1660 continue; 1661 1662 gt->sfc_done[i] = 1663 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1664 } 1665 1666 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1667 } 1668 1669 /* 4: Everything else */ 1670 if (GRAPHICS_VER(i915) >= 11) { 1671 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1672 gt->gtier[0] = 1673 intel_uncore_read(uncore, 1674 GEN11_RENDER_COPY_INTR_ENABLE); 1675 gt->gtier[1] = 1676 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1677 gt->gtier[2] = 1678 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1679 gt->gtier[3] = 1680 intel_uncore_read(uncore, 1681 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1682 gt->gtier[4] = 1683 intel_uncore_read(uncore, 1684 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1685 gt->gtier[5] = 1686 intel_uncore_read(uncore, 1687 GEN11_GUNIT_CSME_INTR_ENABLE); 1688 gt->ngtier = 6; 1689 } else if (GRAPHICS_VER(i915) >= 8) { 1690 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1691 for (i = 0; i < 4; i++) 1692 gt->gtier[i] = 1693 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1694 gt->ngtier = 4; 1695 } else if (HAS_PCH_SPLIT(i915)) { 1696 gt->ier = intel_uncore_read(uncore, DEIER); 1697 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1698 gt->ngtier = 1; 1699 } else if (GRAPHICS_VER(i915) == 2) { 1700 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1701 } else if (!IS_VALLEYVIEW(i915)) { 1702 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1703 } 1704 gt->eir = intel_uncore_read(uncore, EIR); 1705 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1706 } 1707 1708 static void gt_record_info(struct intel_gt_coredump *gt) 1709 { 1710 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1711 } 1712 1713 /* 1714 * Generate a semi-unique error code. The code is not meant to have meaning, The 1715 * code's only purpose is to try to prevent false duplicated bug reports by 1716 * grossly estimating a GPU error state. 1717 * 1718 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1719 * the hang if we could strip the GTT offset information from it. 1720 * 1721 * It's only a small step better than a random number in its current form. 1722 */ 1723 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1724 { 1725 /* 1726 * IPEHR would be an ideal way to detect errors, as it's the gross 1727 * measure of "the command that hung." However, has some very common 1728 * synchronization commands which almost always appear in the case 1729 * strictly a client bug. Use instdone to differentiate those some. 1730 */ 1731 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1732 } 1733 1734 static const char *error_msg(struct i915_gpu_coredump *error) 1735 { 1736 struct intel_engine_coredump *first = NULL; 1737 unsigned int hung_classes = 0; 1738 struct intel_gt_coredump *gt; 1739 int len; 1740 1741 for (gt = error->gt; gt; gt = gt->next) { 1742 struct intel_engine_coredump *cs; 1743 1744 for (cs = gt->engine; cs; cs = cs->next) { 1745 if (cs->hung) { 1746 hung_classes |= BIT(cs->engine->uabi_class); 1747 if (!first) 1748 first = cs; 1749 } 1750 } 1751 } 1752 1753 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1754 "GPU HANG: ecode %d:%x:%08x", 1755 GRAPHICS_VER(error->i915), hung_classes, 1756 generate_ecode(first)); 1757 if (first && first->context.pid) { 1758 /* Just show the first executing process, more is confusing */ 1759 len += scnprintf(error->error_msg + len, 1760 sizeof(error->error_msg) - len, 1761 ", in %s [%d]", 1762 first->context.comm, first->context.pid); 1763 } 1764 1765 return error->error_msg; 1766 } 1767 1768 static void capture_gen(struct i915_gpu_coredump *error) 1769 { 1770 struct drm_i915_private *i915 = error->i915; 1771 1772 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1773 error->suspended = i915->runtime_pm.suspended; 1774 1775 error->iommu = -1; 1776 #ifdef CONFIG_INTEL_IOMMU 1777 error->iommu = intel_iommu_gfx_mapped; 1778 #endif 1779 error->reset_count = i915_reset_count(&i915->gpu_error); 1780 error->suspend_count = i915->suspend_count; 1781 1782 i915_params_copy(&error->params, &i915->params); 1783 memcpy(&error->device_info, 1784 INTEL_INFO(i915), 1785 sizeof(error->device_info)); 1786 memcpy(&error->runtime_info, 1787 RUNTIME_INFO(i915), 1788 sizeof(error->runtime_info)); 1789 error->driver_caps = i915->caps; 1790 } 1791 1792 struct i915_gpu_coredump * 1793 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1794 { 1795 struct i915_gpu_coredump *error; 1796 1797 if (!i915->params.error_capture) 1798 return NULL; 1799 1800 error = kzalloc(sizeof(*error), gfp); 1801 if (!error) 1802 return NULL; 1803 1804 kref_init(&error->ref); 1805 error->i915 = i915; 1806 1807 error->time = ktime_get_real(); 1808 error->boottime = ktime_get_boottime(); 1809 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); 1810 error->capture = jiffies; 1811 1812 capture_gen(error); 1813 1814 return error; 1815 } 1816 1817 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1818 1819 struct intel_gt_coredump * 1820 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1821 { 1822 struct intel_gt_coredump *gc; 1823 1824 gc = kzalloc(sizeof(*gc), gfp); 1825 if (!gc) 1826 return NULL; 1827 1828 gc->_gt = gt; 1829 gc->awake = intel_gt_pm_is_awake(gt); 1830 1831 gt_record_regs(gc); 1832 gt_record_fences(gc); 1833 1834 return gc; 1835 } 1836 1837 struct i915_vma_compress * 1838 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1839 { 1840 struct i915_vma_compress *compress; 1841 1842 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1843 if (!compress) 1844 return NULL; 1845 1846 if (!compress_init(compress)) { 1847 kfree(compress); 1848 return NULL; 1849 } 1850 1851 return compress; 1852 } 1853 1854 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1855 struct i915_vma_compress *compress) 1856 { 1857 if (!compress) 1858 return; 1859 1860 compress_fini(compress); 1861 kfree(compress); 1862 } 1863 1864 struct i915_gpu_coredump * 1865 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask) 1866 { 1867 struct drm_i915_private *i915 = gt->i915; 1868 struct i915_gpu_coredump *error; 1869 1870 /* Check if GPU capture has been disabled */ 1871 error = READ_ONCE(i915->gpu_error.first_error); 1872 if (IS_ERR(error)) 1873 return error; 1874 1875 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1876 if (!error) 1877 return ERR_PTR(-ENOMEM); 1878 1879 error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL); 1880 if (error->gt) { 1881 struct i915_vma_compress *compress; 1882 1883 compress = i915_vma_capture_prepare(error->gt); 1884 if (!compress) { 1885 kfree(error->gt); 1886 kfree(error); 1887 return ERR_PTR(-ENOMEM); 1888 } 1889 1890 gt_record_info(error->gt); 1891 gt_record_engines(error->gt, engine_mask, compress); 1892 1893 if (INTEL_INFO(i915)->has_gt_uc) 1894 error->gt->uc = gt_record_uc(error->gt, compress); 1895 1896 i915_vma_capture_finish(error->gt, compress); 1897 1898 error->simulated |= error->gt->simulated; 1899 } 1900 1901 error->overlay = intel_overlay_capture_error_state(i915); 1902 1903 return error; 1904 } 1905 1906 void i915_error_state_store(struct i915_gpu_coredump *error) 1907 { 1908 struct drm_i915_private *i915; 1909 static bool warned; 1910 1911 if (IS_ERR_OR_NULL(error)) 1912 return; 1913 1914 i915 = error->i915; 1915 drm_info(&i915->drm, "%s\n", error_msg(error)); 1916 1917 if (error->simulated || 1918 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1919 return; 1920 1921 i915_gpu_coredump_get(error); 1922 1923 if (!xchg(&warned, true) && 1924 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1925 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1926 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1927 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1928 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1929 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1930 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1931 i915->drm.primary->index); 1932 } 1933 } 1934 1935 /** 1936 * i915_capture_error_state - capture an error record for later analysis 1937 * @gt: intel_gt which originated the hang 1938 * @engine_mask: hung engines 1939 * 1940 * 1941 * Should be called when an error is detected (either a hang or an error 1942 * interrupt) to capture error state from the time of the error. Fills 1943 * out a structure which becomes available in debugfs for user level tools 1944 * to pick up. 1945 */ 1946 void i915_capture_error_state(struct intel_gt *gt, 1947 intel_engine_mask_t engine_mask) 1948 { 1949 struct i915_gpu_coredump *error; 1950 1951 error = i915_gpu_coredump(gt, engine_mask); 1952 if (IS_ERR(error)) { 1953 cmpxchg(>->i915->gpu_error.first_error, NULL, error); 1954 return; 1955 } 1956 1957 i915_error_state_store(error); 1958 i915_gpu_coredump_put(error); 1959 } 1960 1961 struct i915_gpu_coredump * 1962 i915_first_error_state(struct drm_i915_private *i915) 1963 { 1964 struct i915_gpu_coredump *error; 1965 1966 spin_lock_irq(&i915->gpu_error.lock); 1967 error = i915->gpu_error.first_error; 1968 if (!IS_ERR_OR_NULL(error)) 1969 i915_gpu_coredump_get(error); 1970 spin_unlock_irq(&i915->gpu_error.lock); 1971 1972 return error; 1973 } 1974 1975 void i915_reset_error_state(struct drm_i915_private *i915) 1976 { 1977 struct i915_gpu_coredump *error; 1978 1979 spin_lock_irq(&i915->gpu_error.lock); 1980 error = i915->gpu_error.first_error; 1981 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1982 i915->gpu_error.first_error = NULL; 1983 spin_unlock_irq(&i915->gpu_error.lock); 1984 1985 if (!IS_ERR_OR_NULL(error)) 1986 i915_gpu_coredump_put(error); 1987 } 1988 1989 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1990 { 1991 spin_lock_irq(&i915->gpu_error.lock); 1992 if (!i915->gpu_error.first_error) 1993 i915->gpu_error.first_error = ERR_PTR(err); 1994 spin_unlock_irq(&i915->gpu_error.lock); 1995 } 1996