1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include "i915_drv.h" 31 32 static const char *ring_str(int ring) 33 { 34 switch (ring) { 35 case RCS: return "render"; 36 case VCS: return "bsd"; 37 case BCS: return "blt"; 38 case VECS: return "vebox"; 39 case VCS2: return "bsd2"; 40 default: return ""; 41 } 42 } 43 44 static const char *pin_flag(int pinned) 45 { 46 if (pinned > 0) 47 return " P"; 48 else if (pinned < 0) 49 return " p"; 50 else 51 return ""; 52 } 53 54 static const char *tiling_flag(int tiling) 55 { 56 switch (tiling) { 57 default: 58 case I915_TILING_NONE: return ""; 59 case I915_TILING_X: return " X"; 60 case I915_TILING_Y: return " Y"; 61 } 62 } 63 64 static const char *dirty_flag(int dirty) 65 { 66 return dirty ? " dirty" : ""; 67 } 68 69 static const char *purgeable_flag(int purgeable) 70 { 71 return purgeable ? " purgeable" : ""; 72 } 73 74 static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 75 { 76 77 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 78 e->err = -ENOSPC; 79 return false; 80 } 81 82 if (e->bytes == e->size - 1 || e->err) 83 return false; 84 85 return true; 86 } 87 88 static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 89 unsigned len) 90 { 91 if (e->pos + len <= e->start) { 92 e->pos += len; 93 return false; 94 } 95 96 /* First vsnprintf needs to fit in its entirety for memmove */ 97 if (len >= e->size) { 98 e->err = -EIO; 99 return false; 100 } 101 102 return true; 103 } 104 105 static void __i915_error_advance(struct drm_i915_error_state_buf *e, 106 unsigned len) 107 { 108 /* If this is first printf in this window, adjust it so that 109 * start position matches start of the buffer 110 */ 111 112 if (e->pos < e->start) { 113 const size_t off = e->start - e->pos; 114 115 /* Should not happen but be paranoid */ 116 if (off > len || e->bytes) { 117 e->err = -EIO; 118 return; 119 } 120 121 memmove(e->buf, e->buf + off, len - off); 122 e->bytes = len - off; 123 e->pos = e->start; 124 return; 125 } 126 127 e->bytes += len; 128 e->pos += len; 129 } 130 131 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 132 const char *f, va_list args) 133 { 134 unsigned len; 135 136 if (!__i915_error_ok(e)) 137 return; 138 139 /* Seek the first printf which is hits start position */ 140 if (e->pos < e->start) { 141 va_list tmp; 142 143 va_copy(tmp, args); 144 len = vsnprintf(NULL, 0, f, tmp); 145 va_end(tmp); 146 147 if (!__i915_error_seek(e, len)) 148 return; 149 } 150 151 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 152 if (len >= e->size - e->bytes) 153 len = e->size - e->bytes - 1; 154 155 __i915_error_advance(e, len); 156 } 157 158 static void i915_error_puts(struct drm_i915_error_state_buf *e, 159 const char *str) 160 { 161 unsigned len; 162 163 if (!__i915_error_ok(e)) 164 return; 165 166 len = strlen(str); 167 168 /* Seek the first printf which is hits start position */ 169 if (e->pos < e->start) { 170 if (!__i915_error_seek(e, len)) 171 return; 172 } 173 174 if (len >= e->size - e->bytes) 175 len = e->size - e->bytes - 1; 176 memcpy(e->buf + e->bytes, str, len); 177 178 __i915_error_advance(e, len); 179 } 180 181 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 182 #define err_puts(e, s) i915_error_puts(e, s) 183 184 static void print_error_buffers(struct drm_i915_error_state_buf *m, 185 const char *name, 186 struct drm_i915_error_buffer *err, 187 int count) 188 { 189 int i; 190 191 err_printf(m, " %s [%d]:\n", name, count); 192 193 while (count--) { 194 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 195 upper_32_bits(err->gtt_offset), 196 lower_32_bits(err->gtt_offset), 197 err->size, 198 err->read_domains, 199 err->write_domain); 200 for (i = 0; i < I915_NUM_RINGS; i++) 201 err_printf(m, "%02x ", err->rseqno[i]); 202 203 err_printf(m, "] %02x", err->wseqno); 204 err_puts(m, pin_flag(err->pinned)); 205 err_puts(m, tiling_flag(err->tiling)); 206 err_puts(m, dirty_flag(err->dirty)); 207 err_puts(m, purgeable_flag(err->purgeable)); 208 err_puts(m, err->userptr ? " userptr" : ""); 209 err_puts(m, err->ring != -1 ? " " : ""); 210 err_puts(m, ring_str(err->ring)); 211 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 212 213 if (err->name) 214 err_printf(m, " (name: %d)", err->name); 215 if (err->fence_reg != I915_FENCE_REG_NONE) 216 err_printf(m, " (fence: %d)", err->fence_reg); 217 218 err_puts(m, "\n"); 219 err++; 220 } 221 } 222 223 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 224 { 225 switch (a) { 226 case HANGCHECK_IDLE: 227 return "idle"; 228 case HANGCHECK_WAIT: 229 return "wait"; 230 case HANGCHECK_ACTIVE: 231 return "active"; 232 case HANGCHECK_ACTIVE_LOOP: 233 return "active (loop)"; 234 case HANGCHECK_KICK: 235 return "kick"; 236 case HANGCHECK_HUNG: 237 return "hung"; 238 } 239 240 return "unknown"; 241 } 242 243 static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 244 struct drm_device *dev, 245 struct drm_i915_error_state *error, 246 int ring_idx) 247 { 248 struct drm_i915_error_ring *ring = &error->ring[ring_idx]; 249 250 if (!ring->valid) 251 return; 252 253 err_printf(m, "%s command stream:\n", ring_str(ring_idx)); 254 err_printf(m, " START: 0x%08x\n", ring->start); 255 err_printf(m, " HEAD: 0x%08x\n", ring->head); 256 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 257 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 258 err_printf(m, " HWS: 0x%08x\n", ring->hws); 259 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 260 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 261 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 262 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 263 if (INTEL_INFO(dev)->gen >= 4) { 264 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 265 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 266 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 267 } 268 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 269 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 270 lower_32_bits(ring->faddr)); 271 if (INTEL_INFO(dev)->gen >= 6) { 272 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 273 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 274 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 275 ring->semaphore_mboxes[0], 276 ring->semaphore_seqno[0]); 277 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 278 ring->semaphore_mboxes[1], 279 ring->semaphore_seqno[1]); 280 if (HAS_VEBOX(dev)) { 281 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 282 ring->semaphore_mboxes[2], 283 ring->semaphore_seqno[2]); 284 } 285 } 286 if (USES_PPGTT(dev)) { 287 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 288 289 if (INTEL_INFO(dev)->gen >= 8) { 290 int i; 291 for (i = 0; i < 4; i++) 292 err_printf(m, " PDP%d: 0x%016llx\n", 293 i, ring->vm_info.pdp[i]); 294 } else { 295 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 296 ring->vm_info.pp_dir_base); 297 } 298 } 299 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 300 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 301 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 302 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 303 err_printf(m, " hangcheck: %s [%d]\n", 304 hangcheck_action_to_str(ring->hangcheck_action), 305 ring->hangcheck_score); 306 } 307 308 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 309 { 310 va_list args; 311 312 va_start(args, f); 313 i915_error_vprintf(e, f, args); 314 va_end(args); 315 } 316 317 static void print_error_obj(struct drm_i915_error_state_buf *m, 318 struct drm_i915_error_object *obj) 319 { 320 int page, offset, elt; 321 322 for (page = offset = 0; page < obj->page_count; page++) { 323 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 324 err_printf(m, "%08x : %08x\n", offset, 325 obj->pages[page][elt]); 326 offset += 4; 327 } 328 } 329 } 330 331 static void xprint_error_obj(struct drm_i915_error_object *obj) 332 { 333 int page, offset, elt; 334 335 for (page = offset = 0; page < obj->page_count; page++) { 336 for (elt = 0; elt < PAGE_SIZE/64; elt++) { 337 printf("%08x : %08x\n", offset, 338 obj->pages[page][elt]); 339 offset += 4; 340 } 341 break; 342 } 343 } 344 345 int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 346 const struct i915_error_state_file_priv *error_priv) 347 { 348 struct drm_device *dev = error_priv->dev; 349 struct drm_i915_private *dev_priv = dev->dev_private; 350 struct drm_i915_error_state *error = error_priv->error; 351 struct drm_i915_error_object *obj; 352 int i, j, offset, elt; 353 int max_hangcheck_score; 354 355 if (!error) { 356 err_printf(m, "no error state collected\n"); 357 goto out; 358 } 359 360 err_printf(m, "%s\n", error->error_msg); 361 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 362 error->time.tv_usec); 363 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 364 max_hangcheck_score = 0; 365 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 366 if (error->ring[i].hangcheck_score > max_hangcheck_score) 367 max_hangcheck_score = error->ring[i].hangcheck_score; 368 } 369 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 370 if (error->ring[i].hangcheck_score == max_hangcheck_score && 371 error->ring[i].pid != -1) { 372 err_printf(m, "Active process (on ring %s): %s [%d]\n", 373 ring_str(i), 374 error->ring[i].comm, 375 error->ring[i].pid); 376 } 377 } 378 err_printf(m, "Reset count: %u\n", error->reset_count); 379 err_printf(m, "Suspend count: %u\n", error->suspend_count); 380 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 381 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 382 err_printf(m, "EIR: 0x%08x\n", error->eir); 383 err_printf(m, "IER: 0x%08x\n", error->ier); 384 if (INTEL_INFO(dev)->gen >= 8) { 385 for (i = 0; i < 4; i++) 386 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 387 error->gtier[i]); 388 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 389 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 390 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 391 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 392 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 393 err_printf(m, "CCID: 0x%08x\n", error->ccid); 394 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 395 396 for (i = 0; i < dev_priv->num_fence_regs; i++) 397 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); 398 399 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 400 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 401 error->extra_instdone[i]); 402 403 if (INTEL_INFO(dev)->gen >= 6) { 404 err_printf(m, "ERROR: 0x%08x\n", error->error); 405 406 if (INTEL_INFO(dev)->gen >= 8) 407 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 408 error->fault_data1, error->fault_data0); 409 410 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 411 } 412 413 if (INTEL_INFO(dev)->gen == 7) 414 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 415 416 for (i = 0; i < ARRAY_SIZE(error->ring); i++) 417 i915_ring_error_state(m, dev, error, i); 418 419 for (i = 0; i < error->vm_count; i++) { 420 err_printf(m, "vm[%d]\n", i); 421 422 print_error_buffers(m, "Active", 423 error->active_bo[i], 424 error->active_bo_count[i]); 425 426 print_error_buffers(m, "Pinned", 427 error->pinned_bo[i], 428 error->pinned_bo_count[i]); 429 } 430 431 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 432 obj = error->ring[i].batchbuffer; 433 if (obj) { 434 err_puts(m, dev_priv->ring[i].name); 435 if (error->ring[i].pid != -1) 436 err_printf(m, " (submitted by %s [%d])", 437 error->ring[i].comm, 438 error->ring[i].pid); 439 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 440 upper_32_bits(obj->gtt_offset), 441 lower_32_bits(obj->gtt_offset)); 442 print_error_obj(m, obj); 443 } 444 445 obj = error->ring[i].wa_batchbuffer; 446 if (obj) { 447 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 448 dev_priv->ring[i].name, 449 lower_32_bits(obj->gtt_offset)); 450 print_error_obj(m, obj); 451 } 452 453 if (error->ring[i].num_requests) { 454 err_printf(m, "%s --- %d requests\n", 455 dev_priv->ring[i].name, 456 error->ring[i].num_requests); 457 for (j = 0; j < error->ring[i].num_requests; j++) { 458 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 459 error->ring[i].requests[j].seqno, 460 error->ring[i].requests[j].jiffies, 461 error->ring[i].requests[j].tail); 462 } 463 } 464 465 if ((obj = error->ring[i].ringbuffer)) { 466 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 467 dev_priv->ring[i].name, 468 lower_32_bits(obj->gtt_offset)); 469 print_error_obj(m, obj); 470 } 471 472 if ((obj = error->ring[i].hws_page)) { 473 u64 hws_offset = obj->gtt_offset; 474 u32 *hws_page = &obj->pages[0][0]; 475 476 if (i915.enable_execlists) { 477 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE; 478 hws_page = &obj->pages[LRC_PPHWSP_PN][0]; 479 } 480 err_printf(m, "%s --- HW Status = 0x%08llx\n", 481 dev_priv->ring[i].name, hws_offset); 482 offset = 0; 483 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 484 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 485 offset, 486 hws_page[elt], 487 hws_page[elt+1], 488 hws_page[elt+2], 489 hws_page[elt+3]); 490 offset += 16; 491 } 492 } 493 494 if ((obj = error->ring[i].ctx)) { 495 err_printf(m, "%s --- HW Context = 0x%08x\n", 496 dev_priv->ring[i].name, 497 lower_32_bits(obj->gtt_offset)); 498 print_error_obj(m, obj); 499 } 500 } 501 502 if ((obj = error->semaphore_obj)) { 503 err_printf(m, "Semaphore page = 0x%08x\n", 504 lower_32_bits(obj->gtt_offset)); 505 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 506 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 507 elt * 4, 508 obj->pages[0][elt], 509 obj->pages[0][elt+1], 510 obj->pages[0][elt+2], 511 obj->pages[0][elt+3]); 512 } 513 } 514 515 if (error->overlay) 516 intel_overlay_print_error_state(m, error->overlay); 517 518 if (error->display) 519 intel_display_print_error_state(m, dev, error->display); 520 521 out: 522 if (m->bytes == 0 && m->err) 523 return m->err; 524 525 return 0; 526 } 527 528 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 529 struct drm_i915_private *i915, 530 size_t count, loff_t pos) 531 { 532 memset(ebuf, 0, sizeof(*ebuf)); 533 ebuf->i915 = i915; 534 535 /* We need to have enough room to store any i915_error_state printf 536 * so that we can move it to start position. 537 */ 538 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 539 ebuf->buf = kmalloc(ebuf->size, 540 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 541 542 if (ebuf->buf == NULL) { 543 ebuf->size = PAGE_SIZE; 544 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 545 } 546 547 if (ebuf->buf == NULL) { 548 ebuf->size = 128; 549 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 550 } 551 552 if (ebuf->buf == NULL) 553 return -ENOMEM; 554 555 ebuf->start = pos; 556 557 return 0; 558 } 559 560 static void i915_error_object_free(struct drm_i915_error_object *obj) 561 { 562 int page; 563 564 if (obj == NULL) 565 return; 566 567 for (page = 0; page < obj->page_count; page++) 568 kfree(obj->pages[page]); 569 570 kfree(obj); 571 } 572 573 static void i915_error_state_free(struct kref *error_ref) 574 { 575 struct drm_i915_error_state *error = container_of(error_ref, 576 typeof(*error), ref); 577 int i; 578 579 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 580 i915_error_object_free(error->ring[i].batchbuffer); 581 i915_error_object_free(error->ring[i].wa_batchbuffer); 582 i915_error_object_free(error->ring[i].ringbuffer); 583 i915_error_object_free(error->ring[i].hws_page); 584 i915_error_object_free(error->ring[i].ctx); 585 kfree(error->ring[i].requests); 586 } 587 588 i915_error_object_free(error->semaphore_obj); 589 590 for (i = 0; i < error->vm_count; i++) 591 kfree(error->active_bo[i]); 592 593 kfree(error->active_bo); 594 kfree(error->active_bo_count); 595 kfree(error->pinned_bo); 596 kfree(error->pinned_bo_count); 597 kfree(error->overlay); 598 kfree(error->display); 599 kfree(error); 600 } 601 602 static struct drm_i915_error_object * 603 i915_error_object_create(struct drm_i915_private *dev_priv, 604 struct drm_i915_gem_object *src, 605 struct i915_address_space *vm) 606 { 607 struct drm_i915_error_object *dst; 608 struct i915_vma *vma = NULL; 609 int num_pages; 610 bool use_ggtt; 611 int i = 0; 612 u64 reloc_offset; 613 614 if (src == NULL || src->pages == NULL) 615 return NULL; 616 617 num_pages = src->base.size >> PAGE_SHIFT; 618 619 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 620 if (dst == NULL) 621 return NULL; 622 623 if (i915_gem_obj_bound(src, vm)) 624 dst->gtt_offset = i915_gem_obj_offset(src, vm); 625 else 626 dst->gtt_offset = -1; 627 628 reloc_offset = dst->gtt_offset; 629 if (i915_is_ggtt(vm)) 630 vma = i915_gem_obj_to_ggtt(src); 631 use_ggtt = (src->cache_level == I915_CACHE_NONE && 632 vma && (vma->bound & GLOBAL_BIND) && 633 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end); 634 635 /* Cannot access stolen address directly, try to use the aperture */ 636 if (src->stolen) { 637 use_ggtt = true; 638 639 if (!(vma && vma->bound & GLOBAL_BIND)) 640 goto unwind; 641 642 reloc_offset = i915_gem_obj_ggtt_offset(src); 643 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end) 644 goto unwind; 645 } 646 647 /* Cannot access snooped pages through the aperture */ 648 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) 649 goto unwind; 650 651 dst->page_count = num_pages; 652 while (num_pages--) { 653 unsigned long flags; 654 void *d; 655 656 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 657 if (d == NULL) 658 goto unwind; 659 660 local_irq_save(flags); 661 if (use_ggtt) { 662 bus_space_handle_t bsh; 663 void __iomem *s; 664 665 /* Simply ignore tiling or any overlapping fence. 666 * It's part of the error state, and this hopefully 667 * captures what the GPU read. 668 */ 669 670 #ifdef __linux__ 671 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 672 reloc_offset); 673 #else 674 agp_map_atomic(dev_priv->agph, reloc_offset, &bsh); 675 s = bus_space_vaddr(dev_priv->bst, bsh); 676 #endif 677 memcpy_fromio(d, s, PAGE_SIZE); 678 #ifdef __linux__ 679 io_mapping_unmap_atomic(s); 680 #else 681 agp_unmap_atomic(dev_priv->agph, bsh); 682 #endif 683 } else { 684 struct vm_page *page; 685 void *s; 686 687 page = i915_gem_object_get_page(src, i); 688 689 drm_clflush_pages(&page, 1); 690 691 s = kmap_atomic(page); 692 memcpy(d, s, PAGE_SIZE); 693 kunmap_atomic(s); 694 695 drm_clflush_pages(&page, 1); 696 } 697 local_irq_restore(flags); 698 699 dst->pages[i++] = d; 700 reloc_offset += PAGE_SIZE; 701 } 702 703 return dst; 704 705 unwind: 706 while (i--) 707 kfree(dst->pages[i]); 708 kfree(dst); 709 return NULL; 710 } 711 #define i915_error_ggtt_object_create(dev_priv, src) \ 712 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base) 713 714 static void capture_bo(struct drm_i915_error_buffer *err, 715 struct i915_vma *vma) 716 { 717 struct drm_i915_gem_object *obj = vma->obj; 718 int i; 719 720 err->size = obj->base.size; 721 err->name = obj->base.name; 722 for (i = 0; i < I915_NUM_RINGS; i++) 723 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); 724 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); 725 err->gtt_offset = vma->node.start; 726 err->read_domains = obj->base.read_domains; 727 err->write_domain = obj->base.write_domain; 728 err->fence_reg = obj->fence_reg; 729 err->pinned = 0; 730 if (i915_gem_obj_is_pinned(obj)) 731 err->pinned = 1; 732 err->tiling = obj->tiling_mode; 733 err->dirty = obj->dirty; 734 err->purgeable = obj->madv != I915_MADV_WILLNEED; 735 err->userptr = obj->userptr.mm != NULL; 736 err->ring = obj->last_write_req ? 737 i915_gem_request_get_ring(obj->last_write_req)->id : -1; 738 err->cache_level = obj->cache_level; 739 } 740 741 static u32 capture_active_bo(struct drm_i915_error_buffer *err, 742 int count, struct list_head *head) 743 { 744 struct i915_vma *vma; 745 int i = 0; 746 747 list_for_each_entry(vma, head, mm_list) { 748 capture_bo(err++, vma); 749 if (++i == count) 750 break; 751 } 752 753 return i; 754 } 755 756 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 757 int count, struct list_head *head, 758 struct i915_address_space *vm) 759 { 760 struct drm_i915_gem_object *obj; 761 struct drm_i915_error_buffer * const first = err; 762 struct drm_i915_error_buffer * const last = err + count; 763 764 list_for_each_entry(obj, head, global_list) { 765 struct i915_vma *vma; 766 767 if (err == last) 768 break; 769 770 list_for_each_entry(vma, &obj->vma_list, vma_link) 771 if (vma->vm == vm && vma->pin_count > 0) 772 capture_bo(err++, vma); 773 } 774 775 return err - first; 776 } 777 778 /* Generate a semi-unique error code. The code is not meant to have meaning, The 779 * code's only purpose is to try to prevent false duplicated bug reports by 780 * grossly estimating a GPU error state. 781 * 782 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 783 * the hang if we could strip the GTT offset information from it. 784 * 785 * It's only a small step better than a random number in its current form. 786 */ 787 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 788 struct drm_i915_error_state *error, 789 int *ring_id) 790 { 791 uint32_t error_code = 0; 792 int i; 793 794 /* IPEHR would be an ideal way to detect errors, as it's the gross 795 * measure of "the command that hung." However, has some very common 796 * synchronization commands which almost always appear in the case 797 * strictly a client bug. Use instdone to differentiate those some. 798 */ 799 for (i = 0; i < I915_NUM_RINGS; i++) { 800 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 801 if (ring_id) 802 *ring_id = i; 803 804 return error->ring[i].ipehr ^ error->ring[i].instdone; 805 } 806 } 807 808 return error_code; 809 } 810 811 static void i915_gem_record_fences(struct drm_device *dev, 812 struct drm_i915_error_state *error) 813 { 814 struct drm_i915_private *dev_priv = dev->dev_private; 815 int i; 816 817 if (IS_GEN3(dev) || IS_GEN2(dev)) { 818 for (i = 0; i < dev_priv->num_fence_regs; i++) 819 error->fence[i] = I915_READ(FENCE_REG(i)); 820 } else if (IS_GEN5(dev) || IS_GEN4(dev)) { 821 for (i = 0; i < dev_priv->num_fence_regs; i++) 822 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 823 } else if (INTEL_INFO(dev)->gen >= 6) { 824 for (i = 0; i < dev_priv->num_fence_regs; i++) 825 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 826 } 827 } 828 829 830 static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 831 struct drm_i915_error_state *error, 832 struct intel_engine_cs *ring, 833 struct drm_i915_error_ring *ering) 834 { 835 struct intel_engine_cs *to; 836 int i; 837 838 if (!i915_semaphore_is_enabled(dev_priv->dev)) 839 return; 840 841 if (!error->semaphore_obj) 842 error->semaphore_obj = 843 i915_error_ggtt_object_create(dev_priv, 844 dev_priv->semaphore_obj); 845 846 for_each_ring(to, dev_priv, i) { 847 int idx; 848 u16 signal_offset; 849 u32 *tmp; 850 851 if (ring == to) 852 continue; 853 854 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) 855 / 4; 856 tmp = error->semaphore_obj->pages[0]; 857 idx = intel_ring_sync_index(ring, to); 858 859 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 860 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; 861 } 862 } 863 864 static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 865 struct intel_engine_cs *ring, 866 struct drm_i915_error_ring *ering) 867 { 868 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); 869 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); 870 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; 871 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; 872 873 if (HAS_VEBOX(dev_priv->dev)) { 874 ering->semaphore_mboxes[2] = 875 I915_READ(RING_SYNC_2(ring->mmio_base)); 876 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; 877 } 878 } 879 880 static void i915_record_ring_state(struct drm_device *dev, 881 struct drm_i915_error_state *error, 882 struct intel_engine_cs *ring, 883 struct drm_i915_error_ring *ering) 884 { 885 struct drm_i915_private *dev_priv = dev->dev_private; 886 887 if (INTEL_INFO(dev)->gen >= 6) { 888 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 889 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 890 if (INTEL_INFO(dev)->gen >= 8) 891 gen8_record_semaphore_state(dev_priv, error, ring, ering); 892 else 893 gen6_record_semaphore_state(dev_priv, ring, ering); 894 } 895 896 if (INTEL_INFO(dev)->gen >= 4) { 897 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 898 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 899 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 900 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 901 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 902 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 903 if (INTEL_INFO(dev)->gen >= 8) { 904 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 905 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 906 } 907 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 908 } else { 909 ering->faddr = I915_READ(DMA_FADD_I8XX); 910 ering->ipeir = I915_READ(IPEIR); 911 ering->ipehr = I915_READ(IPEHR); 912 ering->instdone = I915_READ(GEN2_INSTDONE); 913 } 914 915 ering->waiting = waitqueue_active(&ring->irq_queue); 916 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 917 ering->seqno = ring->get_seqno(ring, false); 918 ering->acthd = intel_ring_get_active_head(ring); 919 ering->start = I915_READ_START(ring); 920 ering->head = I915_READ_HEAD(ring); 921 ering->tail = I915_READ_TAIL(ring); 922 ering->ctl = I915_READ_CTL(ring); 923 924 if (I915_NEED_GFX_HWS(dev)) { 925 int mmio; 926 927 if (IS_GEN7(dev)) { 928 switch (ring->id) { 929 default: 930 case RCS: 931 mmio = RENDER_HWS_PGA_GEN7; 932 break; 933 case BCS: 934 mmio = BLT_HWS_PGA_GEN7; 935 break; 936 case VCS: 937 mmio = BSD_HWS_PGA_GEN7; 938 break; 939 case VECS: 940 mmio = VEBOX_HWS_PGA_GEN7; 941 break; 942 } 943 } else if (IS_GEN6(ring->dev)) { 944 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 945 } else { 946 /* XXX: gen8 returns to sanity */ 947 mmio = RING_HWS_PGA(ring->mmio_base); 948 } 949 950 ering->hws = I915_READ(mmio); 951 } 952 953 ering->hangcheck_score = ring->hangcheck.score; 954 ering->hangcheck_action = ring->hangcheck.action; 955 956 if (USES_PPGTT(dev)) { 957 int i; 958 959 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 960 961 if (IS_GEN6(dev)) 962 ering->vm_info.pp_dir_base = 963 I915_READ(RING_PP_DIR_BASE_READ(ring)); 964 else if (IS_GEN7(dev)) 965 ering->vm_info.pp_dir_base = 966 I915_READ(RING_PP_DIR_BASE(ring)); 967 else if (INTEL_INFO(dev)->gen >= 8) 968 for (i = 0; i < 4; i++) { 969 ering->vm_info.pdp[i] = 970 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 971 ering->vm_info.pdp[i] <<= 32; 972 ering->vm_info.pdp[i] |= 973 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 974 } 975 } 976 } 977 978 979 static void i915_gem_record_active_context(struct intel_engine_cs *ring, 980 struct drm_i915_error_state *error, 981 struct drm_i915_error_ring *ering) 982 { 983 struct drm_i915_private *dev_priv = ring->dev->dev_private; 984 struct drm_i915_gem_object *obj; 985 986 /* Currently render ring is the only HW context user */ 987 if (ring->id != RCS || !error->ccid) 988 return; 989 990 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 991 if (!i915_gem_obj_ggtt_bound(obj)) 992 continue; 993 994 if (trunc_page(error->ccid) == i915_gem_obj_ggtt_offset(obj)) { 995 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 996 break; 997 } 998 } 999 } 1000 1001 static void i915_gem_record_rings(struct drm_device *dev, 1002 struct drm_i915_error_state *error) 1003 { 1004 struct drm_i915_private *dev_priv = dev->dev_private; 1005 struct drm_i915_gem_request *request; 1006 int i, count; 1007 1008 for (i = 0; i < I915_NUM_RINGS; i++) { 1009 struct intel_engine_cs *ring = &dev_priv->ring[i]; 1010 struct intel_ringbuffer *rbuf; 1011 1012 error->ring[i].pid = -1; 1013 1014 if (ring->dev == NULL) 1015 continue; 1016 1017 error->ring[i].valid = true; 1018 1019 i915_record_ring_state(dev, error, ring, &error->ring[i]); 1020 1021 request = i915_gem_find_active_request(ring); 1022 if (request) { 1023 struct i915_address_space *vm; 1024 1025 vm = request->ctx && request->ctx->ppgtt ? 1026 &request->ctx->ppgtt->base : 1027 &dev_priv->gtt.base; 1028 1029 /* We need to copy these to an anonymous buffer 1030 * as the simplest method to avoid being overwritten 1031 * by userspace. 1032 */ 1033 error->ring[i].batchbuffer = 1034 i915_error_object_create(dev_priv, 1035 request->batch_obj, 1036 vm); 1037 1038 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) 1039 error->ring[i].wa_batchbuffer = 1040 i915_error_ggtt_object_create(dev_priv, 1041 ring->scratch.obj); 1042 1043 #ifdef __linux__ 1044 if (request->pid) { 1045 struct task_struct *task; 1046 1047 rcu_read_lock(); 1048 task = pid_task(request->pid, PIDTYPE_PID); 1049 if (task) { 1050 strcpy(error->ring[i].comm, task->comm); 1051 error->ring[i].pid = task->pid; 1052 } 1053 rcu_read_unlock(); 1054 } 1055 #endif 1056 } 1057 1058 if (i915.enable_execlists) { 1059 /* TODO: This is only a small fix to keep basic error 1060 * capture working, but we need to add more information 1061 * for it to be useful (e.g. dump the context being 1062 * executed). 1063 */ 1064 if (request) 1065 rbuf = request->ctx->engine[ring->id].ringbuf; 1066 else 1067 rbuf = ring->default_context->engine[ring->id].ringbuf; 1068 } else 1069 rbuf = ring->buffer; 1070 1071 error->ring[i].cpu_ring_head = rbuf->head; 1072 error->ring[i].cpu_ring_tail = rbuf->tail; 1073 1074 error->ring[i].ringbuffer = 1075 i915_error_ggtt_object_create(dev_priv, rbuf->obj); 1076 1077 error->ring[i].hws_page = 1078 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 1079 1080 i915_gem_record_active_context(ring, error, &error->ring[i]); 1081 1082 count = 0; 1083 list_for_each_entry(request, &ring->request_list, list) 1084 count++; 1085 1086 error->ring[i].num_requests = count; 1087 error->ring[i].requests = 1088 kcalloc(count, sizeof(*error->ring[i].requests), 1089 GFP_ATOMIC); 1090 if (error->ring[i].requests == NULL) { 1091 error->ring[i].num_requests = 0; 1092 continue; 1093 } 1094 1095 count = 0; 1096 list_for_each_entry(request, &ring->request_list, list) { 1097 struct drm_i915_error_request *erq; 1098 1099 erq = &error->ring[i].requests[count++]; 1100 erq->seqno = request->seqno; 1101 erq->jiffies = request->emitted_jiffies; 1102 erq->tail = request->postfix; 1103 } 1104 } 1105 } 1106 1107 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1108 * VM. 1109 */ 1110 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1111 struct drm_i915_error_state *error, 1112 struct i915_address_space *vm, 1113 const int ndx) 1114 { 1115 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1116 struct drm_i915_gem_object *obj; 1117 struct i915_vma *vma; 1118 int i; 1119 1120 i = 0; 1121 list_for_each_entry(vma, &vm->active_list, mm_list) 1122 i++; 1123 error->active_bo_count[ndx] = i; 1124 1125 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1126 list_for_each_entry(vma, &obj->vma_list, vma_link) 1127 if (vma->vm == vm && vma->pin_count > 0) 1128 i++; 1129 } 1130 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1131 1132 if (i) { 1133 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1134 if (active_bo) 1135 pinned_bo = active_bo + error->active_bo_count[ndx]; 1136 } 1137 1138 if (active_bo) 1139 error->active_bo_count[ndx] = 1140 capture_active_bo(active_bo, 1141 error->active_bo_count[ndx], 1142 &vm->active_list); 1143 1144 if (pinned_bo) 1145 error->pinned_bo_count[ndx] = 1146 capture_pinned_bo(pinned_bo, 1147 error->pinned_bo_count[ndx], 1148 &dev_priv->mm.bound_list, vm); 1149 error->active_bo[ndx] = active_bo; 1150 error->pinned_bo[ndx] = pinned_bo; 1151 } 1152 1153 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1154 struct drm_i915_error_state *error) 1155 { 1156 struct i915_address_space *vm; 1157 int cnt = 0, i = 0; 1158 1159 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1160 cnt++; 1161 1162 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1163 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1164 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1165 GFP_ATOMIC); 1166 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1167 GFP_ATOMIC); 1168 1169 if (error->active_bo == NULL || 1170 error->pinned_bo == NULL || 1171 error->active_bo_count == NULL || 1172 error->pinned_bo_count == NULL) { 1173 kfree(error->active_bo); 1174 kfree(error->active_bo_count); 1175 kfree(error->pinned_bo); 1176 kfree(error->pinned_bo_count); 1177 1178 error->active_bo = NULL; 1179 error->active_bo_count = NULL; 1180 error->pinned_bo = NULL; 1181 error->pinned_bo_count = NULL; 1182 } else { 1183 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1184 i915_gem_capture_vm(dev_priv, error, vm, i++); 1185 1186 error->vm_count = cnt; 1187 } 1188 } 1189 1190 /* Capture all registers which don't fit into another category. */ 1191 static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1192 struct drm_i915_error_state *error) 1193 { 1194 struct drm_device *dev = dev_priv->dev; 1195 int i; 1196 1197 /* General organization 1198 * 1. Registers specific to a single generation 1199 * 2. Registers which belong to multiple generations 1200 * 3. Feature specific registers. 1201 * 4. Everything else 1202 * Please try to follow the order. 1203 */ 1204 1205 /* 1: Registers specific to a single generation */ 1206 if (IS_VALLEYVIEW(dev)) { 1207 error->gtier[0] = I915_READ(GTIER); 1208 error->ier = I915_READ(VLV_IER); 1209 error->forcewake = I915_READ(FORCEWAKE_VLV); 1210 } 1211 1212 if (IS_GEN7(dev)) 1213 error->err_int = I915_READ(GEN7_ERR_INT); 1214 1215 if (INTEL_INFO(dev)->gen >= 8) { 1216 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1217 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1218 } 1219 1220 if (IS_GEN6(dev)) { 1221 error->forcewake = I915_READ(FORCEWAKE); 1222 error->gab_ctl = I915_READ(GAB_CTL); 1223 error->gfx_mode = I915_READ(GFX_MODE); 1224 } 1225 1226 /* 2: Registers which belong to multiple generations */ 1227 if (INTEL_INFO(dev)->gen >= 7) 1228 error->forcewake = I915_READ(FORCEWAKE_MT); 1229 1230 if (INTEL_INFO(dev)->gen >= 6) { 1231 error->derrmr = I915_READ(DERRMR); 1232 error->error = I915_READ(ERROR_GEN6); 1233 error->done_reg = I915_READ(DONE_REG); 1234 } 1235 1236 /* 3: Feature specific registers */ 1237 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1238 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1239 error->gac_eco = I915_READ(GAC_ECO_BITS); 1240 } 1241 1242 /* 4: Everything else */ 1243 if (HAS_HW_CONTEXTS(dev)) 1244 error->ccid = I915_READ(CCID); 1245 1246 if (INTEL_INFO(dev)->gen >= 8) { 1247 error->ier = I915_READ(GEN8_DE_MISC_IER); 1248 for (i = 0; i < 4; i++) 1249 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1250 } else if (HAS_PCH_SPLIT(dev)) { 1251 error->ier = I915_READ(DEIER); 1252 error->gtier[0] = I915_READ(GTIER); 1253 } else if (IS_GEN2(dev)) { 1254 error->ier = I915_READ16(IER); 1255 } else if (!IS_VALLEYVIEW(dev)) { 1256 error->ier = I915_READ(IER); 1257 } 1258 error->eir = I915_READ(EIR); 1259 error->pgtbl_er = I915_READ(PGTBL_ER); 1260 1261 i915_get_extra_instdone(dev, error->extra_instdone); 1262 } 1263 1264 static void i915_error_capture_msg(struct drm_device *dev, 1265 struct drm_i915_error_state *error, 1266 bool wedged, 1267 const char *error_msg) 1268 { 1269 struct drm_i915_private *dev_priv = dev->dev_private; 1270 u32 ecode; 1271 int ring_id = -1, len; 1272 1273 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1274 1275 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1276 "GPU HANG: ecode %d:%d:0x%08x", 1277 INTEL_INFO(dev)->gen, ring_id, ecode); 1278 1279 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1280 len += scnprintf(error->error_msg + len, 1281 sizeof(error->error_msg) - len, 1282 ", in %s [%d]", 1283 error->ring[ring_id].comm, 1284 error->ring[ring_id].pid); 1285 1286 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1287 ", reason: %s, action: %s", 1288 error_msg, 1289 wedged ? "reset" : "continue"); 1290 } 1291 1292 static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1293 struct drm_i915_error_state *error) 1294 { 1295 error->iommu = -1; 1296 #ifdef CONFIG_INTEL_IOMMU 1297 error->iommu = intel_iommu_gfx_mapped; 1298 #endif 1299 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1300 error->suspend_count = dev_priv->suspend_count; 1301 } 1302 1303 /** 1304 * i915_capture_error_state - capture an error record for later analysis 1305 * @dev: drm device 1306 * 1307 * Should be called when an error is detected (either a hang or an error 1308 * interrupt) to capture error state from the time of the error. Fills 1309 * out a structure which becomes available in debugfs for user level tools 1310 * to pick up. 1311 */ 1312 void i915_capture_error_state(struct drm_device *dev, bool wedged, 1313 const char *error_msg) 1314 { 1315 static bool warned; 1316 struct drm_i915_private *dev_priv = dev->dev_private; 1317 struct drm_i915_error_state *error; 1318 unsigned long flags; 1319 1320 /* Account for pipe specific data like PIPE*STAT */ 1321 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1322 if (!error) { 1323 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1324 return; 1325 } 1326 1327 kref_init(&error->ref); 1328 1329 i915_capture_gen_state(dev_priv, error); 1330 i915_capture_reg_state(dev_priv, error); 1331 i915_gem_capture_buffers(dev_priv, error); 1332 i915_gem_record_fences(dev, error); 1333 i915_gem_record_rings(dev, error); 1334 1335 do_gettimeofday(&error->time); 1336 1337 error->overlay = intel_overlay_capture_error_state(dev); 1338 error->display = intel_display_capture_error_state(dev); 1339 1340 i915_error_capture_msg(dev, error, wedged, error_msg); 1341 DRM_INFO("%s\n", error->error_msg); 1342 1343 int i, offset, elt; 1344 struct drm_i915_error_object *obj; 1345 static bool printed; 1346 1347 if (printed) 1348 goto end; 1349 printed = 1; 1350 1351 printf("EIR: 0x%08x\n", error->eir); 1352 printf("IER: 0x%08x\n", error->ier); 1353 if (INTEL_INFO(dev)->gen >= 8) { 1354 for (i = 0; i < 4; i++) 1355 printf("GTIER gt %d: 0x%08x\n", i, 1356 error->gtier[i]); 1357 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 1358 printf("GTIER: 0x%08x\n", error->gtier[0]); 1359 printf("PGTBL_ER: 0x%08x\n", error->pgtbl_er); 1360 printf("FORCEWAKE: 0x%08x\n", error->forcewake); 1361 printf("DERRMR: 0x%08x\n", error->derrmr); 1362 printf("CCID: 0x%08x\n", error->ccid); 1363 printf("Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 1364 1365 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 1366 printf(" INSTDONE_%d: 0x%08x\n", i, 1367 error->extra_instdone[i]); 1368 1369 if (INTEL_INFO(dev)->gen >= 6) { 1370 printf("ERROR: 0x%08x\n", error->error); 1371 1372 if (INTEL_INFO(dev)->gen >= 8) 1373 printf("FAULT_TLB_DATA: 0x%08x 0x%08x\n", 1374 error->fault_data1, error->fault_data0); 1375 1376 printf("DONE_REG: 0x%08x\n", error->done_reg); 1377 } 1378 1379 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 1380 struct drm_i915_error_ring *ring = &error->ring[i]; 1381 1382 if (!ring->valid) 1383 continue; 1384 1385 printf("%s command stream:\n", ring_str(i)); 1386 printf(" START: 0x%08x\n", ring->start); 1387 printf(" HEAD: 0x%08x\n", ring->head); 1388 printf(" TAIL: 0x%08x\n", ring->tail); 1389 printf(" CTL: 0x%08x\n", ring->ctl); 1390 printf(" HWS: 0x%08x\n", ring->hws); 1391 printf(" ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 1392 printf(" IPEIR: 0x%08x\n", ring->ipeir); 1393 printf(" IPEHR: 0x%08x\n", ring->ipehr); 1394 printf(" INSTDONE: 0x%08x\n", ring->instdone); 1395 if (INTEL_INFO(dev)->gen >= 4) { 1396 printf(" BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 1397 printf(" BB_STATE: 0x%08x\n", ring->bbstate); 1398 printf(" INSTPS: 0x%08x\n", ring->instps); 1399 } 1400 printf(" INSTPM: 0x%08x\n", ring->instpm); 1401 printf(" FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 1402 lower_32_bits(ring->faddr)); 1403 if (INTEL_INFO(dev)->gen >= 6) { 1404 printf(" RC PSMI: 0x%08x\n", ring->rc_psmi); 1405 printf(" FAULT_REG: 0x%08x\n", ring->fault_reg); 1406 printf(" SYNC_0: 0x%08x [last synced 0x%08x]\n", 1407 ring->semaphore_mboxes[0], 1408 ring->semaphore_seqno[0]); 1409 printf(" SYNC_1: 0x%08x [last synced 0x%08x]\n", 1410 ring->semaphore_mboxes[1], 1411 ring->semaphore_seqno[1]); 1412 if (HAS_VEBOX(dev)) { 1413 printf(" SYNC_2: 0x%08x [last synced 0x%08x]\n", 1414 ring->semaphore_mboxes[2], 1415 ring->semaphore_seqno[2]); 1416 } 1417 } 1418 if (USES_PPGTT(dev)) { 1419 printf(" GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 1420 1421 if (INTEL_INFO(dev)->gen >= 8) { 1422 int i; 1423 for (i = 0; i < 4; i++) 1424 printf(" PDP%d: 0x%016llx\n", 1425 i, ring->vm_info.pdp[i]); 1426 } else { 1427 printf(" PP_DIR_BASE: 0x%08x\n", 1428 ring->vm_info.pp_dir_base); 1429 } 1430 } 1431 printf(" seqno: 0x%08x\n", ring->seqno); 1432 printf(" waiting: %s\n", yesno(ring->waiting)); 1433 printf(" ring->head: 0x%08x\n", ring->cpu_ring_head); 1434 printf(" ring->tail: 0x%08x\n", ring->cpu_ring_tail); 1435 printf(" hangcheck: %s [%d]\n", 1436 hangcheck_action_to_str(ring->hangcheck_action), 1437 ring->hangcheck_score); 1438 1439 if ((obj = error->ring[i].ringbuffer)) { 1440 printf("%s --- ringbuffer = 0x%08x\n", 1441 dev_priv->ring[i].name, 1442 lower_32_bits(obj->gtt_offset)); 1443 xprint_error_obj(obj); 1444 } 1445 1446 if ((obj = error->ring[i].hws_page)) { 1447 u64 hws_offset = obj->gtt_offset; 1448 u32 *hws_page = &obj->pages[0][0]; 1449 1450 if (i915.enable_execlists) { 1451 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE; 1452 hws_page = &obj->pages[LRC_PPHWSP_PN][0]; 1453 } 1454 printf("%s --- HW Status = 0x%08llx\n", 1455 dev_priv->ring[i].name, hws_offset); 1456 offset = 0; 1457 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 1458 printf("[%04x] %08x %08x %08x %08x\n", 1459 offset, 1460 hws_page[elt], 1461 hws_page[elt+1], 1462 hws_page[elt+2], 1463 hws_page[elt+3]); 1464 offset += 16; 1465 } 1466 } 1467 1468 if ((obj = error->ring[i].ctx)) { 1469 printf("%s --- HW Context = 0x%08x\n", 1470 dev_priv->ring[i].name, 1471 lower_32_bits(obj->gtt_offset)); 1472 // print_error_obj(m, obj); 1473 } 1474 } 1475 1476 end: 1477 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1478 if (dev_priv->gpu_error.first_error == NULL) { 1479 dev_priv->gpu_error.first_error = error; 1480 error = NULL; 1481 } 1482 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1483 1484 if (error) { 1485 i915_error_state_free(&error->ref); 1486 return; 1487 } 1488 1489 if (!warned) { 1490 #ifdef __linux__ 1491 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1492 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1493 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1494 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1495 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1496 #endif 1497 warned = true; 1498 } 1499 } 1500 1501 void i915_error_state_get(struct drm_device *dev, 1502 struct i915_error_state_file_priv *error_priv) 1503 { 1504 struct drm_i915_private *dev_priv = dev->dev_private; 1505 1506 spin_lock_irq(&dev_priv->gpu_error.lock); 1507 error_priv->error = dev_priv->gpu_error.first_error; 1508 if (error_priv->error) 1509 kref_get(&error_priv->error->ref); 1510 spin_unlock_irq(&dev_priv->gpu_error.lock); 1511 1512 } 1513 1514 void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1515 { 1516 if (error_priv->error) 1517 kref_put(&error_priv->error->ref, i915_error_state_free); 1518 } 1519 1520 void i915_destroy_error_state(struct drm_device *dev) 1521 { 1522 struct drm_i915_private *dev_priv = dev->dev_private; 1523 struct drm_i915_error_state *error; 1524 1525 spin_lock_irq(&dev_priv->gpu_error.lock); 1526 error = dev_priv->gpu_error.first_error; 1527 dev_priv->gpu_error.first_error = NULL; 1528 spin_unlock_irq(&dev_priv->gpu_error.lock); 1529 1530 if (error) 1531 kref_put(&error->ref, i915_error_state_free); 1532 } 1533 1534 const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1535 { 1536 switch (type) { 1537 case I915_CACHE_NONE: return " uncached"; 1538 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1539 case I915_CACHE_L3_LLC: return " L3+LLC"; 1540 case I915_CACHE_WT: return " WT"; 1541 default: return ""; 1542 } 1543 } 1544 1545 /* NB: please notice the memset */ 1546 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1547 { 1548 struct drm_i915_private *dev_priv = dev->dev_private; 1549 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1550 1551 if (IS_GEN2(dev) || IS_GEN3(dev)) 1552 instdone[0] = I915_READ(GEN2_INSTDONE); 1553 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { 1554 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1555 instdone[1] = I915_READ(GEN4_INSTDONE1); 1556 } else if (INTEL_INFO(dev)->gen >= 7) { 1557 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1558 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1559 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1560 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1561 } 1562 } 1563