1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_atomic.h" 40 #include "display/intel_csr.h" 41 #include "display/intel_overlay.h" 42 43 #include "gem/i915_gem_context.h" 44 #include "gem/i915_gem_lmem.h" 45 #include "gt/intel_gt.h" 46 #include "gt/intel_gt_pm.h" 47 48 #include "i915_drv.h" 49 #include "i915_gpu_error.h" 50 #include "i915_memcpy.h" 51 #include "i915_scatterlist.h" 52 53 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 54 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 55 56 static void __sg_set_buf(struct scatterlist *sg, 57 void *addr, unsigned int len, loff_t it) 58 { 59 STUB(); 60 #ifdef notyet 61 sg->page_link = (unsigned long)virt_to_page(addr); 62 sg->offset = offset_in_page(addr); 63 sg->length = len; 64 sg->dma_address = it; 65 #endif 66 } 67 68 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 69 { 70 STUB(); 71 return false; 72 #ifdef notyet 73 if (!len) 74 return false; 75 76 if (e->bytes + len + 1 <= e->size) 77 return true; 78 79 if (e->bytes) { 80 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 81 e->iter += e->bytes; 82 e->buf = NULL; 83 e->bytes = 0; 84 } 85 86 if (e->cur == e->end) { 87 struct scatterlist *sgl; 88 89 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 90 if (!sgl) { 91 e->err = -ENOMEM; 92 return false; 93 } 94 95 if (e->cur) { 96 e->cur->offset = 0; 97 e->cur->length = 0; 98 e->cur->page_link = 99 (unsigned long)sgl | SG_CHAIN; 100 } else { 101 e->sgl = sgl; 102 } 103 104 e->cur = sgl; 105 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 106 } 107 108 e->size = roundup2(len + 1, SZ_64K); 109 e->buf = kmalloc(e->size, ALLOW_FAIL); 110 if (!e->buf) { 111 e->size = PAGE_ALIGN(len + 1); 112 e->buf = kmalloc(e->size, GFP_KERNEL); 113 } 114 if (!e->buf) { 115 e->err = -ENOMEM; 116 return false; 117 } 118 119 return true; 120 #endif 121 } 122 123 __printf(2, 0) 124 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 125 const char *fmt, va_list args) 126 { 127 va_list ap; 128 int len; 129 130 if (e->err) 131 return; 132 133 va_copy(ap, args); 134 len = vsnprintf(NULL, 0, fmt, ap); 135 va_end(ap); 136 if (len <= 0) { 137 e->err = len; 138 return; 139 } 140 141 if (!__i915_error_grow(e, len)) 142 return; 143 144 GEM_BUG_ON(e->bytes >= e->size); 145 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 146 if (len < 0) { 147 e->err = len; 148 return; 149 } 150 e->bytes += len; 151 } 152 153 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 154 { 155 unsigned len; 156 157 if (e->err || !str) 158 return; 159 160 len = strlen(str); 161 if (!__i915_error_grow(e, len)) 162 return; 163 164 GEM_BUG_ON(e->bytes + len > e->size); 165 memcpy(e->buf + e->bytes, str, len); 166 e->bytes += len; 167 } 168 169 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 170 #define err_puts(e, s) i915_error_puts(e, s) 171 172 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 173 { 174 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 175 } 176 177 static inline struct drm_printer 178 i915_error_printer(struct drm_i915_error_state_buf *e) 179 { 180 struct drm_printer p = { 181 .printfn = __i915_printfn_error, 182 .arg = e, 183 }; 184 return p; 185 } 186 187 /* single threaded page allocator with a reserved stash for emergencies */ 188 static void pool_fini(struct pagevec *pv) 189 { 190 STUB(); 191 #ifdef notyet 192 pagevec_release(pv); 193 #endif 194 } 195 196 static int pool_refill(struct pagevec *pv, gfp_t gfp) 197 { 198 while (pagevec_space(pv)) { 199 struct vm_page *p; 200 201 p = alloc_page(gfp); 202 if (!p) 203 return -ENOMEM; 204 205 pagevec_add(pv, p); 206 } 207 208 return 0; 209 } 210 211 static int intel_pool_init(struct pagevec *pv, gfp_t gfp) 212 { 213 int err; 214 215 pagevec_init(pv); 216 217 err = pool_refill(pv, gfp); 218 if (err) 219 pool_fini(pv); 220 221 return err; 222 } 223 224 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 225 { 226 STUB(); 227 return NULL; 228 #ifdef notyet 229 struct vm_page *p; 230 231 p = alloc_page(gfp); 232 if (!p && pagevec_count(pv)) 233 p = pv->pages[--pv->nr]; 234 235 return p ? page_address(p) : NULL; 236 #endif 237 } 238 239 static void pool_free(struct pagevec *pv, void *addr) 240 { 241 STUB(); 242 #ifdef notyet 243 struct vm_page *p = virt_to_page(addr); 244 245 if (pagevec_space(pv)) 246 pagevec_add(pv, p); 247 else 248 __free_page(p); 249 #endif 250 } 251 252 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 253 254 struct i915_vma_compress { 255 struct pagevec pool; 256 struct z_stream_s zstream; 257 void *tmp; 258 }; 259 260 static bool compress_init(struct i915_vma_compress *c) 261 { 262 struct z_stream_s *zstream = &c->zstream; 263 264 if (intel_pool_init(&c->pool, ALLOW_FAIL)) 265 return false; 266 267 zstream->workspace = 268 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 269 ALLOW_FAIL); 270 if (!zstream->workspace) { 271 pool_fini(&c->pool); 272 return false; 273 } 274 275 c->tmp = NULL; 276 if (i915_has_memcpy_from_wc()) 277 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 278 279 return true; 280 } 281 282 static bool compress_start(struct i915_vma_compress *c) 283 { 284 struct z_stream_s *zstream = &c->zstream; 285 void *workspace = zstream->workspace; 286 287 memset(zstream, 0, sizeof(*zstream)); 288 zstream->workspace = workspace; 289 290 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 291 } 292 293 static void *compress_next_page(struct i915_vma_compress *c, 294 struct i915_vma_coredump *dst) 295 { 296 void *page; 297 298 if (dst->page_count >= dst->num_pages) 299 return ERR_PTR(-ENOSPC); 300 301 page = pool_alloc(&c->pool, ALLOW_FAIL); 302 if (!page) 303 return ERR_PTR(-ENOMEM); 304 305 return dst->pages[dst->page_count++] = page; 306 } 307 308 static int compress_page(struct i915_vma_compress *c, 309 void *src, 310 struct i915_vma_coredump *dst, 311 bool wc) 312 { 313 struct z_stream_s *zstream = &c->zstream; 314 315 zstream->next_in = src; 316 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 317 zstream->next_in = c->tmp; 318 zstream->avail_in = PAGE_SIZE; 319 320 do { 321 if (zstream->avail_out == 0) { 322 zstream->next_out = compress_next_page(c, dst); 323 if (IS_ERR(zstream->next_out)) 324 return PTR_ERR(zstream->next_out); 325 326 zstream->avail_out = PAGE_SIZE; 327 } 328 329 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 330 return -EIO; 331 332 cond_resched(); 333 } while (zstream->avail_in); 334 335 /* Fallback to uncompressed if we increase size? */ 336 if (0 && zstream->total_out > zstream->total_in) 337 return -E2BIG; 338 339 return 0; 340 } 341 342 static int compress_flush(struct i915_vma_compress *c, 343 struct i915_vma_coredump *dst) 344 { 345 struct z_stream_s *zstream = &c->zstream; 346 347 do { 348 switch (zlib_deflate(zstream, Z_FINISH)) { 349 case Z_OK: /* more space requested */ 350 zstream->next_out = compress_next_page(c, dst); 351 if (IS_ERR(zstream->next_out)) 352 return PTR_ERR(zstream->next_out); 353 354 zstream->avail_out = PAGE_SIZE; 355 break; 356 357 case Z_STREAM_END: 358 goto end; 359 360 default: /* any error */ 361 return -EIO; 362 } 363 } while (1); 364 365 end: 366 memset(zstream->next_out, 0, zstream->avail_out); 367 dst->unused = zstream->avail_out; 368 return 0; 369 } 370 371 static void compress_finish(struct i915_vma_compress *c) 372 { 373 zlib_deflateEnd(&c->zstream); 374 } 375 376 static void compress_fini(struct i915_vma_compress *c) 377 { 378 kfree(c->zstream.workspace); 379 if (c->tmp) 380 pool_free(&c->pool, c->tmp); 381 pool_fini(&c->pool); 382 } 383 384 static void err_compression_marker(struct drm_i915_error_state_buf *m) 385 { 386 err_puts(m, ":"); 387 } 388 389 #else 390 391 struct i915_vma_compress { 392 struct pagevec pool; 393 }; 394 395 static bool compress_init(struct i915_vma_compress *c) 396 { 397 return intel_pool_init(&c->pool, ALLOW_FAIL) == 0; 398 } 399 400 static bool compress_start(struct i915_vma_compress *c) 401 { 402 return true; 403 } 404 405 static int compress_page(struct i915_vma_compress *c, 406 void *src, 407 struct i915_vma_coredump *dst, 408 bool wc) 409 { 410 void *ptr; 411 412 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 413 if (!ptr) 414 return -ENOMEM; 415 416 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 417 memcpy(ptr, src, PAGE_SIZE); 418 dst->pages[dst->page_count++] = ptr; 419 cond_resched(); 420 421 return 0; 422 } 423 424 static int compress_flush(struct i915_vma_compress *c, 425 struct i915_vma_coredump *dst) 426 { 427 return 0; 428 } 429 430 static void compress_finish(struct i915_vma_compress *c) 431 { 432 } 433 434 static void compress_fini(struct i915_vma_compress *c) 435 { 436 pool_fini(&c->pool); 437 } 438 439 static void err_compression_marker(struct drm_i915_error_state_buf *m) 440 { 441 err_puts(m, "~"); 442 } 443 444 #endif 445 446 static void error_print_instdone(struct drm_i915_error_state_buf *m, 447 const struct intel_engine_coredump *ee) 448 { 449 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 450 int slice; 451 int subslice; 452 453 err_printf(m, " INSTDONE: 0x%08x\n", 454 ee->instdone.instdone); 455 456 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3) 457 return; 458 459 err_printf(m, " SC_INSTDONE: 0x%08x\n", 460 ee->instdone.slice_common); 461 462 if (INTEL_GEN(m->i915) <= 6) 463 return; 464 465 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 466 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 467 slice, subslice, 468 ee->instdone.sampler[slice][subslice]); 469 470 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 471 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 472 slice, subslice, 473 ee->instdone.row[slice][subslice]); 474 475 if (INTEL_GEN(m->i915) < 12) 476 return; 477 478 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 479 ee->instdone.slice_common_extra[0]); 480 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 481 ee->instdone.slice_common_extra[1]); 482 } 483 484 static void error_print_request(struct drm_i915_error_state_buf *m, 485 const char *prefix, 486 const struct i915_request_coredump *erq) 487 { 488 if (!erq->seqno) 489 return; 490 491 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 492 prefix, erq->pid, erq->context, erq->seqno, 493 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 494 &erq->flags) ? "!" : "", 495 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 496 &erq->flags) ? "+" : "", 497 erq->sched_attr.priority, 498 erq->head, erq->tail); 499 } 500 501 static void error_print_context(struct drm_i915_error_state_buf *m, 502 const char *header, 503 const struct i915_gem_context_coredump *ctx) 504 { 505 const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; 506 507 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 508 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 509 ctx->guilty, ctx->active, 510 ctx->total_runtime * period, 511 mul_u32_u32(ctx->avg_runtime, period)); 512 } 513 514 static struct i915_vma_coredump * 515 __find_vma(struct i915_vma_coredump *vma, const char *name) 516 { 517 while (vma) { 518 if (strcmp(vma->name, name) == 0) 519 return vma; 520 vma = vma->next; 521 } 522 523 return NULL; 524 } 525 526 static struct i915_vma_coredump * 527 find_batch(const struct intel_engine_coredump *ee) 528 { 529 return __find_vma(ee->vma, "batch"); 530 } 531 532 static void error_print_engine(struct drm_i915_error_state_buf *m, 533 const struct intel_engine_coredump *ee) 534 { 535 struct i915_vma_coredump *batch; 536 int n; 537 538 err_printf(m, "%s command stream:\n", ee->engine->name); 539 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 540 err_printf(m, " START: 0x%08x\n", ee->start); 541 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 542 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 543 ee->tail, ee->rq_post, ee->rq_tail); 544 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 545 err_printf(m, " MODE: 0x%08x\n", ee->mode); 546 err_printf(m, " HWS: 0x%08x\n", ee->hws); 547 err_printf(m, " ACTHD: 0x%08x %08x\n", 548 (u32)(ee->acthd>>32), (u32)ee->acthd); 549 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 550 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 551 err_printf(m, " ESR: 0x%08x\n", ee->esr); 552 553 error_print_instdone(m, ee); 554 555 batch = find_batch(ee); 556 if (batch) { 557 u64 start = batch->gtt_offset; 558 u64 end = start + batch->gtt_size; 559 560 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 561 upper_32_bits(start), lower_32_bits(start), 562 upper_32_bits(end), lower_32_bits(end)); 563 } 564 if (INTEL_GEN(m->i915) >= 4) { 565 err_printf(m, " BBADDR: 0x%08x_%08x\n", 566 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 567 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 568 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 569 } 570 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 571 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 572 lower_32_bits(ee->faddr)); 573 if (INTEL_GEN(m->i915) >= 6) { 574 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 575 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 576 } 577 if (HAS_PPGTT(m->i915)) { 578 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 579 580 if (INTEL_GEN(m->i915) >= 8) { 581 int i; 582 for (i = 0; i < 4; i++) 583 err_printf(m, " PDP%d: 0x%016llx\n", 584 i, ee->vm_info.pdp[i]); 585 } else { 586 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 587 ee->vm_info.pp_dir_base); 588 } 589 } 590 err_printf(m, " engine reset count: %u\n", ee->reset_count); 591 592 for (n = 0; n < ee->num_ports; n++) { 593 err_printf(m, " ELSP[%d]:", n); 594 error_print_request(m, " ", &ee->execlist[n]); 595 } 596 597 error_print_context(m, " Active context: ", &ee->context); 598 } 599 600 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 601 { 602 va_list args; 603 604 va_start(args, f); 605 i915_error_vprintf(e, f, args); 606 va_end(args); 607 } 608 609 static void print_error_vma(struct drm_i915_error_state_buf *m, 610 const struct intel_engine_cs *engine, 611 const struct i915_vma_coredump *vma) 612 { 613 STUB(); 614 #ifdef notyet 615 char out[ASCII85_BUFSZ]; 616 int page; 617 618 if (!vma) 619 return; 620 621 err_printf(m, "%s --- %s = 0x%08x %08x\n", 622 engine ? engine->name : "global", vma->name, 623 upper_32_bits(vma->gtt_offset), 624 lower_32_bits(vma->gtt_offset)); 625 626 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 627 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 628 629 err_compression_marker(m); 630 for (page = 0; page < vma->page_count; page++) { 631 int i, len; 632 633 len = PAGE_SIZE; 634 if (page == vma->page_count - 1) 635 len -= vma->unused; 636 len = ascii85_encode_len(len); 637 638 for (i = 0; i < len; i++) 639 err_puts(m, ascii85_encode(vma->pages[page][i], out)); 640 } 641 err_puts(m, "\n"); 642 #endif 643 } 644 645 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 646 struct i915_gpu_coredump *error) 647 { 648 struct drm_printer p = i915_error_printer(m); 649 650 intel_device_info_print_static(&error->device_info, &p); 651 intel_device_info_print_runtime(&error->runtime_info, &p); 652 intel_driver_caps_print(&error->driver_caps, &p); 653 } 654 655 static void err_print_params(struct drm_i915_error_state_buf *m, 656 const struct i915_params *params) 657 { 658 struct drm_printer p = i915_error_printer(m); 659 660 i915_params_dump(params, &p); 661 } 662 663 static void err_print_pciid(struct drm_i915_error_state_buf *m, 664 struct drm_i915_private *i915) 665 { 666 struct pci_dev *pdev = i915->drm.pdev; 667 668 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 669 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 670 err_printf(m, "PCI Subsystem: %04x:%04x\n", 671 pdev->subsystem_vendor, 672 pdev->subsystem_device); 673 } 674 675 static void err_print_uc(struct drm_i915_error_state_buf *m, 676 const struct intel_uc_coredump *error_uc) 677 { 678 struct drm_printer p = i915_error_printer(m); 679 680 intel_uc_fw_dump(&error_uc->guc_fw, &p); 681 intel_uc_fw_dump(&error_uc->huc_fw, &p); 682 print_error_vma(m, NULL, error_uc->guc_log); 683 } 684 685 static void err_free_sgl(struct scatterlist *sgl) 686 { 687 STUB(); 688 #ifdef notyet 689 while (sgl) { 690 struct scatterlist *sg; 691 692 for (sg = sgl; !sg_is_chain(sg); sg++) { 693 kfree(sg_virt(sg)); 694 if (sg_is_last(sg)) 695 break; 696 } 697 698 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 699 free_page((unsigned long)sgl); 700 sgl = sg; 701 } 702 #endif 703 } 704 705 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 706 struct intel_gt_coredump *gt) 707 { 708 struct drm_printer p = i915_error_printer(m); 709 710 intel_gt_info_print(>->info, &p); 711 intel_sseu_print_topology(>->info.sseu, &p); 712 } 713 714 static void err_print_gt(struct drm_i915_error_state_buf *m, 715 struct intel_gt_coredump *gt) 716 { 717 const struct intel_engine_coredump *ee; 718 int i; 719 720 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 721 err_printf(m, "EIR: 0x%08x\n", gt->eir); 722 err_printf(m, "IER: 0x%08x\n", gt->ier); 723 for (i = 0; i < gt->ngtier; i++) 724 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 725 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 726 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 727 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 728 729 for (i = 0; i < gt->nfence; i++) 730 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 731 732 if (IS_GEN_RANGE(m->i915, 6, 11)) { 733 err_printf(m, "ERROR: 0x%08x\n", gt->error); 734 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 735 } 736 737 if (INTEL_GEN(m->i915) >= 8) 738 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 739 gt->fault_data1, gt->fault_data0); 740 741 if (IS_GEN(m->i915, 7)) 742 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 743 744 if (IS_GEN_RANGE(m->i915, 8, 11)) 745 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 746 747 if (IS_GEN(m->i915, 12)) 748 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 749 750 if (INTEL_GEN(m->i915) >= 12) { 751 int i; 752 753 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 754 /* 755 * SFC_DONE resides in the VD forcewake domain, so it 756 * only exists if the corresponding VCS engine is 757 * present. 758 */ 759 if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) 760 continue; 761 762 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 763 gt->sfc_done[i]); 764 } 765 766 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 767 } 768 769 for (ee = gt->engine; ee; ee = ee->next) { 770 const struct i915_vma_coredump *vma; 771 772 error_print_engine(m, ee); 773 for (vma = ee->vma; vma; vma = vma->next) 774 print_error_vma(m, ee->engine, vma); 775 } 776 777 if (gt->uc) 778 err_print_uc(m, gt->uc); 779 780 err_print_gt_info(m, gt); 781 } 782 783 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 784 struct i915_gpu_coredump *error) 785 { 786 const struct intel_engine_coredump *ee; 787 struct timespec64 ts; 788 789 if (*error->error_msg) 790 err_printf(m, "%s\n", error->error_msg); 791 #ifdef __linux__ 792 err_printf(m, "Kernel: %s %s\n", 793 init_utsname()->release, 794 init_utsname()->machine); 795 #else 796 extern char machine[]; 797 err_printf(m, "Kernel: %s %s\n", 798 osrelease, 799 machine); 800 #endif 801 err_printf(m, "Driver: %s\n", DRIVER_DATE); 802 ts = ktime_to_timespec64(error->time); 803 err_printf(m, "Time: %lld s %ld us\n", 804 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 805 ts = ktime_to_timespec64(error->boottime); 806 err_printf(m, "Boottime: %lld s %ld us\n", 807 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 808 ts = ktime_to_timespec64(error->uptime); 809 err_printf(m, "Uptime: %lld s %ld us\n", 810 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 811 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 812 error->capture, jiffies_to_msecs(jiffies - error->capture)); 813 814 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 815 err_printf(m, "Active process (on ring %s): %s [%d]\n", 816 ee->engine->name, 817 ee->context.comm, 818 ee->context.pid); 819 820 err_printf(m, "Reset count: %u\n", error->reset_count); 821 err_printf(m, "Suspend count: %u\n", error->suspend_count); 822 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 823 err_printf(m, "Subplatform: 0x%x\n", 824 intel_subplatform(&error->runtime_info, 825 error->device_info.platform)); 826 err_print_pciid(m, m->i915); 827 828 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 829 830 if (HAS_CSR(m->i915)) { 831 struct intel_csr *csr = &m->i915->csr; 832 833 err_printf(m, "DMC loaded: %s\n", 834 yesno(csr->dmc_payload != NULL)); 835 err_printf(m, "DMC fw version: %d.%d\n", 836 CSR_VERSION_MAJOR(csr->version), 837 CSR_VERSION_MINOR(csr->version)); 838 } 839 840 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 841 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 842 843 if (error->gt) 844 err_print_gt(m, error->gt); 845 846 if (error->overlay) 847 intel_overlay_print_error_state(m, error->overlay); 848 849 if (error->display) 850 intel_display_print_error_state(m, error->display); 851 852 err_print_capabilities(m, error); 853 err_print_params(m, &error->params); 854 } 855 856 static int err_print_to_sgl(struct i915_gpu_coredump *error) 857 { 858 struct drm_i915_error_state_buf m; 859 860 if (IS_ERR(error)) 861 return PTR_ERR(error); 862 863 if (READ_ONCE(error->sgl)) 864 return 0; 865 866 memset(&m, 0, sizeof(m)); 867 m.i915 = error->i915; 868 869 __err_print_to_sgl(&m, error); 870 871 if (m.buf) { 872 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 873 m.bytes = 0; 874 m.buf = NULL; 875 } 876 if (m.cur) { 877 GEM_BUG_ON(m.end < m.cur); 878 sg_mark_end(m.cur - 1); 879 } 880 GEM_BUG_ON(m.sgl && !m.cur); 881 882 if (m.err) { 883 err_free_sgl(m.sgl); 884 return m.err; 885 } 886 887 if (cmpxchg(&error->sgl, NULL, m.sgl)) 888 err_free_sgl(m.sgl); 889 890 return 0; 891 } 892 893 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 894 char *buf, loff_t off, size_t rem) 895 { 896 STUB(); 897 return -ENOSYS; 898 #ifdef notyet 899 struct scatterlist *sg; 900 size_t count; 901 loff_t pos; 902 int err; 903 904 if (!error || !rem) 905 return 0; 906 907 err = err_print_to_sgl(error); 908 if (err) 909 return err; 910 911 sg = READ_ONCE(error->fit); 912 if (!sg || off < sg->dma_address) 913 sg = error->sgl; 914 if (!sg) 915 return 0; 916 917 pos = sg->dma_address; 918 count = 0; 919 do { 920 size_t len, start; 921 922 if (sg_is_chain(sg)) { 923 sg = sg_chain_ptr(sg); 924 GEM_BUG_ON(sg_is_chain(sg)); 925 } 926 927 len = sg->length; 928 if (pos + len <= off) { 929 pos += len; 930 continue; 931 } 932 933 start = sg->offset; 934 if (pos < off) { 935 GEM_BUG_ON(off - pos > len); 936 len -= off - pos; 937 start += off - pos; 938 pos = off; 939 } 940 941 len = min(len, rem); 942 GEM_BUG_ON(!len || len > sg->length); 943 944 memcpy(buf, page_address(sg_page(sg)) + start, len); 945 946 count += len; 947 pos += len; 948 949 buf += len; 950 rem -= len; 951 if (!rem) { 952 WRITE_ONCE(error->fit, sg); 953 break; 954 } 955 } while (!sg_is_last(sg++)); 956 957 return count; 958 #endif 959 } 960 961 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 962 { 963 while (vma) { 964 struct i915_vma_coredump *next = vma->next; 965 int page; 966 967 for (page = 0; page < vma->page_count; page++) 968 free_page((unsigned long)vma->pages[page]); 969 970 kfree(vma); 971 vma = next; 972 } 973 } 974 975 static void cleanup_params(struct i915_gpu_coredump *error) 976 { 977 i915_params_free(&error->params); 978 } 979 980 static void cleanup_uc(struct intel_uc_coredump *uc) 981 { 982 kfree(uc->guc_fw.path); 983 kfree(uc->huc_fw.path); 984 i915_vma_coredump_free(uc->guc_log); 985 986 kfree(uc); 987 } 988 989 static void cleanup_gt(struct intel_gt_coredump *gt) 990 { 991 while (gt->engine) { 992 struct intel_engine_coredump *ee = gt->engine; 993 994 gt->engine = ee->next; 995 996 i915_vma_coredump_free(ee->vma); 997 kfree(ee); 998 } 999 1000 if (gt->uc) 1001 cleanup_uc(gt->uc); 1002 1003 kfree(gt); 1004 } 1005 1006 void __i915_gpu_coredump_free(struct kref *error_ref) 1007 { 1008 struct i915_gpu_coredump *error = 1009 container_of(error_ref, typeof(*error), ref); 1010 1011 while (error->gt) { 1012 struct intel_gt_coredump *gt = error->gt; 1013 1014 error->gt = gt->next; 1015 cleanup_gt(gt); 1016 } 1017 1018 kfree(error->overlay); 1019 kfree(error->display); 1020 1021 cleanup_params(error); 1022 1023 err_free_sgl(error->sgl); 1024 kfree(error); 1025 } 1026 1027 static struct i915_vma_coredump * 1028 i915_vma_coredump_create(const struct intel_gt *gt, 1029 const struct i915_vma *vma, 1030 const char *name, 1031 struct i915_vma_compress *compress) 1032 { 1033 STUB(); 1034 return NULL; 1035 #ifdef notyet 1036 struct i915_ggtt *ggtt = gt->ggtt; 1037 const u64 slot = ggtt->error_capture.start; 1038 struct i915_vma_coredump *dst; 1039 unsigned long num_pages; 1040 struct sgt_iter iter; 1041 int ret; 1042 1043 might_sleep(); 1044 1045 if (!vma || !vma->pages || !compress) 1046 return NULL; 1047 1048 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 1049 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 1050 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); 1051 if (!dst) 1052 return NULL; 1053 1054 if (!compress_start(compress)) { 1055 kfree(dst); 1056 return NULL; 1057 } 1058 1059 strlcpy(dst->name, name, sizeof(dst->name)); 1060 dst->next = NULL; 1061 1062 dst->gtt_offset = vma->node.start; 1063 dst->gtt_size = vma->node.size; 1064 dst->gtt_page_sizes = vma->page_sizes.gtt; 1065 dst->num_pages = num_pages; 1066 dst->page_count = 0; 1067 dst->unused = 0; 1068 1069 ret = -EINVAL; 1070 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1071 void __iomem *s; 1072 dma_addr_t dma; 1073 1074 for_each_sgt_daddr(dma, iter, vma->pages) { 1075 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1076 I915_CACHE_NONE, 0); 1077 mb(); 1078 1079 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1080 ret = compress_page(compress, 1081 (void __force *)s, dst, 1082 true); 1083 io_mapping_unmap(s); 1084 if (ret) 1085 break; 1086 } 1087 } else if (i915_gem_object_is_lmem(vma->obj)) { 1088 struct intel_memory_region *mem = vma->obj->mm.region; 1089 dma_addr_t dma; 1090 1091 for_each_sgt_daddr(dma, iter, vma->pages) { 1092 void __iomem *s; 1093 1094 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE); 1095 ret = compress_page(compress, 1096 (void __force *)s, dst, 1097 true); 1098 io_mapping_unmap(s); 1099 if (ret) 1100 break; 1101 } 1102 } else { 1103 struct vm_page *page; 1104 1105 for_each_sgt_page(page, iter, vma->pages) { 1106 void *s; 1107 1108 drm_clflush_pages(&page, 1); 1109 1110 s = kmap(page); 1111 ret = compress_page(compress, s, dst, false); 1112 kunmap(page); 1113 1114 drm_clflush_pages(&page, 1); 1115 1116 if (ret) 1117 break; 1118 } 1119 } 1120 1121 if (ret || compress_flush(compress, dst)) { 1122 while (dst->page_count--) 1123 pool_free(&compress->pool, dst->pages[dst->page_count]); 1124 kfree(dst); 1125 dst = NULL; 1126 } 1127 compress_finish(compress); 1128 1129 return dst; 1130 #endif 1131 } 1132 1133 static void gt_record_fences(struct intel_gt_coredump *gt) 1134 { 1135 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1136 struct intel_uncore *uncore = gt->_gt->uncore; 1137 int i; 1138 1139 if (INTEL_GEN(uncore->i915) >= 6) { 1140 for (i = 0; i < ggtt->num_fences; i++) 1141 gt->fence[i] = 1142 intel_uncore_read64(uncore, 1143 FENCE_REG_GEN6_LO(i)); 1144 } else if (INTEL_GEN(uncore->i915) >= 4) { 1145 for (i = 0; i < ggtt->num_fences; i++) 1146 gt->fence[i] = 1147 intel_uncore_read64(uncore, 1148 FENCE_REG_965_LO(i)); 1149 } else { 1150 for (i = 0; i < ggtt->num_fences; i++) 1151 gt->fence[i] = 1152 intel_uncore_read(uncore, FENCE_REG(i)); 1153 } 1154 gt->nfence = i; 1155 } 1156 1157 static void engine_record_registers(struct intel_engine_coredump *ee) 1158 { 1159 const struct intel_engine_cs *engine = ee->engine; 1160 struct drm_i915_private *i915 = engine->i915; 1161 1162 if (INTEL_GEN(i915) >= 6) { 1163 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1164 1165 if (INTEL_GEN(i915) >= 12) 1166 ee->fault_reg = intel_uncore_read(engine->uncore, 1167 GEN12_RING_FAULT_REG); 1168 else if (INTEL_GEN(i915) >= 8) 1169 ee->fault_reg = intel_uncore_read(engine->uncore, 1170 GEN8_RING_FAULT_REG); 1171 else 1172 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1173 } 1174 1175 if (INTEL_GEN(i915) >= 4) { 1176 ee->esr = ENGINE_READ(engine, RING_ESR); 1177 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1178 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1179 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1180 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1181 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1182 ee->ccid = ENGINE_READ(engine, CCID); 1183 if (INTEL_GEN(i915) >= 8) { 1184 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1185 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1186 } 1187 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1188 } else { 1189 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1190 ee->ipeir = ENGINE_READ(engine, IPEIR); 1191 ee->ipehr = ENGINE_READ(engine, IPEHR); 1192 } 1193 1194 intel_engine_get_instdone(engine, &ee->instdone); 1195 1196 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1197 ee->acthd = intel_engine_get_active_head(engine); 1198 ee->start = ENGINE_READ(engine, RING_START); 1199 ee->head = ENGINE_READ(engine, RING_HEAD); 1200 ee->tail = ENGINE_READ(engine, RING_TAIL); 1201 ee->ctl = ENGINE_READ(engine, RING_CTL); 1202 if (INTEL_GEN(i915) > 2) 1203 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1204 1205 if (!HWS_NEEDS_PHYSICAL(i915)) { 1206 i915_reg_t mmio; 1207 1208 if (IS_GEN(i915, 7)) { 1209 switch (engine->id) { 1210 default: 1211 MISSING_CASE(engine->id); 1212 fallthrough; 1213 case RCS0: 1214 mmio = RENDER_HWS_PGA_GEN7; 1215 break; 1216 case BCS0: 1217 mmio = BLT_HWS_PGA_GEN7; 1218 break; 1219 case VCS0: 1220 mmio = BSD_HWS_PGA_GEN7; 1221 break; 1222 case VECS0: 1223 mmio = VEBOX_HWS_PGA_GEN7; 1224 break; 1225 } 1226 } else if (IS_GEN(engine->i915, 6)) { 1227 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1228 } else { 1229 /* XXX: gen8 returns to sanity */ 1230 mmio = RING_HWS_PGA(engine->mmio_base); 1231 } 1232 1233 ee->hws = intel_uncore_read(engine->uncore, mmio); 1234 } 1235 1236 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1237 1238 if (HAS_PPGTT(i915)) { 1239 int i; 1240 1241 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1242 1243 if (IS_GEN(i915, 6)) { 1244 ee->vm_info.pp_dir_base = 1245 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1246 } else if (IS_GEN(i915, 7)) { 1247 ee->vm_info.pp_dir_base = 1248 ENGINE_READ(engine, RING_PP_DIR_BASE); 1249 } else if (INTEL_GEN(i915) >= 8) { 1250 u32 base = engine->mmio_base; 1251 1252 for (i = 0; i < 4; i++) { 1253 ee->vm_info.pdp[i] = 1254 intel_uncore_read(engine->uncore, 1255 GEN8_RING_PDP_UDW(base, i)); 1256 ee->vm_info.pdp[i] <<= 32; 1257 ee->vm_info.pdp[i] |= 1258 intel_uncore_read(engine->uncore, 1259 GEN8_RING_PDP_LDW(base, i)); 1260 } 1261 } 1262 } 1263 } 1264 1265 static void record_request(const struct i915_request *request, 1266 struct i915_request_coredump *erq) 1267 { 1268 erq->flags = request->fence.flags; 1269 erq->context = request->fence.context; 1270 erq->seqno = request->fence.seqno; 1271 erq->sched_attr = request->sched.attr; 1272 erq->head = request->head; 1273 erq->tail = request->tail; 1274 1275 erq->pid = 0; 1276 rcu_read_lock(); 1277 if (!intel_context_is_closed(request->context)) { 1278 const struct i915_gem_context *ctx; 1279 1280 ctx = rcu_dereference(request->context->gem_context); 1281 if (ctx) 1282 #ifdef __linux__ 1283 erq->pid = pid_nr(ctx->pid); 1284 #else 1285 erq->pid = ctx->pid; 1286 #endif 1287 } 1288 rcu_read_unlock(); 1289 } 1290 1291 static void engine_record_execlists(struct intel_engine_coredump *ee) 1292 { 1293 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1294 struct i915_request * const *port = el->active; 1295 unsigned int n = 0; 1296 1297 while (*port) 1298 record_request(*port++, &ee->execlist[n++]); 1299 1300 ee->num_ports = n; 1301 } 1302 1303 static bool record_context(struct i915_gem_context_coredump *e, 1304 const struct i915_request *rq) 1305 { 1306 struct i915_gem_context *ctx; 1307 struct task_struct *task; 1308 bool simulated; 1309 1310 rcu_read_lock(); 1311 ctx = rcu_dereference(rq->context->gem_context); 1312 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1313 ctx = NULL; 1314 rcu_read_unlock(); 1315 if (!ctx) 1316 return true; 1317 1318 #ifdef __linux__ 1319 rcu_read_lock(); 1320 task = pid_task(ctx->pid, PIDTYPE_PID); 1321 if (task) { 1322 strcpy(e->comm, task->comm); 1323 e->pid = task->pid; 1324 } 1325 rcu_read_unlock(); 1326 #endif 1327 1328 e->sched_attr = ctx->sched; 1329 e->guilty = atomic_read(&ctx->guilty_count); 1330 e->active = atomic_read(&ctx->active_count); 1331 1332 e->total_runtime = rq->context->runtime.total; 1333 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1334 1335 simulated = i915_gem_context_no_error_capture(ctx); 1336 1337 i915_gem_context_put(ctx); 1338 return simulated; 1339 } 1340 1341 struct intel_engine_capture_vma { 1342 struct intel_engine_capture_vma *next; 1343 struct i915_vma *vma; 1344 char name[16]; 1345 }; 1346 1347 static struct intel_engine_capture_vma * 1348 capture_vma(struct intel_engine_capture_vma *next, 1349 struct i915_vma *vma, 1350 const char *name, 1351 gfp_t gfp) 1352 { 1353 struct intel_engine_capture_vma *c; 1354 1355 if (!vma) 1356 return next; 1357 1358 c = kmalloc(sizeof(*c), gfp); 1359 if (!c) 1360 return next; 1361 1362 if (!i915_active_acquire_if_busy(&vma->active)) { 1363 kfree(c); 1364 return next; 1365 } 1366 1367 strlcpy(c->name, name, sizeof(c->name)); 1368 c->vma = vma; /* reference held while active */ 1369 1370 c->next = next; 1371 return c; 1372 } 1373 1374 static struct intel_engine_capture_vma * 1375 capture_user(struct intel_engine_capture_vma *capture, 1376 const struct i915_request *rq, 1377 gfp_t gfp) 1378 { 1379 struct i915_capture_list *c; 1380 1381 for (c = rq->capture_list; c; c = c->next) 1382 capture = capture_vma(capture, c->vma, "user", gfp); 1383 1384 return capture; 1385 } 1386 1387 static void add_vma(struct intel_engine_coredump *ee, 1388 struct i915_vma_coredump *vma) 1389 { 1390 if (vma) { 1391 vma->next = ee->vma; 1392 ee->vma = vma; 1393 } 1394 } 1395 1396 struct intel_engine_coredump * 1397 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1398 { 1399 struct intel_engine_coredump *ee; 1400 1401 ee = kzalloc(sizeof(*ee), gfp); 1402 if (!ee) 1403 return NULL; 1404 1405 ee->engine = engine; 1406 1407 engine_record_registers(ee); 1408 engine_record_execlists(ee); 1409 1410 return ee; 1411 } 1412 1413 struct intel_engine_capture_vma * 1414 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1415 struct i915_request *rq, 1416 gfp_t gfp) 1417 { 1418 struct intel_engine_capture_vma *vma = NULL; 1419 1420 ee->simulated |= record_context(&ee->context, rq); 1421 if (ee->simulated) 1422 return NULL; 1423 1424 /* 1425 * We need to copy these to an anonymous buffer 1426 * as the simplest method to avoid being overwritten 1427 * by userspace. 1428 */ 1429 vma = capture_vma(vma, rq->batch, "batch", gfp); 1430 vma = capture_user(vma, rq, gfp); 1431 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1432 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1433 1434 ee->rq_head = rq->head; 1435 ee->rq_post = rq->postfix; 1436 ee->rq_tail = rq->tail; 1437 1438 return vma; 1439 } 1440 1441 void 1442 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1443 struct intel_engine_capture_vma *capture, 1444 struct i915_vma_compress *compress) 1445 { 1446 const struct intel_engine_cs *engine = ee->engine; 1447 1448 while (capture) { 1449 struct intel_engine_capture_vma *this = capture; 1450 struct i915_vma *vma = this->vma; 1451 1452 add_vma(ee, 1453 i915_vma_coredump_create(engine->gt, 1454 vma, this->name, 1455 compress)); 1456 1457 i915_active_release(&vma->active); 1458 1459 capture = this->next; 1460 kfree(this); 1461 } 1462 1463 add_vma(ee, 1464 i915_vma_coredump_create(engine->gt, 1465 engine->status_page.vma, 1466 "HW Status", 1467 compress)); 1468 1469 add_vma(ee, 1470 i915_vma_coredump_create(engine->gt, 1471 engine->wa_ctx.vma, 1472 "WA context", 1473 compress)); 1474 } 1475 1476 static struct intel_engine_coredump * 1477 capture_engine(struct intel_engine_cs *engine, 1478 struct i915_vma_compress *compress) 1479 { 1480 struct intel_engine_capture_vma *capture = NULL; 1481 struct intel_engine_coredump *ee; 1482 struct i915_request *rq; 1483 unsigned long flags; 1484 1485 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); 1486 if (!ee) 1487 return NULL; 1488 1489 spin_lock_irqsave(&engine->active.lock, flags); 1490 rq = intel_engine_find_active_request(engine); 1491 if (rq) 1492 capture = intel_engine_coredump_add_request(ee, rq, 1493 ATOMIC_MAYFAIL); 1494 spin_unlock_irqrestore(&engine->active.lock, flags); 1495 if (!capture) { 1496 kfree(ee); 1497 return NULL; 1498 } 1499 1500 intel_engine_coredump_add_vma(ee, capture, compress); 1501 1502 return ee; 1503 } 1504 1505 static void 1506 gt_record_engines(struct intel_gt_coredump *gt, 1507 struct i915_vma_compress *compress) 1508 { 1509 struct intel_engine_cs *engine; 1510 enum intel_engine_id id; 1511 1512 for_each_engine(engine, gt->_gt, id) { 1513 struct intel_engine_coredump *ee; 1514 1515 /* Refill our page pool before entering atomic section */ 1516 pool_refill(&compress->pool, ALLOW_FAIL); 1517 1518 ee = capture_engine(engine, compress); 1519 if (!ee) 1520 continue; 1521 1522 gt->simulated |= ee->simulated; 1523 if (ee->simulated) { 1524 kfree(ee); 1525 continue; 1526 } 1527 1528 ee->next = gt->engine; 1529 gt->engine = ee; 1530 } 1531 } 1532 1533 static struct intel_uc_coredump * 1534 gt_record_uc(struct intel_gt_coredump *gt, 1535 struct i915_vma_compress *compress) 1536 { 1537 const struct intel_uc *uc = >->_gt->uc; 1538 struct intel_uc_coredump *error_uc; 1539 1540 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1541 if (!error_uc) 1542 return NULL; 1543 1544 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1545 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1546 1547 /* Non-default firmware paths will be specified by the modparam. 1548 * As modparams are generally accesible from the userspace make 1549 * explicit copies of the firmware paths. 1550 */ 1551 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1552 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1553 error_uc->guc_log = 1554 i915_vma_coredump_create(gt->_gt, 1555 uc->guc.log.vma, "GuC log buffer", 1556 compress); 1557 1558 return error_uc; 1559 } 1560 1561 static void gt_capture_prepare(struct intel_gt_coredump *gt) 1562 { 1563 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1564 1565 mutex_lock(&ggtt->error_mutex); 1566 } 1567 1568 static void gt_capture_finish(struct intel_gt_coredump *gt) 1569 { 1570 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1571 1572 if (drm_mm_node_allocated(&ggtt->error_capture)) 1573 ggtt->vm.clear_range(&ggtt->vm, 1574 ggtt->error_capture.start, 1575 PAGE_SIZE); 1576 1577 mutex_unlock(&ggtt->error_mutex); 1578 } 1579 1580 /* Capture all registers which don't fit into another category. */ 1581 static void gt_record_regs(struct intel_gt_coredump *gt) 1582 { 1583 struct intel_uncore *uncore = gt->_gt->uncore; 1584 struct drm_i915_private *i915 = uncore->i915; 1585 int i; 1586 1587 /* 1588 * General organization 1589 * 1. Registers specific to a single generation 1590 * 2. Registers which belong to multiple generations 1591 * 3. Feature specific registers. 1592 * 4. Everything else 1593 * Please try to follow the order. 1594 */ 1595 1596 /* 1: Registers specific to a single generation */ 1597 if (IS_VALLEYVIEW(i915)) { 1598 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1599 gt->ier = intel_uncore_read(uncore, VLV_IER); 1600 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1601 } 1602 1603 if (IS_GEN(i915, 7)) 1604 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1605 1606 if (INTEL_GEN(i915) >= 12) { 1607 gt->fault_data0 = intel_uncore_read(uncore, 1608 GEN12_FAULT_TLB_DATA0); 1609 gt->fault_data1 = intel_uncore_read(uncore, 1610 GEN12_FAULT_TLB_DATA1); 1611 } else if (INTEL_GEN(i915) >= 8) { 1612 gt->fault_data0 = intel_uncore_read(uncore, 1613 GEN8_FAULT_TLB_DATA0); 1614 gt->fault_data1 = intel_uncore_read(uncore, 1615 GEN8_FAULT_TLB_DATA1); 1616 } 1617 1618 if (IS_GEN(i915, 6)) { 1619 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1620 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1621 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1622 } 1623 1624 /* 2: Registers which belong to multiple generations */ 1625 if (INTEL_GEN(i915) >= 7) 1626 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1627 1628 if (INTEL_GEN(i915) >= 6) { 1629 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1630 if (INTEL_GEN(i915) < 12) { 1631 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1632 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1633 } 1634 } 1635 1636 /* 3: Feature specific registers */ 1637 if (IS_GEN_RANGE(i915, 6, 7)) { 1638 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1639 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1640 } 1641 1642 if (IS_GEN_RANGE(i915, 8, 11)) 1643 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1644 1645 if (IS_GEN(i915, 12)) 1646 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1647 1648 if (INTEL_GEN(i915) >= 12) { 1649 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1650 /* 1651 * SFC_DONE resides in the VD forcewake domain, so it 1652 * only exists if the corresponding VCS engine is 1653 * present. 1654 */ 1655 if (!HAS_ENGINE(gt->_gt, _VCS(i * 2))) 1656 continue; 1657 1658 gt->sfc_done[i] = 1659 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1660 } 1661 1662 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1663 } 1664 1665 /* 4: Everything else */ 1666 if (INTEL_GEN(i915) >= 11) { 1667 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1668 gt->gtier[0] = 1669 intel_uncore_read(uncore, 1670 GEN11_RENDER_COPY_INTR_ENABLE); 1671 gt->gtier[1] = 1672 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1673 gt->gtier[2] = 1674 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1675 gt->gtier[3] = 1676 intel_uncore_read(uncore, 1677 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1678 gt->gtier[4] = 1679 intel_uncore_read(uncore, 1680 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1681 gt->gtier[5] = 1682 intel_uncore_read(uncore, 1683 GEN11_GUNIT_CSME_INTR_ENABLE); 1684 gt->ngtier = 6; 1685 } else if (INTEL_GEN(i915) >= 8) { 1686 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1687 for (i = 0; i < 4; i++) 1688 gt->gtier[i] = 1689 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1690 gt->ngtier = 4; 1691 } else if (HAS_PCH_SPLIT(i915)) { 1692 gt->ier = intel_uncore_read(uncore, DEIER); 1693 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1694 gt->ngtier = 1; 1695 } else if (IS_GEN(i915, 2)) { 1696 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1697 } else if (!IS_VALLEYVIEW(i915)) { 1698 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1699 } 1700 gt->eir = intel_uncore_read(uncore, EIR); 1701 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1702 } 1703 1704 static void gt_record_info(struct intel_gt_coredump *gt) 1705 { 1706 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1707 } 1708 1709 /* 1710 * Generate a semi-unique error code. The code is not meant to have meaning, The 1711 * code's only purpose is to try to prevent false duplicated bug reports by 1712 * grossly estimating a GPU error state. 1713 * 1714 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1715 * the hang if we could strip the GTT offset information from it. 1716 * 1717 * It's only a small step better than a random number in its current form. 1718 */ 1719 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1720 { 1721 /* 1722 * IPEHR would be an ideal way to detect errors, as it's the gross 1723 * measure of "the command that hung." However, has some very common 1724 * synchronization commands which almost always appear in the case 1725 * strictly a client bug. Use instdone to differentiate those some. 1726 */ 1727 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1728 } 1729 1730 static const char *error_msg(struct i915_gpu_coredump *error) 1731 { 1732 struct intel_engine_coredump *first = NULL; 1733 struct intel_gt_coredump *gt; 1734 intel_engine_mask_t engines; 1735 int len; 1736 1737 engines = 0; 1738 for (gt = error->gt; gt; gt = gt->next) { 1739 struct intel_engine_coredump *cs; 1740 1741 if (gt->engine && !first) 1742 first = gt->engine; 1743 1744 for (cs = gt->engine; cs; cs = cs->next) 1745 engines |= cs->engine->mask; 1746 } 1747 1748 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1749 "GPU HANG: ecode %d:%x:%08x", 1750 INTEL_GEN(error->i915), engines, 1751 generate_ecode(first)); 1752 if (first && first->context.pid) { 1753 /* Just show the first executing process, more is confusing */ 1754 len += scnprintf(error->error_msg + len, 1755 sizeof(error->error_msg) - len, 1756 ", in %s [%d]", 1757 first->context.comm, first->context.pid); 1758 } 1759 1760 return error->error_msg; 1761 } 1762 1763 static void capture_gen(struct i915_gpu_coredump *error) 1764 { 1765 struct drm_i915_private *i915 = error->i915; 1766 1767 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1768 error->suspended = i915->runtime_pm.suspended; 1769 1770 error->iommu = -1; 1771 #ifdef CONFIG_INTEL_IOMMU 1772 error->iommu = intel_iommu_gfx_mapped; 1773 #endif 1774 error->reset_count = i915_reset_count(&i915->gpu_error); 1775 error->suspend_count = i915->suspend_count; 1776 1777 i915_params_copy(&error->params, &i915->params); 1778 memcpy(&error->device_info, 1779 INTEL_INFO(i915), 1780 sizeof(error->device_info)); 1781 memcpy(&error->runtime_info, 1782 RUNTIME_INFO(i915), 1783 sizeof(error->runtime_info)); 1784 error->driver_caps = i915->caps; 1785 } 1786 1787 struct i915_gpu_coredump * 1788 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1789 { 1790 struct i915_gpu_coredump *error; 1791 1792 if (!i915->params.error_capture) 1793 return NULL; 1794 1795 error = kzalloc(sizeof(*error), gfp); 1796 if (!error) 1797 return NULL; 1798 1799 kref_init(&error->ref); 1800 error->i915 = i915; 1801 1802 error->time = ktime_get_real(); 1803 error->boottime = ktime_get_boottime(); 1804 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); 1805 error->capture = jiffies; 1806 1807 capture_gen(error); 1808 1809 return error; 1810 } 1811 1812 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1813 1814 struct intel_gt_coredump * 1815 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1816 { 1817 struct intel_gt_coredump *gc; 1818 1819 gc = kzalloc(sizeof(*gc), gfp); 1820 if (!gc) 1821 return NULL; 1822 1823 gc->_gt = gt; 1824 gc->awake = intel_gt_pm_is_awake(gt); 1825 1826 gt_record_regs(gc); 1827 gt_record_fences(gc); 1828 1829 return gc; 1830 } 1831 1832 struct i915_vma_compress * 1833 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1834 { 1835 struct i915_vma_compress *compress; 1836 1837 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1838 if (!compress) 1839 return NULL; 1840 1841 if (!compress_init(compress)) { 1842 kfree(compress); 1843 return NULL; 1844 } 1845 1846 gt_capture_prepare(gt); 1847 1848 return compress; 1849 } 1850 1851 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1852 struct i915_vma_compress *compress) 1853 { 1854 if (!compress) 1855 return; 1856 1857 gt_capture_finish(gt); 1858 1859 compress_fini(compress); 1860 kfree(compress); 1861 } 1862 1863 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) 1864 { 1865 struct i915_gpu_coredump *error; 1866 1867 /* Check if GPU capture has been disabled */ 1868 error = READ_ONCE(i915->gpu_error.first_error); 1869 if (IS_ERR(error)) 1870 return error; 1871 1872 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1873 if (!error) 1874 return ERR_PTR(-ENOMEM); 1875 1876 error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL); 1877 if (error->gt) { 1878 struct i915_vma_compress *compress; 1879 1880 compress = i915_vma_capture_prepare(error->gt); 1881 if (!compress) { 1882 kfree(error->gt); 1883 kfree(error); 1884 return ERR_PTR(-ENOMEM); 1885 } 1886 1887 gt_record_info(error->gt); 1888 gt_record_engines(error->gt, compress); 1889 1890 if (INTEL_INFO(i915)->has_gt_uc) 1891 error->gt->uc = gt_record_uc(error->gt, compress); 1892 1893 i915_vma_capture_finish(error->gt, compress); 1894 1895 error->simulated |= error->gt->simulated; 1896 } 1897 1898 error->overlay = intel_overlay_capture_error_state(i915); 1899 error->display = intel_display_capture_error_state(i915); 1900 1901 return error; 1902 } 1903 1904 void i915_error_state_store(struct i915_gpu_coredump *error) 1905 { 1906 struct drm_i915_private *i915; 1907 static bool warned; 1908 1909 if (IS_ERR_OR_NULL(error)) 1910 return; 1911 1912 i915 = error->i915; 1913 drm_info(&i915->drm, "%s\n", error_msg(error)); 1914 1915 if (error->simulated || 1916 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1917 return; 1918 1919 i915_gpu_coredump_get(error); 1920 1921 if (!xchg(&warned, true) && 1922 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1923 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1924 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1925 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1926 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1927 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1928 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1929 i915->drm.primary->index); 1930 } 1931 } 1932 1933 /** 1934 * i915_capture_error_state - capture an error record for later analysis 1935 * @i915: i915 device 1936 * 1937 * Should be called when an error is detected (either a hang or an error 1938 * interrupt) to capture error state from the time of the error. Fills 1939 * out a structure which becomes available in debugfs for user level tools 1940 * to pick up. 1941 */ 1942 void i915_capture_error_state(struct drm_i915_private *i915) 1943 { 1944 struct i915_gpu_coredump *error; 1945 1946 error = i915_gpu_coredump(i915); 1947 if (IS_ERR(error)) { 1948 cmpxchg(&i915->gpu_error.first_error, NULL, error); 1949 return; 1950 } 1951 1952 i915_error_state_store(error); 1953 i915_gpu_coredump_put(error); 1954 } 1955 1956 struct i915_gpu_coredump * 1957 i915_first_error_state(struct drm_i915_private *i915) 1958 { 1959 struct i915_gpu_coredump *error; 1960 1961 spin_lock_irq(&i915->gpu_error.lock); 1962 error = i915->gpu_error.first_error; 1963 if (!IS_ERR_OR_NULL(error)) 1964 i915_gpu_coredump_get(error); 1965 spin_unlock_irq(&i915->gpu_error.lock); 1966 1967 return error; 1968 } 1969 1970 void i915_reset_error_state(struct drm_i915_private *i915) 1971 { 1972 struct i915_gpu_coredump *error; 1973 1974 spin_lock_irq(&i915->gpu_error.lock); 1975 error = i915->gpu_error.first_error; 1976 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1977 i915->gpu_error.first_error = NULL; 1978 spin_unlock_irq(&i915->gpu_error.lock); 1979 1980 if (!IS_ERR_OR_NULL(error)) 1981 i915_gpu_coredump_put(error); 1982 } 1983 1984 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1985 { 1986 spin_lock_irq(&i915->gpu_error.lock); 1987 if (!i915->gpu_error.first_error) 1988 i915->gpu_error.first_error = ERR_PTR(err); 1989 spin_unlock_irq(&i915->gpu_error.lock); 1990 } 1991