1 /* 2 * Copyright (c) 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Keith Packard <keithp@keithp.com> 26 * Mika Kuoppala <mika.kuoppala@intel.com> 27 * 28 */ 29 30 #include <linux/ascii85.h> 31 #include <linux/nmi.h> 32 #include <linux/pagevec.h> 33 #include <linux/scatterlist.h> 34 #include <linux/utsname.h> 35 #include <linux/zlib.h> 36 37 #include <drm/drm_print.h> 38 39 #include "display/intel_atomic.h" 40 #include "display/intel_csr.h" 41 #include "display/intel_overlay.h" 42 43 #include "gem/i915_gem_context.h" 44 #include "gem/i915_gem_lmem.h" 45 #include "gt/intel_gt.h" 46 #include "gt/intel_gt_pm.h" 47 48 #include "i915_drv.h" 49 #include "i915_gpu_error.h" 50 #include "i915_memcpy.h" 51 #include "i915_scatterlist.h" 52 53 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN) 54 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN) 55 56 static void __sg_set_buf(struct scatterlist *sg, 57 void *addr, unsigned int len, loff_t it) 58 { 59 STUB(); 60 #ifdef notyet 61 sg->page_link = (unsigned long)virt_to_page(addr); 62 sg->offset = offset_in_page(addr); 63 sg->length = len; 64 sg->dma_address = it; 65 #endif 66 } 67 68 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len) 69 { 70 STUB(); 71 return false; 72 #ifdef notyet 73 if (!len) 74 return false; 75 76 if (e->bytes + len + 1 <= e->size) 77 return true; 78 79 if (e->bytes) { 80 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter); 81 e->iter += e->bytes; 82 e->buf = NULL; 83 e->bytes = 0; 84 } 85 86 if (e->cur == e->end) { 87 struct scatterlist *sgl; 88 89 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL); 90 if (!sgl) { 91 e->err = -ENOMEM; 92 return false; 93 } 94 95 if (e->cur) { 96 e->cur->offset = 0; 97 e->cur->length = 0; 98 e->cur->page_link = 99 (unsigned long)sgl | SG_CHAIN; 100 } else { 101 e->sgl = sgl; 102 } 103 104 e->cur = sgl; 105 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1; 106 } 107 108 e->size = roundup2(len + 1, SZ_64K); 109 e->buf = kmalloc(e->size, ALLOW_FAIL); 110 if (!e->buf) { 111 e->size = PAGE_ALIGN(len + 1); 112 e->buf = kmalloc(e->size, GFP_KERNEL); 113 } 114 if (!e->buf) { 115 e->err = -ENOMEM; 116 return false; 117 } 118 119 return true; 120 #endif 121 } 122 123 __printf(2, 0) 124 static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 125 const char *fmt, va_list args) 126 { 127 va_list ap; 128 int len; 129 130 if (e->err) 131 return; 132 133 va_copy(ap, args); 134 len = vsnprintf(NULL, 0, fmt, ap); 135 va_end(ap); 136 if (len <= 0) { 137 e->err = len; 138 return; 139 } 140 141 if (!__i915_error_grow(e, len)) 142 return; 143 144 GEM_BUG_ON(e->bytes >= e->size); 145 len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args); 146 if (len < 0) { 147 e->err = len; 148 return; 149 } 150 e->bytes += len; 151 } 152 153 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str) 154 { 155 unsigned len; 156 157 if (e->err || !str) 158 return; 159 160 len = strlen(str); 161 if (!__i915_error_grow(e, len)) 162 return; 163 164 GEM_BUG_ON(e->bytes + len > e->size); 165 memcpy(e->buf + e->bytes, str, len); 166 e->bytes += len; 167 } 168 169 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 170 #define err_puts(e, s) i915_error_puts(e, s) 171 172 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf) 173 { 174 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va); 175 } 176 177 static inline struct drm_printer 178 i915_error_printer(struct drm_i915_error_state_buf *e) 179 { 180 struct drm_printer p = { 181 .printfn = __i915_printfn_error, 182 .arg = e, 183 }; 184 return p; 185 } 186 187 /* single threaded page allocator with a reserved stash for emergencies */ 188 static void pool_fini(struct pagevec *pv) 189 { 190 STUB(); 191 #ifdef notyet 192 pagevec_release(pv); 193 #endif 194 } 195 196 static int pool_refill(struct pagevec *pv, gfp_t gfp) 197 { 198 while (pagevec_space(pv)) { 199 struct vm_page *p; 200 201 p = alloc_page(gfp); 202 if (!p) 203 return -ENOMEM; 204 205 pagevec_add(pv, p); 206 } 207 208 return 0; 209 } 210 211 static int intel_pool_init(struct pagevec *pv, gfp_t gfp) 212 { 213 int err; 214 215 pagevec_init(pv); 216 217 err = pool_refill(pv, gfp); 218 if (err) 219 pool_fini(pv); 220 221 return err; 222 } 223 224 static void *pool_alloc(struct pagevec *pv, gfp_t gfp) 225 { 226 STUB(); 227 return NULL; 228 #ifdef notyet 229 struct vm_page *p; 230 231 p = alloc_page(gfp); 232 if (!p && pagevec_count(pv)) 233 p = pv->pages[--pv->nr]; 234 235 return p ? page_address(p) : NULL; 236 #endif 237 } 238 239 static void pool_free(struct pagevec *pv, void *addr) 240 { 241 STUB(); 242 #ifdef notyet 243 struct vm_page *p = virt_to_page(addr); 244 245 if (pagevec_space(pv)) 246 pagevec_add(pv, p); 247 else 248 __free_page(p); 249 #endif 250 } 251 252 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR 253 254 struct i915_vma_compress { 255 struct pagevec pool; 256 struct z_stream_s zstream; 257 void *tmp; 258 }; 259 260 static bool compress_init(struct i915_vma_compress *c) 261 { 262 struct z_stream_s *zstream = &c->zstream; 263 264 if (intel_pool_init(&c->pool, ALLOW_FAIL)) 265 return false; 266 267 zstream->workspace = 268 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL), 269 ALLOW_FAIL); 270 if (!zstream->workspace) { 271 pool_fini(&c->pool); 272 return false; 273 } 274 275 c->tmp = NULL; 276 if (i915_has_memcpy_from_wc()) 277 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL); 278 279 return true; 280 } 281 282 static bool compress_start(struct i915_vma_compress *c) 283 { 284 struct z_stream_s *zstream = &c->zstream; 285 void *workspace = zstream->workspace; 286 287 memset(zstream, 0, sizeof(*zstream)); 288 zstream->workspace = workspace; 289 290 return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK; 291 } 292 293 static void *compress_next_page(struct i915_vma_compress *c, 294 struct i915_vma_coredump *dst) 295 { 296 void *page; 297 298 if (dst->page_count >= dst->num_pages) 299 return ERR_PTR(-ENOSPC); 300 301 page = pool_alloc(&c->pool, ALLOW_FAIL); 302 if (!page) 303 return ERR_PTR(-ENOMEM); 304 305 return dst->pages[dst->page_count++] = page; 306 } 307 308 static int compress_page(struct i915_vma_compress *c, 309 void *src, 310 struct i915_vma_coredump *dst, 311 bool wc) 312 { 313 struct z_stream_s *zstream = &c->zstream; 314 315 zstream->next_in = src; 316 if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE)) 317 zstream->next_in = c->tmp; 318 zstream->avail_in = PAGE_SIZE; 319 320 do { 321 if (zstream->avail_out == 0) { 322 zstream->next_out = compress_next_page(c, dst); 323 if (IS_ERR(zstream->next_out)) 324 return PTR_ERR(zstream->next_out); 325 326 zstream->avail_out = PAGE_SIZE; 327 } 328 329 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK) 330 return -EIO; 331 332 cond_resched(); 333 } while (zstream->avail_in); 334 335 /* Fallback to uncompressed if we increase size? */ 336 if (0 && zstream->total_out > zstream->total_in) 337 return -E2BIG; 338 339 return 0; 340 } 341 342 static int compress_flush(struct i915_vma_compress *c, 343 struct i915_vma_coredump *dst) 344 { 345 struct z_stream_s *zstream = &c->zstream; 346 347 do { 348 switch (zlib_deflate(zstream, Z_FINISH)) { 349 case Z_OK: /* more space requested */ 350 zstream->next_out = compress_next_page(c, dst); 351 if (IS_ERR(zstream->next_out)) 352 return PTR_ERR(zstream->next_out); 353 354 zstream->avail_out = PAGE_SIZE; 355 break; 356 357 case Z_STREAM_END: 358 goto end; 359 360 default: /* any error */ 361 return -EIO; 362 } 363 } while (1); 364 365 end: 366 memset(zstream->next_out, 0, zstream->avail_out); 367 dst->unused = zstream->avail_out; 368 return 0; 369 } 370 371 static void compress_finish(struct i915_vma_compress *c) 372 { 373 zlib_deflateEnd(&c->zstream); 374 } 375 376 static void compress_fini(struct i915_vma_compress *c) 377 { 378 kfree(c->zstream.workspace); 379 if (c->tmp) 380 pool_free(&c->pool, c->tmp); 381 pool_fini(&c->pool); 382 } 383 384 static void err_compression_marker(struct drm_i915_error_state_buf *m) 385 { 386 err_puts(m, ":"); 387 } 388 389 #else 390 391 struct i915_vma_compress { 392 struct pagevec pool; 393 }; 394 395 static bool compress_init(struct i915_vma_compress *c) 396 { 397 return intel_pool_init(&c->pool, ALLOW_FAIL) == 0; 398 } 399 400 static bool compress_start(struct i915_vma_compress *c) 401 { 402 return true; 403 } 404 405 static int compress_page(struct i915_vma_compress *c, 406 void *src, 407 struct i915_vma_coredump *dst, 408 bool wc) 409 { 410 void *ptr; 411 412 ptr = pool_alloc(&c->pool, ALLOW_FAIL); 413 if (!ptr) 414 return -ENOMEM; 415 416 if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE))) 417 memcpy(ptr, src, PAGE_SIZE); 418 dst->pages[dst->page_count++] = ptr; 419 cond_resched(); 420 421 return 0; 422 } 423 424 static int compress_flush(struct i915_vma_compress *c, 425 struct i915_vma_coredump *dst) 426 { 427 return 0; 428 } 429 430 static void compress_finish(struct i915_vma_compress *c) 431 { 432 } 433 434 static void compress_fini(struct i915_vma_compress *c) 435 { 436 pool_fini(&c->pool); 437 } 438 439 static void err_compression_marker(struct drm_i915_error_state_buf *m) 440 { 441 err_puts(m, "~"); 442 } 443 444 #endif 445 446 static void error_print_instdone(struct drm_i915_error_state_buf *m, 447 const struct intel_engine_coredump *ee) 448 { 449 const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu; 450 int slice; 451 int subslice; 452 453 err_printf(m, " INSTDONE: 0x%08x\n", 454 ee->instdone.instdone); 455 456 if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3) 457 return; 458 459 err_printf(m, " SC_INSTDONE: 0x%08x\n", 460 ee->instdone.slice_common); 461 462 if (INTEL_GEN(m->i915) <= 6) 463 return; 464 465 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 466 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n", 467 slice, subslice, 468 ee->instdone.sampler[slice][subslice]); 469 470 for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice) 471 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n", 472 slice, subslice, 473 ee->instdone.row[slice][subslice]); 474 475 if (INTEL_GEN(m->i915) < 12) 476 return; 477 478 err_printf(m, " SC_INSTDONE_EXTRA: 0x%08x\n", 479 ee->instdone.slice_common_extra[0]); 480 err_printf(m, " SC_INSTDONE_EXTRA2: 0x%08x\n", 481 ee->instdone.slice_common_extra[1]); 482 } 483 484 static void error_print_request(struct drm_i915_error_state_buf *m, 485 const char *prefix, 486 const struct i915_request_coredump *erq) 487 { 488 if (!erq->seqno) 489 return; 490 491 err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n", 492 prefix, erq->pid, erq->context, erq->seqno, 493 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, 494 &erq->flags) ? "!" : "", 495 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, 496 &erq->flags) ? "+" : "", 497 erq->sched_attr.priority, 498 erq->head, erq->tail); 499 } 500 501 static void error_print_context(struct drm_i915_error_state_buf *m, 502 const char *header, 503 const struct i915_gem_context_coredump *ctx) 504 { 505 const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns; 506 507 err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n", 508 header, ctx->comm, ctx->pid, ctx->sched_attr.priority, 509 ctx->guilty, ctx->active, 510 ctx->total_runtime * period, 511 mul_u32_u32(ctx->avg_runtime, period)); 512 } 513 514 static struct i915_vma_coredump * 515 __find_vma(struct i915_vma_coredump *vma, const char *name) 516 { 517 while (vma) { 518 if (strcmp(vma->name, name) == 0) 519 return vma; 520 vma = vma->next; 521 } 522 523 return NULL; 524 } 525 526 static struct i915_vma_coredump * 527 find_batch(const struct intel_engine_coredump *ee) 528 { 529 return __find_vma(ee->vma, "batch"); 530 } 531 532 static void error_print_engine(struct drm_i915_error_state_buf *m, 533 const struct intel_engine_coredump *ee) 534 { 535 struct i915_vma_coredump *batch; 536 int n; 537 538 err_printf(m, "%s command stream:\n", ee->engine->name); 539 err_printf(m, " CCID: 0x%08x\n", ee->ccid); 540 err_printf(m, " START: 0x%08x\n", ee->start); 541 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head); 542 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n", 543 ee->tail, ee->rq_post, ee->rq_tail); 544 err_printf(m, " CTL: 0x%08x\n", ee->ctl); 545 err_printf(m, " MODE: 0x%08x\n", ee->mode); 546 err_printf(m, " HWS: 0x%08x\n", ee->hws); 547 err_printf(m, " ACTHD: 0x%08x %08x\n", 548 (u32)(ee->acthd>>32), (u32)ee->acthd); 549 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir); 550 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr); 551 err_printf(m, " ESR: 0x%08x\n", ee->esr); 552 553 error_print_instdone(m, ee); 554 555 batch = find_batch(ee); 556 if (batch) { 557 u64 start = batch->gtt_offset; 558 u64 end = start + batch->gtt_size; 559 560 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n", 561 upper_32_bits(start), lower_32_bits(start), 562 upper_32_bits(end), lower_32_bits(end)); 563 } 564 if (INTEL_GEN(m->i915) >= 4) { 565 err_printf(m, " BBADDR: 0x%08x_%08x\n", 566 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); 567 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); 568 err_printf(m, " INSTPS: 0x%08x\n", ee->instps); 569 } 570 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); 571 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), 572 lower_32_bits(ee->faddr)); 573 if (INTEL_GEN(m->i915) >= 6) { 574 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); 575 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); 576 } 577 if (HAS_PPGTT(m->i915)) { 578 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); 579 580 if (INTEL_GEN(m->i915) >= 8) { 581 int i; 582 for (i = 0; i < 4; i++) 583 err_printf(m, " PDP%d: 0x%016llx\n", 584 i, ee->vm_info.pdp[i]); 585 } else { 586 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 587 ee->vm_info.pp_dir_base); 588 } 589 } 590 err_printf(m, " engine reset count: %u\n", ee->reset_count); 591 592 for (n = 0; n < ee->num_ports; n++) { 593 err_printf(m, " ELSP[%d]:", n); 594 error_print_request(m, " ", &ee->execlist[n]); 595 } 596 597 error_print_context(m, " Active context: ", &ee->context); 598 } 599 600 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 601 { 602 va_list args; 603 604 va_start(args, f); 605 i915_error_vprintf(e, f, args); 606 va_end(args); 607 } 608 609 static void print_error_vma(struct drm_i915_error_state_buf *m, 610 const struct intel_engine_cs *engine, 611 const struct i915_vma_coredump *vma) 612 { 613 STUB(); 614 #ifdef notyet 615 char out[ASCII85_BUFSZ]; 616 int page; 617 618 if (!vma) 619 return; 620 621 err_printf(m, "%s --- %s = 0x%08x %08x\n", 622 engine ? engine->name : "global", vma->name, 623 upper_32_bits(vma->gtt_offset), 624 lower_32_bits(vma->gtt_offset)); 625 626 if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K) 627 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes); 628 629 err_compression_marker(m); 630 for (page = 0; page < vma->page_count; page++) { 631 int i, len; 632 633 len = PAGE_SIZE; 634 if (page == vma->page_count - 1) 635 len -= vma->unused; 636 len = ascii85_encode_len(len); 637 638 for (i = 0; i < len; i++) 639 err_puts(m, ascii85_encode(vma->pages[page][i], out)); 640 } 641 err_puts(m, "\n"); 642 #endif 643 } 644 645 static void err_print_capabilities(struct drm_i915_error_state_buf *m, 646 struct i915_gpu_coredump *error) 647 { 648 struct drm_printer p = i915_error_printer(m); 649 650 intel_device_info_print_static(&error->device_info, &p); 651 intel_device_info_print_runtime(&error->runtime_info, &p); 652 intel_driver_caps_print(&error->driver_caps, &p); 653 } 654 655 static void err_print_params(struct drm_i915_error_state_buf *m, 656 const struct i915_params *params) 657 { 658 struct drm_printer p = i915_error_printer(m); 659 660 i915_params_dump(params, &p); 661 } 662 663 static void err_print_pciid(struct drm_i915_error_state_buf *m, 664 struct drm_i915_private *i915) 665 { 666 struct pci_dev *pdev = i915->drm.pdev; 667 668 err_printf(m, "PCI ID: 0x%04x\n", pdev->device); 669 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision); 670 err_printf(m, "PCI Subsystem: %04x:%04x\n", 671 pdev->subsystem_vendor, 672 pdev->subsystem_device); 673 } 674 675 static void err_print_uc(struct drm_i915_error_state_buf *m, 676 const struct intel_uc_coredump *error_uc) 677 { 678 struct drm_printer p = i915_error_printer(m); 679 680 intel_uc_fw_dump(&error_uc->guc_fw, &p); 681 intel_uc_fw_dump(&error_uc->huc_fw, &p); 682 print_error_vma(m, NULL, error_uc->guc_log); 683 } 684 685 static void err_free_sgl(struct scatterlist *sgl) 686 { 687 STUB(); 688 #ifdef notyet 689 while (sgl) { 690 struct scatterlist *sg; 691 692 for (sg = sgl; !sg_is_chain(sg); sg++) { 693 kfree(sg_virt(sg)); 694 if (sg_is_last(sg)) 695 break; 696 } 697 698 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg); 699 free_page((unsigned long)sgl); 700 sgl = sg; 701 } 702 #endif 703 } 704 705 static void err_print_gt_info(struct drm_i915_error_state_buf *m, 706 struct intel_gt_coredump *gt) 707 { 708 struct drm_printer p = i915_error_printer(m); 709 710 intel_gt_info_print(>->info, &p); 711 intel_sseu_print_topology(>->info.sseu, &p); 712 } 713 714 static void err_print_gt(struct drm_i915_error_state_buf *m, 715 struct intel_gt_coredump *gt) 716 { 717 const struct intel_engine_coredump *ee; 718 int i; 719 720 err_printf(m, "GT awake: %s\n", yesno(gt->awake)); 721 err_printf(m, "EIR: 0x%08x\n", gt->eir); 722 err_printf(m, "IER: 0x%08x\n", gt->ier); 723 for (i = 0; i < gt->ngtier; i++) 724 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]); 725 err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er); 726 err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake); 727 err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr); 728 729 for (i = 0; i < gt->nfence; i++) 730 err_printf(m, " fence[%d] = %08llx\n", i, gt->fence[i]); 731 732 if (IS_GEN_RANGE(m->i915, 6, 11)) { 733 err_printf(m, "ERROR: 0x%08x\n", gt->error); 734 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg); 735 } 736 737 if (INTEL_GEN(m->i915) >= 8) 738 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 739 gt->fault_data1, gt->fault_data0); 740 741 if (IS_GEN(m->i915, 7)) 742 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int); 743 744 if (IS_GEN_RANGE(m->i915, 8, 11)) 745 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache); 746 747 if (IS_GEN(m->i915, 12)) 748 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err); 749 750 if (INTEL_GEN(m->i915) >= 12) { 751 int i; 752 753 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) 754 err_printf(m, " SFC_DONE[%d]: 0x%08x\n", i, 755 gt->sfc_done[i]); 756 757 err_printf(m, " GAM_DONE: 0x%08x\n", gt->gam_done); 758 } 759 760 for (ee = gt->engine; ee; ee = ee->next) { 761 const struct i915_vma_coredump *vma; 762 763 error_print_engine(m, ee); 764 for (vma = ee->vma; vma; vma = vma->next) 765 print_error_vma(m, ee->engine, vma); 766 } 767 768 if (gt->uc) 769 err_print_uc(m, gt->uc); 770 771 err_print_gt_info(m, gt); 772 } 773 774 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, 775 struct i915_gpu_coredump *error) 776 { 777 const struct intel_engine_coredump *ee; 778 struct timespec64 ts; 779 780 if (*error->error_msg) 781 err_printf(m, "%s\n", error->error_msg); 782 #ifdef __linux__ 783 err_printf(m, "Kernel: %s %s\n", 784 init_utsname()->release, 785 init_utsname()->machine); 786 #else 787 extern char machine[]; 788 err_printf(m, "Kernel: %s %s\n", 789 osrelease, 790 machine); 791 #endif 792 err_printf(m, "Driver: %s\n", DRIVER_DATE); 793 ts = ktime_to_timespec64(error->time); 794 err_printf(m, "Time: %lld s %ld us\n", 795 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 796 ts = ktime_to_timespec64(error->boottime); 797 err_printf(m, "Boottime: %lld s %ld us\n", 798 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 799 ts = ktime_to_timespec64(error->uptime); 800 err_printf(m, "Uptime: %lld s %ld us\n", 801 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC); 802 err_printf(m, "Capture: %lu jiffies; %d ms ago\n", 803 error->capture, jiffies_to_msecs(jiffies - error->capture)); 804 805 for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next) 806 err_printf(m, "Active process (on ring %s): %s [%d]\n", 807 ee->engine->name, 808 ee->context.comm, 809 ee->context.pid); 810 811 err_printf(m, "Reset count: %u\n", error->reset_count); 812 err_printf(m, "Suspend count: %u\n", error->suspend_count); 813 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform)); 814 err_printf(m, "Subplatform: 0x%x\n", 815 intel_subplatform(&error->runtime_info, 816 error->device_info.platform)); 817 err_print_pciid(m, m->i915); 818 819 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 820 821 if (HAS_CSR(m->i915)) { 822 struct intel_csr *csr = &m->i915->csr; 823 824 err_printf(m, "DMC loaded: %s\n", 825 yesno(csr->dmc_payload != NULL)); 826 err_printf(m, "DMC fw version: %d.%d\n", 827 CSR_VERSION_MAJOR(csr->version), 828 CSR_VERSION_MINOR(csr->version)); 829 } 830 831 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock)); 832 err_printf(m, "PM suspended: %s\n", yesno(error->suspended)); 833 834 if (error->gt) 835 err_print_gt(m, error->gt); 836 837 if (error->overlay) 838 intel_overlay_print_error_state(m, error->overlay); 839 840 if (error->display) 841 intel_display_print_error_state(m, error->display); 842 843 err_print_capabilities(m, error); 844 err_print_params(m, &error->params); 845 } 846 847 static int err_print_to_sgl(struct i915_gpu_coredump *error) 848 { 849 struct drm_i915_error_state_buf m; 850 851 if (IS_ERR(error)) 852 return PTR_ERR(error); 853 854 if (READ_ONCE(error->sgl)) 855 return 0; 856 857 memset(&m, 0, sizeof(m)); 858 m.i915 = error->i915; 859 860 __err_print_to_sgl(&m, error); 861 862 if (m.buf) { 863 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter); 864 m.bytes = 0; 865 m.buf = NULL; 866 } 867 if (m.cur) { 868 GEM_BUG_ON(m.end < m.cur); 869 sg_mark_end(m.cur - 1); 870 } 871 GEM_BUG_ON(m.sgl && !m.cur); 872 873 if (m.err) { 874 err_free_sgl(m.sgl); 875 return m.err; 876 } 877 878 if (cmpxchg(&error->sgl, NULL, m.sgl)) 879 err_free_sgl(m.sgl); 880 881 return 0; 882 } 883 884 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error, 885 char *buf, loff_t off, size_t rem) 886 { 887 STUB(); 888 return -ENOSYS; 889 #ifdef notyet 890 struct scatterlist *sg; 891 size_t count; 892 loff_t pos; 893 int err; 894 895 if (!error || !rem) 896 return 0; 897 898 err = err_print_to_sgl(error); 899 if (err) 900 return err; 901 902 sg = READ_ONCE(error->fit); 903 if (!sg || off < sg->dma_address) 904 sg = error->sgl; 905 if (!sg) 906 return 0; 907 908 pos = sg->dma_address; 909 count = 0; 910 do { 911 size_t len, start; 912 913 if (sg_is_chain(sg)) { 914 sg = sg_chain_ptr(sg); 915 GEM_BUG_ON(sg_is_chain(sg)); 916 } 917 918 len = sg->length; 919 if (pos + len <= off) { 920 pos += len; 921 continue; 922 } 923 924 start = sg->offset; 925 if (pos < off) { 926 GEM_BUG_ON(off - pos > len); 927 len -= off - pos; 928 start += off - pos; 929 pos = off; 930 } 931 932 len = min(len, rem); 933 GEM_BUG_ON(!len || len > sg->length); 934 935 memcpy(buf, page_address(sg_page(sg)) + start, len); 936 937 count += len; 938 pos += len; 939 940 buf += len; 941 rem -= len; 942 if (!rem) { 943 WRITE_ONCE(error->fit, sg); 944 break; 945 } 946 } while (!sg_is_last(sg++)); 947 948 return count; 949 #endif 950 } 951 952 static void i915_vma_coredump_free(struct i915_vma_coredump *vma) 953 { 954 while (vma) { 955 struct i915_vma_coredump *next = vma->next; 956 int page; 957 958 for (page = 0; page < vma->page_count; page++) 959 free_page((unsigned long)vma->pages[page]); 960 961 kfree(vma); 962 vma = next; 963 } 964 } 965 966 static void cleanup_params(struct i915_gpu_coredump *error) 967 { 968 i915_params_free(&error->params); 969 } 970 971 static void cleanup_uc(struct intel_uc_coredump *uc) 972 { 973 kfree(uc->guc_fw.path); 974 kfree(uc->huc_fw.path); 975 i915_vma_coredump_free(uc->guc_log); 976 977 kfree(uc); 978 } 979 980 static void cleanup_gt(struct intel_gt_coredump *gt) 981 { 982 while (gt->engine) { 983 struct intel_engine_coredump *ee = gt->engine; 984 985 gt->engine = ee->next; 986 987 i915_vma_coredump_free(ee->vma); 988 kfree(ee); 989 } 990 991 if (gt->uc) 992 cleanup_uc(gt->uc); 993 994 kfree(gt); 995 } 996 997 void __i915_gpu_coredump_free(struct kref *error_ref) 998 { 999 struct i915_gpu_coredump *error = 1000 container_of(error_ref, typeof(*error), ref); 1001 1002 while (error->gt) { 1003 struct intel_gt_coredump *gt = error->gt; 1004 1005 error->gt = gt->next; 1006 cleanup_gt(gt); 1007 } 1008 1009 kfree(error->overlay); 1010 kfree(error->display); 1011 1012 cleanup_params(error); 1013 1014 err_free_sgl(error->sgl); 1015 kfree(error); 1016 } 1017 1018 static struct i915_vma_coredump * 1019 i915_vma_coredump_create(const struct intel_gt *gt, 1020 const struct i915_vma *vma, 1021 const char *name, 1022 struct i915_vma_compress *compress) 1023 { 1024 STUB(); 1025 return NULL; 1026 #ifdef notyet 1027 struct i915_ggtt *ggtt = gt->ggtt; 1028 const u64 slot = ggtt->error_capture.start; 1029 struct i915_vma_coredump *dst; 1030 unsigned long num_pages; 1031 struct sgt_iter iter; 1032 int ret; 1033 1034 might_sleep(); 1035 1036 if (!vma || !vma->pages || !compress) 1037 return NULL; 1038 1039 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT; 1040 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */ 1041 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL); 1042 if (!dst) 1043 return NULL; 1044 1045 if (!compress_start(compress)) { 1046 kfree(dst); 1047 return NULL; 1048 } 1049 1050 strlcpy(dst->name, name, sizeof(dst->name)); 1051 dst->next = NULL; 1052 1053 dst->gtt_offset = vma->node.start; 1054 dst->gtt_size = vma->node.size; 1055 dst->gtt_page_sizes = vma->page_sizes.gtt; 1056 dst->num_pages = num_pages; 1057 dst->page_count = 0; 1058 dst->unused = 0; 1059 1060 ret = -EINVAL; 1061 if (drm_mm_node_allocated(&ggtt->error_capture)) { 1062 void __iomem *s; 1063 dma_addr_t dma; 1064 1065 for_each_sgt_daddr(dma, iter, vma->pages) { 1066 ggtt->vm.insert_page(&ggtt->vm, dma, slot, 1067 I915_CACHE_NONE, 0); 1068 mb(); 1069 1070 s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE); 1071 ret = compress_page(compress, 1072 (void __force *)s, dst, 1073 true); 1074 io_mapping_unmap(s); 1075 if (ret) 1076 break; 1077 } 1078 } else if (i915_gem_object_is_lmem(vma->obj)) { 1079 struct intel_memory_region *mem = vma->obj->mm.region; 1080 dma_addr_t dma; 1081 1082 for_each_sgt_daddr(dma, iter, vma->pages) { 1083 void __iomem *s; 1084 1085 s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE); 1086 ret = compress_page(compress, 1087 (void __force *)s, dst, 1088 true); 1089 io_mapping_unmap(s); 1090 if (ret) 1091 break; 1092 } 1093 } else { 1094 struct vm_page *page; 1095 1096 for_each_sgt_page(page, iter, vma->pages) { 1097 void *s; 1098 1099 drm_clflush_pages(&page, 1); 1100 1101 s = kmap(page); 1102 ret = compress_page(compress, s, dst, false); 1103 kunmap(page); 1104 1105 drm_clflush_pages(&page, 1); 1106 1107 if (ret) 1108 break; 1109 } 1110 } 1111 1112 if (ret || compress_flush(compress, dst)) { 1113 while (dst->page_count--) 1114 pool_free(&compress->pool, dst->pages[dst->page_count]); 1115 kfree(dst); 1116 dst = NULL; 1117 } 1118 compress_finish(compress); 1119 1120 return dst; 1121 #endif 1122 } 1123 1124 static void gt_record_fences(struct intel_gt_coredump *gt) 1125 { 1126 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1127 struct intel_uncore *uncore = gt->_gt->uncore; 1128 int i; 1129 1130 if (INTEL_GEN(uncore->i915) >= 6) { 1131 for (i = 0; i < ggtt->num_fences; i++) 1132 gt->fence[i] = 1133 intel_uncore_read64(uncore, 1134 FENCE_REG_GEN6_LO(i)); 1135 } else if (INTEL_GEN(uncore->i915) >= 4) { 1136 for (i = 0; i < ggtt->num_fences; i++) 1137 gt->fence[i] = 1138 intel_uncore_read64(uncore, 1139 FENCE_REG_965_LO(i)); 1140 } else { 1141 for (i = 0; i < ggtt->num_fences; i++) 1142 gt->fence[i] = 1143 intel_uncore_read(uncore, FENCE_REG(i)); 1144 } 1145 gt->nfence = i; 1146 } 1147 1148 static void engine_record_registers(struct intel_engine_coredump *ee) 1149 { 1150 const struct intel_engine_cs *engine = ee->engine; 1151 struct drm_i915_private *i915 = engine->i915; 1152 1153 if (INTEL_GEN(i915) >= 6) { 1154 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); 1155 1156 if (INTEL_GEN(i915) >= 12) 1157 ee->fault_reg = intel_uncore_read(engine->uncore, 1158 GEN12_RING_FAULT_REG); 1159 else if (INTEL_GEN(i915) >= 8) 1160 ee->fault_reg = intel_uncore_read(engine->uncore, 1161 GEN8_RING_FAULT_REG); 1162 else 1163 ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine); 1164 } 1165 1166 if (INTEL_GEN(i915) >= 4) { 1167 ee->esr = ENGINE_READ(engine, RING_ESR); 1168 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD); 1169 ee->ipeir = ENGINE_READ(engine, RING_IPEIR); 1170 ee->ipehr = ENGINE_READ(engine, RING_IPEHR); 1171 ee->instps = ENGINE_READ(engine, RING_INSTPS); 1172 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR); 1173 ee->ccid = ENGINE_READ(engine, CCID); 1174 if (INTEL_GEN(i915) >= 8) { 1175 ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32; 1176 ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32; 1177 } 1178 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE); 1179 } else { 1180 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX); 1181 ee->ipeir = ENGINE_READ(engine, IPEIR); 1182 ee->ipehr = ENGINE_READ(engine, IPEHR); 1183 } 1184 1185 intel_engine_get_instdone(engine, &ee->instdone); 1186 1187 ee->instpm = ENGINE_READ(engine, RING_INSTPM); 1188 ee->acthd = intel_engine_get_active_head(engine); 1189 ee->start = ENGINE_READ(engine, RING_START); 1190 ee->head = ENGINE_READ(engine, RING_HEAD); 1191 ee->tail = ENGINE_READ(engine, RING_TAIL); 1192 ee->ctl = ENGINE_READ(engine, RING_CTL); 1193 if (INTEL_GEN(i915) > 2) 1194 ee->mode = ENGINE_READ(engine, RING_MI_MODE); 1195 1196 if (!HWS_NEEDS_PHYSICAL(i915)) { 1197 i915_reg_t mmio; 1198 1199 if (IS_GEN(i915, 7)) { 1200 switch (engine->id) { 1201 default: 1202 MISSING_CASE(engine->id); 1203 fallthrough; 1204 case RCS0: 1205 mmio = RENDER_HWS_PGA_GEN7; 1206 break; 1207 case BCS0: 1208 mmio = BLT_HWS_PGA_GEN7; 1209 break; 1210 case VCS0: 1211 mmio = BSD_HWS_PGA_GEN7; 1212 break; 1213 case VECS0: 1214 mmio = VEBOX_HWS_PGA_GEN7; 1215 break; 1216 } 1217 } else if (IS_GEN(engine->i915, 6)) { 1218 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 1219 } else { 1220 /* XXX: gen8 returns to sanity */ 1221 mmio = RING_HWS_PGA(engine->mmio_base); 1222 } 1223 1224 ee->hws = intel_uncore_read(engine->uncore, mmio); 1225 } 1226 1227 ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine); 1228 1229 if (HAS_PPGTT(i915)) { 1230 int i; 1231 1232 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7); 1233 1234 if (IS_GEN(i915, 6)) { 1235 ee->vm_info.pp_dir_base = 1236 ENGINE_READ(engine, RING_PP_DIR_BASE_READ); 1237 } else if (IS_GEN(i915, 7)) { 1238 ee->vm_info.pp_dir_base = 1239 ENGINE_READ(engine, RING_PP_DIR_BASE); 1240 } else if (INTEL_GEN(i915) >= 8) { 1241 u32 base = engine->mmio_base; 1242 1243 for (i = 0; i < 4; i++) { 1244 ee->vm_info.pdp[i] = 1245 intel_uncore_read(engine->uncore, 1246 GEN8_RING_PDP_UDW(base, i)); 1247 ee->vm_info.pdp[i] <<= 32; 1248 ee->vm_info.pdp[i] |= 1249 intel_uncore_read(engine->uncore, 1250 GEN8_RING_PDP_LDW(base, i)); 1251 } 1252 } 1253 } 1254 } 1255 1256 static void record_request(const struct i915_request *request, 1257 struct i915_request_coredump *erq) 1258 { 1259 erq->flags = request->fence.flags; 1260 erq->context = request->fence.context; 1261 erq->seqno = request->fence.seqno; 1262 erq->sched_attr = request->sched.attr; 1263 erq->head = request->head; 1264 erq->tail = request->tail; 1265 1266 erq->pid = 0; 1267 rcu_read_lock(); 1268 if (!intel_context_is_closed(request->context)) { 1269 const struct i915_gem_context *ctx; 1270 1271 ctx = rcu_dereference(request->context->gem_context); 1272 if (ctx) 1273 #ifdef __linux__ 1274 erq->pid = pid_nr(ctx->pid); 1275 #else 1276 erq->pid = ctx->pid; 1277 #endif 1278 } 1279 rcu_read_unlock(); 1280 } 1281 1282 static void engine_record_execlists(struct intel_engine_coredump *ee) 1283 { 1284 const struct intel_engine_execlists * const el = &ee->engine->execlists; 1285 struct i915_request * const *port = el->active; 1286 unsigned int n = 0; 1287 1288 while (*port) 1289 record_request(*port++, &ee->execlist[n++]); 1290 1291 ee->num_ports = n; 1292 } 1293 1294 static bool record_context(struct i915_gem_context_coredump *e, 1295 const struct i915_request *rq) 1296 { 1297 struct i915_gem_context *ctx; 1298 struct task_struct *task; 1299 bool simulated; 1300 1301 rcu_read_lock(); 1302 ctx = rcu_dereference(rq->context->gem_context); 1303 if (ctx && !kref_get_unless_zero(&ctx->ref)) 1304 ctx = NULL; 1305 rcu_read_unlock(); 1306 if (!ctx) 1307 return true; 1308 1309 #ifdef __linux__ 1310 rcu_read_lock(); 1311 task = pid_task(ctx->pid, PIDTYPE_PID); 1312 if (task) { 1313 strcpy(e->comm, task->comm); 1314 e->pid = task->pid; 1315 } 1316 rcu_read_unlock(); 1317 #endif 1318 1319 e->sched_attr = ctx->sched; 1320 e->guilty = atomic_read(&ctx->guilty_count); 1321 e->active = atomic_read(&ctx->active_count); 1322 1323 e->total_runtime = rq->context->runtime.total; 1324 e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg); 1325 1326 simulated = i915_gem_context_no_error_capture(ctx); 1327 1328 i915_gem_context_put(ctx); 1329 return simulated; 1330 } 1331 1332 struct intel_engine_capture_vma { 1333 struct intel_engine_capture_vma *next; 1334 struct i915_vma *vma; 1335 char name[16]; 1336 }; 1337 1338 static struct intel_engine_capture_vma * 1339 capture_vma(struct intel_engine_capture_vma *next, 1340 struct i915_vma *vma, 1341 const char *name, 1342 gfp_t gfp) 1343 { 1344 struct intel_engine_capture_vma *c; 1345 1346 if (!vma) 1347 return next; 1348 1349 c = kmalloc(sizeof(*c), gfp); 1350 if (!c) 1351 return next; 1352 1353 if (!i915_active_acquire_if_busy(&vma->active)) { 1354 kfree(c); 1355 return next; 1356 } 1357 1358 strlcpy(c->name, name, sizeof(c->name)); 1359 c->vma = vma; /* reference held while active */ 1360 1361 c->next = next; 1362 return c; 1363 } 1364 1365 static struct intel_engine_capture_vma * 1366 capture_user(struct intel_engine_capture_vma *capture, 1367 const struct i915_request *rq, 1368 gfp_t gfp) 1369 { 1370 struct i915_capture_list *c; 1371 1372 for (c = rq->capture_list; c; c = c->next) 1373 capture = capture_vma(capture, c->vma, "user", gfp); 1374 1375 return capture; 1376 } 1377 1378 static void add_vma(struct intel_engine_coredump *ee, 1379 struct i915_vma_coredump *vma) 1380 { 1381 if (vma) { 1382 vma->next = ee->vma; 1383 ee->vma = vma; 1384 } 1385 } 1386 1387 struct intel_engine_coredump * 1388 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp) 1389 { 1390 struct intel_engine_coredump *ee; 1391 1392 ee = kzalloc(sizeof(*ee), gfp); 1393 if (!ee) 1394 return NULL; 1395 1396 ee->engine = engine; 1397 1398 engine_record_registers(ee); 1399 engine_record_execlists(ee); 1400 1401 return ee; 1402 } 1403 1404 struct intel_engine_capture_vma * 1405 intel_engine_coredump_add_request(struct intel_engine_coredump *ee, 1406 struct i915_request *rq, 1407 gfp_t gfp) 1408 { 1409 struct intel_engine_capture_vma *vma = NULL; 1410 1411 ee->simulated |= record_context(&ee->context, rq); 1412 if (ee->simulated) 1413 return NULL; 1414 1415 /* 1416 * We need to copy these to an anonymous buffer 1417 * as the simplest method to avoid being overwritten 1418 * by userspace. 1419 */ 1420 vma = capture_vma(vma, rq->batch, "batch", gfp); 1421 vma = capture_user(vma, rq, gfp); 1422 vma = capture_vma(vma, rq->ring->vma, "ring", gfp); 1423 vma = capture_vma(vma, rq->context->state, "HW context", gfp); 1424 1425 ee->rq_head = rq->head; 1426 ee->rq_post = rq->postfix; 1427 ee->rq_tail = rq->tail; 1428 1429 return vma; 1430 } 1431 1432 void 1433 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee, 1434 struct intel_engine_capture_vma *capture, 1435 struct i915_vma_compress *compress) 1436 { 1437 const struct intel_engine_cs *engine = ee->engine; 1438 1439 while (capture) { 1440 struct intel_engine_capture_vma *this = capture; 1441 struct i915_vma *vma = this->vma; 1442 1443 add_vma(ee, 1444 i915_vma_coredump_create(engine->gt, 1445 vma, this->name, 1446 compress)); 1447 1448 i915_active_release(&vma->active); 1449 1450 capture = this->next; 1451 kfree(this); 1452 } 1453 1454 add_vma(ee, 1455 i915_vma_coredump_create(engine->gt, 1456 engine->status_page.vma, 1457 "HW Status", 1458 compress)); 1459 1460 add_vma(ee, 1461 i915_vma_coredump_create(engine->gt, 1462 engine->wa_ctx.vma, 1463 "WA context", 1464 compress)); 1465 } 1466 1467 static struct intel_engine_coredump * 1468 capture_engine(struct intel_engine_cs *engine, 1469 struct i915_vma_compress *compress) 1470 { 1471 struct intel_engine_capture_vma *capture = NULL; 1472 struct intel_engine_coredump *ee; 1473 struct i915_request *rq; 1474 unsigned long flags; 1475 1476 ee = intel_engine_coredump_alloc(engine, GFP_KERNEL); 1477 if (!ee) 1478 return NULL; 1479 1480 spin_lock_irqsave(&engine->active.lock, flags); 1481 rq = intel_engine_find_active_request(engine); 1482 if (rq) 1483 capture = intel_engine_coredump_add_request(ee, rq, 1484 ATOMIC_MAYFAIL); 1485 spin_unlock_irqrestore(&engine->active.lock, flags); 1486 if (!capture) { 1487 kfree(ee); 1488 return NULL; 1489 } 1490 1491 intel_engine_coredump_add_vma(ee, capture, compress); 1492 1493 return ee; 1494 } 1495 1496 static void 1497 gt_record_engines(struct intel_gt_coredump *gt, 1498 struct i915_vma_compress *compress) 1499 { 1500 struct intel_engine_cs *engine; 1501 enum intel_engine_id id; 1502 1503 for_each_engine(engine, gt->_gt, id) { 1504 struct intel_engine_coredump *ee; 1505 1506 /* Refill our page pool before entering atomic section */ 1507 pool_refill(&compress->pool, ALLOW_FAIL); 1508 1509 ee = capture_engine(engine, compress); 1510 if (!ee) 1511 continue; 1512 1513 gt->simulated |= ee->simulated; 1514 if (ee->simulated) { 1515 kfree(ee); 1516 continue; 1517 } 1518 1519 ee->next = gt->engine; 1520 gt->engine = ee; 1521 } 1522 } 1523 1524 static struct intel_uc_coredump * 1525 gt_record_uc(struct intel_gt_coredump *gt, 1526 struct i915_vma_compress *compress) 1527 { 1528 const struct intel_uc *uc = >->_gt->uc; 1529 struct intel_uc_coredump *error_uc; 1530 1531 error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL); 1532 if (!error_uc) 1533 return NULL; 1534 1535 memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw)); 1536 memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw)); 1537 1538 /* Non-default firmware paths will be specified by the modparam. 1539 * As modparams are generally accesible from the userspace make 1540 * explicit copies of the firmware paths. 1541 */ 1542 error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL); 1543 error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL); 1544 error_uc->guc_log = 1545 i915_vma_coredump_create(gt->_gt, 1546 uc->guc.log.vma, "GuC log buffer", 1547 compress); 1548 1549 return error_uc; 1550 } 1551 1552 static void gt_capture_prepare(struct intel_gt_coredump *gt) 1553 { 1554 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1555 1556 mutex_lock(&ggtt->error_mutex); 1557 } 1558 1559 static void gt_capture_finish(struct intel_gt_coredump *gt) 1560 { 1561 struct i915_ggtt *ggtt = gt->_gt->ggtt; 1562 1563 if (drm_mm_node_allocated(&ggtt->error_capture)) 1564 ggtt->vm.clear_range(&ggtt->vm, 1565 ggtt->error_capture.start, 1566 PAGE_SIZE); 1567 1568 mutex_unlock(&ggtt->error_mutex); 1569 } 1570 1571 /* Capture all registers which don't fit into another category. */ 1572 static void gt_record_regs(struct intel_gt_coredump *gt) 1573 { 1574 struct intel_uncore *uncore = gt->_gt->uncore; 1575 struct drm_i915_private *i915 = uncore->i915; 1576 int i; 1577 1578 /* 1579 * General organization 1580 * 1. Registers specific to a single generation 1581 * 2. Registers which belong to multiple generations 1582 * 3. Feature specific registers. 1583 * 4. Everything else 1584 * Please try to follow the order. 1585 */ 1586 1587 /* 1: Registers specific to a single generation */ 1588 if (IS_VALLEYVIEW(i915)) { 1589 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1590 gt->ier = intel_uncore_read(uncore, VLV_IER); 1591 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV); 1592 } 1593 1594 if (IS_GEN(i915, 7)) 1595 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT); 1596 1597 if (INTEL_GEN(i915) >= 12) { 1598 gt->fault_data0 = intel_uncore_read(uncore, 1599 GEN12_FAULT_TLB_DATA0); 1600 gt->fault_data1 = intel_uncore_read(uncore, 1601 GEN12_FAULT_TLB_DATA1); 1602 } else if (INTEL_GEN(i915) >= 8) { 1603 gt->fault_data0 = intel_uncore_read(uncore, 1604 GEN8_FAULT_TLB_DATA0); 1605 gt->fault_data1 = intel_uncore_read(uncore, 1606 GEN8_FAULT_TLB_DATA1); 1607 } 1608 1609 if (IS_GEN(i915, 6)) { 1610 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE); 1611 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL); 1612 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE); 1613 } 1614 1615 /* 2: Registers which belong to multiple generations */ 1616 if (INTEL_GEN(i915) >= 7) 1617 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT); 1618 1619 if (INTEL_GEN(i915) >= 6) { 1620 gt->derrmr = intel_uncore_read(uncore, DERRMR); 1621 if (INTEL_GEN(i915) < 12) { 1622 gt->error = intel_uncore_read(uncore, ERROR_GEN6); 1623 gt->done_reg = intel_uncore_read(uncore, DONE_REG); 1624 } 1625 } 1626 1627 /* 3: Feature specific registers */ 1628 if (IS_GEN_RANGE(i915, 6, 7)) { 1629 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK); 1630 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS); 1631 } 1632 1633 if (IS_GEN_RANGE(i915, 8, 11)) 1634 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN); 1635 1636 if (IS_GEN(i915, 12)) 1637 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG); 1638 1639 if (INTEL_GEN(i915) >= 12) { 1640 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) { 1641 gt->sfc_done[i] = 1642 intel_uncore_read(uncore, GEN12_SFC_DONE(i)); 1643 } 1644 1645 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE); 1646 } 1647 1648 /* 4: Everything else */ 1649 if (INTEL_GEN(i915) >= 11) { 1650 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1651 gt->gtier[0] = 1652 intel_uncore_read(uncore, 1653 GEN11_RENDER_COPY_INTR_ENABLE); 1654 gt->gtier[1] = 1655 intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE); 1656 gt->gtier[2] = 1657 intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE); 1658 gt->gtier[3] = 1659 intel_uncore_read(uncore, 1660 GEN11_GPM_WGBOXPERF_INTR_ENABLE); 1661 gt->gtier[4] = 1662 intel_uncore_read(uncore, 1663 GEN11_CRYPTO_RSVD_INTR_ENABLE); 1664 gt->gtier[5] = 1665 intel_uncore_read(uncore, 1666 GEN11_GUNIT_CSME_INTR_ENABLE); 1667 gt->ngtier = 6; 1668 } else if (INTEL_GEN(i915) >= 8) { 1669 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER); 1670 for (i = 0; i < 4; i++) 1671 gt->gtier[i] = 1672 intel_uncore_read(uncore, GEN8_GT_IER(i)); 1673 gt->ngtier = 4; 1674 } else if (HAS_PCH_SPLIT(i915)) { 1675 gt->ier = intel_uncore_read(uncore, DEIER); 1676 gt->gtier[0] = intel_uncore_read(uncore, GTIER); 1677 gt->ngtier = 1; 1678 } else if (IS_GEN(i915, 2)) { 1679 gt->ier = intel_uncore_read16(uncore, GEN2_IER); 1680 } else if (!IS_VALLEYVIEW(i915)) { 1681 gt->ier = intel_uncore_read(uncore, GEN2_IER); 1682 } 1683 gt->eir = intel_uncore_read(uncore, EIR); 1684 gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER); 1685 } 1686 1687 static void gt_record_info(struct intel_gt_coredump *gt) 1688 { 1689 memcpy(>->info, >->_gt->info, sizeof(struct intel_gt_info)); 1690 } 1691 1692 /* 1693 * Generate a semi-unique error code. The code is not meant to have meaning, The 1694 * code's only purpose is to try to prevent false duplicated bug reports by 1695 * grossly estimating a GPU error state. 1696 * 1697 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 1698 * the hang if we could strip the GTT offset information from it. 1699 * 1700 * It's only a small step better than a random number in its current form. 1701 */ 1702 static u32 generate_ecode(const struct intel_engine_coredump *ee) 1703 { 1704 /* 1705 * IPEHR would be an ideal way to detect errors, as it's the gross 1706 * measure of "the command that hung." However, has some very common 1707 * synchronization commands which almost always appear in the case 1708 * strictly a client bug. Use instdone to differentiate those some. 1709 */ 1710 return ee ? ee->ipehr ^ ee->instdone.instdone : 0; 1711 } 1712 1713 static const char *error_msg(struct i915_gpu_coredump *error) 1714 { 1715 struct intel_engine_coredump *first = NULL; 1716 struct intel_gt_coredump *gt; 1717 intel_engine_mask_t engines; 1718 int len; 1719 1720 engines = 0; 1721 for (gt = error->gt; gt; gt = gt->next) { 1722 struct intel_engine_coredump *cs; 1723 1724 if (gt->engine && !first) 1725 first = gt->engine; 1726 1727 for (cs = gt->engine; cs; cs = cs->next) 1728 engines |= cs->engine->mask; 1729 } 1730 1731 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1732 "GPU HANG: ecode %d:%x:%08x", 1733 INTEL_GEN(error->i915), engines, 1734 generate_ecode(first)); 1735 if (first && first->context.pid) { 1736 /* Just show the first executing process, more is confusing */ 1737 len += scnprintf(error->error_msg + len, 1738 sizeof(error->error_msg) - len, 1739 ", in %s [%d]", 1740 first->context.comm, first->context.pid); 1741 } 1742 1743 return error->error_msg; 1744 } 1745 1746 static void capture_gen(struct i915_gpu_coredump *error) 1747 { 1748 struct drm_i915_private *i915 = error->i915; 1749 1750 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count); 1751 error->suspended = i915->runtime_pm.suspended; 1752 1753 error->iommu = -1; 1754 #ifdef CONFIG_INTEL_IOMMU 1755 error->iommu = intel_iommu_gfx_mapped; 1756 #endif 1757 error->reset_count = i915_reset_count(&i915->gpu_error); 1758 error->suspend_count = i915->suspend_count; 1759 1760 i915_params_copy(&error->params, &i915->params); 1761 memcpy(&error->device_info, 1762 INTEL_INFO(i915), 1763 sizeof(error->device_info)); 1764 memcpy(&error->runtime_info, 1765 RUNTIME_INFO(i915), 1766 sizeof(error->runtime_info)); 1767 error->driver_caps = i915->caps; 1768 } 1769 1770 struct i915_gpu_coredump * 1771 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp) 1772 { 1773 struct i915_gpu_coredump *error; 1774 1775 if (!i915->params.error_capture) 1776 return NULL; 1777 1778 error = kzalloc(sizeof(*error), gfp); 1779 if (!error) 1780 return NULL; 1781 1782 kref_init(&error->ref); 1783 error->i915 = i915; 1784 1785 error->time = ktime_get_real(); 1786 error->boottime = ktime_get_boottime(); 1787 error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time); 1788 error->capture = jiffies; 1789 1790 capture_gen(error); 1791 1792 return error; 1793 } 1794 1795 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x)) 1796 1797 struct intel_gt_coredump * 1798 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp) 1799 { 1800 struct intel_gt_coredump *gc; 1801 1802 gc = kzalloc(sizeof(*gc), gfp); 1803 if (!gc) 1804 return NULL; 1805 1806 gc->_gt = gt; 1807 gc->awake = intel_gt_pm_is_awake(gt); 1808 1809 gt_record_regs(gc); 1810 gt_record_fences(gc); 1811 1812 return gc; 1813 } 1814 1815 struct i915_vma_compress * 1816 i915_vma_capture_prepare(struct intel_gt_coredump *gt) 1817 { 1818 struct i915_vma_compress *compress; 1819 1820 compress = kmalloc(sizeof(*compress), ALLOW_FAIL); 1821 if (!compress) 1822 return NULL; 1823 1824 if (!compress_init(compress)) { 1825 kfree(compress); 1826 return NULL; 1827 } 1828 1829 gt_capture_prepare(gt); 1830 1831 return compress; 1832 } 1833 1834 void i915_vma_capture_finish(struct intel_gt_coredump *gt, 1835 struct i915_vma_compress *compress) 1836 { 1837 if (!compress) 1838 return; 1839 1840 gt_capture_finish(gt); 1841 1842 compress_fini(compress); 1843 kfree(compress); 1844 } 1845 1846 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915) 1847 { 1848 struct i915_gpu_coredump *error; 1849 1850 /* Check if GPU capture has been disabled */ 1851 error = READ_ONCE(i915->gpu_error.first_error); 1852 if (IS_ERR(error)) 1853 return error; 1854 1855 error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL); 1856 if (!error) 1857 return ERR_PTR(-ENOMEM); 1858 1859 error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL); 1860 if (error->gt) { 1861 struct i915_vma_compress *compress; 1862 1863 compress = i915_vma_capture_prepare(error->gt); 1864 if (!compress) { 1865 kfree(error->gt); 1866 kfree(error); 1867 return ERR_PTR(-ENOMEM); 1868 } 1869 1870 gt_record_info(error->gt); 1871 gt_record_engines(error->gt, compress); 1872 1873 if (INTEL_INFO(i915)->has_gt_uc) 1874 error->gt->uc = gt_record_uc(error->gt, compress); 1875 1876 i915_vma_capture_finish(error->gt, compress); 1877 1878 error->simulated |= error->gt->simulated; 1879 } 1880 1881 error->overlay = intel_overlay_capture_error_state(i915); 1882 error->display = intel_display_capture_error_state(i915); 1883 1884 return error; 1885 } 1886 1887 void i915_error_state_store(struct i915_gpu_coredump *error) 1888 { 1889 struct drm_i915_private *i915; 1890 static bool warned; 1891 1892 if (IS_ERR_OR_NULL(error)) 1893 return; 1894 1895 i915 = error->i915; 1896 drm_info(&i915->drm, "%s\n", error_msg(error)); 1897 1898 if (error->simulated || 1899 cmpxchg(&i915->gpu_error.first_error, NULL, error)) 1900 return; 1901 1902 i915_gpu_coredump_get(error); 1903 1904 if (!xchg(&warned, true) && 1905 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) { 1906 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1907 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n"); 1908 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n"); 1909 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1910 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n"); 1911 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n", 1912 i915->drm.primary->index); 1913 } 1914 } 1915 1916 /** 1917 * i915_capture_error_state - capture an error record for later analysis 1918 * @i915: i915 device 1919 * 1920 * Should be called when an error is detected (either a hang or an error 1921 * interrupt) to capture error state from the time of the error. Fills 1922 * out a structure which becomes available in debugfs for user level tools 1923 * to pick up. 1924 */ 1925 void i915_capture_error_state(struct drm_i915_private *i915) 1926 { 1927 struct i915_gpu_coredump *error; 1928 1929 error = i915_gpu_coredump(i915); 1930 if (IS_ERR(error)) { 1931 cmpxchg(&i915->gpu_error.first_error, NULL, error); 1932 return; 1933 } 1934 1935 i915_error_state_store(error); 1936 i915_gpu_coredump_put(error); 1937 } 1938 1939 struct i915_gpu_coredump * 1940 i915_first_error_state(struct drm_i915_private *i915) 1941 { 1942 struct i915_gpu_coredump *error; 1943 1944 spin_lock_irq(&i915->gpu_error.lock); 1945 error = i915->gpu_error.first_error; 1946 if (!IS_ERR_OR_NULL(error)) 1947 i915_gpu_coredump_get(error); 1948 spin_unlock_irq(&i915->gpu_error.lock); 1949 1950 return error; 1951 } 1952 1953 void i915_reset_error_state(struct drm_i915_private *i915) 1954 { 1955 struct i915_gpu_coredump *error; 1956 1957 spin_lock_irq(&i915->gpu_error.lock); 1958 error = i915->gpu_error.first_error; 1959 if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */ 1960 i915->gpu_error.first_error = NULL; 1961 spin_unlock_irq(&i915->gpu_error.lock); 1962 1963 if (!IS_ERR_OR_NULL(error)) 1964 i915_gpu_coredump_put(error); 1965 } 1966 1967 void i915_disable_error_state(struct drm_i915_private *i915, int err) 1968 { 1969 spin_lock_irq(&i915->gpu_error.lock); 1970 if (!i915->gpu_error.first_error) 1971 i915->gpu_error.first_error = ERR_PTR(err); 1972 spin_unlock_irq(&i915->gpu_error.lock); 1973 } 1974