1c349dbc7Sjsg /*
2c349dbc7Sjsg * Copyright(c) 2011-2017 Intel Corporation. All rights reserved.
3c349dbc7Sjsg *
4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"),
6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation
7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions:
10c349dbc7Sjsg *
11c349dbc7Sjsg * The above copyright notice and this permission notice (including the next
12c349dbc7Sjsg * paragraph) shall be included in all copies or substantial portions of the
13c349dbc7Sjsg * Software.
14c349dbc7Sjsg *
15c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16c349dbc7Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18c349dbc7Sjsg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19c349dbc7Sjsg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20c349dbc7Sjsg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21c349dbc7Sjsg * SOFTWARE.
22c349dbc7Sjsg */
23c349dbc7Sjsg #include <linux/debugfs.h>
24c349dbc7Sjsg #include <linux/list_sort.h>
25c349dbc7Sjsg #include "i915_drv.h"
26c349dbc7Sjsg #include "gvt.h"
27c349dbc7Sjsg
28c349dbc7Sjsg struct mmio_diff_param {
29c349dbc7Sjsg struct intel_vgpu *vgpu;
30c349dbc7Sjsg int total;
31c349dbc7Sjsg int diff;
32c349dbc7Sjsg struct list_head diff_mmio_list;
33c349dbc7Sjsg };
34c349dbc7Sjsg
35c349dbc7Sjsg struct diff_mmio {
36c349dbc7Sjsg struct list_head node;
37c349dbc7Sjsg u32 offset;
38c349dbc7Sjsg u32 preg;
39c349dbc7Sjsg u32 vreg;
40c349dbc7Sjsg };
41c349dbc7Sjsg
42c349dbc7Sjsg /* Compare two diff_mmio items. */
mmio_offset_compare(void * priv,const struct list_head * a,const struct list_head * b)43c349dbc7Sjsg static int mmio_offset_compare(void *priv,
446dafb210Sjsg const struct list_head *a, const struct list_head *b)
45c349dbc7Sjsg {
46c349dbc7Sjsg struct diff_mmio *ma;
47c349dbc7Sjsg struct diff_mmio *mb;
48c349dbc7Sjsg
49c349dbc7Sjsg ma = container_of(a, struct diff_mmio, node);
50c349dbc7Sjsg mb = container_of(b, struct diff_mmio, node);
51c349dbc7Sjsg if (ma->offset < mb->offset)
52c349dbc7Sjsg return -1;
53c349dbc7Sjsg else if (ma->offset > mb->offset)
54c349dbc7Sjsg return 1;
55c349dbc7Sjsg return 0;
56c349dbc7Sjsg }
57c349dbc7Sjsg
mmio_diff_handler(struct intel_gvt * gvt,u32 offset,void * data)58c349dbc7Sjsg static inline int mmio_diff_handler(struct intel_gvt *gvt,
59c349dbc7Sjsg u32 offset, void *data)
60c349dbc7Sjsg {
61c349dbc7Sjsg struct mmio_diff_param *param = data;
62c349dbc7Sjsg struct diff_mmio *node;
63c349dbc7Sjsg u32 preg, vreg;
64c349dbc7Sjsg
65c349dbc7Sjsg preg = intel_uncore_read_notrace(gvt->gt->uncore, _MMIO(offset));
66c349dbc7Sjsg vreg = vgpu_vreg(param->vgpu, offset);
67c349dbc7Sjsg
68c349dbc7Sjsg if (preg != vreg) {
69ad8b1aafSjsg node = kmalloc(sizeof(*node), GFP_ATOMIC);
70c349dbc7Sjsg if (!node)
71c349dbc7Sjsg return -ENOMEM;
72c349dbc7Sjsg
73c349dbc7Sjsg node->offset = offset;
74c349dbc7Sjsg node->preg = preg;
75c349dbc7Sjsg node->vreg = vreg;
76c349dbc7Sjsg list_add(&node->node, ¶m->diff_mmio_list);
77c349dbc7Sjsg param->diff++;
78c349dbc7Sjsg }
79c349dbc7Sjsg param->total++;
80c349dbc7Sjsg return 0;
81c349dbc7Sjsg }
82c349dbc7Sjsg
83c349dbc7Sjsg /* Show the all the different values of tracked mmio. */
vgpu_mmio_diff_show(struct seq_file * s,void * unused)84c349dbc7Sjsg static int vgpu_mmio_diff_show(struct seq_file *s, void *unused)
85c349dbc7Sjsg {
86c349dbc7Sjsg struct intel_vgpu *vgpu = s->private;
87c349dbc7Sjsg struct intel_gvt *gvt = vgpu->gvt;
88c349dbc7Sjsg struct mmio_diff_param param = {
89c349dbc7Sjsg .vgpu = vgpu,
90c349dbc7Sjsg .total = 0,
91c349dbc7Sjsg .diff = 0,
92c349dbc7Sjsg };
93c349dbc7Sjsg struct diff_mmio *node, *next;
94c349dbc7Sjsg
95c349dbc7Sjsg INIT_LIST_HEAD(¶m.diff_mmio_list);
96c349dbc7Sjsg
97c349dbc7Sjsg mutex_lock(&gvt->lock);
98c349dbc7Sjsg spin_lock_bh(&gvt->scheduler.mmio_context_lock);
99c349dbc7Sjsg
100c349dbc7Sjsg mmio_hw_access_pre(gvt->gt);
101c349dbc7Sjsg /* Recognize all the diff mmios to list. */
102c349dbc7Sjsg intel_gvt_for_each_tracked_mmio(gvt, mmio_diff_handler, ¶m);
103c349dbc7Sjsg mmio_hw_access_post(gvt->gt);
104c349dbc7Sjsg
105c349dbc7Sjsg spin_unlock_bh(&gvt->scheduler.mmio_context_lock);
106c349dbc7Sjsg mutex_unlock(&gvt->lock);
107c349dbc7Sjsg
108c349dbc7Sjsg /* In an ascending order by mmio offset. */
109c349dbc7Sjsg list_sort(NULL, ¶m.diff_mmio_list, mmio_offset_compare);
110c349dbc7Sjsg
111c349dbc7Sjsg seq_printf(s, "%-8s %-8s %-8s %-8s\n", "Offset", "HW", "vGPU", "Diff");
112c349dbc7Sjsg list_for_each_entry_safe(node, next, ¶m.diff_mmio_list, node) {
113c349dbc7Sjsg u32 diff = node->preg ^ node->vreg;
114c349dbc7Sjsg
115c349dbc7Sjsg seq_printf(s, "%08x %08x %08x %*pbl\n",
116c349dbc7Sjsg node->offset, node->preg, node->vreg,
117c349dbc7Sjsg 32, &diff);
118c349dbc7Sjsg list_del(&node->node);
119c349dbc7Sjsg kfree(node);
120c349dbc7Sjsg }
121c349dbc7Sjsg seq_printf(s, "Total: %d, Diff: %d\n", param.total, param.diff);
122c349dbc7Sjsg return 0;
123c349dbc7Sjsg }
124c349dbc7Sjsg DEFINE_SHOW_ATTRIBUTE(vgpu_mmio_diff);
125c349dbc7Sjsg
126c349dbc7Sjsg static int
vgpu_scan_nonprivbb_get(void * data,u64 * val)127c349dbc7Sjsg vgpu_scan_nonprivbb_get(void *data, u64 *val)
128c349dbc7Sjsg {
129c349dbc7Sjsg struct intel_vgpu *vgpu = (struct intel_vgpu *)data;
130c349dbc7Sjsg
131c349dbc7Sjsg *val = vgpu->scan_nonprivbb;
132c349dbc7Sjsg return 0;
133c349dbc7Sjsg }
134c349dbc7Sjsg
135c349dbc7Sjsg /*
136c349dbc7Sjsg * set/unset bit engine_id of vgpu->scan_nonprivbb to turn on/off scanning
137c349dbc7Sjsg * of non-privileged batch buffer. e.g.
138c349dbc7Sjsg * if vgpu->scan_nonprivbb=3, then it will scan non-privileged batch buffer
139c349dbc7Sjsg * on engine 0 and 1.
140c349dbc7Sjsg */
141c349dbc7Sjsg static int
vgpu_scan_nonprivbb_set(void * data,u64 val)142c349dbc7Sjsg vgpu_scan_nonprivbb_set(void *data, u64 val)
143c349dbc7Sjsg {
144c349dbc7Sjsg struct intel_vgpu *vgpu = (struct intel_vgpu *)data;
145c349dbc7Sjsg
146c349dbc7Sjsg vgpu->scan_nonprivbb = val;
147c349dbc7Sjsg return 0;
148c349dbc7Sjsg }
149c349dbc7Sjsg
150*f005ef32Sjsg DEFINE_DEBUGFS_ATTRIBUTE(vgpu_scan_nonprivbb_fops,
151c349dbc7Sjsg vgpu_scan_nonprivbb_get, vgpu_scan_nonprivbb_set,
152c349dbc7Sjsg "0x%llx\n");
153c349dbc7Sjsg
vgpu_status_get(void * data,u64 * val)154*f005ef32Sjsg static int vgpu_status_get(void *data, u64 *val)
155*f005ef32Sjsg {
156*f005ef32Sjsg struct intel_vgpu *vgpu = (struct intel_vgpu *)data;
157*f005ef32Sjsg
158*f005ef32Sjsg *val = 0;
159*f005ef32Sjsg
160*f005ef32Sjsg if (test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
161*f005ef32Sjsg *val |= (1 << INTEL_VGPU_STATUS_ATTACHED);
162*f005ef32Sjsg if (test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status))
163*f005ef32Sjsg *val |= (1 << INTEL_VGPU_STATUS_ACTIVE);
164*f005ef32Sjsg
165*f005ef32Sjsg return 0;
166*f005ef32Sjsg }
167*f005ef32Sjsg
168*f005ef32Sjsg DEFINE_DEBUGFS_ATTRIBUTE(vgpu_status_fops, vgpu_status_get, NULL, "0x%llx\n");
169*f005ef32Sjsg
170c349dbc7Sjsg /**
171c349dbc7Sjsg * intel_gvt_debugfs_add_vgpu - register debugfs entries for a vGPU
172c349dbc7Sjsg * @vgpu: a vGPU
173c349dbc7Sjsg */
intel_gvt_debugfs_add_vgpu(struct intel_vgpu * vgpu)174c349dbc7Sjsg void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu)
175c349dbc7Sjsg {
176c349dbc7Sjsg char name[16] = "";
177c349dbc7Sjsg
178c349dbc7Sjsg snprintf(name, 16, "vgpu%d", vgpu->id);
179c349dbc7Sjsg vgpu->debugfs = debugfs_create_dir(name, vgpu->gvt->debugfs_root);
180c349dbc7Sjsg
181c349dbc7Sjsg debugfs_create_file("mmio_diff", 0444, vgpu->debugfs, vgpu,
182c349dbc7Sjsg &vgpu_mmio_diff_fops);
183*f005ef32Sjsg debugfs_create_file_unsafe("scan_nonprivbb", 0644, vgpu->debugfs, vgpu,
184c349dbc7Sjsg &vgpu_scan_nonprivbb_fops);
185*f005ef32Sjsg debugfs_create_file_unsafe("status", 0644, vgpu->debugfs, vgpu,
186*f005ef32Sjsg &vgpu_status_fops);
187c349dbc7Sjsg }
188c349dbc7Sjsg
189c349dbc7Sjsg /**
190c349dbc7Sjsg * intel_gvt_debugfs_remove_vgpu - remove debugfs entries of a vGPU
191c349dbc7Sjsg * @vgpu: a vGPU
192c349dbc7Sjsg */
intel_gvt_debugfs_remove_vgpu(struct intel_vgpu * vgpu)193c349dbc7Sjsg void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu)
194c349dbc7Sjsg {
195b6d02092Sjsg struct intel_gvt *gvt = vgpu->gvt;
196b6d02092Sjsg struct drm_minor *minor = gvt->gt->i915->drm.primary;
197b6d02092Sjsg
198b6d02092Sjsg if (minor->debugfs_root && gvt->debugfs_root) {
199c349dbc7Sjsg debugfs_remove_recursive(vgpu->debugfs);
200c349dbc7Sjsg vgpu->debugfs = NULL;
201c349dbc7Sjsg }
202b6d02092Sjsg }
203c349dbc7Sjsg
204c349dbc7Sjsg /**
205c349dbc7Sjsg * intel_gvt_debugfs_init - register gvt debugfs root entry
206c349dbc7Sjsg * @gvt: GVT device
207c349dbc7Sjsg */
intel_gvt_debugfs_init(struct intel_gvt * gvt)208c349dbc7Sjsg void intel_gvt_debugfs_init(struct intel_gvt *gvt)
209c349dbc7Sjsg {
210c349dbc7Sjsg struct drm_minor *minor = gvt->gt->i915->drm.primary;
211c349dbc7Sjsg
212c349dbc7Sjsg gvt->debugfs_root = debugfs_create_dir("gvt", minor->debugfs_root);
213c349dbc7Sjsg
214c349dbc7Sjsg debugfs_create_ulong("num_tracked_mmio", 0444, gvt->debugfs_root,
215c349dbc7Sjsg &gvt->mmio.num_tracked_mmio);
216c349dbc7Sjsg }
217c349dbc7Sjsg
218c349dbc7Sjsg /**
219c349dbc7Sjsg * intel_gvt_debugfs_clean - remove debugfs entries
220c349dbc7Sjsg * @gvt: GVT device
221c349dbc7Sjsg */
intel_gvt_debugfs_clean(struct intel_gvt * gvt)222c349dbc7Sjsg void intel_gvt_debugfs_clean(struct intel_gvt *gvt)
223c349dbc7Sjsg {
224059ed2c0Sjsg struct drm_minor *minor = gvt->gt->i915->drm.primary;
225059ed2c0Sjsg
226059ed2c0Sjsg if (minor->debugfs_root) {
227c349dbc7Sjsg debugfs_remove_recursive(gvt->debugfs_root);
228c349dbc7Sjsg gvt->debugfs_root = NULL;
229c349dbc7Sjsg }
230059ed2c0Sjsg }
231