15ca02815Sjsg /* SPDX-License-Identifier: MIT */ 2c349dbc7Sjsg /* 35ca02815Sjsg * Copyright © 2015 Intel Corporation 4c349dbc7Sjsg */ 5c349dbc7Sjsg 6c349dbc7Sjsg #ifndef INTEL_MOCS_H 7c349dbc7Sjsg #define INTEL_MOCS_H 8c349dbc7Sjsg 9c349dbc7Sjsg /** 10c349dbc7Sjsg * DOC: Memory Objects Control State (MOCS) 11c349dbc7Sjsg * 12c349dbc7Sjsg * Motivation: 13c349dbc7Sjsg * In previous Gens the MOCS settings was a value that was set by user land as 14c349dbc7Sjsg * part of the batch. In Gen9 this has changed to be a single table (per ring) 15c349dbc7Sjsg * that all batches now reference by index instead of programming the MOCS 16c349dbc7Sjsg * directly. 17c349dbc7Sjsg * 18c349dbc7Sjsg * The one wrinkle in this is that only PART of the MOCS tables are included 19c349dbc7Sjsg * in context (The GFX_MOCS_0 - GFX_MOCS_64 and the LNCFCMOCS0 - LNCFCMOCS32 20c349dbc7Sjsg * registers). The rest are not (the settings for the other rings). 21c349dbc7Sjsg * 22c349dbc7Sjsg * This table needs to be set at system start-up because the way the table 23c349dbc7Sjsg * interacts with the contexts and the GmmLib interface. 24c349dbc7Sjsg * 25c349dbc7Sjsg * 26c349dbc7Sjsg * Implementation: 27c349dbc7Sjsg * 28c349dbc7Sjsg * The tables (one per supported platform) are defined in intel_mocs.c 29c349dbc7Sjsg * and are programmed in the first batch after the context is loaded 30c349dbc7Sjsg * (with the hardware workarounds). This will then let the usual 31c349dbc7Sjsg * context handling keep the MOCS in step. 32c349dbc7Sjsg */ 33c349dbc7Sjsg 34c349dbc7Sjsg struct intel_engine_cs; 35c349dbc7Sjsg struct intel_gt; 36c349dbc7Sjsg 37c349dbc7Sjsg void intel_mocs_init(struct intel_gt *gt); 38c349dbc7Sjsg void intel_mocs_init_engine(struct intel_engine_cs *engine); 39*1bb76ff1Sjsg void intel_set_mocs_index(struct intel_gt *gt); 40c349dbc7Sjsg 41c349dbc7Sjsg #endif 42